Trench structure and preparation method thereof, and semiconductor device and preparation method thereof

Abstract

The embodiment of the invention provides a groove structure and a preparation method thereof, and a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. The trench structure comprises: a trench, which is located in a substrate; the oxide layer pattern is positioned on the surface of the groove; the nitride layer pattern is positioned on the oxide layer pattern and is far away from the surface of the groove; and the semiconductor film pattern is positioned on the nitride layer pattern and is far away from the oxide layer pattern. The embodiment of the invention is at least beneficial to improving hot electron induced punch-through.

Description

Technical Field

[0001] The present disclosure belongs to the field of semiconductor technology, and specifically relates to a trench structure and a preparation method thereof, a semiconductor device and a preparation method thereof. Background Art

[0002] As the integration of semiconductor devices continues to increase, the design rules of semiconductor device components continue to decrease. In particular, the gate length continues to decrease, which may cause additional hot electron induced punch through (HEIP) phenomenon, resulting in unexpected electrical performance of semiconductor devices. Summary of the invention

[0003] The embodiments of the present disclosure provide a trench structure and a method for manufacturing the same, a semiconductor device and a method for manufacturing the same, which can at least improve HEIP.

[0004] An embodiment of the present disclosure provides a groove structure, comprising: a groove, wherein the groove is located in a substrate; an oxide layer pattern, wherein the oxide layer pattern is located on a surface of the groove; a nitride layer pattern, wherein the nitride layer pattern is located on the oxide layer pattern and away from the surface of the groove; and a semiconductor film pattern, wherein the semiconductor film pattern is located on the nitride layer pattern and away from the oxide layer pattern.

[0005] An embodiment of the present disclosure provides a method for preparing a groove structure, comprising: forming a groove in a substrate; forming an oxide layer on the surface of the substrate and the groove; forming a nitride layer on the oxide layer, and the nitride layer is away from the surface of the groove; forming a semiconductor film on the nitride layer, and the semiconductor film is away from the oxide layer.

[0006] An embodiment of the present disclosure provides a semiconductor device, comprising: a substrate; and a trench structure as described in any embodiment of the present disclosure.

[0007] An embodiment of the present disclosure provides a method for preparing a semiconductor device, comprising: providing a substrate; forming a groove in the substrate; forming an oxide layer on the surface of the substrate and the groove; forming a nitride layer on the oxide layer, and the nitride layer is away from the surface of the groove; forming a semiconductor film on the nitride layer, and the semiconductor film is away from the oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0009] Figure 1 (a) and Figure 1 (b) shows a top view and a cross-sectional view (front view) along the BB' direction of a semiconductor device.

[0010] Figure 2 A top view of a semiconductor device is shown.

[0011] Figure 3 Shows Figure 2 Cross-sectional view along the AA' direction.

[0012] Figure 4 Shows Figure 2 Cross-sectional view along the BB' direction.

[0013] Figure 5 A schematic structural diagram of a semiconductor device is shown.

[0014] Figure 6 A schematic diagram showing the relationship between electrostatic potential and action distance is shown.

[0015] Figure 7 A schematic diagram of a groove structure provided by an embodiment of the present disclosure is shown.

[0016] Figure 8 Shows Figure 7 Schematic diagram of the trench structure provided.

[0017] Fig. 9 Shows Figure 7 A schematic diagram of the electrostatic field distribution of the groove structure is provided.

[0018] Fig.10 Shows Figure 7 Another schematic diagram of electrostatic field distribution of the groove structure provided.

[0019] Fig.11 A structural schematic diagram corresponding to a step in the method for preparing a groove structure provided in an embodiment of the present disclosure is shown.

[0020] Fig.12 A structural schematic diagram corresponding to another step in the method for preparing the groove structure provided in an embodiment of the present disclosure is shown.

[0021] Fig.13A structural schematic diagram corresponding to another step in the method for preparing the groove structure provided in an embodiment of the present disclosure is shown.

[0022] Fig.14 A structural schematic diagram corresponding to another step in the method for preparing the groove structure provided in an embodiment of the present disclosure is shown.

[0023] Fig.15 A structural schematic diagram corresponding to another step in the method for preparing the groove structure provided in an embodiment of the present disclosure is shown.

[0024] Fig.16 Shows Figure 7 Schematic diagram of the relationship between the electrostatic potential and distance of the trench structure provided. DETAILED DESCRIPTION

[0025] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the present disclosure is not limited to the following description, and its mode and details can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents recorded in the embodiments shown below.

[0026] In addition, for ease of understanding, the position, size, range, etc. of each structure shown in the drawings and the like may not represent its actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like.

[0027] In addition, in this specification, for the sake of convenience, ordinal numbers such as first and second are added, but they do not sometimes indicate the order of processes or the order of stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third" for description. In addition, the ordinal numbers recorded in this specification and the like are sometimes inconsistent with the ordinal numbers used to specify one embodiment of the present disclosure.

[0028] In this specification, for convenience, words and phrases such as "upper" and "lower" indicating configuration are used to explain the positional relationship of the components with reference to the drawings. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, the words and phrases described in this specification are not limited and can be appropriately replaced according to the situation.

[0029] Note that in this specification and the like, when describing the configuration of the invention using drawings, reference numerals may be used in common to indicate the same components in different drawings.

[0030] In the disclosed embodiments, a transistor refers to an element including at least three terminals: a gate (gate electrode), a drain (drain electrode) and a source (source electrode). The transistor has a channel region between the drain and the source, and current can flow through the drain, the channel region and the source. The channel region refers to the region where the current mainly flows. In the disclosed embodiments, a thin film transistor is a field effect transistor.

[0031] In addition, when transistors with different polarities are used or the direction of current changes during circuit operation, the functions of the source and drain may be interchanged. Therefore, in the embodiments of the present disclosure, the source and drain may be interchanged.

[0032] Note that the channel length refers to, for example, the area where the semiconductor layer (or the portion of the semiconductor layer through which current flows when the transistor is in the on state) and the gate electrode overlap with each other in a top view of the transistor, or the distance between the source and the drain in the area where the channel is formed.

[0033] In the embodiments of the present disclosure, "electrical connection" includes connection through "an element having some kind of electrical function". Here, "an element having some kind of electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected objects. For example, "an element having some kind of electrical function" includes not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0034] refer to Figures 1 to 4 , is a schematic diagram of a model of HEIP induced by a trench structure (e.g., STI (shallow trench isolation) 4). Here, a semiconductor device is taken as an example, PMOS (Positive Channel Metal Oxide Semiconductor, which refers to a MOS tube with an n-type substrate and a p-channel that transports current by the flow of holes). 2 represents the drain of PMOS, 1 represents the gate of PMOS, 3 represents the source of PMOS, 4 represents STI, 41 represents the oxide layer of the sidewall in STI, 42 represents the silicon nitride layer (Si3N4 liner) inside STI, and electron trap.

[0035] STI is mostly an ONO (i.e., oxide layer-nitride layer-oxide layer) structure, in which the oxide layer can be, for example, silicon dioxide, and the nitride layer can be, for example, silicon nitride, but is not limited thereto. Due to the capture of electrons at the ON interface in the STI, holes are concentrated in the active area (AA) near the STI, causing HEIP. The electrons captured in the top area of ​​the ON interface of the STI cause the Vth (threshold voltage) at the edge of the active area of ​​the transistor (active edge of transistor) to decrease, thereby causing the off-state current (I off )Increase.

[0036] Figure 3 and Figure 4 The circled “+” in the graph represents a hole (h+ in the following text), and the circled “-” represents an electron (electron in the following text, e-).

[0037] Figure 5 A schematic structural diagram of a semiconductor device is shown.

[0038] like Figure 5 As shown, 500 represents a PMOS, 501 represents a gate of the PMOS, 502 represents a drain of the PMOS, 503 represents a source of the PMOS, and 504 represents a STI.

[0039] from Figure 5 It can be known that the ON interface in the STI 504 captures electrons, so that electrons are accumulated at the boundary between the STI 504 and the gate 501 , resulting in a decrease in the electrostatic potential at the boundary between the drain 502 and the gate 501 , and accumulation of holes.

[0040] The trapped electrons reduce the electrostatic potential of the PMOS channel on the side close to the trapped electrons. From the Boltzmann factor, it can be known that holes accumulate in the channel on the side close to the trapped electrons.

[0041] In physics, the Boltzmann factor is a weighting factor that determines the relative probability of state i in a multi-state system that is in thermodynamic equilibrium at temperature T. Among them, k B is Boltzmann's constant, E i is the energy of state i. The ratio of the probabilities of two states is given by the ratio of their Boltzmann factors.

[0042] Figure 6From the perspective of Fermi level, Fermi level The formula is as follows:

[0043]

[0044] in, It is the standard state and is only related to the material (assuming that all carriers are electrons). Therefore, N-type, P-type and intrinsic semiconductors have the same (Standard chemical potential, chemical potential at standard state). It is called the concentration term, but sometimes the more precise activity term is used. (activity term) instead, a represents the activity of electrons in the α phase. α is the electrostatic energy of a single electron in the α phase. k is the Boltzmann constant. is the electron concentration in the α phase.

[0045] The captured electrons reduce the electrostatic potential on the side of the PMOS channel close to the captured electrons. In order to satisfy the equal Fermi level at any position, the channel close to the captured electron side will inevitably have less electron concentration at the bottom to reduce Any position X at equilibrium e ×X h is a constant, X e and X h represent the electron concentration and hole concentration respectively, resulting in the accumulation of holes in the channel close to the side where electrons are captured.

[0046] Figure 6 The figure shows the relationship between electrostatic potential and action distance. p represents the electrostatic potential on the side of the PMOS channel close to the captured electrons, and r represents the distance between the active region and the top region of the STI ON interface that captures electrons. Figure 6 It can be seen that according to Coulomb's law, the electrostatic potential E p Inversely proportional to the square of the distance r, the electrostatic potential E p It decays rapidly with the increase of the action distance r.

[0047] The groove structure and preparation method thereof provided in the embodiments of the present disclosure can reduce the influence of captured electrons on the electrostatic potential of the channel close to the captured electrons, thereby reducing the accumulation of holes in the channel on the captured electron side, thereby achieving the purpose of improving HEIP.

[0048] Figure 7A schematic diagram of a groove structure provided by an embodiment of the present disclosure is shown.

[0049] like Figure 7 As shown, the trench structure provided by the embodiment of the present disclosure includes a trench 100 , an oxide layer pattern 310 , a nitride layer pattern 320 and a semiconductor film pattern 330 .

[0050] The trench 100 may be located in the substrate 200. The oxide layer pattern 310 may be located on the surface of the trench 100. Specifically, the surface of the trench 100 may include a bottom surface 100B and two side surfaces 100S, and the oxide layer pattern 310 may be located on the bottom surface 100B and the two side surfaces 100S of the trench 100.

[0051] The trench structure formed in the embodiment of the present disclosure may be located in a substrate and used to define an active area.

[0052] In the embodiment of the present disclosure, the oxide layer pattern 310 may conformally cover the bottom surface 100B and both side surfaces 100S of the trench 100 and the upper surface of the substrate 100. The nitride layer pattern 320 may conformally cover the surface of the oxide layer pattern 310 away from the trench 100.

[0053] The nitride layer pattern 320 may be located on the oxide layer pattern 310 and away from the surface of the trench 100. The semiconductor film pattern 330 may be located on the nitride layer pattern 320 and away from the oxide layer pattern 310.

[0054] In some embodiments, the upper surface of the semiconductor film pattern 330 may be flush with the upper surface of the nitride layer pattern 320. However, the present disclosure is not limited thereto.

[0055] The trench structure provided by the embodiment of the present disclosure, on the one hand, can reduce the accumulation of positive charges on the side close to the electron capture side by adding a semiconductor film pattern on the side of the nitride layer pattern of the trench structure away from the substrate, thereby improving the hot electron induced punch-through (HEIP) phenomenon; on the other hand, since the semiconductor film pattern is added on the side of the nitride layer pattern of the trench structure away from the substrate, the distance between the semiconductor film pattern and the active area in the substrate can be increased, especially the distance between the semiconductor film pattern and the drain area in the active area (corresponding to the drain of the semiconductor device), thereby preventing the semiconductor film pattern and the drain area of ​​the active area from forming a parasitic capacitance, reducing delay and reducing loss.

[0056] Continue to refer Figure 7 The trench structure may further include an insulating layer pattern 340 . The insulating layer pattern 340 may be located on the semiconductor film pattern 330 and away from the nitride layer pattern 320 .

[0057] In an exemplary embodiment, the insulating layer pattern 340 includes oxide, that is, the STI is an ONO structure. In the embodiment of the present disclosure, the insulating layer pattern 340 and the oxide layer pattern 310 may include the same oxide, for example, both include silicon dioxide, but the present disclosure is not limited thereto.

[0058] In exemplary embodiments, the insulation layer pattern 340 fills the trench 100 .

[0059] In an exemplary embodiment, the semiconductor film pattern 330 includes a P-type doped or N-type doped semiconductor material.

[0060] In an exemplary embodiment, the semiconductor film pattern 330 includes polysilicon (poly).

[0061] The semiconductor film pattern 330 in the embodiment of the present disclosure may include any semiconductor material including polysilicon.

[0062] For example, N-type doped semiconductor materials can be polysilicon doped with pentavalent impurity elements (such as phosphorus, arsenic, etc.), in which free electrons are the majority carriers and holes are the minority carriers. P-type doped semiconductor materials can be polysilicon doped with trivalent impurity elements (such as boron, gallium, etc.), in which holes are the majority carriers and free electrons are the minority carriers.

[0063] In an exemplary embodiment, the trench structure is a shallow trench isolation structure. In the following embodiments, the trench structure is illustrated as STI, but the present disclosure is not limited thereto.

[0064] The groove structure provided in the embodiment of the present disclosure, on the one hand, can reduce the accumulation of holes on the side of the PMOS channel close to the captured electrons by weakening the electrostatic potential effect of the captured electrons on the PMOS channel, thereby improving the hot electron induced punch-through HEIP phenomenon. On the other hand, the semiconductor film pattern added in the embodiment of the present disclosure is farther away from the active area in the substrate, thereby preventing the semiconductor film pattern and the drain area of ​​the active area from forming a parasitic capacitance, thereby reducing delay and reducing loss.

[0065] Figure 8 Shows Figure 7 The schematic diagram of the groove structure is provided. Figure 8 As shown, on the side of the oxide-nitride interface (i.e., the ON interface, where the ON interface refers to the interface between the nitride layer pattern 320 and the insulating layer pattern 340, where the insulating layer pattern 340 includes oxide), an Figure 8The dipole (ie, semiconductor film pattern 330) oriented as shown in FIG. 1 increases the barrier for electron capture (trap) in the interface region, that is, trapping electrons at the oxide-nitride interface, resulting in the semiconductor film pattern 330 being close to the end for trapping electrons (eg, Figure 8 The A end shown is in the top area of ​​the ON interface, which is the location where electrons are captured) to accumulate holes.

[0066] Figure 8 E shown in c It stands for conduction band edge, which is the energy space formed by free electrons, that is, the energy range of electrons moving freely in a fixed structure. v It stands for valence bandedge, the edge of the valence band (the top of the valence band). The electrons in the atomic orbital and in a bonding state are called valence electrons. The many energy levels occupied by these valence electrons can be combined and regarded as a single continuous energy range. This low energy band formed by the energy levels of the atomic orbital that are already filled with electrons is called the valence band (full band) of energy levels. Any energy change usually occurs within the valence band.

[0067] Assume that the oxide included in the insulating layer pattern 340 is silicon dioxide (SiO2). When hot electrons cross potential barriers and are captured at the interface between the silicon dioxide and nitride layer pattern 320, the electric potential (represented by φ) at the A end decreases. In order to make the Fermi level equal at any position, the A end will accumulate positive charge (provided by a position farther away from the captured electron). The positive charge at the A end offsets the effect of electron capture on the PMOS channel potential. The positive charge accumulated at the A end in the disclosed embodiment may be a positively charged hole or a fixed positive charge, depending on the doping type of the semiconductor film pattern.

[0068] Fig. 9 Shows Figure 7 A schematic diagram of the electrostatic field distribution of the groove structure is provided. Fig. 9 X represents the distance from the channel to the drain, and Y represents the electric potential (i.e., the electrostatic potential E p ).from Fig. 9 It can be seen that as the electrostatic potential decreases, holes accumulate at the interface of the channel close to the drain, while the interface electrostatic potential between the source and the gate remains unchanged.

[0069] Fig.10 Shows Figure 7 Another schematic diagram of electrostatic field distribution of the groove structure provided. Fig.10 In the figure, X' represents the distance from end A. Figure 8 , assuming A is the origin on the X' axis, B is point B on the X' axis, then Y represents the electric potential.

[0070] HEIP is caused by STI capturing negatively charged electrons, which in turn affects the distribution of the channel electrostatic potential, resulting in the accumulation of holes on the side close to the captured electrons, which is equivalent to a reduction in the channel length. The groove structure provided by the embodiment of the present disclosure introduces a semiconductor film pattern between the nitride layer pattern and the insulating layer pattern in the STI. When the STI captures electrons, positive charges accumulate in the area of ​​the semiconductor film pattern close to the captured electrons, thereby weakening the effect of the captured electrons on the electrostatic potential of the active area and improving the HEIP effect. At the same time, since the oxide-nitride insulating film is separated from the semiconductor film pattern and the active area, the semiconductor film will not contact the conductive structure on the substrate, thereby ensuring the reliability of the semiconductor device.

[0071] An embodiment of the present disclosure also provides a method for preparing a groove structure, comprising: forming a groove in a substrate; forming an oxide layer on the surface of the substrate and the groove; forming a nitride layer on the oxide layer, and the nitride layer is away from the surface of the groove; forming a semiconductor film on the nitride layer, and the semiconductor film is away from the oxide layer.

[0072] In an exemplary embodiment, the method for preparing the trench structure provided by the embodiment of the present disclosure may further include: forming an insulating layer on the semiconductor film, wherein the insulating layer is away from the nitride layer.

[0073] In an exemplary embodiment, the preparation method of the trench structure provided in the embodiment of the present disclosure may also include: performing a planarization treatment on the trench structure to form the oxide layer, the nitride layer, the semiconductor film and the insulating layer into an oxide layer pattern, a nitride layer pattern, a semiconductor film pattern and an insulating layer pattern of the trench structure, respectively, and the surface height of the trench structure is flush with the surface height of the substrate.

[0074] The method for preparing the trench structure provided by the embodiment of the present disclosure, on the one hand, can reduce the accumulation of positive charges on the side close to the electron capture by adding a semiconductor film pattern on the side of the nitride layer pattern of the trench structure away from the substrate, thereby improving the hot electron induced punch-through (HEIP) phenomenon; on the other hand, since the semiconductor film pattern is added on the side of the nitride layer pattern of the trench structure away from the substrate, the distance between the semiconductor film pattern and the active area in the substrate can be increased, especially the distance between the semiconductor film pattern and the drain area in the active area (corresponding to the drain of the semiconductor device), thereby preventing the semiconductor film pattern and the drain area of ​​the active area from forming a parasitic capacitance, reducing delay and reducing loss.

[0075] Combine the following Figures 11 to 15 The method for preparing the groove structure provided in the embodiment of the present disclosure is illustrated by way of example, but the present disclosure is not limited thereto.

[0076] like Fig.11 As shown, here, the preparation of STI is taken as an example, and a substrate 200 is first provided, for example, it can be a silicon substrate, but the present disclosure is not limited to this. Then the substrate 200 is etched to form a groove 100 in the substrate. Dry etching or wet etching can be used, and the present disclosure does not limit the etching method. The groove 100 formed by etching may include a bottom surface 100B and two side surfaces 100S. In the embodiment of the present disclosure, the groove 100 formed by etching can be an inverted trapezoid, that is, the width of the upper surface is greater than the width of the lower surface, but the present disclosure is not limited to this. The width refers to the direction parallel to the upper surface of the substrate 100.

[0077] like Fig.12 As shown in the above Fig.11 Based on the formed trench 100, an oxide layer 310a is deposited on the bottom surface 100B and two side surfaces 100S of the trench 100 and the upper surface of the substrate 200. The oxide layer 310a can conformally cover the bottom surface 100B and two side surfaces 100S of the trench 100 and the upper surface of the substrate 200, but does not completely fill the trench 100.

[0078] like Fig.13 As shown in the above Fig.12 Based on the trench 100 including the oxide layer 310a, a nitride layer 320a is deposited on the bottom surface, two side surfaces and the top surface of the oxide layer 310a. The nitride layer 320a can conformally cover the bottom surface, two side surfaces and the top surface of the oxide layer 310a, but does not completely fill the trench 100.

[0079] like Fig.14 As shown in the above Fig.13 On the basis of the above, the semiconductor film 330a is continuously deposited on the bottom surface and two side surfaces of the nitride layer 320a. The semiconductor film 330a does not completely fill the trench 100. The upper surface of the semiconductor film 330a may be flush with the upper surface of the nitride layer 320a, that is, the upper surface of the nitride layer 320a does not cover the semiconductor film 330a.

[0080] like Fig.15 As shown in the above Fig.14 On the basis of the above, the remaining gap in the trench 100 is continuously filled with an insulating layer, that is, the bottom surface and the side surface of the semiconductor film 330a are covered with an insulating layer, and the insulating layer is away from the nitride layer 320a. Fig.15After that, the trench structure can be planarized, for example, by performing a CMP (Chemical Mechanical Polishing) operation to remove part of the oxide layer 310a, the nitride layer 320a, the semiconductor film 330a and the insulating layer to expose the upper surface of the substrate 200, so that the upper surfaces of the oxide layer 310a, the nitride layer 320a, the semiconductor film 330a and the insulating layer are all flush with the exposed upper surface of the substrate 200, and an oxide layer pattern 310, a nitride layer pattern 320, a semiconductor film pattern 330 and an insulating layer pattern 340 of the trench structure are respectively formed, and the surface height of the trench structure is flush with the surface height of the substrate 200.

[0081] In the disclosed embodiment, any one or more deposition processes may be used to deposit and form the oxide layer 310a, the nitride layer 320a, the semiconductor film 330a and the insulating layer, such as PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), ALD (atomic layer deposition), etc. PVD is a technology that uses physical methods to vaporize the surface of a material source (solid or liquid) into gaseous atoms, molecules or partially ionize them into ions under vacuum conditions, and deposits a thin film with a certain special function on the surface of the substrate through a low-pressure gas (or plasma) process. CVD is mainly a method of using one or more gas phase compounds or single substances containing film elements to chemically react on the surface of the substrate to generate a thin film. As the integration of integrated circuits becomes higher and higher, and the size becomes smaller and smaller, high dielectric constant (high k) gate dielectrics gradually replace traditional silicon oxide gates, and at the same time, the aspect ratio becomes larger and larger, which puts higher requirements on the step coverage ability of the deposition technology. Therefore, ALD has been increasingly adopted as a new deposition process that can meet the above requirements. ALD is a method of forming a deposited film by alternately passing gaseous precursor pulses into the reactor and chemically adsorbing and reacting on the deposition substrate. Unlike CVD, during the deposition process of ALD, the reaction precursors are deposited alternately, and the chemical reaction of the new layer of atomic film is directly related to the previous layer. This method allows only one layer of atoms to be deposited each time.

[0082] The method for preparing the trench structure provided in the embodiment of the present disclosure, on the one hand, can reduce the accumulation of holes on the side of the PMOS channel close to the captured electrons by weakening the electrostatic potential effect of the captured electrons on the PMOS channel, thereby improving the HEIP phenomenon. On the other hand, the semiconductor film pattern added in the embodiment of the present disclosure is farther away from the active area in the substrate, thereby preventing the semiconductor film pattern and the drain area of ​​the active area from forming a parasitic capacitance, thereby reducing delay and reducing loss.

[0083] Furthermore, an embodiment of the present disclosure also provides a semiconductor device, comprising: a substrate; and a trench structure as described in any embodiment of the present disclosure.

[0084] In an exemplary embodiment, the substrate further includes an active region, the active region is located between adjacent trench structures, and the distance between the semiconductor film pattern and the active region is greater than a preset threshold.

[0085] In an exemplary embodiment, the preset threshold is 2 μm.

[0086] Fig.16 Shows Figure 7 Schematic diagram of the relationship between the electrostatic potential and distance of the trench structure provided.

[0087] from Fig.16 It can be seen that if the distance between the semiconductor film pattern and the active area is less than the preset threshold, even if the STI does not capture electrons, the semiconductor film pattern in the STI will induce charges (charges in response to the potential of the active area AA). At this time, the semiconductor film pattern and the drain area (drain) in the active area AA form a parasitic capacitor, increasing the delay and increasing power consumption. The embodiment of the present disclosure sets the distance between the semiconductor film pattern added in the STI and the active area to be greater than the preset threshold, so as to avoid the formation of parasitic capacitance between the semiconductor film in the STI and the active area, especially the drain area in the active area, thereby reducing the delay, reducing power consumption, and improving the performance of the semiconductor device.

[0088] In an exemplary embodiment, the semiconductor device includes a P-type metal oxide semiconductor field effect transistor.

[0089] The semiconductor device in the embodiments of the present disclosure may be a semiconductor memory device, that is, a semiconductor device having a storage function or capable of assisting in forming a storage function, for example, it may be a PMOS in an array area, core area or peripheral area of ​​a DRAM (Dynamic Random Access Memory).

[0090] Furthermore, an embodiment of the present disclosure also provides a method for preparing a semiconductor device, comprising: providing a substrate; forming a groove in the substrate; forming an oxide layer on the surface of the substrate and the groove; forming a nitride layer on the oxide layer, and the nitride layer is away from the surface of the groove; forming a semiconductor film on the nitride layer, and the semiconductor film is away from the oxide layer.

[0091] In an exemplary embodiment, the method for manufacturing a semiconductor device provided by the embodiment of the present disclosure may further include: forming an insulating layer on the semiconductor film, wherein the insulating layer is away from the nitride layer.

[0092] In an exemplary embodiment, the method for preparing a semiconductor device provided in an embodiment of the present disclosure may further include: performing a planarization treatment to form an oxide layer pattern, a nitride layer pattern, a semiconductor film pattern and an insulating layer pattern of a groove structure of the oxide layer, the nitride layer, the semiconductor film and the insulating layer, respectively, and the surface height of the groove structure is flush with the surface height of the substrate.

[0093] The method for preparing a semiconductor device provided by the embodiment of the present disclosure, on the one hand, can reduce the accumulation of positive charges on the side close to the electron capture by adding a semiconductor film pattern on the side of the nitride layer pattern of the trench structure away from the substrate, thereby improving the hot electron induced punch-through (HEIP) phenomenon; on the other hand, since the semiconductor film pattern is added on the side of the nitride layer pattern of the trench structure away from the substrate, the distance between the semiconductor film pattern and the active area in the substrate can be increased, especially the distance between the semiconductor film pattern and the drain area in the active area (corresponding to the drain of the semiconductor device), thereby preventing the semiconductor film pattern and the drain area of ​​the active area from forming a parasitic capacitance, reducing delay and reducing loss.

[0094] The switching characteristics of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) are derived from "Vg regulating surface potential" to achieve the purpose of controlling the carrier concentration in the channel. Vg represents the gate voltage of MOSFET. Therefore, except for the gate to bulk (gate to substrate, strictly speaking, Cox (oxide capacitance per unit area)) capacitance, the remaining capacitances are redundant and harmful. These redundant and harmful capacitances are called parasitic capacitance (para.cap. for short). The groove structure and preparation method thereof, the semiconductor device and preparation method thereof provided in the embodiments of the present disclosure can reduce delay and power consumption by avoiding the formation of parasitic capacitance between the semiconductor film pattern in STI and the active area.

[0095] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0096] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and cannot be construed as limitations on the present disclosure. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and specification of the present disclosure shall fall within the scope covered by the patent of the present disclosure.

Claims

1. A groove structure, characterized in that: include: a trench located in the substrate; an oxide layer pattern, the oxide layer pattern being located on a surface of the trench; a nitride layer pattern, wherein the nitride layer pattern is located on the oxide layer pattern and away from a surface of the trench; A semiconductor film pattern is located on the nitride layer pattern and away from the oxide layer pattern.

2. The groove structure according to claim 1, characterized in that: Also includes: An insulating layer pattern is located on the semiconductor film pattern and away from the nitride layer pattern.

3. The groove structure according to claim 2, characterized in that: The insulating layer pattern includes oxide.

4. The groove structure according to claim 2, characterized in that: The insulating layer pattern fills the trench.

5. The groove structure according to claim 1, characterized in that: The semiconductor film pattern includes a P-type doped or N-type doped semiconductor material.

6. The groove structure according to claim 1, characterized in that: The semiconductor film pattern includes polysilicon.

7. The groove structure according to claim 1, characterized in that: The trench structure is a shallow trench isolation structure.

8. A method for preparing a groove structure, characterized in that: include: forming a trench in a substrate; forming an oxide layer on surfaces of the substrate and the trench; forming a nitride layer on the oxide layer, wherein the nitride layer is away from a surface of the trench; A semiconductor film is formed on the nitride layer, and the semiconductor film is away from the oxide layer.

9. The groove structure according to claim 8, characterized in that: Also includes: An insulating layer is formed on the semiconductor film, and the insulating layer is away from the nitride layer.

10. The groove structure according to claim 9, characterized in that: Also includes: The trench structure is planarized to form the oxide layer, the nitride layer, the semiconductor film and the insulating layer into an oxide layer pattern, a nitride layer pattern, a semiconductor film pattern and an insulating layer pattern of the trench structure respectively, and the surface height of the trench structure is flush with the surface height of the substrate.

11. A semiconductor device, characterized in that: include: substrate; A groove structure as claimed in any one of claims 1 to 7.

12. The semiconductor device according to claim 11, characterized in that The substrate also includes an active region, and the active region is located between adjacent trench structures; The distance between the semiconductor film pattern and the active area is greater than a preset threshold.

13. The semiconductor device according to claim 12, characterized in that The preset threshold is 2 μm.

14. The semiconductor device according to claim 11, characterized in that The semiconductor device includes a P-type metal oxide semiconductor field effect transistor.

15. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming a trench in the substrate; forming an oxide layer on surfaces of the substrate and the trench; forming a nitride layer on the oxide layer, wherein the nitride layer is away from a surface of the trench; A semiconductor film is formed on the nitride layer, and the semiconductor film is away from the oxide layer.

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