Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and relates to the technical field of semiconductors, and a metal connecting hole (3) adopted in the semiconductor device has a relatively small resistance value and relatively high reliability. The semiconductor device comprises a substrate (10), and a lower conductive pattern (1), an upper conductive pattern (2), a lower dielectric layer (11), an upper dielectric layer (12) and a metal connecting hole (3) which are arranged on the substrate (10). Wherein the lower dielectric layer (11) and the upper dielectric layer (12) are located between the lower conductive pattern (1) and the upper conductive pattern (2), the metal connecting hole (3) is located in the two dielectric layers, and the lower conductive pattern (1) and the upper conductive pattern (2) are electrically connected through the metal connecting hole (3). The metal connection hole (3) comprises a first metal column (31), and the bottom of the first metal column (31) is in contact with the lower conductive pattern (1). A bonding layer (a1) is arranged between the first metal column (31) and the upper dielectric layer (12), and the first metal column (31) is in contact with the lower dielectric layer (11).

Description

Semiconductor device and manufacturing method thereof, and electronic device Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] In semiconductor devices, conductive patterns located on different layers need to be electrically connected through metal vias. However, with the development of semiconductor technology, the resistance of metal vias has become increasingly critical to device performance.

[0003] As shown in FIG1 , taking the example of using a tungsten (W) connection hole V to connect a lower conductive pattern a1 and an upper conductive pattern (not shown), in a conventional tungsten deposition process using metal oxide chemical vapor deposition (MOCVD), a bonding layer b (such as a TiN layer) must be formed before tungsten deposition to improve adhesion between the tungsten and the hole wall. However, tungsten deposition under this process results in a gap S. Furthermore, the contact resistance between the bonding layer b at the bottom of the connection hole and the lower conductive pattern a1 is high, making it difficult to reduce the resistance of the metal connection hole.

[0004] Summary of the Invention

[0005] Embodiments of the present application provide a semiconductor device and a manufacturing method thereof, and an electronic device, which can reduce the resistance of a metal connection hole.

[0006] The present application provides a semiconductor device, which may include a substrate, and a first conductive pattern (i.e., a lower conductive pattern), a second conductive pattern (i.e., an upper conductive pattern), a first dielectric layer, a second dielectric layer, and a metal connection hole arranged on the substrate. The second conductive pattern is located above the first conductive pattern (i.e., the second conductive pattern is located on the side of the first conductive pattern away from the substrate), the first dielectric layer and the second dielectric layer are located between the first conductive pattern and the second conductive pattern, and the first dielectric layer is located below the second dielectric layer (i.e., the first dielectric layer is closer to the first conductive pattern relative to the second dielectric layer). The metal connection hole is located in the first dielectric layer and the second dielectric layer, and the first conductive pattern and the second conductive pattern are electrically connected through the metal connection hole. The metal connection hole includes a first metal column, and the bottom of the first metal column is in contact with the first conductive pattern. A first bonding layer is provided between the first metal column and the second dielectric layer, and the first metal column is in contact with the first dielectric layer.

[0007] In the semiconductor device of the present application, a first metal pillar is used in the metal via, and the bottom of the first metal pillar is arranged to directly contact the first conductive pattern, thereby reducing the contact resistance between the first metal pillar and the first conductive pattern. At the same time, a first bonding layer is provided between the sidewall of the first metal pillar and the second dielectric layer. In other words, a bonding material is filled between the sidewall of the first metal pillar and the second dielectric layer. This improves the adhesion between the first metal pillar and the second dielectric layer located above. This avoids defects caused by gaps between the sidewall of the first metal pillar and the second dielectric layer, thereby improving the reliability of the metal connection hole.

[0008] In some possible implementations, the top of the first metal pillar contacts the second conductive pattern; that is, the top of the first metal pillar is directly connected to the second conductive pattern, ensuring a smaller contact resistance between the top of the first metal pillar and the second conductive pattern.

[0009] In some possible implementations, the metal connection hole further includes a second metal post; the second metal post is located on top of the first metal post, and a second adhesive layer is disposed between the second metal post and the top of the first metal post, and between the second metal post and the second dielectric layer; the top of the second metal post contacts the second conductive pattern. In this case, forming the second adhesive layer on the bottom and sidewalls of the second metal post further reduces the probability of polishing agents contacting the first conductive pattern during subsequent polishing of the surface of the second dielectric layer.

[0010] In some possible implementations, the surface of the first conductive pattern has a recessed portion, with the edge of the recess located outside the wall of the metal connection hole; the bottom of the first metal pillar extends into and fills the recessed portion. In this case, the first metal pillar forms a rivet structure at the bottom, creating a "rivet effect" that further reduces the chance of polishing agents coming into contact with the first conductive pattern during subsequent polishing of the second dielectric layer.

[0011] In some possible implementations, the material used for the first bonding layer includes at least one of TiN, Ti, Ta, or TaN.

[0012] In some possible implementations, the material used for the second bonding layer includes at least one of TiN, Ti, Ta, or TaN.

[0013] In some possible implementations, the material used for the first dielectric layer includes SiN; the material used for the second dielectric layer includes SiO2.

[0014] In some possible implementations, the first metal pillar is manufactured using a selective deposition process.

[0015] In some possible implementations, the second metal pillar is manufactured using a metal oxide chemical vapor deposition process.

[0016] An embodiment of the present application also provides an electronic device, which includes a printed circuit board and a semiconductor device provided in any of the possible implementation methods described above; the semiconductor device is electrically connected to the printed circuit board.

[0017] An embodiment of the present application also provides a method for manufacturing a semiconductor device, which may include: manufacturing a first conductive pattern on a substrate. Sequentially manufacturing a first dielectric layer and a second dielectric layer on the surface of the first conductive pattern. Forming a first via hole in the second dielectric layer at a position corresponding to the first conductive pattern, and forming a first adhesive layer on the sidewall of the first via hole. Etching the first dielectric layer at a position corresponding to the first via hole to form a second via hole, and exposing the first conductive pattern. Using a selective deposition process, forming a first metal pillar on the surface of the exposed first conductive pattern, and the first metal pillar extending into the second dielectric layer. Forming a second conductive pattern electrically connected to the first metal pillar on the surface of the second dielectric layer.

[0018] In some possible implementations, forming the second conductive pattern electrically connected to the first metal pillar on the surface of the second dielectric layer may include forming the second conductive pattern on the surface of the second dielectric layer in contact with the surface of the first metal pillar. Specifically, the top of the first metal pillar is in direct contact with the second conductive pattern, thereby ensuring low contact resistance between the top of the first metal pillar and the second conductive pattern.

[0019] In some possible implementations, the above-mentioned formation of the second conductive pattern electrically connected to the first metal pillar on the surface of the second dielectric layer may include: forming a second bonding layer on the surface of the substrate on which the first metal pillar is formed; forming a second metal pillar on the second bonding layer and in the first via hole using a metal oxide chemical vapor deposition method; and forming a second conductive pattern connected to the surface of the second metal pillar on the surface of the second dielectric layer.

[0020] In some possible implementations, the above-mentioned etching of the first dielectric layer at a position corresponding to the first via hole to form a second via hole and leaking the first conductive pattern may include: etching the first dielectric layer at a position corresponding to the first via hole to form a second via hole, and etching the surface of the first conductive pattern to form a recessed portion; wherein the edge of the recessed portion is located on the outside of the hole wall of the second via hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG1 is a schematic diagram of a metal connection hole in a semiconductor device provided in the prior art;

[0022] FIG2 is a schematic diagram of a metal connection hole in a semiconductor device provided by an embodiment of the present application;

[0023] FIG3 is a schematic diagram of a metal connection hole in a semiconductor device provided by an embodiment of the present application;

[0024] FIG4 is a schematic diagram of a metal connection hole in a semiconductor device provided by an embodiment of the present application;

[0025] FIG5 is a schematic diagram of a metal connection hole in a semiconductor device provided by an embodiment of the present application;

[0026] FIG6 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0027] FIG7 is a schematic structural diagram of a semiconductor device during the manufacturing process provided by an embodiment of the present application;

[0028] FIG8 is a schematic structural diagram of a semiconductor device during the manufacturing process provided by an embodiment of the present application;

[0029] FIG9 is a schematic structural diagram of a semiconductor device during the manufacturing process provided by an embodiment of the present application;

[0030] FIG10 is a schematic structural diagram of a semiconductor device during the manufacturing process provided by an embodiment of the present application;

[0031] FIG11 is a schematic structural diagram of a semiconductor device during the manufacturing process provided by an embodiment of the present application;

[0032] FIG12 is a schematic structural diagram of a semiconductor device during the manufacturing process provided by an embodiment of the present application;

[0033] FIG13 is a schematic structural diagram of a semiconductor device during the manufacturing process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0035] The terms "first", "second", etc. in the specification, embodiments, claims, and drawings of this application are only used to distinguish the purpose of description and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple. Similar words such as "connected" and "connected" are used to express the intercommunication or interaction between different components, and can include direct connection or indirect connection through other components. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion, for example, including a series of steps or units. Methods, systems, products, or devices are not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices. "Up", "down", "left", "right", "top", "bottom", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for relative description and clarification, and they may change accordingly according to the changes in the orientation of the components in the drawings.

[0036] An embodiment of the present application provides an electronic device, which includes a printed circuit board (PCB) and a semiconductor device connected to the printed circuit board. The semiconductor device includes conductive patterns located on different layers, and the conductive patterns on different layers are electrically connected through metal connection holes. In the embodiment of the present application, a new type of metal connection hole with a lower resistance is used, thereby improving the performance of the semiconductor device.

[0037] This application does not limit the configuration of the above-mentioned electronic device. For example, the electronic device can be a mobile phone, tablet computer, notebook, car computer, smart watch, smart bracelet and other electronic products.

[0038] The present application does not limit the configuration of the semiconductor device. For example, the semiconductor device may be a memory, a processor, a sensor, or the like.

[0039] The specific structure of the semiconductor device provided in the embodiments of the present application is schematically described below.

[0040] As shown in FIG2 , an embodiment of the present application provides a semiconductor device comprising a substrate 10 and a first conductive pattern 1 and a second conductive pattern 2 disposed on the substrate 10 and located on different layers. The second conductive pattern 2 is located above the first conductive pattern 1 (i.e., on a side away from the substrate 10). A first dielectric layer 11 (i.e., a lower dielectric layer) and a second dielectric layer 12 (i.e., an upper dielectric layer) are disposed between the first conductive pattern 1 and the second conductive pattern 2. The first dielectric layer 11 is located below the second dielectric layer 12 (i.e., the first dielectric layer 11 is closer to the substrate 10 relative to the second dielectric layer 12). The first conductive pattern 1 and the second conductive pattern 2 are electrically connected via metal connection holes 3 disposed in the first dielectric layer 11 and the second dielectric layer 12.

[0041] The present application does not impose any limitation on the specific configuration of the substrate 10 , the first conductive pattern 1 , and the second conductive pattern 2 , which may be determined in practice according to the specific structure of the semiconductor device.

[0042] Schematically, the substrate 10 may include a substrate and a transistor disposed on the substrate. The first conductive pattern 1 may be a source, drain, or gate of the transistor, or may be a conductive pattern such as a signal line. The second conductive pattern 2 may be a conductive pattern such as a signal line or a capacitor electrode. This is not limited in this application. For example, in some possible implementations, the first conductive pattern 1 may be a source, drain, or gate of the transistor, and the second conductive pattern 2 may be a signal line. For another example, in some possible implementations, the first conductive pattern 1 and the second conductive pattern 2 may both be signal lines.

[0043] In addition, for the above-mentioned metal connection hole 3 located in the first dielectric layer 11 and the second dielectric layer 12, a through hole can be formed in the first dielectric layer 11 and the second dielectric layer 12, and one or more metal pillars can be formed in the through hole to form the metal connection hole 3; that is, the metal connection hole 3 can include one metal pillar, or two or more metal pillars. Of course, according to actual needs, the metal connection hole 3 can also include other structures, and this application does not impose any restrictions on this. For details, please refer to the description of the metal connection hole 3.

[0044] 2 , in some possible implementations, the metal connection hole 3 includes a first metal pillar 31, the bottom of which is in direct contact with the first conductive pattern 1, thereby reducing the contact resistance between the first metal pillar 31 and the first conductive pattern 1. A first bonding layer a1 is provided between the portion of the first metal pillar 31 located in the second dielectric layer 12 and the second dielectric layer 12, and the portion of the first metal pillar 31 located in the first dielectric layer 11 is in direct contact with the first dielectric layer 11.

[0045] It should be noted that the "top" and "bottom" mentioned in this application are two relative positions of components, and the "top" is closer to the substrate 10 than the "bottom". For example, the "bottom of the first metal pillar 31" refers to the end of the first metal pillar 31 close to the substrate 10, and the "top of the first metal pillar 31" refers to the end of the first metal pillar 31 away from the substrate 10. In addition, the "direct contact" mentioned in this application means that there is no other component between the two components, and the two components are directly connected; for example, the "bottom of the first metal pillar 31 is in direct contact with the first conductive pattern 1" mentioned above, please refer to the corresponding relevant instructions below for details. In addition, it can be understood that by providing a first adhesive layer a1 between the side wall of the first metal pillar 31 and the second dielectric layer 12, that is, filling the side wall of the first metal pillar 31 and the second dielectric layer 12 with an adhesive material, the adhesion between the first metal pillar 31 and the second dielectric layer 12 located on the upper layer can be improved, thereby avoiding the defect problem caused by the gap between the side wall of the first metal pillar 31 and the second dielectric layer 12 (see the description below for details), thereby improving the reliability of the metal connection hole 3.

[0046] Regarding the aforementioned "defects caused by the gap between the sidewall of the first metal pillar 31 and the second dielectric layer 12," it is understandable that the adhesion between the metal material and the dielectric layer is poor. If the first bonding layer a1 is not provided, a gap will be generated between the sidewall of the first metal pillar 31 and the second dielectric layer 12 during the deposition process to form the first metal pillar 31. Due to the presence of this gap, when the surface of the second dielectric layer 12 is polished (such as chemical mechanical polishing) during the subsequent manufacturing process, the polishing agent will flow downward from the gap position, resulting in missing sidewalls of the first metal pillar 31. At the same time, the polishing agent will contact the first conductive pattern 1, causing damage to the first conductive pattern 1. Therefore, in the present application, by providing the first bonding layer a1 between the first metal pillar 31 and the second dielectric layer 12 located above, the probability of the above-mentioned defects is reduced, thereby improving the reliability of the device.

[0047] In addition, based on the setting method in which the bottom of the first metal pillar 31 is in direct contact with the first conductive pattern 1, in the actual production process, in some possible implementation methods, a selective deposition process can be used to produce the first metal pillar 31, that is, selectively depositing metal material on the surface of the first conductive pattern 1 to form the first metal pillar 31, so that the bottom of the first metal pillar 31 is in direct contact with the first conductive pattern 1, avoiding the problem of high contact resistance between the bottom of the first metal pillar 31 and the first conductive pattern 1 due to the bonding layer in the prior art using MOCVD (refer to Figure 1), and at the same time avoiding the formation of a gap in the central area of ​​the first metal pillar 31 (refer to S in Figure 1); that is, reducing the resistance of the metal connection hole.

[0048] It is understandable that different semiconductor devices respond differently to increasing the resistance of the metal contact hole 3. Typically, increasing the resistance of the metal contact hole 3 by approximately 50% improves device performance by approximately 5%. Especially for more advanced semiconductor devices, the resistance of the metal contact hole 3 is increasingly crucial to device performance. By employing the metal contact hole in the embodiments of the present application, the constraints imposed by the resistance of the metal contact hole on the device can be reduced.

[0049] The present application does not limit the conductive materials used for the first conductive pattern 1 and the second conductive pattern 2. For example, the first conductive pattern 1 and the second conductive pattern 2 can be made of conductive materials such as Co, Cu, and W. For example, in some possible implementations, the first conductive pattern 1 and the second conductive pattern 2 can be made of Co.

[0050] The present application does not limit the metal material used for the first metal pillar 31. For example, the first metal pillar 31 can be made of metal materials such as W, Cu, and Co. For example, in some possible implementations, the first metal pillar 31 can be made of W.

[0051] The present application does not limit the material used for the first bonding layer a1. For example, the material used for the first bonding layer a1 may include at least one of TiN, Ti, Ta, and TaN. For example, in some possible implementations, the first bonding layer a1 may be made of TiN.

[0052] Furthermore, this application does not limit the materials used for the first dielectric layer 11 and the second dielectric layer 12, nor the number of layers provided. For example, in some possible implementations, the first dielectric layer 11 can be a single dielectric layer. For another example, in some possible implementations, as shown in FIG3 , the first dielectric layer 11 can include two dielectric layers ( A1 and A2 ). Similarly, the second dielectric layer 12 can be a single dielectric layer or multiple dielectric layers.

[0053] In addition, the present application does not limit the insulating dielectric materials used in the first dielectric layer 11 and the second dielectric layer 12. For example, the first dielectric layer 11 and the second dielectric layer 12 can be made of oxide (such as SiO2), nitride (such as SiN), oxynitride (SiO y N x ) or other insulating dielectric materials. In some possible implementations, the first dielectric layer 11 includes two SiN layers (A1, A2), and the second dielectric layer 12 is a SiO2 layer. Of course, other film patterns may be provided between the two SiN layers (A1, A2) in the area outside the metal connection hole 3.

[0054] Furthermore, in some possible implementations, as shown in FIG4 , a recessed portion T may be provided on the surface of the first conductive pattern 1, with the edge of the recessed portion T located outside the wall of the metal connection hole 3. The bottom of the first metal pillar 31 extends into and fills the recessed portion T. In this case, the first metal pillar 31 forms a rivet structure at the bottom, thereby generating a "rivet effect," further reducing the probability of contact between the polishing agent and the first conductive pattern 1 during subsequent polishing of the surface of the second dielectric layer 12 (details will be described below).

[0055] In addition, the present application does not limit the electrical connection method between the first metal pillar 31 and the second conductive pattern 2 . The second conductive pattern 2 and the first metal pillar 31 can be directly connected or indirectly connected.

[0056] For example, in some possible implementations, as shown in FIG. 4 , the top of the first metal pillar 31 may be in direct contact with the second conductive pattern 2 to form an electrical connection.

[0057] For another example, in some possible implementations, as shown in FIG5 , the metal connection hole 3 may further include a second metal pillar 32, which is located on top of the first metal pillar 31. A second adhesive layer a2 is provided between the bottom of the second metal pillar 32 and the first metal pillar 31, and between the side of the second metal pillar 32 and the second dielectric layer 12; that is, the second adhesive layer a2 wraps around the side and bottom of the second metal pillar 32. In this case, the top of the second metal pillar 32 contacts the second conductive pattern 2, meaning that the second conductive pattern 2 is electrically connected to the first metal pillar 31 via the second metal pillar 32. Providing the second adhesive layer a2 on the bottom and side of the second metal pillar further reduces the probability of the polishing agent coming into contact with the first conductive pattern 1 during subsequent polishing of the surface of the second dielectric layer 12.

[0058] The material of the second bonding layer a2 can be the same as or different from that of the first bonding layer a1, and this application does not limit this. Schematically, the material of the second bonding layer a2 can be at least one of TiN, Ti, Ta, and TaN.

[0059] Regarding the fabrication of the second metal pillar 32, in some possible implementations, metal oxide chemical vapor deposition (MOCVD) can be used. It should be understood that because the second metal pillar 32 is located at the top of the entire metal connection hole 3, the probability of the top of the via being completely blocked during the deposition process is low, that is, the probability of a gap forming in the center of the second metal pillar 32 is low.

[0060] It should be noted that, in the case where the metal connection hole 3 includes both a first metal pillar 31 and a second metal pillar 32, in some embodiments, as shown in FIG5 , the first bonding layer a1 located on the side of the first metal pillar 31 extends upward to the side of the second metal pillar 32, that is, the first bonding layer a1 and the second bonding layer a2 are provided between the sidewall of the second metal pillar 32 and the second dielectric layer 12. The present application also provides a method for manufacturing a semiconductor device, as shown in FIG6 , which may include:

[0061] Step 01, referring to FIG. 7 , a first conductive pattern 1 is formed on a substrate 10 , and a first dielectric layer 11 and a second dielectric layer 12 are sequentially formed on the surface of the first conductive pattern 1 .

[0062] As shown, in some possible implementations, the substrate 10 may include a substrate and other structures disposed on the substrate. In step 01, a Co conductive pattern (1) is formed on the surface of the substrate 10. The Co conductive pattern (1) may serve as a source, drain, gate, etc. of a transistor. Then, a first dielectric layer 11, such as two SiN layers (A1, A2), is formed on the surface of the Co conductive pattern (1); and a second dielectric layer 12, such as a SiO2 layer, is formed on the surface of the first dielectric layer 11.

[0063] It should be understood that the first conductive pattern 1, the first dielectric layer 11, and the second dielectric layer 12 are not necessarily produced in sequence and continuously, but depend on the structure of the entire device. For example, other patterned film layers (located in the area outside the first conductive pattern 1) may be produced between the two SiN layers (A1, A2) in the first dielectric layer 11; similarly, other film layers may be produced between the first dielectric layer 11 and the second dielectric layer 12 in the area outside the first conductive pattern 1.

[0064] Step 02, referring to FIG. 8 , a first via hole V1 is formed in the second dielectric layer 12 at a position corresponding to the first conductive pattern 1, and a first adhesive layer a1 is formed on a sidewall of the first via hole V1.

[0065] Schematically, in some possible implementations, referring to FIG8 (a), in step 02, dry etching is first performed on the second dielectric layer 12 at a location corresponding to the first conductive pattern 1 to form a first via V1, and the etching stops on the first dielectric layer 11. In other words, the first dielectric layer 11 serves as a contact etch stop layer (CESL). Of course, after the etching of the first via V1 is completed, post-etching processing is required, such as wet cleaning and removal of etching byproducts. Then, referring to FIG8 (b) and (c), a first adhesive layer a1 is deposited on the surface of the second dielectric layer 12. The first adhesive layer a1 located at the bottom of the first via V1 and the upper surface of the second dielectric layer 12 is removed, leaving only the first adhesive layer a1 located on the sidewalls of the first via V1 to protect the sidewalls of the first via V1.

[0066] Step 03, referring to FIG. 9 , the first dielectric layer 11 is etched at a position corresponding to the first via hole V1 to form a second via hole V2 , and the first conductive pattern 1 is exposed.

[0067] 9 , in some possible implementations, in step 03, dry etching is performed on the first dielectric layer 11 at a location corresponding to the first via hole V1 to form a second via hole V2, that is, a via hole V' is formed that penetrates the first dielectric layer 11 and the second dielectric layer 12. Of course, after etching is completed, post-etching processing is required, such as wet cleaning and removal of etching byproducts.

[0068] Of course, in other possible implementations, as shown in FIG10 , when forming the second via V2 in step 03, the etching depth can be controlled to etch the surface of the first conductive pattern 1 to form a recess T, and the edge of the recess T is ensured to be located outside the wall of the second via V2. In this way, as shown in FIG4 , the bottom of the subsequently formed first metal pillar 31 can extend and fill the recess T to form a rivet structure, thereby producing a "rivet effect." For related explanations, please refer to the previous text and will not be repeated here.

[0069] Step 04 , referring to FIG. 11 , a selective deposition process is used to form a first metal pillar 31 on the surface of the leaked first conductive pattern 1 , and the first metal pillar 31 extends into the second dielectric layer 12 .

[0070] As shown, in some possible implementations, in step 04, a selective tungsten deposition process is used to grow W on the surface of the first conductive pattern 1 (e.g., a Co conductive pattern) located in the via hole V', thereby forming a first tungsten metal column (31). Before the selective tungsten deposition process is performed, the surface of the first conductive pattern 1 can be pre-treated, such as removing surface dangling bonds, to increase selectivity.

[0071] It can be understood here that based on the first bonding layer a1 formed in step 02, when the first tungsten metal column (31) is formed in step 04, the first bonding layer a1 can be filled between the first tungsten metal column (31) and the second dielectric layer 12. Since the growth rate of the metal on the bonding layer (such as TiN) is greater than the growth rate directly on the dielectric layer (such as SiO2), the bonding between the tungsten (W) and the sidewall can be increased by providing the first bonding layer a1. In this case, on the one hand, the process window is increased and the control difficulty of the process is reduced; on the other hand, the first bonding layer a1 can reduce the probability of a gap between the first tungsten metal column (31) and the second dielectric layer 12, reduce the loss of the first tungsten metal column (31) (i.e., tungsten loss) and the damage of the Co conductive pattern (1) (i.e., cobalt damage), thereby improving the reliability of the device.

[0072] Step 05 , referring to FIG. 3 , a second conductive pattern 2 electrically connected to the first metal pillar 31 is formed on the surface of the second dielectric layer 12 .

[0073] Schematically, in some possible implementations, as shown in FIG3 , after the first metal pillars 31 are formed in step 04, the surface of the second dielectric layer 12 is directly polished, such as by chemical mechanical polishing (CMP). Then, in step 05, a second conductive pattern 2 connected to the first metal pillars 31 is formed on the surface of the second dielectric layer 12. In this case, the metal connection holes 3 do not need to be formed using metal oxide chemical vapor deposition (MOCVD), thereby reducing process difficulty and cost.

[0074] Of course, as another possible implementation, as shown in FIG12(a), after the first metal pillar 31 is formed in step 04, a first via V1 of a certain depth is left unfilled above the first metal pillar 31. Then, as shown in FIG12(b), in step 05, a second bonding layer a2 is first deposited on the substrate surface where the first metal pillar 31 is formed, so as to cover the upper surface of the second dielectric layer 12, the top of the first metal pillar 31, and the sidewalls of the via with bonding material. Then, as shown in FIG12(c), a second metal pillar 32 is formed on the second bonding layer a2 and in the first via V1 using metal oxide chemical vapor deposition (MOCVD). In this case, the first bonding layer a1 and the second bonding layer a2 are disposed between the sidewalls of the second metal pillar 32 and the second dielectric layer 12. After the second metal pillars 32 are formed, depending on the actual needs of the semiconductor device, when the surface of the second dielectric layer 12 is polished, the second metal pillars 32 and the second adhesive layer a2 can be completely removed as a polishing sacrificial layer to expose the tops of the first metal pillars 31, and then the second conductive pattern 2 can be formed (see the structure of FIG3 ). Of course, as another possible implementation method, as shown in FIG13 , when the surface of the second dielectric layer 12 is polished, at least a portion of the second metal pillars 32 can be retained, and then the second conductive pattern 2 can be formed.

[0075] Regarding other relevant contents in the above-mentioned semiconductor device manufacturing method embodiment, reference can be made to the corresponding parts in the above-mentioned semiconductor device structure embodiment, and no further details will be given here. Regarding the relevant structures in the above-mentioned semiconductor device structure embodiment, reference can be made to the corresponding structures in the above-mentioned semiconductor device manufacturing method embodiment, or they can be made by combining relevant technologies with appropriate adjustments, and this application does not impose any restrictions on this.

[0076] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0077] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: a first conductive pattern disposed on the substrate; a second conductive pattern, the second conductive pattern being located on a side of the first conductive pattern away from the substrate; a first dielectric layer and a second dielectric layer, wherein the first dielectric layer and the second dielectric layer are located between the first conductive pattern and the second conductive pattern, and the first dielectric layer is closer to the first conductive pattern than the second dielectric layer; a metal connection hole, wherein the metal connection hole is provided in the first dielectric layer and the second dielectric layer, and the first conductive pattern and the second conductive pattern are electrically connected through the metal connection hole; The metal connection hole includes a first metal column, the bottom of which is in contact with the first conductive pattern; a first adhesive layer is provided between the first metal column and the second dielectric layer, and the first metal column is in contact with the first dielectric layer.

2. The semiconductor device according to claim 1, wherein A top portion of the first metal pillar contacts the second conductive pattern.

3. The semiconductor device according to claim 1, wherein The metal connection hole further includes a second metal column; The second metal column is located on the top of the first metal column, and a second bonding layer is provided between the second metal column and the top of the first metal column, and between the side of the second metal column and the second dielectric layer; the top of the second metal column contacts the second conductive pattern.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The surface of the first conductive pattern has a recessed portion, and the edge of the recessed portion is located outside the hole wall of the metal connection hole; The bottom of the first metal column extends into and fills the recess.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The material of the first bonding layer includes at least one of TiN, Ti, Ta or TaN.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: The material used for the first dielectric layer includes SiN; The material of the second dielectric layer includes SiO2.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The first metal column is manufactured by a selective deposition process.

8. The semiconductor device according to any one of claims 3 to 7, wherein: The second metal column is manufactured by using a metal oxide chemical vapor deposition process.

9. An electronic device, characterized in that: The invention comprises a printed circuit board and the semiconductor device according to any one of claims 1 to 8; the semiconductor device is electrically connected to the printed circuit board.

10. A method for manufacturing a semiconductor device, characterized in that: include: forming a first conductive pattern on a substrate; sequentially forming a first dielectric layer and a second dielectric layer on the surface of the first conductive pattern; forming a first via hole in the second dielectric layer at a position corresponding to the first conductive pattern, and forming a first adhesive layer on a sidewall of the first via hole; Etching the first dielectric layer at a position corresponding to the first via hole to form a second via hole, and exposing the first conductive pattern; Using a selective deposition process, forming a first metal pillar on the surface of the leaked first conductive pattern, and the first metal pillar extends into the second dielectric layer; A second conductive pattern electrically connected to the first metal pillar is formed on the surface of the second dielectric layer.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The step of forming a second conductive pattern electrically connected to the first metal pillar on the surface of the second dielectric layer includes: A second conductive pattern connected to the surface of the first metal pillar is formed on the surface of the second dielectric layer.

12. The method for manufacturing a semiconductor device according to claim 10, wherein: The step of forming a second conductive pattern electrically connected to the first metal pillar on the surface of the second dielectric layer includes: forming a second bonding layer on the surface of the substrate on which the first metal pillar is formed; forming a second metal pillar on the second bonding layer and in the first via hole by using a metal oxide chemical vapor deposition method; A second conductive pattern connected to the surface of the second metal pillar is formed on the surface of the second dielectric layer.

13. The method for manufacturing a semiconductor device according to any one of claims 10 to 12, wherein: The etching of the first dielectric layer at a position corresponding to the first via hole to form a second via hole and expose the first conductive pattern includes: The first dielectric layer is etched at a position corresponding to the first via hole to form a second via hole, and the surface of the first conductive pattern is etched to form a recessed portion; wherein the edge of the recessed portion is located outside the hole wall of the second via hole.

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