Test structure and gate parasitic capacitance calibration method

Abstract

The invention provides a test structure and a gate parasitic capacitance calibration method. The first test structure can calibrate a size and thickness table related to a first metal layer in an ITF document; the second test structure is an MOS structure, a contact hole of a source region and a drain region is removed, the second test structure with the same channel length, the same surrounding environment and different channel widths is designed, and the size and the thickness value of a grid electrode in an ITF document are calibrated through the second test structure; the third test structure is an MOS structure, metal connecting wires of source and drain regions are removed, a shallow doping source and drain region formed by a first conduction type lightly doped region is removed, a second conduction type lightly doped well region and a second conduction type heavily doped region body lead-out layer are replaced by the first conduction type lightly doped well region and a first conduction type heavily doped region body lead-out layer, and a second conduction type heavily doped region body lead-out layer is replaced by a second conduction type heavily doped well region and a second conduction type heavily doped region body lead-out layer; a table related to Cco and Cf capacitors in the ITF is calibrated according to the structure; the fourth test structure is an MOS structure, and the actual capacitance test result of the fourth test structure is compared with a post-simulation result, so that it is ensured that the grid parasitic capacitance conforms to model simulation.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a test structure and a calibration method for gate parasitic capacitance. Background Art

[0002] With the development of integrated circuit manufacturing, the feature size is getting smaller and smaller, the line width and spacing are getting smaller and smaller, and the delay of parasitic effects is becoming more and more obvious. The accuracy requirements for the input file ITF of the back-end parasitic capacitance and resistance extraction tools (such as StarRC) are also getting higher and higher. How to effectively design the layout to obtain test data to calibrate the ITF is particularly critical. In particular, the structure around the gate is complex, and the parasitic capacitance of the front-end metal interconnect structure is more complex than that of the back-end. The capacitance related to the gate includes the capacitance of the gate to the metal connection (Cgm), the capacitance of the gate to the contact hole (Cco), the capacitance of the gate to the source and drain region (Cf), and the internal capacitance of the device (including the channel capacitance, the capacitance of the shallowly doped source region or the shallowly doped drain region and the overlapping area of ​​the gate structure, and the junction capacitance). Among them, Cco and Cf affect each other and are not easy to separate. For example, when the spacing of the contact hole and the spacing between the contact hole and the gate change, Cco will be affected. At the same time, the surface area of ​​the source and drain region and the gate will also change accordingly, which will affect Cf; in addition, the internal capacitance of the device and the parasitic capacitance of Cco and Cf are not easy to separate.

[0003] There are many reports on the test structure of splitting Cco and Cf. Such reports measure the Cco+Cf capacitance when there are contact holes in the source and drain regions of the test structure, and measure the Cf capacitance when there are no contact holes in the source and drain regions, thereby splitting the Cco and Cf capacitances. However, such test methods do not consider the impact of the arrangement of contact holes on the Cf capacitance, and deviate from the actual results. Therefore, it is particularly important to use effective calibration methods to calibrate the parasitic parameters related to the gate parasitic capacitance and improve the accuracy of ITF. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a test structure and a gate parasitic capacitance calibration method, so as to solve the problem that parasitic parameters related to calibrating gate parasitic capacitance in the prior art deviate from actual results.

[0005] To achieve the above-mentioned and other related purposes, the present invention provides a test structure, comprising at least:

[0006] MOS structure, the MOS structure comprising: a silicon substrate, a second conductivity type lightly doped well region located on the silicon substrate, a first conductivity type heavily doped source and drain region, a shallow trench isolation region and a second conductivity type heavily doped body lead-out region sequentially spaced from each other in a shallow region located in the second conductivity type lightly doped well region; a gate located on the second conductivity type lightly doped well region between the first conductivity type heavily doped source and drain regions; a shallowly doped source and drain region composed of a first conductivity type lightly doped region located in the second conductivity type lightly doped well region on both sides of the gate and overlapping with the first conductivity type heavily doped source and drain region; contact holes connected to the first conductivity type heavily doped source and drain region and the second conductivity type heavily doped body lead-out region respectively; a first metal wire located on the contact hole;

[0007] The gate-related capacitance of the MOS structure includes parasitic capacitance and device internal capacitance Cin; the parasitic capacitance includes: capacitance Cf between the gate and the source and drain regions, capacitance Cco between the gate and the contact hole, and capacitance Cgm1 between the gate and the first metal line; the device internal capacitance Cin includes: channel capacitance Cgd between the gate and the well region, capacitance Cov of the shallowly doped source and drain regions respectively overlapping the gate structure, and junction capacitance between the heavily doped source and drain regions of the first conductivity type and the lightly doped well region of the second conductivity type;

[0008] The first test structure includes a plurality of same-layer capacitance test structures, an inter-layer capacitance test structure, and an inter-layer and same-layer test structure, wherein:

[0009] Each of the multiple same-layer capacitance test structures is composed of metal lines belonging to the same layer, and the metal lines have the same width and the spacing between adjacent metal lines is the same; the metal lines of the multiple same-layer capacitance test structures are different in width and the spacing between adjacent metal lines is different, the metal lines in the multiple same-layer capacitance test structures belong to different layers, and the same-layer capacitance test structures are used to measure the capacitance between metal lines in the same layer;

[0010] The interlayer capacitance test structure is composed of the same-layer capacitance test structures belonging to different layers, and is used to measure the capacitance between metal lines of different layers;

[0011] The inter-layer and same-layer test structure is composed of the same-layer capacitance test structure and the inter-layer capacitance test structure, and is used to measure the capacitance between metal wires in the same layer and the sum of the capacitance between metal wires in different layers;

[0012] A second test structure is formed by removing the contact hole from the MOS structure, and is used to measure the capacitance Cgm1 between the gate and the first metal line; the second test structure includes different test structures composed of the same channel length, the same surrounding environment and different channel widths, and is used to calculate the difference in capacitance Cgm1 between each other;

[0013] A third test structure is formed by removing the first metal line on the first conductive type heavily doped source and drain region, and removing the lightly doped source and drain region composed of the first conductive type lightly doped region, and replacing the second conductive type lightly doped well region and the second conductive type heavily doped body lead-out region with the first conductive type lightly doped well region and the first conductive type heavily doped body lead-out region in sequence; the third test structure includes different test structures composed of the same channel width, the same surrounding environment and different channel lengths, which are used to measure the difference in channel capacitance Cgd between each other; the third test structure also includes different test structures composed of different intervals between contact holes and different intervals between contact holes and gates;

[0014] A fourth test structure is formed by the MOS structure, and the fourth test structure includes different test structures composed of the same channel length, the same surrounding environment and different channel widths, and is used to measure the capacitance Cf between the gate and the source and drain region of the different test structures, the capacitance Cco between the gate and the contact hole, the capacitance Cgm1 between the gate and the first metal line, and the total difference Ctotal of the internal capacitance Cin of the device.

[0015] Preferably, the MOS structure is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type.

[0016] Preferably, the MOS structure is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0017] Preferably, the capacitance of the third test structure is the sum of the capacitance Cf between the gate and the source and drain regions, the capacitance Cco between the gate and the contact hole, and the channel capacitance Cgd between the gate and the well region.

[0018] The present invention also provides a parasitic capacitance calibration method, which at least comprises:

[0019] Step 1: Provide a first test structure, wherein the first test structure includes a plurality of same-layer capacitance test structures, an inter-layer capacitance test structure, and an inter-layer and same-layer test structure, wherein:

[0020] Each of the multiple same-layer capacitance test structures is composed of metal lines belonging to the same layer, and the metal lines have the same width and the spacing between adjacent metal lines is the same; while the metal lines of the multiple same-layer capacitance test structures have different widths and different spacing between adjacent metal lines, and the metal lines in the multiple same-layer capacitance test structures belong to different layers;

[0021] The interlayer capacitance test structure is composed of the same-layer capacitance test structures belonging to different layers;

[0022] The inter-layer and same-layer test structure is composed of the same-layer capacitance test structure and the inter-layer capacitance test structure;

[0023] The capacitance between metal wires in the same layer of the same-layer capacitance test structure, the capacitance between metal wires in different layers of the inter-layer capacitance test structure, the capacitance between metal wires in the same layer of the inter-layer same-layer test structure and the sum of the capacitance between metal wires in different layers are measured respectively; the measurement results of the capacitance and the sum of the capacitance are the actual capacitance value;

[0024] Respectively measure the actual width and thickness of the metal lines in the first test structure and the spacing between adjacent metal lines, and write the measured values ​​into an ITF file; the ITF file is an input file for a back-end parasitic capacitance and resistance extraction tool;

[0025] Compare the actual capacitance value with the respective simulation value, and adjust the values ​​in the ETCH table and the thickness table in the ITF file so that the simulation result is consistent with the actual measurement result;

[0026] Step 2, providing a MOS structure, the MOS structure comprising: a silicon substrate, a second conductivity type lightly doped well region located on the silicon substrate, a first conductivity type heavily doped source and drain region, a shallow trench isolation region and a second conductivity type heavily doped body lead-out region sequentially spaced from each other in a shallow region located in the second conductivity type lightly doped well region; a gate located on the second conductivity type lightly doped well region between the first conductivity type heavily doped source and drain regions; a shallowly doped source and drain region composed of the first conductivity type lightly doped region located in the second conductivity type lightly doped well region on both sides of the gate and overlapping with the first conductivity type heavily doped source and drain region; contact holes connected to the first conductivity type heavily doped source and drain region and the second conductivity type heavily doped body lead-out region respectively; a first metal wire located on the contact hole;

[0027] The gate-related capacitance of the MOS structure includes parasitic capacitance and device internal capacitance Cin; the parasitic capacitance includes: capacitance Cf between the gate and the source and drain regions, capacitance Cco between the gate and the contact hole, and capacitance Cgm1 between the gate and the first metal line; the device internal capacitance Cin includes: channel capacitance Cgd between the gate and the well region, capacitance Cov of the shallowly doped source and drain regions respectively overlapping the gate structure, and junction capacitance between the heavily doped source and drain regions of the first conductivity type and the lightly doped well region of the second conductivity type;

[0028] Providing a second test structure, wherein the second test structure is formed by removing the contact hole from the MOS structure; the second test structure comprises different test structures having the same channel length, the same surrounding environment and different channel widths, measuring the capacitance Cgm1 between the gate and the first metal line of the different test structures, and calculating the difference between the capacitances Cgm1;

[0029] Using the back-end parasitic capacitance and resistance extraction tool to simulate the capacitance Cgm1 between the gate and the first metal line of the different test structures, obtain a simulation value, and calculate the difference between the simulation value capacitance Cgm1 of the different test structures;

[0030] Compare the difference of the simulated capacitance Cgm with the difference of the capacitance Cgm1 between different test structures obtained by measurement, and adjust the size of the gate in the ITF file so that the simulation result is consistent with the actual measurement result;

[0031] Step 3, providing a third test structure, wherein the third test structure is formed by removing the first metal line on the first conductive type heavily doped source and drain region of the MOS structure, removing the lightly doped source and drain region composed of the first conductive type lightly doped region, and replacing the second conductive type lightly doped well region and the second conductive type heavily doped body lead-out region with the first conductive type lightly doped well region and the first conductive type heavily doped body lead-out region in sequence; the third test structure comprises different test structures composed of the same channel width, the same surrounding environment and different channel lengths, measuring the channel capacitance Cgd of the different test structures, and calculating the difference in capacitance Cgd between each other;

[0032] Using the back-end parasitic capacitance and resistance extraction tool to simulate the channel capacitance Cgd of the different test structures, obtain simulation values, and calculate the difference between the simulation value capacitance Cgd of the different test structures;

[0033] Compare the difference of the simulated capacitance Cgd with the difference of the capacitance Cgd between different test structures obtained by measurement, and adjust the size of the gate in the ITF file so that the simulation result is consistent with the actual measurement result;

[0034] The third test structure also includes different test structures formed by different intervals between contact holes and different intervals between contact holes and gates; measuring the capacitance values ​​of the different test structures; determining the capacitance Cco related parameters in the ITF file, and then calibrating the capacitance Cf table in the ITF file according to the actually measured capacitance values;

[0035] Step 4, providing a fourth test structure, wherein the fourth test structure is formed by the MOS structure, and the fourth test structure includes different test structures composed of the same channel length, the same surrounding environment and different channel widths; measuring the capacitance Cf between the gate and the source and drain region, the capacitance Cco between the gate and the contact hole, the capacitance Cgm1 between the gate and the first metal line, and the internal capacitance Cin of the device of the different test structures, and calculating the total capacitance difference Ctotal;

[0036] The total capacitance difference Ctotal of the different test structures is simulated using the back-end parasitic capacitance and resistance extraction tool to obtain a simulation value, and the simulation value is compared with the actual measured value to adjust the Cf table in the ITF file.

[0037] Preferably, in step one, an electron transmission microscope is used to measure the width and spacing of the metal lines respectively, and WAT measures the capacitance between the metal lines in the same layer in the same-layer capacitance test structure, the capacitance between the metal lines in different layers in the inter-layer capacitance test structure, the capacitance between the metal lines in the same layer in the inter-layer same-layer test structure, and the sum of the capacitance between the metal lines in different layers.

[0038] Preferably, the back-end parasitic capacitance and resistance extraction tool in steps 1 to 4 is StarRC.

[0039] Preferably, in step 2, WAT is used to measure the capacitance Cgm1 between the gates of the different test structures and the first metal line respectively.

[0040] Preferably, in step three, WAT is used to measure the channel capacitances Cgd of the different test structures respectively.

[0041] Preferably, in step 4, WAT is used to measure the capacitance Cf between the gate and the source and drain regions, the capacitance Cco between the gate and the contact hole, the capacitance Cgm1 between the gate and the first metal line, and the internal capacitance Cin of the device of the different test structures respectively.

[0042] As described above, a test structure and a gate parasitic capacitance calibration method of the present invention have the following beneficial effects: the method of the present invention can calibrate the capacitance Cgm from the gate to the metal connection, the capacitance Cco from the gate to the contact hole, and the capacitance Cf from the gate to the source and drain region, respectively, while ensuring that the parasitic capacitance is consistent with the internal capacitance of the device involved in the model, which can effectively improve the accuracy of the parasitic capacitance extraction tool. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 Shown is a flow chart of a parasitic capacitance calibration method of the present invention;

[0044] Figure 2Shown is a schematic diagram of the cross-sectional structure of the MOS structure of the present invention;

[0045] Figure 3a It is a schematic top view of a same-layer capacitance test structure in a first test structure of the present invention;

[0046] Figure 3b It is a schematic top view of an interlayer capacitance test structure in a first test structure of the present invention;

[0047] Figure 3c It is a schematic top view of the inter-layer and same-layer capacitance test structure in the first test structure of the present invention;

[0048] Figure 4 Shown is a schematic cross-sectional structure diagram of a second test structure of the present invention;

[0049] Figure 5a It is a schematic diagram showing the layout of a test structure with a channel width of W1 in the second test structure of the present invention;

[0050] Figure 5b It is a schematic diagram showing the layout of a test structure with a channel width of W2 in the second test structure of the present invention;

[0051] Figure 5c Shown as the present invention Figure 5a The test structure and Figure 5b A schematic diagram of the layout corresponding to the capacitance difference of the test structure;

[0052] Figure 6 Shown is a schematic cross-sectional structure diagram of a third test structure of the present invention;

[0053] Figure 7a It is a schematic diagram showing the layout of a test structure with a channel length of L1 in the third test structure of the present invention;

[0054] Figure 7b A schematic diagram showing a layout of a test structure having a channel length of L2 in a third test structure of the present invention;

[0055] Figure 7c The test structure 7a of the present invention is shown and Figure 7b A schematic diagram of the layout corresponding to the capacitance difference of the test structure;

[0056] Figure 8 It is a schematic diagram showing the layout of different contact hole spacings and contact hole-gate spacings in the third test structure of the present invention;

[0057] Figure 9a A schematic diagram showing a layout of a structure of four contact holes in a fourth test structure of the present invention;

[0058] Figure 9bA schematic layout diagram showing a structure of two contact holes in a fourth test structure of the present invention;

[0059] Fig.9c The test structure 9a of the present invention is shown and Figure 9b Schematic diagram of the layout corresponding to the capacitance difference of the test structure. DETAILED DESCRIPTION

[0060] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0061] See also Figures 1 to 9c It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0062] The present invention provides a test structure, comprising at least:

[0063] MOS structure, such as Figure 2 As shown, Figure 2 The MOS structure of the present invention is shown as a schematic diagram of a longitudinal cross-section structure. The MOS structure includes: a silicon substrate 01, a second conductive type lightly doped well region 02 located on the silicon substrate 01, and a first conductive type heavily doped source and drain region 03 located in a shallow region of the second conductive type lightly doped well region 02 and spaced from each other in sequence. Figure 2 03 is used to mark the source region or drain region), a shallow trench isolation region 04 and a second conductivity type heavily doped body lead-out region 05; a gate 06 located on the second conductivity type lightly doped well region 02 between the first conductivity type heavily doped source and drain regions (between the source region and the drain region); a shallowly doped source and drain region 09 composed of a first conductivity type lightly doped region located in the second conductivity type lightly doped well region 02 on both sides of the gate 06 and overlapping with the first conductivity type heavily doped source and drain region 03; a contact hole 07 connected by the first conductivity type heavily doped source and drain region 03 and the second conductivity type heavily doped body lead-out region 05 respectively; a first metal wire 08 (i.e., a first layer of metal wire) located on the contact hole 07;

[0064] The gate-related capacitance of the MOS structure includes parasitic capacitance and device internal capacitance Cin; the parasitic capacitance includes: capacitance Cf between the gate and the source and drain regions, capacitance Cco between the gate and the contact hole, and capacitance Cgm1 between the gate and the first metal line; the device internal capacitance Cin includes: channel capacitance Cgd between the gate and the well region, capacitance Cov of the shallowly doped source and drain regions respectively overlapping the gate structure, and junction capacitance between the heavily doped source and drain regions of the first conductivity type and the lightly doped well region of the second conductivity type;

[0065] The first test structure includes a plurality of same-layer capacitance test structures, an inter-layer capacitance test structure, and an inter-layer and same-layer test structure, wherein:

[0066] Each of the multiple same-layer capacitance test structures is composed of metal lines belonging to the same layer, and the metal lines have the same width and the spacing between adjacent metal lines is the same; the metal lines of the multiple same-layer capacitance test structures are different in width and the spacing between adjacent metal lines is different, the metal lines in the multiple same-layer capacitance test structures belong to different layers, and the same-layer capacitance test structures are used to measure the capacitance between metal lines in the same layer;

[0067] The interlayer capacitance test structure is composed of the same-layer capacitance test structures belonging to different layers, and is used to measure the capacitance between metal lines of different layers;

[0068] The inter-layer and same-layer test structure is composed of the same-layer capacitance test structure and the inter-layer capacitance test structure, and is used to measure the capacitance between metal wires in the same layer and the sum of the capacitance between metal wires in different layers;

[0069] A second test structure is formed by removing the contact hole from the MOS structure, and is used to measure the capacitance Cgm1 between the gate and the first metal line; the second test structure includes different test structures composed of the same channel length, the same surrounding environment and different channel widths, and is used to calculate the difference in capacitance Cgm1 between each other;

[0070] A third test structure is formed by removing the first metal line on the first conductive type heavily doped source and drain region, and removing the lightly doped source and drain region composed of the first conductive type lightly doped region, and replacing the second conductive type lightly doped well region and the second conductive type heavily doped body lead-out region with the first conductive type lightly doped well region and the first conductive type heavily doped body lead-out region in sequence; the third test structure includes different test structures composed of the same channel width, the same surrounding environment and different channel lengths, which are used to measure the difference in channel capacitance Cgd between each other; the third test structure also includes different test structures composed of different intervals between contact holes and different intervals between contact holes and gates;

[0071] A fourth test structure is formed by the MOS structure, and the fourth test structure includes different test structures composed of the same channel length, the same surrounding environment and different channel widths, and is used to measure the capacitance Cf between the gate and the source and drain region of the different test structures, the capacitance Cco between the gate and the contact hole, the capacitance Cgm1 between the gate and the first metal line, and the total difference Ctotal of the internal capacitance Cin of the device.

[0072] Furthermore, in the present invention, the MOS structure is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type.

[0073] Furthermore, in the present invention, the MOS structure is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0074] In the present invention, the capacitance of the third test structure is the sum of the capacitance Cf between the gate and the source and drain regions, the capacitance Cco between the gate and the contact hole, and the channel capacitance Cgd between the gate and the well region.

[0075] The present invention also provides a parasitic capacitance calibration method, such as Figure 1 As shown, Figure 1 The flow chart of the parasitic capacitance calibration method of the present invention is shown, and the method at least includes:

[0076] Step 1: Provide a first test structure, wherein the first test structure includes a plurality of same-layer capacitance test structures, an inter-layer capacitance test structure, and an inter-layer and same-layer test structure, wherein:

[0077] Each of the multiple same-layer capacitance test structures is composed of metal lines belonging to the same layer, and the metal lines have the same width and the spacing between adjacent metal lines is the same; while the metal lines of the multiple same-layer capacitance test structures have different widths and different spacing between adjacent metal lines, and the metal lines in the multiple same-layer capacitance test structures belong to different layers;

[0078] The interlayer capacitance test structure is composed of the same-layer capacitance test structures belonging to different layers;

[0079] The inter-layer and same-layer test structure is composed of the same-layer capacitance test structure and the inter-layer capacitance test structure;

[0080] The capacitance between metal wires in the same layer of the same-layer capacitance test structure, the capacitance between metal wires in different layers of the inter-layer capacitance test structure, the capacitance between metal wires in the same layer of the inter-layer same-layer test structure and the sum of the capacitance between metal wires in different layers are measured respectively; the measurement results of the capacitance and the sum of the capacitance are the actual capacitance value;

[0081] Respectively measure the actual width and thickness of the metal lines in the first test structure and the spacing between adjacent metal lines, and write the measured values ​​into an ITF file; the ITF file is an input file for a back-end parasitic capacitance and resistance extraction tool;

[0082] Compare the actual capacitance value with the respective simulation value, and adjust the values ​​in the ETCH table and the thickness table in the ITF file so that the simulation result is consistent with the actual measurement result;

[0083] The present invention further measures the metal width and spacing respectively in step one by using an electron transmission microscope, and WAT measures the capacitance between metal wires in the same layer in the same-layer capacitance test structure, the capacitance between metal wires in different layers in the interlayer capacitance test structure, the capacitance between metal wires in the same layer in the interlayer same-layer test structure, and the sum of the capacitance between metal wires in different layers.

[0084] In the present invention, the back-end parasitic capacitance and resistance extraction tool in step 1 is StarRC.

[0085] Step 2, providing a MOS structure, the MOS structure comprising: a silicon substrate, a second conductivity type lightly doped well region located on the silicon substrate, a first conductivity type heavily doped source and drain region, a shallow trench isolation region and a second conductivity type heavily doped body lead-out region sequentially spaced from each other in a shallow region located in the second conductivity type lightly doped well region; a gate located on the second conductivity type lightly doped well region between the first conductivity type heavily doped source and drain regions; a shallowly doped source and drain region composed of the first conductivity type lightly doped region located in the second conductivity type lightly doped well region on both sides of the gate and overlapping with the first conductivity type heavily doped source and drain region; contact holes connected to the first conductivity type heavily doped source and drain region and the second conductivity type heavily doped body lead-out region respectively; a first metal wire located on the contact hole;

[0086] The gate-related capacitance of the MOS structure includes parasitic capacitance and device internal capacitance Cin; the parasitic capacitance includes: capacitance Cf between the gate and the source and drain regions, capacitance Cco between the gate and the contact hole, and capacitance Cgm1 between the gate and the first metal line; the device internal capacitance Cin includes: channel capacitance Cgd between the gate and the well region, capacitance Cov of the shallowly doped source and drain regions respectively overlapping the gate structure, and junction capacitance between the heavily doped source and drain regions of the first conductivity type and the lightly doped well region of the second conductivity type;

[0087] Providing a second test structure, wherein the second test structure is formed by removing the contact hole from the MOS structure; the second test structure comprises different test structures having the same channel length, the same surrounding environment and different channel widths, measuring the capacitance Cgm1 between the gate and the first metal line of the different test structures, and calculating the difference between the capacitances Cgm1;

[0088] Using the back-end parasitic capacitance and resistance extraction tool to simulate the capacitance Cgm1 between the gate and the first metal line of the different test structures, obtain a simulation value, and calculate the difference between the simulation value capacitance Cgm1 of the different test structures;

[0089] Compare the difference of the simulated capacitance Cgm1 with the difference of the capacitance Cgm1 between different test structures obtained by measurement, and adjust the size of the gate in the ITF file so that the simulation result is consistent with the actual measurement result;

[0090] In the present invention, further, in step 2, WAT is used to measure the capacitance Cgm1 between the gate and the first metal line of the different test structures respectively.

[0091] In the present invention, the back-end parasitic capacitance and resistance extraction tool in step 2 is StarRC.

[0092] Step 3, providing a third test structure, wherein the third test structure is formed by removing the first metal line on the first conductive type heavily doped source and drain region of the MOS structure, removing the lightly doped source and drain region composed of the first conductive type lightly doped region, and replacing the second conductive type lightly doped well region and the second conductive type heavily doped body lead-out region with the first conductive type lightly doped well region and the first conductive type heavily doped body lead-out region in sequence; the third test structure comprises different test structures composed of the same channel width, the same surrounding environment and different channel lengths, measuring the channel capacitance Cgd of the different test structures, and calculating the difference in capacitance Cgd between each other;

[0093] Using the back-end parasitic capacitance and resistance extraction tool to simulate the channel capacitance Cgd of the different test structures, obtain simulation values, and calculate the difference between the simulation value capacitance Cgd of the different test structures;

[0094] Compare the difference of the simulated capacitance Cgd with the difference of the capacitance Cgd between different test structures obtained by measurement, and adjust the size of the gate in the ITF file so that the simulation result is consistent with the actual measurement result;

[0095] The third test structure also includes different test structures formed by different intervals between contact holes and different intervals between contact holes and gates; measuring the capacitance values ​​of the different test structures; determining the capacitance Cco related parameters in the ITF file, and then calibrating the capacitance Cf table in the ITF file according to the actually measured capacitance values;

[0096] In the present invention, further, in step three, WAT is used to measure the channel capacitances Cgd of the different test structures respectively.

[0097] In the present invention, the back-end parasitic capacitance and resistance extraction tool in step three is StarRC.

[0098] Step 4, providing a fourth test structure, wherein the fourth test structure is formed by the MOS structure, and the fourth test structure includes different test structures composed of the same channel length, the same surrounding environment, and different channel widths; measuring the capacitance Cf between the gate and the source and drain region, the capacitance Cco between the gate and the contact hole, the capacitance Cgm between the gate and the first metal line, and the internal capacitance Cin of the device of the different test structures, and calculating the total capacitance difference Ctotal;

[0099] The total capacitance difference Ctotal of the different test structures is simulated using the back-end parasitic capacitance and resistance extraction tool to obtain a simulation value, and the simulation value is compared with the actual measured value to adjust the Cf table in the ITF file.

[0100] The present invention further uses WAT in step 4 to measure the capacitance Cf between the gate and the source and drain regions, the capacitance Cco between the gate and the contact hole, the capacitance Cgm1 between the gate and the first metal line, and the internal capacitance Cin of the device of the different test structures.

[0101] In the present invention, the back-end parasitic capacitance and resistance extraction tool in step 4 is StarRC.

[0102] Example

[0103] The present invention takes the calibration of 28HK gate parasitic capacitance as an example, uses virtuoso to draw different test layouts, uses synopsis parasitic capacitance extraction tool StarRC to extract parasitic capacitance, uses hspice to simulate parasitic capacitance and device internal capacitance, performs WAT test capacitance, and uses transmission electron microscopy (TEM) to measure size thickness and width.

[0104] Parameter Description:

[0105] AA: active area;

[0106] S / D: source-drain region;

[0107] Gate: gate;

[0108] Fgate: the portion of the gate in the passive region;

[0109] M1, M2, M3: the first layer metal wire (first metal wire), the second layer metal wire, and the third layer metal wire, respectively; V1: a through hole connecting M1 and M2;

[0110] V2: a through hole connecting M2 and M3;

[0111] CT: contact hole, through hole connecting the source and drain regions with M1; through hole connecting the gate with M1;

[0112] Cgm: capacitance between the gate and the metal connection;

[0113] Cgm1: capacitance between the gate and the first metal line;

[0114] Cco: parasitic capacitance between gate and contact hole;

[0115] Cf: parasitic capacitance between gate and source / drain;

[0116] Cgd: channel capacitance between gate and well region;

[0117] Cov: capacitance of the overlapping area between the shallowly doped source region or the shallowly doped drain region and the gate structure;

[0118] Cin: internal capacitance of the device, including Cgd, Cov and junction capacitance;

[0119] L1, L2: channel length;

[0120] W1, W2: channel width;

[0121] a and b: the length of the Gate above and below exceeding AA respectively;

[0122] c and d: the length of M1 above and below AA respectively;

[0123] e: Width of the lead line M1 in the source and drain regions;

[0124] f: the distance between Gate and AA edge;

[0125] g: Width of source / drain region lead line M2; Width of gate lead line M1;

[0126] i: the size of M1 enclosing CT, the size of M2 enclosing V1;

[0127] h: Size of AA wrapping CT.

[0128] The schematic diagram of the MOS structure in the embodiment of the present invention is as follows Figure 2 As shown, the metal interconnection lines above M2 are omitted. The MOS structure consists of a gate structure, a lightly doped source region and a lightly doped drain region composed of a first conductivity type lightly doped region, a first conductivity type heavily doped source region and a drain region, a second conductivity type lightly doped well region, a second conductivity type heavily doped region body lead layer, a contact hole (CT), and metal wiring.

[0129] (1) A lightly doped source region and a lightly doped drain region composed of the first conductive type lightly doped region are formed on both sides of the gate and extend to below the bottom of the gate, and a Cov capacitor is formed between this portion and the gate;

[0130] (2) The first conductive type heavily doped source and drain regions are formed on both sides of the gate and are wrapped in the second conductive type lightly doped well region, and there is a junction capacitance between the heavily doped source and drain regions of different conductive types and the lightly doped well region; a conductive channel is formed on the surface of the second conductive type lightly doped well region covered by the gate structure, and there is a channel capacitance Cgd between the gate and the lightly doped well region;

[0131] (3) There is a sidewall capacitance Cf between the gate structure and the heavily doped source and drain regions of the first conductivity type;

[0132] (4) There is a positive capacitance Cco between the gate structure and CT;

[0133] (5) There is a Cgm capacitor between the gate structure and the metal connection.

[0134] The capacitance associated with the gate structure shown is divided into parasitic capacitance and device internal capacitance. The parasitic capacitance includes: Cf, Cco, Cgm, and the device internal capacitance includes: Cgd, Cov, and junction capacitance.

[0135] The method of this embodiment is as follows:

[0136] Step 1: Design the first test structure, including:

[0137] 1. Design the same-layer capacitance test structure with different widths and spacings of the first metal layer (i.e., the first metal line) (e.g. Figure 3a As shown), interlayer capacitance test structure (as shown Figure 3b as shown), inter-layer and same-layer test structures (as shown Figure 3c and test the actual capacitance values ​​respectively.

[0138] (1) Same-layer capacitance test structure ( Figure 3a ) Test the side wall capacitance between M1 and M1. The actual width and thickness of M1 affect this part of the capacitance;

[0139] (2) Interlayer capacitance test structure ( Figure 3b) Test the capacitance between M1 and M2. The actual width of M1 affects this part of the capacitance.

[0140] (3) Same-layer + inter-layer test structure ( Figure 3c ) Test the side wall capacitance between M1 and M1 and the interlayer capacitance between M1 and M2. The actual width and thickness of M1 affect this part of the capacitance.

[0141] 2. TEM measures the actual width and thickness of the test structure and writes the following syntax into ITF:

[0142] (1) Table related to the size of the first metal layer in ITF: etch table

[0143]

[0144] (2) Table related to the thickness of the first metal layer in ITF: thickness table

[0145]

[0146] Note: S1 S2 S3 S4… and W1 W2 W3 W4… are the layout width and spacing of test structure 1 respectively; ETCHS1W1 is the width deviation value when the width is W1 and the spacing is S1 obtained according to TEM slices, and the meanings of ETCHS2W1ETCHS3W1 are the same as ETCHS1W1; THICKS1W1 is the thickness deviation value when the width is W1 and the spacing is S1 obtained according to TEM slices, and the meanings of THICKS2W1 THICKS3W1 are the same as THICKS1W1.

[0147] 3. Compare the StarRC simulation results of each test structure with the actual test results, and adjust the ETCH table (ETCHS1W1...) and thickness table (THICKS1W1...) in ITF to make the simulation results consistent with the actual test results.

[0148] This method calibrates the size and thickness tables of the first metal layer in the ITF instrument.

[0149] Step 2: Design test structure 2. Figure 2 The MOS structure removes the contact holes of the source and drain regions, such as Figure 4 As shown, Figure 4 It is a cross-sectional schematic diagram of the second test structure of the present invention; the A-end PAD is connected to zero potential, the B-end (Gate) PAD is pressurized and tested with current, the C-end (bulk) PAD has the same voltage as the Gate, and the measured capacitance is Cgm.

[0150] 1. Design test structure 2 with the same channel length, the same surrounding environment, and different channel widths, such as Figure 5a and Figure 5b , and test their capacitance values ​​Cgma and Cgmb respectively.

[0151] 2. The same surrounding environment refers to Figure 5a and Figure 5b The values ​​of parameters a, b, c, d, e, f, g, and i are the same, so that the capacitance from Fgate / Gate to M1 on STI and the metal layers above M1 in the two graphics are basically the same. Then Cgma-Cgmb can exclude the influence of this part of parasitic capacitance, and the capacitance is only related to the gate and M1, such as Figure 5c .

[0152] 3. Figure 5a and Figure 5b The layout channel length is the same as L1, and the channel width is different, namely W1 and W2. The corresponding lengths of M1 in the source and drain regions are W1 and W2 respectively. It can be obtained that the difference between Cgma and Cgmb is caused by the change in the area facing Gate and M1. That is, when the channel length is L1, the channel width is W1-W2, and the length of M1 is W1-W2, Cgm1=

[0153] Cgma-Cgmb.

[0154] 4. Figure 5a and Figure 5b The difference between the StarRC simulation results of the corresponding layout is compared with the difference Cgm1 of the actual capacitance test results. Because the parameters (size, thickness) related to the parasitic capacitance of M1 have been determined by the test structure 1, it is only necessary to adjust the size and thickness of the Gate in the ITF to make the simulation results consistent with the actual test results.

[0155] This method calibrates the size and thickness of the Gate.

[0156] Step 3: Design test structure 3. Figure 2 The metal connection of the source and drain regions is removed from the MOS structure, the lightly doped source region and the lightly doped drain region composed of the first conductive type lightly doped region are removed, and the second type lightly doped well region and the second type heavily doped region body lead-out layer are replaced with the first type lightly doped well region 10 and the first type heavily doped region body lead-out layer 11 to form a structure as shown in FIG. Figure 6 In the structure shown, the PAD connected to the B end (Gate) is pressurized and the current is tested, and the PAD connected to the C end (bulk) is connected to zero potential. The tested capacitance is C3a=Cf+Cco+Cgd.

[0157] 1. Design test structures with the same channel width, the same surrounding environment, and different channel lengths, such as Figure 7a and Figure 7b, and test their capacitance values ​​C3a1 and C3a2 respectively.

[0158] 2. The same surrounding environment refers to Figure 7a and Figure 7b The values ​​of parameters a, b, c, d, e, f, g, and i are the same, so that the capacitance from Gate to CT and the source and drain regions in the two graphs are basically the same. Then C3a2-C3a1 can exclude the influence of this part of parasitic capacitance, and the capacitance is only related to the gate and the first type lightly doped well region, such as Figure 7c .

[0159] 3. Figure 7a and Figure 7b The layout channel width is the same as W1, and the channel length is different as L1 and L2 respectively. It can be obtained that the difference between C3a2 and C3a1 is caused by the change of channel length, that is, when the channel width is W1 and the channel length is L2-L1, Cgd=

[0160] C3a2-C3a1.

[0161] 4. Figure 7a and Figure 7b Compare the difference between the StarRC simulation results of the corresponding layout and the difference Cgd of the actual capacitance test results. If they are consistent, the Gate size in ITF does not need to be adjusted; if they are inconsistent, the Gate size in ITF needs to be adjusted to make the simulation results consistent with the actual test results, and then readjust the Gate thickness in ITF to make Figure 5a and Figure 5b The difference between the StarRC simulation results of the corresponding layout is consistent with the difference Cgm1 of the actual capacitance test results.

[0162] 5. So far, the parameters related to Cgd in ITF have been determined. The following steps will confirm the parameters related to Cco and Cf respectively.

[0163] 6. Design different CT intervals: S(CT to CT) = Scc1 Scc2 Scc3 Scc4…, test structure three with different Gate and CT intervals: S(Gate to CT) = Sgc1 Sgc2 Sgc3 Sgc4…, such as Figure 8 As shown, and their actual capacitance values ​​are tested respectively.

[0164] 7.TEM measures the CT size offset of the test structure 3 at different CT spacings and different Gate and CT intervals, and writes them into the ITF table, thereby determining the Cco related parameters in the ITF.

[0165] Cco form:

[0166]

[0167] Note: Sgc1Scc1 is the offset of CT, and the actual CT size can be calculated from this value. Sgc1Scc2…have the same meaning as Sgc1Scc1.

[0168] 8. Set the table related to Cf and Gate and CT interval in ITF as shown below. Figure 8 The StarRC simulation results of each test structure are compared with the actual test results, and the Cf table is adjusted to make the simulation results consistent with the actual test results.

[0169] Cf form:

[0170] CF VS Gate to CT space

[0171] Gate to CT space{Scc1 Scc2 Scc3 Scc4…}

[0172] CF VS Gate to CT space{Cf1 Cf2 Cf3 Cf4…}

[0173] }

[0174] Note: Cf1 is the Cf capacitance value when the Gate to CT distance is Scc1. The meanings of Cf2, Cf3, Cf4, etc. are consistent with those of Cf1.

[0175] This method calibrates the Cco and Cf related tables in the ITF document respectively, so that the Cco and Cf capacitances simulated by StarRC are affected by the CT interval and the distance between Gate and CT, which is consistent with the actual situation.

[0176] Step 4: Test structure 4 is a MOS structure, such as Figure 2 As shown, the A-end (S / D) PAD is connected to zero potential, the B-end (Gate) PAD is pressurized and tested for current, the C-end (bulk) PAD is connected to zero potential, and the test capacitance is Ctotal=Cf+Cco+Cgm+Cin.

[0177] 1. Design test structures with the same channel length, the same surrounding environment, and different channel widths, such as Figure 9a and Figure 9b , and test the capacitance values ​​Ctotal1 and Ctotal2 respectively.

[0178] 2. The same surrounding environment refers to Figure 9a and Figure 9bThe values ​​of parameters a, b, c, d, e, f, g, h, i, j, and k are the same, so that the capacitance from Fgate / CT / M1 to AA / CT / M1 in the two figures is basically the same. Then Ctotal1-Ctotal2 can exclude the influence of this part of parasitic capacitance and only obtain the capacitance around the channel.

[0179] 3. Figure 9a and Figure 9b The layout channel length is the same as L1, and the channel width is different as W1 and W2. It can be obtained that the difference between Ctotal1 and Ctotal1 is caused by the change in channel width. Therefore, the capacitance Ctotal_1 = Ctotal1-Ctotal2 = Cf+Cco+Cgm1+Cin when the channel length is L1 and the channel width is W1-W2 can be calculated. The calculated capacitance value has nothing to do with the metal interconnects above M1, such as Fig.9c .

[0180] 4. Figure 9a and Figure 9b The structure is simulated by StarRC and hspice respectively, and the difference of the simulation results is compared with the actual test result Ctotal_1 to check whether they are consistent. If not, adjust the model or Cf table in ITF.

[0181] This approach ensures that the parasitic capacitances match the internal capacitances of the device involved in the model.

[0182] In summary, the method of the present invention can calibrate the capacitance Cgm from the gate to the metal connection, the capacitance Cco from the gate to the contact hole, and the capacitance Cf from the gate to the source and drain region, respectively, and at the same time ensure that the parasitic capacitance is consistent with the internal capacitance of the device involved in the model, which can effectively improve the accuracy of the parasitic capacitance extraction tool. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0183] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A test structure, characterized in that: At least: MOS structure, the MOS structure comprising: a silicon substrate, a second conductivity type lightly doped well region located on the silicon substrate, a first conductivity type heavily doped source and drain region, a shallow trench isolation region and a second conductivity type heavily doped body lead-out region sequentially spaced from each other in a shallow region located in the second conductivity type lightly doped well region; a gate located on the second conductivity type lightly doped well region between the first conductivity type heavily doped source and drain regions; a shallowly doped source and drain region composed of a first conductivity type lightly doped region located in the second conductivity type lightly doped well region on both sides of the gate and overlapping with the first conductivity type heavily doped source and drain region; contact holes connected to the first conductivity type heavily doped source and drain region and the second conductivity type heavily doped body lead-out region respectively; a first metal wire located on the contact hole; The gate-related capacitance of the MOS structure includes parasitic capacitance and device internal capacitance Cin; the parasitic capacitance includes: capacitance Cf between the gate and the source and drain regions, capacitance Cco between the gate and the contact hole, and capacitance Cgm1 between the gate and the first metal line; the device internal capacitance Cin includes: channel capacitance Cgd between the gate and the well region, capacitance Cov of the shallowly doped source and drain regions respectively overlapping the gate structure, and junction capacitance between the heavily doped source and drain regions of the first conductivity type and the lightly doped well region of the second conductivity type; The first test structure includes a plurality of same-layer capacitance test structures, an inter-layer capacitance test structure, and an inter-layer and same-layer test structure, wherein: Each of the multiple same-layer capacitance test structures is composed of metal lines belonging to the same layer, and the metal lines have the same width and the spacing between adjacent metal lines is the same; the metal lines of the multiple same-layer capacitance test structures are different in width and the spacing between adjacent metal lines is different, the metal lines in the multiple same-layer capacitance test structures belong to different layers, and the same-layer capacitance test structures are used to measure the capacitance between metal lines in the same layer; The interlayer capacitance test structure is composed of the same-layer capacitance test structures belonging to different layers, and is used to measure the capacitance between metal lines of different layers; The inter-layer and same-layer test structure is composed of the same-layer capacitance test structure and the inter-layer capacitance test structure, and is used to measure the capacitance between metal wires in the same layer and the sum of the capacitance between metal wires in different layers; A second test structure is formed by removing the contact hole from the MOS structure, and is used to measure the capacitance Cgm1 between the gate and the first metal line; the second test structure includes different test structures composed of the same channel length, the same surrounding environment and different channel widths, and is used to calculate the difference in capacitance Cgm1 between each other; A third test structure is formed by removing the first metal line on the first conductive type heavily doped source and drain region, and removing the lightly doped source and drain region composed of the first conductive type lightly doped region, and replacing the second conductive type lightly doped well region and the second conductive type heavily doped body lead-out region with the first conductive type lightly doped well region and the first conductive type heavily doped body lead-out region in sequence; the third test structure includes different test structures composed of the same channel width, the same surrounding environment and different channel lengths, which are used to measure the difference in channel capacitance Cgd between each other; the third test structure also includes different test structures composed of different intervals between contact holes and different intervals between contact holes and gates; A fourth test structure is formed by the MOS structure, and the fourth test structure includes different test structures composed of the same channel length, the same surrounding environment and different channel widths, and is used to measure the capacitance Cf between the gate and the source and drain region of the different test structures, the capacitance Cco between the gate and the contact hole, the capacitance Cgm1 between the gate and the first metal line, and the total difference Ctotal of the internal capacitance Cin of the device.

2. The test structure according to claim 1, characterized in that: The MOS structure is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type.

3. The test structure according to claim 1, characterized in that: The MOS structure is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

4. The test structure according to claim 1, characterized in that: The capacitance of the third test structure is the sum of the capacitance Cf between the gate and the source and drain regions, the capacitance Cco between the gate and the contact hole, and the channel capacitance Cgd between the gate and the well region.

5. A parasitic capacitance calibration method, characterized in that: At least: Step 1: Provide a first test structure, wherein the first test structure includes a plurality of same-layer capacitance test structures, an inter-layer capacitance test structure, and an inter-layer and same-layer test structure, wherein: Each of the multiple same-layer capacitance test structures is composed of metal lines belonging to the same layer, and the metal lines have the same width and the spacing between adjacent metal lines is the same; while the metal lines of the multiple same-layer capacitance test structures have different widths and different spacing between adjacent metal lines, and the metal lines in the multiple same-layer capacitance test structures belong to different layers; The interlayer capacitance test structure is composed of the same-layer capacitance test structures belonging to different layers; The inter-layer and same-layer test structure is composed of the same-layer capacitance test structure and the inter-layer capacitance test structure; The capacitance between metal wires in the same layer of the same-layer capacitance test structure, the capacitance between metal wires in different layers of the inter-layer capacitance test structure, the capacitance between metal wires in the same layer of the inter-layer same-layer test structure and the sum of the capacitance between metal wires in different layers are measured respectively; the measurement results of the capacitance and the sum of the capacitance are the actual capacitance value; Respectively measure the actual width and thickness of the metal lines in the first test structure and the spacing between adjacent metal lines, and write the measured values ​​into an ITF file; the ITF file is an input file for a back-end parasitic capacitance and resistance extraction tool; Compare the actual capacitance value with the respective simulation value, and adjust the values ​​in the ETCH table and the thickness table in the ITF file so that the simulation result is consistent with the actual measurement result; Step 2, providing a MOS structure, the MOS structure comprising: a silicon substrate, a second conductivity type lightly doped well region located on the silicon substrate, a first conductivity type heavily doped source and drain region, a shallow trench isolation region and a second conductivity type heavily doped body lead-out region sequentially spaced from each other in a shallow region located in the second conductivity type lightly doped well region; a gate located on the second conductivity type lightly doped well region between the first conductivity type heavily doped source and drain regions; a shallowly doped source and drain region composed of the first conductivity type lightly doped region located in the second conductivity type lightly doped well region on both sides of the gate and overlapping with the first conductivity type heavily doped source and drain region; contact holes connected to the first conductivity type heavily doped source and drain region and the second conductivity type heavily doped body lead-out region respectively; a first metal wire located on the contact hole; The gate-related capacitance of the MOS structure includes parasitic capacitance and device internal capacitance Cin; the parasitic capacitance includes: capacitance Cf between the gate and the source and drain regions, capacitance Cco between the gate and the contact hole, and capacitance Cgm1 between the gate and the first metal line; the device internal capacitance Cin includes: channel capacitance Cgd between the gate and the well region, capacitance Cov of the shallowly doped source and drain regions respectively overlapping the gate structure, and junction capacitance between the heavily doped source and drain regions of the first conductivity type and the lightly doped well region of the second conductivity type; Providing a second test structure, wherein the second test structure is formed by removing the contact hole from the MOS structure; the second test structure comprises different test structures having the same channel length, the same surrounding environment and different channel widths, measuring the capacitance Cgm1 between the gate and the first metal line of the different test structures, and calculating the difference between the capacitances Cgm1; Using the back-end parasitic capacitance and resistance extraction tool to simulate the capacitance Cgm between the gate and the first metal line of the different test structures, obtain a simulation value, and calculate the difference between the simulation value capacitance Cgm1 of the different test structures; Compare the difference of the simulated capacitance Cgm with the difference of the capacitance Cgm1 between different test structures obtained by measurement, and adjust the size of the gate in the ITF file so that the simulation result is consistent with the actual measurement result; Step 3, providing a third test structure, wherein the third test structure is formed by removing the first metal line on the first conductive type heavily doped source and drain region of the MOS structure, removing the lightly doped source and drain region composed of the first conductive type lightly doped region, and replacing the second conductive type lightly doped well region and the second conductive type heavily doped body lead-out region with the first conductive type lightly doped well region and the first conductive type heavily doped body lead-out region in sequence; the third test structure comprises different test structures composed of the same channel width, the same surrounding environment and different channel lengths, measuring the channel capacitance Cgd of the different test structures, and calculating the difference in capacitance Cgd between each other; Using the back-end parasitic capacitance and resistance extraction tool to simulate the channel capacitance Cgd of the different test structures, obtain simulation values, and calculate the difference between the simulation value capacitance Cgd of the different test structures; Compare the difference of the simulated capacitance Cgd with the difference of the capacitance Cgd between different test structures obtained by measurement, and adjust the size of the gate in the ITF file so that the simulation result is consistent with the actual measurement result; The third test structure also includes different test structures formed by different intervals between contact holes and different intervals between contact holes and gates; measuring the capacitance values ​​of the different test structures; determining the capacitance Cco related parameters in the ITF file, and then calibrating the capacitance Cf table in the ITF file according to the actually measured capacitance values; Step 4, providing a fourth test structure, wherein the fourth test structure is formed by the MOS structure, and the fourth test structure includes different test structures composed of the same channel length, the same surrounding environment and different channel widths; measuring the capacitance Cf between the gate and the source and drain region, the capacitance Cco between the gate and the contact hole, the capacitance Cgm1 between the gate and the first metal line, and the internal capacitance Cin of the device of the different test structures, and calculating the total capacitance difference Ctotal; The total capacitance difference Ctotal of the different test structures is simulated using the back-end parasitic capacitance and resistance extraction tool to obtain a simulation value, and the simulation value is compared with the actual measured value to adjust the Cf table in the ITF file.

6. The parasitic capacitance calibration method according to claim 5, characterized in that: In step 1, an electron transmission microscope is used to measure the width and spacing of the metal lines respectively, and WAT measures the capacitance between the metal lines in the same layer in the same-layer capacitance test structure, the capacitance between the metal lines in different layers in the inter-layer capacitance test structure, the capacitance between the metal lines in the same layer in the inter-layer same-layer test structure, and the sum of the capacitance between the metal lines in different layers.

7. The parasitic capacitance calibration method according to claim 5, characterized in that: The back-end parasitic capacitance and resistance extraction tool in steps 1 to 4 is StarRC.

8. The parasitic capacitance calibration method according to claim 5, characterized in that: In step 2, the capacitance Cgm1 between the gate and the first metal line of the different test structures is measured by using WAT.

9. The parasitic capacitance calibration method according to claim 5, characterized in that: In step three, WAT is used to measure the channel capacitances Cgd of the different test structures respectively.

10. The parasitic capacitance calibration method according to claim 5, characterized in that: In step 4, WAT is used to measure the capacitance Cf between the gate and the source and drain regions, the capacitance Cco between the gate and the contact hole, the capacitance Cgm1 between the gate and the first metal line, and the internal capacitance Cin of the device of the different test structures.

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