Accelerated degradation model of SiC MOSFET under alternating gate drive

Abstract

The invention discloses an accelerated degradation model of a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) under alternating gate drive, which takes gate negative bias voltage, junction temperature, multiple stresses of gate voltage rise time and switching times as inputs and threshold voltage variation as outputs, solves the problem of inaccurate threshold voltage drift prediction of the SiC MOSFET under alternating-current BTI (Bias Temperature Instability), and improves the prediction accuracy of the SiC MOSFET under alternating-current BTI. The method can be used for describing the SiC MOSFET threshold voltage degradation rule in the alternating gate drive mode. According to the invention, the change rule of key performance parameters in the long-term use process of the SiC MOSFET device can be reflected, and the method has important significance for accurately evaluating and optimizing and improving the use reliability of the device.

Description

Technical Field

[0001] The invention belongs to the field of reliability assessment, relates to an accelerated degradation model, and specifically relates to an accelerated degradation model of a SiC MOSFET under alternating gate drive. Background Art

[0002] As a representative of the new generation of semiconductor materials, SiC has a wider bandgap, better thermal conductivity and higher electron mobility than silicon (Si), which has prompted many power electronic devices, including MOSFET, to adopt SiC as a substitute for Si. However, the application potential of SiC MOSFET is hindered by serious reliability issues, mainly related to its gate oxide layer. The gate oxide layer exhibits a threshold voltage drift phenomenon under the long-term action of the gate bias voltage, which is called bias temperature instability (BTI). However, under typical application conditions such as switching power supplies and inverters, the gate drive of SiC MOSFET often exhibits positive and negative alternation rather than constant bias. Under this driving mode, the threshold voltage drift law of SiC MOSFET is fundamentally different from the classic BTI, which is called AC BTI. For this failure mechanism, the existing linear or superlinear degradation trajectory fitting models cannot quantitatively describe the influence of accelerating factors such as temperature and bias voltage, which seriously restricts the effective reliability evaluation and life prediction of SiC MOSFET in most application scenarios. Summary of the invention

[0003] The purpose of the present invention is to provide an accelerated degradation model of SiC MOSFET under alternating gate drive, which takes into account the accelerated degradation model of SiC MOSFET threshold voltage under multiple stress coupling, such as gate negative bias voltage, junction temperature and gate voltage rise time. The threshold voltage degradation data is obtained through experiments, and the undetermined coefficients in the model are fitted based on these data, so as to improve the prediction accuracy and infer the degradation trajectory of the threshold voltage in multiple stress dimensions.

[0004] The objective of the present invention is achieved through the following technical solutions:

[0005] An accelerated degradation model of SiC MOSFET under alternating gate drive, with the gate negative bias voltage V n (V), junction temperature T(K) and gate voltage rise time t on (ns) Multiple stresses and switching times N cycle (times) as input, and the threshold voltage change ΔVth(V) as output, the model form is as follows:

[0006]

[0007] Among them, A, β, Ea, r and n are unknown coefficients. A is the unknown coefficient with normal distribution characteristics due to the dispersion of product degradation. k = 8.62905625 × 10 -5 eV / K is the Boltzmann constant.

[0008] In the present invention, the value of the undetermined coefficient is related to the specific specifications of the SiC MOSFET, and the specific determination steps are as follows:

[0009] Step 1: Obtain the threshold voltage degradation data of SiC MOSFET of the same specification under different stress combinations. The specific steps are as follows:

[0010] Step 1.1: Design a three-factor, multi-level experiment based on the chiral principle, where the three factors are V n , T, t on , select H levels for each factor, and get G experimental combinations, G = 3*H-2, H is not less than 3;

[0011] Step 1.2: Select n SiC MOSFETs of the same specification and perform accelerated degradation tests under these G test combinations to collect the threshold voltage data set V of SiC MOSFET under m equally spaced switching times. th1(i，j) ,V th2(i，j) ,...,V thG(i，j) , where i = 1, 2, ..., n, j = 1, 2, ..., m, n is not less than 10, m is not less than 10, and the sampling interval is ΔNcycle;

[0012] Step 2: Based on the SiC MOSFET accelerated degradation model and the threshold voltage data set obtained in step 1, the parameter values ​​of A, β, Ea, r, and n are obtained by least squares fitting.

[0013] Compared with the prior art, the present invention has the following advantages:

[0014] 1. The accelerated degradation model of the present invention takes multiple stresses including gate negative bias voltage, junction temperature, gate voltage rise time and switching times as inputs and threshold voltage change as output, which solves the problem of inaccurate threshold voltage drift prediction of SiC MOSFET under AC BTI and can be used to describe the threshold voltage degradation law of SiC MOSFET under alternating gate drive.

[0015] 2. The present invention can reflect the changing patterns of key performance parameters of SiC MOSFET devices during long-term use, which is of great significance for accurately evaluating, optimizing and improving the reliability of device use. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1This is the SiC MOSFET threshold voltage test flow chart;

[0017] Figure 2 It is the fitting curve of threshold voltage accelerated degradation data. DETAILED DESCRIPTION

[0018] The technical solution of the present invention is further described below in conjunction with the accompanying drawings, but is not limited thereto. Any modification or equivalent replacement of the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention should be included in the protection scope of the present invention.

[0019] This embodiment provides an accelerated degradation model of SiC MOSFET under alternating gate drive. Taking a certain specification of SiC MOSFET as an example, the accelerated degradation model is based on the gate negative bias voltage V n (V), junction temperature T(K) and gate voltage rise time t on (ns) Multiple stresses and switching times N cycle (times) as input, and the threshold voltage change ΔVth(V) as output, the model form is as follows:

[0020]

[0021] Among them, A, β, Ea, r and n are unknown coefficients, A is the unknown coefficient with normal distribution characteristics due to the dispersion of product degradation, k = 8.62905625×10 -5 eV / K is the Boltzmann constant.

[0022] The value of the coefficient to be determined is related to the specific specifications of SiC MOSFET, such as Figure 1 As shown, the specific determination steps are as follows:

[0023] Step 1: Obtain the threshold voltage degradation data of SiC MOSFET of the same specification under different stress combinations. The specific steps are as follows:

[0024] Step 1.1: Design a three-factor, three-level experiment based on the chiral principle, where the three factors are V n , T, t on , 3 levels are selected for each factor group, namely -5V, -8V, -10V; 298K, 348K, 393K; 100ns, 150ns, 200ns. 7 test combinations are established, and the detailed test combinations are shown in Table 1.

[0025] Table 1

[0026]

[0027] Step 1.2: Select 70 SiC MOSFETs of the same specification and conduct accelerated degradation tests under the seven test combinations. There are 10 SiC MOSFETs in each test combination. 10 The threshold voltage dataset under the switching times is 2.0*10. 9 .

[0028] Step 2: Based on the SiC MOSFET accelerated degradation model and the threshold voltage data set obtained in step 1, the parameter values ​​of A, β, Ea, r, and n are obtained by least squares fitting. The fitting curve is shown in Figure 2 The fitting results are shown in Table 2.

[0029] Table 2

[0030] Serial number parameter Parameter Value 1 A <![CDATA[A~N(2.702*10 -5 ,(2.106*10 -6 ) 2 )]]> 2 β 0.6853 3 Ea -0.02695 4 r -0.2861 5 n 0.3658

Claims

1. An accelerated degradation model of SiC MOSFET under alternating gate drive, characterized in that The model uses a negative gate bias voltage V n , junction temperature T and gate voltage rise time t on Multiple stresses and switching times N cycle As input, the threshold voltage change ΔVth is output, and its model form is as follows: Among them, A, β, Ea, r and n are unknown coefficients, and k is the Boltzmann constant.

2. The accelerated degradation model of SiC MOSFET under alternating gate drive according to claim 1, characterized in that The specific steps for determining the undetermined coefficients A, β, Ea, r and n are as follows: Step 1: Obtain threshold voltage degradation data of SiC MOSFET of the same specification under different stress combinations; Step 2: Based on the SiC MOSFET accelerated degradation model and the threshold voltage data set obtained in step 1, the parameter values ​​of A, β, Ea, r, and n are obtained by least squares fitting.

3. The accelerated degradation model of SiC MOSFET under variable gate drive according to claim 2, characterized in that The specific steps of step 1 are as follows: Step 1.1: Design a three-factor, multi-level experiment based on the chiral principle, where the three factors are V n , T, t on , select H levels for each factor and get G experimental combinations; Step 1.2: Select n SiC MOSFETs of the same specification and perform accelerated degradation tests under these G test combinations to collect the threshold voltage data set V of SiC MOSFET under m equally spaced switching times. th1(i，j) ,V th2(i，j) ,...,V thG(i，j) , where i = 1, 2, ..., n, j = 1, 2, ..., m, and the sampling interval is ΔNcycle.

4. The accelerated degradation model of SiC MOSFET under variable gate drive according to claim 3, characterized in that The H is not less than 3, G=3*H-2, n is not less than 10, and m is not less than 10.

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