Working mode switching method of system on chip, integrated circuit and electronic equipment

Abstract

The invention discloses a working mode switching method of a system on chip, an integrated circuit and electronic equipment, and relates to the technical field of chips. The method comprises the following steps: determining a current first working mode of the system on chip and a first number of memories in an enabled state in the first working mode; determining to switch the first working mode of the system on chip into a second working mode; based on the second working mode, determining a second number of memories needing to be started in the second working mode; controlling the working states of a plurality of memories in the system on chip on the basis of the second number of memories needing to be started, so that the second number of memories are all in a starting state; and in the second working mode, accessing the second number of memories through the bus of the system on chip. According to the technical scheme, different numbers of memories are started for different working modes, and the problems that power consumption is increased and system resources are wasted due to the fact that all the memories are normally used can be solved.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, and in particular to a method for switching working modes of a system on a chip, an integrated circuit, and an electronic device. Background Art

[0002] A multi-channel chip system is a SoC (System on Chip) that integrates multiple memory channels. In a multi-channel chip system, each memory channel can be connected to a memory to perform tasks such as memory management and data transfer.

[0003] In response to different business needs, the multi-channel chip system can adopt different working modes to achieve corresponding functions. Summary of the invention

[0004] For some working modes with low workload, only a few memories are needed to meet the load requirements. At this time, if all memories work normally, it will lead to increased power consumption and waste of system resources.

[0005] In order to solve the above technical problems, the present disclosure provides a method for switching the working mode of a system on chip, a system on chip and an electronic device. Different numbers of memories are used for different working modes to be implemented to avoid the problems of increased power consumption and waste of system resources caused by the normal use of all memories.

[0006] A first aspect of the present disclosure provides a method for switching an operating mode of a system on chip, including: determining a current first operating mode of the system on chip and a first number of memories that are enabled in the first operating mode; determining to switch the first operating mode of the system on chip to a second operating mode; based on the second operating mode, determining a second number of memories that need to be enabled in the second operating mode; based on the second number of memories that need to be enabled, controlling the operating states of multiple memories in the system on chip so that a second number of memories are all enabled; and in the second operating mode, accessing the second number of memories through a bus of the system on chip.

[0007] A second aspect of the present disclosure provides an integrated circuit, comprising: a bus, a plurality of memories connected to the bus, and a processor connected to the bus; the processor is used to execute the operating mode switching method of the system on chip provided in the first aspect above.

[0008] The third aspect of the present disclosure provides an electronic device, which includes the integrated circuit provided by the second aspect above; or, the electronic device includes: a processor; a memory for storing processor executable instructions; a processor, used to read executable instructions from the memory and execute the instructions to implement the working mode switching method of the on-chip system provided by the first aspect above.

[0009] A fourth aspect of the present disclosure provides a computer-readable storage medium storing a computer program for executing the operating mode switching method of the system on chip provided in the first aspect.

[0010] A fifth aspect of the present disclosure provides a computer program product. When instructions in the computer program product are executed by a processor, the operating mode switching method of the system on chip provided in the first aspect is executed.

[0011] Based on the operating mode switching method of the system on chip provided by the present disclosure, by determining the number of memories required to be enabled for each operating mode, it is possible to control the number of memories required for the second operating mode to be switched to be enabled. In this way, the number of memories in the enabled state is sufficient to support the smooth operation of the second operating mode. In addition, other memories are not in the enabled state, which can solve the energy waste problem caused by all memories of the current system on chip being enabled. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a structural diagram of an integrated circuit provided by an exemplary embodiment of the present disclosure.

[0013] Figure 2 is a structural diagram of an integrated circuit provided by another exemplary embodiment of the present disclosure.

[0014] Figure 3 It is a flowchart of a method for switching operating modes of a system on chip provided by an exemplary embodiment of the present disclosure.

[0015] Figure 4 It is a flowchart of a method for switching operating modes of a system on chip provided by another exemplary embodiment of the present disclosure.

[0016] Figure 5 It is a flowchart of a method for switching operating modes of a system on chip provided by another exemplary embodiment of the present disclosure.

[0017] Figure 6 It is a flowchart of a method for switching operating modes of a system on chip provided by another exemplary embodiment of the present disclosure.

[0018] Figure 7 It is a flowchart of a method for switching operating modes of a system on chip provided by another exemplary embodiment of the present disclosure.

[0019] Figure 8 It is a flowchart of a method for switching operating modes of a system on chip provided by another exemplary embodiment of the present disclosure.

[0020] Fig. 9It is a flowchart of a method for switching operating modes of a system on chip provided by another exemplary embodiment of the present disclosure.

[0021] Fig.10 is a structural diagram of an electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.

[0023] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0024] Application Overview

[0025] A system on a chip is an integrated circuit that integrates multiple electronic system components onto a single chip, thereby reducing system complexity and improving system performance. The system on a chip can have multiple memory channels, and the bus of the system on a chip is connected to the memory through the memory channel. Accessing the memory through multiple memory channels can effectively increase the bandwidth. For example, a system on a chip can have multiple double data rate (DDR) channels, each DDR channel can be connected to dynamic random access memory (DRAM), and the corresponding access operations on DRAM can be performed through the DDR channel to meet a variety of different application requirements.

[0026] In actual application scenarios, the SoC can use different working modes to meet different application requirements. For example, in a vehicle driving scenario, the SoC can use the intelligent driving mode to improve the user's driving experience, or use the sleep mode to reduce unnecessary energy consumption.

[0027] It is understandable that different working modes have different requirements for memory. For example, in the aforementioned intelligent driving mode, it is necessary to monitor obstacles around the vehicle in real time and perform obstacle avoidance planning based on the monitored obstacles. Therefore, the workload of the system on chip in the intelligent driving mode is large and the performance requirements are high, and more memory is required to realize the monitoring function; while in the aforementioned sleep mode, in order to reduce unnecessary energy consumption, some functions will be turned off. Therefore, in the sleep mode, the workload of the system on chip is small and the performance requirements are low, and only a small amount of memory is needed to realize the sleep function.

[0028] However, when the working mode is switched, the enabled state of the memory does not switch accordingly. For example, if the first number of memories are enabled in the aforementioned intelligent driving mode, after switching to the sleep mode, the aforementioned first number of memories are still in the enabled state. In this way, the number of memories in the enabled state is greater than the number of memories required for the sleep mode, which will lead to a waste of memory resources. That is, for some working modes that consume less resources, if all memories are enabled normally, it will lead to increased power consumption and waste of system resources.

[0029] In order to solve the above technical problems, an embodiment of the present disclosure provides a method for switching the working mode of a system on chip. By controlling the working status of each memory during the switching of the working mode of the system on chip, it can ensure that in each working mode, only the memory required for the working mode is enabled, so as to solve the problem of resource waste caused by enabling too many memories.

[0030] Exemplary Systems

[0031] Figure 1 is a structural diagram of an integrated circuit provided by an exemplary embodiment of the present disclosure.

[0032] The present disclosure provides an integrated circuit, such as Figure 1 As shown, the integrated circuit can be a system on chip (SoC), including a bus, multiple memories connected to the bus, and a processor connected to the bus. The processor can be a central processing unit (CPU) or a graphics processing unit (GPU). The present disclosure does not limit the type of processor. The processor in the present disclosure can be used to execute instructions and process data; the memory can be a DRAM or a synchronous dynamic random access memory (SDRAM), a graphics double data rate memory (GDDR), etc. The present disclosure does not limit the type of memory. The memory in the present disclosure is used to store data; the bus connects the processor and the memory, and can be used to transmit data and control signals between the processor and the memory. In addition, the integrated circuit can also include other modules, such as a hardware accelerator, a multi-function processor, etc. The following is combined with Figure 2 , the structure of the integrated circuit including other modules is introduced.

[0033] Figure 2 is a structural diagram of an integrated circuit provided by another exemplary embodiment of the present disclosure.

[0034] like Figure 2As shown, the integrated circuit can be a system on chip and can include a bus (BUS) for connecting various modules in the integrated circuit, such as a central processing unit, a hardware accelerator and a multi-function processor, a media device, a peripheral interface, etc. The bus is used to provide a communication path for each module in the integrated circuit.

[0035] The integrated circuit may also include a central processing unit (CPU) for executing instructions and processing data to complete computing tasks.

[0036] Integrated circuits may also include hardware accelerators (HW Accelerators) and multi-function processors. Among them, hardware accelerators are used to improve computing efficiency for specific types of computing tasks; multi-function processors can be various types of processors, such as GPUs, artificial intelligence (AI) accelerators, etc., which can be used to complete different types of computing tasks.

[0037] The integrated circuit may also include a media device (Media) interface for connecting to media devices such as storage devices, graphics cards, sound cards, etc.

[0038] The integrated circuit may also include a peripheral device (Peri) interface for connecting external devices such as input devices and output devices. The peripheral interface includes but is not limited to a peripheral component interconnect express (PCIe) interface, an Ethernet interface, a universal flash storage (UFS) interface, a universal serial bus (USB) 3.1 interface, a USB 2.0 interface, an inter-integrated circuit (I2C) interface, an inter-IC sound (I2S) interface, a universal asynchronous receiver / transmitter (UART) interface, and a serial peripheral interface (SPI) interface.

[0039] Integrated circuits can also include application-specific integrated circuits (AO) and safety island modules. AO refers to integrated circuits designed for specific applications or functions, which can be designed according to actual application scenarios; safety island modules refer to modules used to handle safety tasks, which can be used in the automotive, aviation and other fields.

[0040] The integrated circuit may also include N memory channels (such as DDR CH1 to DDR CHN), each memory channel is connected to a memory ( Figure 2 not shown).

[0041] Exemplary Methods

[0042] Figure 3 FIG. 1 is a flow chart of a method for switching the operating mode of a system on chip provided by an exemplary embodiment of the present disclosure. This embodiment can be applied to a processor of a system on chip, such as Figure 3 As shown, the following steps are included:

[0043] Step 31 , determining a current first operating mode of the system on chip and a first number of memories that are enabled in the first operating mode.

[0044] In this step, the current first working mode of the SoC refers to the current operating mode of the SoC. In actual application scenarios, the first working mode of the SoC corresponds to the current application field of the SoC and the currently implemented functions. For example, in the driving field, the first working mode of the SoC can be an intelligent driving mode, a sentinel mode, a locking mode, a sleep mode, etc.

[0045] Among them, the first working mode can be determined by reading the flag bit corresponding to the working mode, or by reading the mode switching log, etc., or by other methods, which is not limited in the present disclosure.

[0046] The system on chip includes a number of memories, and the memories can be in an enabled state or a disabled state, wherein the enabled state refers to a state in which a read operation can be performed normally, and can correspond to a variety of memory working modes, such as the memory in a standard read-write mode, a page mode, etc., which can all be regarded as the memory being in an enabled state; the disabled state refers to a state with low energy consumption, and can correspond to a variety of memory working modes, such as the memory in an idle mode, a sleep mode, a self-refresh mode, etc., which can all be regarded as the memory being in a disabled state, and the present disclosure does not limit this. (It should be noted that in the present disclosure, except for the "memory working mode", other "working modes" all refer to the "working mode of the system on chip".) In the current first working mode, a first number of memories are in an enabled state, and other memories are in a disabled state. At this time, the memory in the enabled state is determined so that the state of the memory can be controlled in subsequent steps.

[0047] Among them, the enabled state of the memory can be determined by reading the flag bit corresponding to the memory state in the memory state register, or by performing an access test on the memory, or by other methods, which is not limited in the present disclosure.

[0048] Step 32: determine to switch the first operating mode of the system on chip to the second operating mode.

[0049] In this step, the second working mode is the operating mode that the system on chip needs to switch to. Similar to the first working mode, the second working mode corresponds to the current application field of the system on chip and the functions to be implemented. For example, in the driving field, the second working mode of the system on chip can be a standby mode, an operating mode, a sleep mode, etc. Exemplarily, if it is determined that the current first working mode of the system on chip is the intelligent driving mode, and it is determined that the second working mode to be switched is the sleep mode, it can be determined that the intelligent driving mode of the system on chip is switched to the sleep mode.

[0050] In actual application scenarios, there are many different triggering methods for switching the working mode of the system on chip. Based on the signal corresponding to each triggering method, the second working mode that the system on chip needs to switch can be determined. For example, based on the manual triggering method, such as the user inputs the mode switching instruction on the central control screen of the vehicle, the system on chip receives the mode switching instruction, and can determine to switch the first working mode to the second working mode indicated by the mode switching instruction; for another example, based on the peripheral perception method, such as the sensor perceives that the driver and the passenger have both got off the car, the system on chip receives the sensor's perception result, determines that the second working mode is the locked mode, and determines to switch the first working mode to the second working mode, that is, to the locked mode; for another example, based on the internal triggering method of the system on chip, the system on chip can store a written program inside, and the switching of the working mode is triggered by the program. At this time, the program can be used to determine to switch the first working mode to the second working mode.

[0051] Step 33: Based on the second working mode, determine a second number of memories to be enabled in the second working mode.

[0052] In this step, since different working modes have different requirements for memory, it can be understood that the second number of memories to be enabled in the second working mode is different from that in the first working mode. Based on this, the second number of memories to be enabled in the second working mode is determined, and then in subsequent steps, the number of enabled memories is ensured to meet the requirements of the second working mode.

[0053] In actual application scenarios, considering that different working modes have different requirements for the number of memories, the main reason is that the workload of the system on chip in each working mode is different. Therefore, the second number of memories to be enabled can be determined according to the workload of the second working mode. Specifically, the required bandwidth and storage space can be determined according to the workload of the second working mode, and then the second number can be determined according to the required bandwidth and storage space.

[0054] It can be understood that the workload is positively correlated with the second number of memories to be enabled, and the greater the workload, the greater the second number. As mentioned above, it will be determined to switch the smart driving mode of the system on chip to the sleep mode. Since the workload in the sleep mode is less than that in the smart driving mode, the second number is less than the first number. It can be understood that this embodiment only takes the switching from the smart driving mode with a large workload to the sleep mode with a small workload as an example. In other embodiments, it is also possible to switch from the sleep mode with a small workload to the smart driving mode with a large workload. At this time, the second number of memories required to be enabled in the smart driving mode is greater than the first number of memories in the enabled state in the sleep mode.

[0055] In addition, in some embodiments, the system on chip is configured with a bus interleaving mode. At this time, whether each memory can be accessed depends on the bus interleaving mode, and the design and implementation of the bus interleaving mode need to follow certain rules and strategies. Therefore, the determination of the second number also needs to take into account the number of memory activations that can be achieved by the bus interleaving mode. For example, in some embodiments, only 4-channel interleaving mode and 8-channel interleaving mode are supported, that is, only 4 memories or 8 memories can be enabled, and if the second working mode needs to enable 6 memories, then the second number is determined to be 8 at this time to meet the constraints of the system on chip workload and the bus interleaving mode at the same time.

[0056] Step 34: Based on the second number of memories to be enabled, control the working states of the plurality of memories in the system on chip so that the second number of memories are all in an enabled state.

[0057] In this step, the working state of the memory in the system on chip is controlled to ensure that at least the second number of memories are in an enabled state to meet the requirements of the second working mode. Further, exactly the second number of memories can be enabled, while other memories are controlled to be disabled, so as to minimize resource consumption on the basis of meeting the requirements of the second working mode.

[0058] In addition, in some embodiments, after determining the second number of memories to be enabled, when configuring the bus interleaving mode, the second number of memories cannot be enabled exactly. For example, in some embodiments, the second number of memories to be enabled is 6, and the system on chip only supports 4-channel interleaving mode and 8-channel interleaving mode. In this case, the second number is 6, but the number of memories actually enabled is 8. In other words, in these embodiments, the bus interleaving mode is configured so that the number of memories enabled is greater than the second number.

[0059] Step 35 : in a second working mode, access a second number of memories through the bus of the system on chip.

[0060] In this step, when the second number of memories are enabled, the second number of memories are accessed, and the functions to be implemented in the second working mode are implemented by performing read and write operations on the memories. Specifically, the processor is connected to the memories through a bus and a memory channel. In the second working mode, the second number of memories can be accessed through the bus and the memory channel in sequence to implement memory access operations on the second number of memories.

[0061] The working mode switching method of the system on chip provided by the embodiment of the present disclosure controls different numbers of memories to be in an enabled state for different working modes, thereby avoiding the waste of resources caused by unnecessary memories always being in a normal enabled state. Specifically, the present disclosure determines the memories that are in an enabled state in the first working mode so as to control the memory state in subsequent steps. Thereafter, after determining to switch from the first working mode to the second working mode, the working state of the memories is adjusted to ensure that the number of enabled memories meets the second number required for the second working mode. In this way, when the second number of memories required for the second working mode is greater than the first number of memories enabled for the first working mode, it can be ensured that the second working mode can run smoothly, avoiding the inability of the second working mode to run due to only enabling the first number of memories. When the second number of memories required for the second working mode is less than the first number of memories enabled for the first working mode, it can be avoided that the first number of memories are all in an enabled state, resulting in a waste of memory resources.

[0062] Figure 4 It is a flowchart of a method for switching operating modes of a system on chip provided by another exemplary embodiment of the present disclosure.

[0063] like Figure 4 As shown in the above Figure 3 Based on the illustrated embodiment, step 34 may include the following steps:

[0064] Step 341, setting the working status of multiple memories in the system on chip to a disabled state.

[0065] In this step, in order to avoid waste of resources caused by redundant memories being in an enabled state, multiple memories in the system on chip can be set to a disabled state. The disabled state is a working state corresponding to the enabled state, and may include a variety of memory working modes with low energy consumption, such as idle mode, sleep mode, self-refresh mode, etc. In actual application scenarios, the working state of the memory can be set to a disabled state by setting the memory to a memory working mode with low energy consumption, such as an idle mode. This embodiment does not limit the specific method for setting the disabled state.

[0066] Step 342: Based on the second number of memories to be enabled, set the working states of the second number of memories to the enabled state.

[0067] In this step, after all the memories of the system on chip are set to the disabled state, in order to ensure that the second working mode can run smoothly, the second number of memories need to be enabled. In the actual application scenario, the second number of memories to be enabled can be determined first, and then the memories to be enabled can be controlled to exit the aforementioned memory working mode with lower energy consumption and enter the memory working mode such as the Noraml mode that efficiently performs various memory access operations.

[0068] The channel numbers of the memory channels connected to the second number of memories to be enabled may be continuous or discontinuous. For example, when four memories are enabled, the memory channels connected to the four memories may be continuous channels 1 to 4, or discontinuous channels 1, 2, 4, and 6, or channels with other numbers, as long as the enabled memories meet the workload requirements of the second mode.

[0069] The method for switching the working mode of the system on chip provided by the embodiment of the present disclosure can make the system on chip have exactly the second number of memories in the enabled state, while the other memories are in the disabled state, by first setting the multiple memories of the system on chip to the disabled state, and then setting the second number of memories to the enabled state. In this way, when the second number is greater than the first number, the requirement of enabling the second number of memories in the second working mode can be met, so that the second working mode can run smoothly; when the second number is less than the first number, it can avoid wasting resources caused by enabling redundant memories, so as to achieve the effect of saving memory and bandwidth resources.

[0070] Figure 5 It is a flowchart of a method for switching operating modes of a system on chip provided by another exemplary embodiment of the present disclosure.

[0071] like Figure 5 As shown in the above Figure 4 Based on the illustrated embodiment, step 341 may include the following steps:

[0072] Step 3411, setting multiple memories in the system on chip to a self-refresh mode.

[0073] In this step, multiple memories in the system on chip are set to a disabled state by setting them to a self-refresh mode. It can be understood that the self-refresh mode is a memory operation mode with low energy consumption. Setting the memory to the self-refresh mode can make it enter a disabled state with low energy consumption. In actual application, the memory can be controlled to enter the self-refresh state by sending a specific instruction to the memory through the bus.

[0074] Step 3412, determining a first number of first memory channels connected between a first number of memories in an enabled state and a bus of the system on chip.

[0075] In this step, based on each memory in an enabled state in the first working mode, a memory channel connected between the memory and the bus is determined, which is recorded as a first memory channel. It can be understood that since each memory is connected to the bus of the system on chip through a memory channel, a first number of first memory channels can be determined based on the first number of memories.

[0076] Step 3413: Determine a third number of second memory channels connected between a memory in a disabled state among the multiple memories and a bus of the system on chip.

[0077] In this step, based on each memory in the disabled state among the multiple memories, a memory channel connected between the memory and the bus is determined, which is recorded as a second memory channel. It can be understood that since each memory is connected to the bus of the system on chip through a memory channel, if a third number of memories are in the disabled state, a third number of second memory channels can be determined.

[0078] Step 3414, deactivate a first number of first memory channels and a third number of second memory channels.

[0079] In this step, since the first memory channels corresponding to the memory in the enabled state and the second memory channels corresponding to the memory in the disabled state have been determined based on the aforementioned steps 3413 and 3414, the deactivation operation can be performed on the determined first number of first memory channels and the third number of second memory channels. In this way, the memory channels connected to each memory can be in the disabled state.

[0080] The working mode switching method of the system on chip provided in the embodiment of the present disclosure realizes the deactivation of multiple memories to reduce resource consumption by setting multiple memories to self-refresh mode and deactivating the first memory channel and the second memory channel connected between the memory and the bus. Among them, since in the self-refresh mode, the memory uses an internal counter to regularly refresh the storage unit inside the memory to ensure that the data is not lost due to charge leakage, setting the memory to the self-refresh mode can avoid data loss in the memory. And, since in the self-refresh mode, most of the functional modules of the memory are turned off or enter a low-power state, therefore, setting the memory to the self-refresh mode can also effectively reduce the energy consumption of the memory. In addition, setting the memory channel to the disabled state reduces the energy consumption of the memory channel, which can further reduce the resource consumption of the system on chip.

[0081] Furthermore, in the aforementioned method, by disabling all memories connected to the system on chip and all memory channels corresponding to the memories and enabling the second number of memories, the second number of memories are enabled to meet the requirement for the number of memories in the second working mode. This method is not only applicable to the case where the first number of memories currently enabled is less than the second number of memories required to be enabled, but also to the case where the first number of memories currently enabled is greater than the second number of memories required to be enabled.

[0082] In the case where the first number of currently enabled memories is greater than the second number of memories that need to be enabled, in addition to the aforementioned method, the second number of memories can be enabled by disabling part of the memories of the system on chip and ensuring that the second number of memories are not disabled, so as to meet the requirement of the second working mode for the number of memories. Exemplarily, in the first working mode, a total of 8 memories are enabled, respectively recorded as memories No. 1 to No. 8, and the first number can be determined to be 8 at this time; if the second number of memories that need to be enabled in the second working mode is 6, memories No. 7 and No. 8 can be set to self-refresh mode, the first memory channels corresponding to memories No. 7 and No. 8 can be disabled, and memories No. 1 to No. 6 and their corresponding first memory channels (which can be recorded as second memory channels in the second working mode) can be kept enabled at all times. In this way, the requirement of enabling 6 memories in the second working mode can be met.

[0083] Figure 6 It is a flowchart of a method for switching operating modes of a system on chip provided by another exemplary embodiment of the present disclosure.

[0084] like Figure 6 As shown in the above Figure 4 Based on the embodiment shown, after step 341, the following steps may also be included:

[0085] Step 61, interrupting or stopping the first task executed by the system on chip in the first working mode.

[0086] In this step, it can be understood that the system on chip can execute corresponding tasks in each working mode to achieve the effect to be achieved by each working mode, so the first task executed in the first working mode is not applicable to the second working mode. Based on this, if it is determined that the working mode of the system on chip is switched from the first working mode to the second working mode, the first task can be interrupted, and the first task can be continued after the working mode of the system on chip is switched back to the first working mode. In addition, if it is determined that the working mode of the system on chip is switched from the first working mode to the second working mode, the first task can be directly stopped, and the first task can be restarted and executed after the working mode of the system on chip is switched back to the first working mode.

[0087] For example, the system on chip can perform tasks such as obstacle detection and obstacle avoidance planning in the aforementioned intelligent driving mode, but does not need to perform such tasks in the sleep mode. Based on this, if it is determined to switch from the intelligent driving mode to the sleep mode, the tasks such as obstacle detection and obstacle avoidance planning can be interrupted or stopped.

[0088] Step 62: disconnecting a first signal transmission channel of a bus used to connect a first external device to the system on chip.

[0089] In this step, considering that there are certain differences in the external devices that need to be connected to the system on chip in different working modes, that is, the external device connected in the first working mode is not suitable for the second working mode, therefore, if it is determined that the working mode of the system on chip is switched to the second working mode, the system on chip can be disconnected from the first external device currently connected to it. Specifically, the first signal transmission channel between the first external device and the bus of the system on chip can be disconnected by physically disconnecting the link. The first signal transmission channel between the first external device and the bus of the system on chip can also be disconnected by setting the peripheral interface corresponding to the first external device in the system on chip to a disabled state.

[0090] The working mode switching method of the system on chip provided by the embodiment of the present disclosure can release the system resources of the system on chip and improve the system performance by interrupting or stopping the first task in the working mode that is no longer needed. In addition, it can also avoid the tasks in the first working mode and the tasks in the second working mode from interfering with each other or causing resource conflicts, thereby improving the reliability of the system on chip. In addition, the working mode switching method of the system on chip provided by the embodiment of the present disclosure can reduce the energy consumption caused by the above-mentioned first external device and increase the service life of the first external device and its corresponding peripheral interface by disconnecting the first external device connected in the first working mode that is no longer needed. In addition, in the case of limited peripheral interfaces, disconnecting the first external device can also avoid problems such as resource conflicts caused by the need for the first external device and the second external device to be connected to the same peripheral interface.

[0091] Figure 7 It is a flowchart of a method for switching operating modes of a system on chip provided by another exemplary embodiment of the present disclosure.

[0092] like Figure 7 As shown in the above Figure 4 Based on the illustrated embodiment, step 342 may include the following steps:

[0093] Step 3421: Based on the second number of memories to be enabled, determine a second number of third memory channels connected between the second number of memories to be enabled and the bus of the system on chip.

[0094] In this step, based on the memory to be enabled in the second working mode, a memory channel connected between the memory and the bus is determined, which is recorded as a third memory channel. It can be understood that since each memory is connected to the bus of the system on chip through a memory channel, a second number of third memory channels can be determined based on the second number of memories to be enabled.

[0095] Step 3422, enable a second number of third memory channels.

[0096] In this step, since the third memory channels corresponding to the second number of memories to be enabled have all been determined based on the aforementioned step 3422, the enabling operation can be performed on the determined second number of third memory channels. In this way, the memory channels connected to the second number of memories to be enabled can all be in an enabled state, and then access paths can be provided for the memories to be enabled through the enabled second number of memory channels.

[0097] In a specific application scenario, the third memory channel can be enabled by configuring the bus interleaving mode. Specifically, the required bus interleaving mode can be enabled by software in the system on chip. For example, if the 4-channel interleaving mode is enabled, 4 default memory channels can be selected for interleaving and the 4 default memory channels can be enabled. At this time, 4 third memory channels are enabled.

[0098] It can be understood that in the bus interleaving mode, the system on chip can access data between the second number of third memory channels in an interleaved manner, so that the data in the memory connected thereto can be independently accessed through each third memory channel, thereby reducing the waiting time for data access, improving data access efficiency, and thus improving the performance of the system on chip.

[0099] Step 3423, setting a second number of memories to a non-self-refresh mode.

[0100] In this step, the second number of memories in the system on chip are set to a non-self-refresh mode to achieve setting the second number of memories to an enabled state. It can be understood that the non-self-refresh mode in the present disclosure does not only refer to a memory operation mode, but a memory operation mode corresponding to the self-refresh mode and capable of normal operation, such as the Normal mode.

[0101] The working mode switching method of the system on chip provided in the embodiment of the present disclosure can make the memory resources and the corresponding memory channel resources meet the requirements of the second working mode by enabling the third memory channel connected between the second number of memories and the bus, and setting the second number of memories to the self-refresh mode. Among them, in the non-self-refresh mode, the memory can work normally; when the third memory channel is enabled, the third memory channel can provide a data transmission path for the memory connected thereto. In this way, the second number of memories can be accessed through the second number of third memory channels to meet the requirement that the second working mode requires the second number of memories to work.

[0102] Furthermore, in the aforementioned method, when all memories of the system on chip and their corresponding memory channels are in a disabled state, the second number of memories and their corresponding memory channels can be enabled to meet the requirement of the second working mode for the number of memories. This method is applicable not only to the case where the first number of memories currently enabled is less than the second number of memories required to be enabled, but also to the case where the first number of memories currently enabled is greater than the second number of memories required to be enabled.

[0103] In the case where the first number of currently enabled memories is greater than the second number of memories to be enabled, if the aforementioned method of disabling part of the memories of the system-on-chip and ensuring that the second number of memories are not disabled is adopted, then in this step, it is only necessary to keep the second number of memories and their corresponding memory channels enabled, and there is no need to re-enable the second number of memories. As in the aforementioned embodiment, if only memories No. 7 and No. 8 are set to the self-refresh mode, the first memory channels corresponding to memories No. 7 and No. 8 are disabled, and the enabled state of memories No. 1 to No. 6 is maintained (that is, memories No. 1 to No. 6 are maintained in the non-self-refresh mode), then in this step, it is only necessary to continue to keep memories No. 1 to No. 6 in the non-self-refresh mode, and keep the second memory channels corresponding to memories No. 1 to No. 6 in the enabled state, and there is no need to readjust the enabled state of memories No. 1 to No. 6 and their corresponding memory channels.

[0104] Figure 8 It is a flowchart of a method for switching operating modes of a system on chip provided by another exemplary embodiment of the present disclosure.

[0105] like Figure 8 As shown in the above Figure 4 Based on the embodiment shown, after step 342, the following steps may also be included:

[0106] Step 81 : opening a second signal transmission channel between a second external device and a bus of the system on chip required in a second working mode.

[0107] In this step, the system on chip is connected to the second external device required for the second working mode, so as to utilize the second external device to realize the function to be realized by the second working mode. Specifically, a physical connection can be established between the second external device and the peripheral interface of the system on chip, such as connecting the I2S audio line of the audio device to the I2S interface of the system on chip to establish a physical connection between the audio device and the I2S interface of the system on chip. Further, in the case where the system on chip has established a physical connection with the second external device, the peripheral interface corresponding to the second external device can be set to an enabled state. For example, in the case where the audio device has been connected to the I2S interface via the I2S audio line, the I2S interface can be enabled by setting the control register corresponding to the I2S interface, thereby realizing the opening of the second signal transmission channel between the second external device and the bus of the system on chip.

[0108] Step 82: Execute a second task in a second working mode based on a second signal transmission channel.

[0109] In this step, as mentioned above, the system on chip can execute corresponding tasks in each working mode to achieve the effect to be achieved in each working mode. For example, based on the first working mode being the intelligent driving mode and the second working mode being the sleep mode, the first task can be an obstacle avoidance planning task, and the second task can be an anti-theft task. Therefore, after determining that the system on chip switches from the first working mode to the second working mode, the corresponding second task can also be executed. Specifically, the second signal transmission channel can be used to realize the interaction between the system on chip and the second external device, so as to utilize the second external device to execute the second task in the second working mode and achieve the effect to be achieved in the second working mode.

[0110] Exemplarily, the system on chip has the aforementioned I2S type peripheral interface, and can be connected to the audio device through the I2S interface. After the second signal transmission channel between the bus of the system on chip and the audio device is established in the aforementioned step 81, in the aforementioned sleep mode, when an illegal intrusion is detected, the second transmission channel can be used to perform the alarm task in the sleep mode using the audio device, and an alarm sound can be issued to inform the owner that the vehicle is currently at risk of being stolen.

[0111] The working mode switching method of the system on chip provided in the embodiment of the present disclosure connects the system on chip with the second external device required in the second working mode through the second signal transmission channel, so as to realize the interaction between the system on chip and the second external device. In this way, the system on chip can receive data or instructions from the second external device, and can also send data or instructions to the second external device. Based on this, the interaction between the system on chip and the second external device can be carried out through the second signal transmission channel between the system on chip and the second external device, and the second task can be performed to realize the effect to be realized in the second working mode.

[0112] Fig. 9 It is a flowchart of a method for switching operating modes of a system on chip provided by another exemplary embodiment of the present disclosure.

[0113] like Fig. 9 As shown in the above Figure 4 Based on the embodiment shown, before step 342, the following steps may also be included:

[0114] Step 91, shut down the clock signal source in the system on chip.

[0115] In this step, a clock signal source is provided in the system on chip for sending a clock signal. The present disclosure can stop the activities of other modules of the system on chip by shutting down the clock signal source, thereby preventing other modules from transmitting data through the bus during the bus reset process in the subsequent step 92, thereby preventing data loss or damage.

[0116] For example, in some embodiments, such as the application scenario where the aforementioned system on chip is installed in a vehicle, the clock signal source shutdown operation can be performed through a dedicated integrated circuit AO or a safety island. In other embodiments, the clock signal source shutdown operation can also be performed in other ways, which is not limited by the present disclosure.

[0117] Step 92, reset the bus of the system on chip.

[0118] In this step, a reset operation is performed on the bus of the system on chip. Specifically, a reset signal for resetting the bus may be first generated by the controller of the system on chip, so as to reset the bus using the reset signal. After the bus is reset to an initial state, a stop reset signal may be generated by the controller to complete the bus reset operation. After the bus of the system on chip is reset, each module in the system on chip is restored to an initial state, so that the system on chip can start to enter the second working mode and work normally in the second working mode.

[0119] Step 93, re-enable the clock signal source.

[0120] In this step, since the clock signal source is turned off in the aforementioned step 91, the clock signal source is re-enabled after the bus reset is completed so that the clock signal source can send clock signals to each module of the system on chip to ensure that each module operates under the same time reference.

[0121] The method for switching the working mode of the system on chip provided by the embodiment of the present disclosure can make each module in the system on chip in a consistent initial state through a bus reset operation, thereby ensuring the stability of the system on chip when entering the second working mode. In addition, by turning off the clock signal source before the bus reset and re-enabling the clock signal source after the bus reset, each module in the chip can be kept stationary during the bus reset process, thereby preventing the modules in the chip from transmitting data through the bus and affecting the bus reset.

[0122] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0123] Exemplary Electronic Devices

[0124] Fig.10 is a structural diagram of an electronic device provided by an exemplary embodiment of the present disclosure.

[0125] like Fig.10 As shown, the electronic device includes at least one processor 101 and a memory 102 .

[0126] The processor 101 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 100 to perform desired functions.

[0127] The memory 102 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 101 may execute one or more computer program instructions to implement the operating mode switching method and / or other desired functions of the system-on-chip of each embodiment of the present disclosure above.

[0128] In one example, the electronic device 100 may further include: an input device 103 and an output device 104 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0129] The input device 103 may also include, for example, a keyboard, a mouse, etc.

[0130] The output device 104 can output various information to the outside, and may include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto.

[0131] Of course, to simplify, Fig.10 Only some of the components related to the present disclosure in the electronic device 100 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device 100 may also include any other appropriate components.

[0132] In one embodiment, the electronic device 100 includes the electronic device described in the above “Exemplary System” section, and the processor of the electronic device can be used to execute the steps in the operating mode switching method of the system on chip of various embodiments of the present disclosure described in the above “Exemplary Method” section.

[0133] Exemplary computer program products and computer-readable storage media

[0134] In addition to the above-mentioned methods and devices, embodiments of the present disclosure may also provide a computer program product, including computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the operating mode switching method of the system on chip of various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section.

[0135] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0136] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the processor executes the steps in the operating mode switching method of the on-chip system of various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section.

[0137] Computer readable storage media can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium is, for example, but not limited to, a system, device or device including electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0138] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and cannot be considered as necessary for each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, rather than limitation, and the above details do not limit the present disclosure to being implemented by adopting the above specific details.

[0139] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present disclosure claims and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A method for switching an operating mode of a system on chip, the method comprising: Determining a current first operating mode of the system on chip and a first number of memories that are enabled in the first operating mode; Determining to switch the first operating mode of the system on chip to a second operating mode; Based on the second working mode, determining a second number of memories to be enabled in the second working mode; Based on the second number of memories to be enabled, controlling the working states of multiple memories in the system on chip so that the second number of memories are all in an enabled state; In the second working mode, the second number of memories are accessed through a bus of the system on chip.

2. The method according to claim 1, wherein: The controlling the working states of the plurality of memories in the system on chip based on the second number of memories to be enabled so that the second number of memories are all in an enabled state includes: Setting the working states of the multiple memories in the system on chip to a disabled state; Based on the second number of memories to be enabled, the working states of the second number of memories are set to an enabled state.

3. The method according to claim 2, wherein: The step of setting the working states of the plurality of memories in the system on chip to a disabled state comprises: Setting a plurality of memories in the system on chip to a self-refresh mode; determining the first number of first memory channels connected between the first number of memories in an enabled state and a bus of the system on chip; determining a third number of second memory channels connected between a memory in a disabled state among the plurality of memories and a bus of the system on chip; The first number of first memory channels and the third number of second memory channels are disabled.

4. The method according to claim 2, wherein: After the operating states of the plurality of memories in the system on chip are set to a disabled state, the method further includes: interrupting or stopping a first task executed by the system on chip in the first working mode; A first signal transmission channel of a bus used to connect a first external device to the system on chip is disconnected.

5. The method according to claim 2, wherein: Based on the second number of memories to be enabled, setting the working states of the second number of memories to an enabled state includes: Based on the second number of memories to be enabled, determining the second number of third memory channels connected between the second number of memories to be enabled and the bus of the system on chip; enabling said second number of third memory channels; The second number of memories are set to a non-self-refresh mode.

6. The method according to claim 2, wherein: Based on the second number of memories to be enabled, after setting the working states of the second number of memories to an enabled state, the method further includes: Opening a second signal transmission channel between a second external device and a bus of the system on chip required in the second working mode; Based on the second signal transmission channel, a second task in the second working mode is performed.

7. The method according to claim 2, before setting the working states of the second number of memories to an enabled state, the method further comprises: Turning off the clock signal source in the system on chip; resetting a bus of the system on chip; Re-enable the clock signal source.

8. An integrated circuit comprising: A bus, a plurality of memories connected to the bus, and a processor connected to the bus; The processor is used to execute the operating mode switching method of the system on chip according to any one of claims 1 to 7.

9. An electronic device, wherein: The electronic device comprises the integrated circuit of claim 8; or, The electronic device comprises a processor and a memory for storing executable instructions, wherein the processor is used to read the instructions from the memory and execute the instructions to implement the working mode switching method of the system on chip according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, wherein the computer program is used to execute the method for switching the operating mode of the system on chip according to any one of claims 1 to 7.

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