Graph neural network-based high-level comprehensive design quality analysis method and device

Abstract

The invention discloses a high-level comprehensive design quality analysis method and device based on a graph neural network, and relates to the technical field of high-level comprehensive design. Then, the potential of the graph neural network in processing classification and prediction tasks related to graph structure data is utilized, and the graph neural network is utilized to process to-be-analyzed high-level comprehensive design data; the related attribute prediction of the graph structure data can be completed in a millisecond-to-second level, so that the quality analysis can be efficiently performed on the high-level comprehensive design based on the graph neural network. Meanwhile, the graph embedded data are analyzed more reasonably by means of the graph network and the neural network, and a more accurate analysis result is obtained, so that quality analysis is accurately carried out on the high-level comprehensive design based on the graph neural network.

Description

Technical Field

[0001] The present invention relates to the technical field of high-level integrated design, and in particular to a high-level integrated design quality analysis method and device based on graph neural network. Background Art

[0002] In the process of modern hardware accelerator design, many design factors need to be weighed and considered. As the structure of domain-specific accelerators becomes increasingly complex and sophisticated, the design process of accelerators has become a systematic project with a large workload and a long turnaround time. The High-Level Synthesis (HLS) tool chain for FPGA accelerator design scenarios plays a vital role in FPGA accelerator design. It allows developers to use high-level languages ​​(such as C / C++ or OpenCL) to describe algorithms, and then automatically converts these high-level language descriptions into FPGA hardware description languages ​​(such as Verilog or VHDL), and finally generates a bitstream file that can run on FPGA. Therefore, high-level synthesis design effectively improves the abstraction level of the design, allowing designers to examine and weigh the design parameters of the microarchitecture from a relatively macro perspective and quickly implement the design iteration of the accelerator microstructure without being confined to the complex RTL-level microarchitecture implementation details. In this way, the problem is abstracted, and the design of the microarchitecture is transformed from complex RTL-level coding to the weighing and trial of different design instruction combinations.

[0003] Although the HLS tool has improved the level of abstraction of the entire design process, users often have to wait from tens of minutes to hours from the time the HLS design parameters are adjusted to the time the accurate design evaluation report is obtained from the Vivado synthesis tool. This situation becomes more serious in large HLS designs, which seriously affects the efficiency of hardware development and evaluation. Although the HLS back-end tool also generates a preliminary design quality report when generating RTL-level code, this report has a large error compared to the standard quality report obtained after the design is implemented. This is because modern EDA tools add many heuristic algorithms to optimize the circuits generated in the synthesis stage during the back-end implementation, which makes the HLS tool chain unable to accurately predict the impact of these optimization algorithms on the final design quality. It can be seen that the existing high-level synthesis design quality analysis methods have the problems of low efficiency and insufficient accuracy. Summary of the invention

[0004] The present invention provides a high-level integrated design quality analysis method and device based on graph neural network, which are used to solve the problems of low efficiency and insufficient accuracy of existing high-level integrated design quality analysis methods.

[0005] In order to solve the above technical problems, the first aspect of the present invention discloses a high-level integrated design quality analysis method based on a graph neural network, the method comprising: Encoding the original node features and the original edge features obtained from the high-level integrated design to be analyzed, mapping the original node features into numerical preprocessed node features, and mapping the original edge features into numerical preprocessed edge features; Performing multi-layer convolution processing on the pre-processed node features and the pre-processed edge features to obtain embeddings of all target nodes after the multi-layer convolution processing; Convert all the target node embeddings into target graph embeddings, where the target graph embeddings are used to describe the information in the corresponding target nodes through a graph structure; The target graph is input and embedded into a preset multi-layer perceptron, and a quality analysis result of the high-level integrated design to be analyzed output by the multi-layer perceptron is obtained.

[0006] The second aspect of the present invention discloses a high-level integrated design quality analysis device based on a graph neural network, the device comprising: A numerical encoder, used for encoding the original node features and the original edge features obtained from the high-level synthesis design to be analyzed, mapping the original node features into numerical preprocessed node features, and mapping the original edge features into numerical preprocessed edge features; A GNN encoder is used to perform multi-layer convolution processing on the pre-processed node features and the pre-processed edge features to obtain embeddings of all target nodes after the multi-layer convolution processing; A global pooler converts all the target node embeddings into a target graph embedding, where the target graph embedding is used to describe the information in the corresponding target node through a graph structure; The multi-layer perceptron is used to input the target graph and embed it into a preset multi-layer perceptron to obtain the quality analysis result of the high-level integrated design to be analyzed output by the multi-layer perceptron.

[0007] The third aspect of the present invention discloses another high-level integrated design quality analysis system based on graph neural network, the system comprising: A memory storing executable program code; a processor coupled to the memory; The processor calls the executable program code stored in the memory to execute the high-level integrated design quality analysis method based on graph neural network disclosed in the first aspect of the present invention.

[0008] The fourth aspect of the present invention discloses a computer storage medium, which stores computer instructions. When the computer instructions are called, they are used to execute the high-level integrated design quality analysis method based on graph neural network disclosed in the first aspect of the present invention.

[0009] Compared with the prior art, the present invention has the following beneficial effects: The embodiment of the present invention first performs a series of processing on the data obtained from the high-level integrated design to be analyzed, so as to obtain graph embedding data that can be used by the graph network neural network, and then utilizes the potential of the graph neural network in processing classification and prediction tasks related to graph structure data, and utilizes the graph neural network to process the data of the high-level integrated design to be analyzed, and can complete the prediction of related attributes of the graph structure data at the level of milliseconds to seconds, so as to efficiently perform quality analysis on the high-level integrated design based on the graph neural network. At the same time, with the help of the graph network neural network, the graph embedding data is analyzed more reasonably, and more accurate analysis results are obtained, so as to accurately perform quality analysis on the high-level integrated design based on the graph neural network. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 It is a structural schematic diagram of a high-level comprehensive design quality analysis device based on a graph neural network disclosed in an embodiment of the present invention; Figure 2 It is a structural schematic diagram of another high-level integrated design quality analysis device based on graph neural network disclosed in an embodiment of the present invention; Figure 3 It is a flow chart of a high-level integrated design quality analysis method based on a graph neural network disclosed in an embodiment of the present invention; Figure 4 Schematic diagram of the working process of the numerical encoder in the embodiment of the present invention; Figure 5 A schematic diagram of a backbone network structure and a set of variable parameters of a high-level integrated design quality analysis method based on a graph neural network disclosed in an embodiment of the present invention; Figure 6 An example diagram illustrating the necessity of introducing a skip knowledge network in an embodiment of the present invention; Figure 7 Schematic diagram of three knowledge aggregation methods of a jumping knowledge network according to an embodiment of the present invention; Figure 8An overall flow chart of converting HLS design into graph structure data according to an embodiment of the present invention; Fig. 9 It is a comparison diagram of prediction errors between the embodiment of the present invention and the comparative experiment; Fig.10 This is a comparison chart of the inference delay of three graph neural network predictors in an embodiment of the present invention and the HLS backend baseline; Fig.11 It is a structural schematic diagram of a high-level integrated design quality analysis system based on a graph neural network disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0012] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] The terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, device, product or end including a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units inherent to these processes, methods, products or ends.

[0014] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0015] The present invention discloses a high-level integrated design quality analysis method and device based on graph neural network. The main inventive concept is: encoding and convolution processing are performed on the original features obtained from the high-level integrated design to be analyzed, so as to obtain graph embedding data that can be used by the graph network neural network, and then the graph neural network is used to process the data of the high-level integrated design to be analyzed to obtain the high-level integrated design quality analysis results.

[0016] Embodiment 1 See also Figure 1 , Figure 1 Schematic diagram of a high-level integrated design quality analysis device based on a graph neural network disclosed in an embodiment of the present invention. Figure 1 The high-level integrated design quality analysis device based on graph neural network described above can be integrated in a cloud server or a local server, and the embodiment of the present invention does not limit this. Figure 1 As shown, the high-level integrated design quality analysis device based on graph neural network may include: The numerical encoder 101 is used to encode the original node features and the original edge features obtained from the hierarchical synthesis design to be analyzed, and map the original node features to numerical preprocessed node features and the original edge features to numerical preprocessed edge features; A GNN encoder 102, used to perform multi-layer convolution processing on the pre-processed node features and the pre-processed edge features to obtain embeddings of all target nodes after the multi-layer convolution processing; A global pooler 103 converts all target node embeddings into target graph embeddings, where the target graph embeddings are used to describe the information in the corresponding target nodes through a graph structure; The multi-layer perceptron 104 is used to input the target graph and embed it into a preset multi-layer perceptron to obtain the quality analysis result of the hierarchical integrated design to be analyzed output by the multi-layer perceptron.

[0017] The embodiment of the present invention first performs a series of processing on the data obtained from the high-level integrated design to be analyzed, so as to obtain graph embedding data that can be used by the graph network neural network (multi-layer perceptron), and then utilizes the potential of the graph neural network in processing classification and prediction tasks related to graph structure data, and uses the graph neural network to process the data of the high-level integrated design to be analyzed, and can complete the prediction of related attributes of the graph structure data at the level of milliseconds to seconds, so as to efficiently perform quality analysis on the high-level integrated design based on the graph neural network. At the same time, with the help of the graph network neural network, the graph embedding data is analyzed more reasonably, and more accurate analysis results are obtained, so as to accurately perform quality analysis on the high-level integrated design based on the graph neural network.

[0018] In an optional embodiment, if Figure 2 As shown, the numerical encoder 101 includes a counter 101a and a one-hot encoder group 101b, and the numerical encoder 101 encodes the original node features and the original edge features obtained from the hierarchical synthesis design to be analyzed, and maps the original node features to numerical preprocessed node features, and maps the original edge features to numerical preprocessed edge features. The specific method may include: The counter 101a counts all feature values ​​of the original node features and the original edge features obtained in the hierarchical synthesis design to be analyzed, and obtains all possible values ​​corresponding to each feature dimension; For each feature dimension, the one-hot encoder group 101b constructs a one-hot encoding corresponding to the feature dimension according to all possible values ​​corresponding to the feature dimension; The one-hot encoder group 101b maps the original node features into numerical preprocessed node features and the original edge features into numerical preprocessed edge features according to the original node features, the original edge features and the one-hot encoding corresponding to all feature dimensions.

[0019] It can be seen that this optional embodiment first statistically obtains all possible values ​​corresponding to each feature dimension, then uses one-hot encoding to construct the one-hot encoding corresponding to each feature dimension, and finally maps the original node features to numerical preprocessed node features, and maps the original edge features to numerical preprocessed edge features. This allows the original data of the high-level integrated design to be analyzed to be more efficiently converted into numerical features while retaining all features of the high-level integrated design to be analyzed to the greatest extent, which is beneficial to subsequent data processing and analysis operations.

[0020] In another optional embodiment, the specific method of the counter 101a counting all feature values ​​of the original node features and the original edge features obtained in the hierarchical synthesis design to be analyzed and obtaining all possible values ​​corresponding to each feature dimension may include: De-duplicate all feature values ​​of the original node features and original edge features obtained in the statistical hierarchical synthesis design to be analyzed in each feature dimension to obtain a set of non-repeated feature values ​​corresponding to all feature dimensions; A hash table without repeated elements is used to record the set of non-repeated feature values ​​corresponding to all feature dimensions, and all possible values ​​corresponding to each feature dimension are obtained.

[0021] It can be seen that this optional embodiment uses a hash table without repeated elements to record all possible values ​​corresponding to each feature dimension, thereby achieving more efficient feature value statistics and recording operations.

[0022] In yet another optional embodiment, Figure 2 As shown, the GNN encoder 102 may include a GNN convolution layer 1021, an activation function layer 1022, and a skip knowledge network layer 1023, and the GNN encoder 102 performs multi-layer convolution processing on the pre-processed node features and the pre-processed edge features, and a specific method of obtaining all target node embeddings after the multi-layer convolution processing may include: The GNN convolution layer 1021 performs multi-layer convolution processing on the preprocessed node features and the preprocessed edge features. For each layer of convolution processing, it may include: according to the preprocessed node features and the preprocessed edge features, aggregating and propagating the features between different neighboring nodes, and giving the graph convolution operator the ability to fit nonlinear boundaries through the activation function layer 1022 activation function, so as to obtain all intermediate node embeddings corresponding to the convolution processing of this layer; The skip knowledge network layer 1023 obtains the embedding of all target nodes after multi-layer convolution processing according to the embedding of all intermediate nodes corresponding to all layers of convolution processing.

[0023] It can be seen that this optional embodiment first aggregates and propagates features between different neighbor nodes, and then gives the graph convolution operator the ability to fit nonlinear boundaries through an activation function, thereby obtaining embeddings of all intermediate nodes corresponding to the convolution processing of this layer. After the convolution processing, the intermediate node embeddings obtain the main features of the high-level integrated design to be analyzed that can be used for quality analysis, and the intermediate node embeddings are also adapted to the nonlinear fitting of the graph convolution operator, thereby improving the accuracy of the quality analysis of the high-level integrated design.

[0024] In another optional embodiment, the skip knowledge network layer 1023 may include a maximum pooling aggregator 1023a, a splicing aggregator 1023b, and an attention weighted aggregator 1023c, and the skip knowledge network layer 1023 obtains the embedding of all target nodes after multi-layer convolution processing according to all intermediate node embeddings corresponding to all layers of convolution processing, which may include: The maximum pooling aggregator 1023a selects the target convolution process with the most significant features of the corresponding intermediate node embedding from all layers of convolution processes, and determines all the intermediate node embeddings corresponding to the target convolution process as all the target node embeddings after the multi-layer convolution process, or The splicing aggregator 1023b splices all the intermediate node embeddings corresponding to each layer of convolution processing to obtain the target node embedding after multi-layer convolution processing, or The attention weighted aggregator 1023c determines the attention scores of all intermediate node embeddings corresponding to each layer of convolution processing based on the embeddings of all intermediate nodes corresponding to all layers of convolution processing, and determines the weight of each layer of convolution processing based on the attention scores of all intermediate node embeddings corresponding to each layer of convolution processing; based on the weight of each layer of convolution processing and all intermediate node embeddings corresponding to each layer of convolution processing, the target node embedding after multi-layer convolution processing is obtained.

[0025] It can be seen that this optional embodiment proposes a method of allowing the predictor to capture the importance of node features extracted by convolutional layers of different depths by itself. Through three methods of obtaining the embedding of all target nodes after multi-layer convolution processing, the graph neural network can adaptively learn the importance of each layer output during the information aggregation process, and finally adopt the most valuable convolution layer output, thereby improving the robustness of the graph neural network to deep convolution.

[0026] In yet another optional embodiment, the specific manner in which the global pooler 103 converts all target node embeddings into target graph embeddings may include: Determine the node weight corresponding to each target node embedding according to the preset attention mechanism, and obtain the target graph embedding according to all target node embeddings and the node weight corresponding to each target node embedding, or All target nodes are input and embedded into a pre-trained LSTM model that is invariant to the permutation of set elements, and the final hidden state of the LSTM model is embedded as the target graph.

[0027] It can be seen that this optional embodiment adopts two different modes in the process of converting all target node embeddings into target graph embeddings, which can give higher importance to key nodes, thereby further improving the accuracy of the high-level integrated design quality analysis method.

[0028] In yet another optional embodiment, the original node features include a function number, a basic block number, a node type, a node text, a loop unrolling instruction, a pipelining instruction, and a loop slicing instruction; The original edge features include the start point of the edge, the end point of the edge, and the category of the edge.

[0029] The original node features and original edge features selected in this optional embodiment can retain the important features in the high-level integrated design to a great extent, thereby providing efficient data for a series of subsequent data processing steps.

[0030] Embodiment 2 See also Figure 3 , Figure 3 1 is a flow chart of a high-level integrated design quality analysis method based on a graph neural network disclosed in an embodiment of the present invention. Figure 3 The described high-level integrated design quality analysis method based on graph neural network can be applied to a high-level integrated design quality analysis device based on graph neural network, and the high-level integrated design quality analysis device based on graph neural network can be integrated in a cloud server or a local server, which is not limited in the embodiments of the present invention. Figure 3 As shown, the high-level synthesis design quality analysis method based on graph neural network can include the following operations: Step 101: Encode the original node features and original edge features obtained from the high-level integrated design to be analyzed, map the original node features into numerical preprocessed node features, and map the original edge features into numerical preprocessed edge features.

[0031] The original node features and original edge features obtained from the high-level integrated design to be analyzed are discrete in nature. In particular, the text information of the node contains string-type data. Such features cannot be directly used in subsequent neural network training and reasoning tasks. Therefore, it is necessary to convert the original features, map the original node features into numerical preprocessed node features, and map the original edge features into numerical preprocessed edge features, so as to provide reasonable and efficient data for subsequent neural network training and analysis tasks.

[0032] Step 102: Perform multi-layer convolution processing on the pre-processed node features and the pre-processed edge features to obtain embeddings of all target nodes after the multi-layer convolution processing.

[0033] In the embodiment of the present invention, the target node embedding is obtained by aggregating the features of the node itself and the features of its neighboring nodes through multi-layer convolution processing, thereby mapping the node to a low-dimensional vector space, and these vectors can capture the features and structural information of the node. Therefore, by performing multi-layer convolution processing on the pre-processed node features and pre-processed edge features, the final target node embedding containing local information and neighborhood information can be obtained, providing data support that meets the requirements for subsequent neural network training and analysis tasks.

[0034] Step 103: Convert all target node embeddings into target graph embeddings.

[0035] In an embodiment of the present invention, since the high-level integrated design quality analysis method based on graph neural network is essentially to perform attribute prediction on the entire graph, it is finally necessary to convert the obtained node embedding into a graph embedding, and the target graph embedding is used to describe the information in the corresponding target node through the graph structure.

[0036] Step 104: input the target graph and embed it into a preset multi-layer perceptron to obtain the quality analysis result of the high-level integrated design to be analyzed output by the multi-layer perceptron.

[0037] In an embodiment of the present invention, optionally, the target graph is embedded into a plurality of different multi-layer perceptrons to predict the usage and delay (in terms of the number of clock cycles) of LUT, FF, and DSP of a specific HLS design on a target platform, thereby obtaining a quality analysis result of the high-level synthesis design to be analyzed output by the multi-layer perceptron.

[0038] The embodiment of the present invention first performs a series of processing on the data obtained from the high-level integrated design to be analyzed, so as to obtain graph embedding data that can be used by the graph network neural network (multi-layer perceptron), and then utilizes the potential of the graph neural network in processing classification and prediction tasks related to graph structure data, and uses the graph neural network to process the data of the high-level integrated design to be analyzed, and can complete the prediction of related attributes of the graph structure data at the level of milliseconds to seconds, so as to efficiently perform quality analysis on the high-level integrated design based on the graph neural network. At the same time, with the help of the graph network neural network, the graph embedding data is analyzed more reasonably, and more accurate analysis results are obtained, so as to accurately perform quality analysis on the high-level integrated design based on the graph neural network.

[0039] In an optional embodiment, encoding the original node features and the original edge features obtained from the high-level synthesis design to be analyzed, mapping the original node features to numerical preprocessed node features, and mapping the original edge features to numerical preprocessed edge features may include: Count all feature values ​​of the original node features and original edge features obtained in the high-level integrated design to be analyzed, and obtain all possible values ​​corresponding to each feature dimension; For each feature dimension, construct the unique hot encoding corresponding to the feature dimension based on all possible values ​​corresponding to the feature dimension; According to the original node features, the original edge features and the unique hot encoding corresponding to all feature dimensions, the original node features are mapped to numerical preprocessed node features, and the original edge features are mapped to numerical preprocessed edge features.

[0040] This optional embodiment illustrates an example of Figure 4 As shown, Figure 4 The complete process of encoding the original features of graph data is demonstrated with a simple example. Assume that the high-level synthesis design to be analyzed corresponds to a very small graph consisting of only two nodes. Each node has two-dimensional features X and Y. The feature vector of node 1 is {1, A}, and the feature vector of node 2 is {2, B}. Therefore, in design 1, there are two features {1, 2} in feature dimension X, and two features {A, B} in feature dimension Y. The same is true for designs 2 to n. Count all feature values ​​in the original node features and original edge features obtained in the high-level synthesis design to be analyzed, and obtain all possible values ​​corresponding to each feature dimension. For example, all possible values ​​of feature X include 1, 2, and 3, and all possible values ​​of feature Y include A, B, and C.

[0041] These features will then be used to train one-hot encodings, where each one-hot encoding is dedicated to encoding a feature dimension, and one-hot encodings can be generated based on the total number of categories of features in that dimension. Figure 4 As shown in the one-hot encoder group in , you can use the OneHotEncoder interface in sklearn to create a one-hot encoder object, and use the fit method to make the encoder generate the corresponding one-hot encoding for each dimension. Finally, according to the original node features, original edge features and the unique hot encoding corresponding to all feature dimensions, the original node features are mapped to numerical preprocessed node features, and the original edge features are mapped to numerical preprocessed edge features. Optionally, taking node encoding as an example, the original design is input into the encoder group again to obtain the encoding of the original design in each feature dimension. Further optionally, in order to obtain a compact and unified representation, the scipy.sparse.hstack method is used here to stack all features of a node in columns, that is, all features of a point will be gathered in a row, thereby obtaining a complete encoding of the node features in the original graph structure data, such as Figure 4 The entire picture of Design 1 on the right is coded as shown.

[0042] It can be seen that this optional embodiment first statistically obtains all possible values ​​corresponding to each feature dimension, then uses one-hot encoding to construct the one-hot encoding corresponding to each feature dimension, and finally maps the original node features to numerical preprocessed node features, and maps the original edge features to numerical preprocessed edge features. This allows the original data of the high-level integrated design to be analyzed to be more efficiently converted into numerical features while retaining all features of the high-level integrated design to be analyzed to the greatest extent, which is beneficial to subsequent data processing and analysis operations.

[0043] In this optional embodiment, further optionally, counting all feature values ​​of the original node features and original edge features obtained in the high-level synthesis design to be analyzed to obtain all possible values ​​corresponding to each feature dimension may include: De-duplicate all feature values ​​of the original node features and original edge features obtained in the statistical analysis of the high-level integrated design in each feature dimension to obtain a set of non-repeated feature values ​​corresponding to all feature dimensions; A hash table without repeated elements is used to record the set of non-repeated feature values ​​corresponding to all feature dimensions, and all possible values ​​corresponding to each feature dimension are obtained.

[0044] This optional embodiment is illustrated as follows: the original features can be sent to a counter, the essence of which can be a hash table that records non-duplicate elements. Different feature values ​​on each feature dimension will be deduplicated and recorded, thereby obtaining all possible values ​​of each feature dimension in all designs.

[0045] This optional embodiment uses a hash table without repeated elements to record all possible values ​​corresponding to each feature dimension, thereby achieving more efficient feature value statistics and recording operations.

[0046] In another optional embodiment, performing multi-layer convolution processing on the pre-processed node features and the pre-processed edge features to obtain all target node embeddings after the multi-layer convolution processing may include: Perform multi-layer convolution processing on the preprocessed node features and preprocessed edge features. For each layer of convolution processing, it includes: aggregating and propagating the features between different neighboring nodes according to the preprocessed node features and preprocessed edge features, and giving the graph convolution operator the ability to fit nonlinear boundaries through the activation function, so as to obtain the embedding of all intermediate nodes corresponding to the convolution processing of this layer; According to all the intermediate node embeddings corresponding to all the layers of convolution processing, all the target node embeddings after multi-layer convolution processing are obtained.

[0047] In this optional embodiment, each layer of multi-layer convolution processing first uses a graph convolution operator to aggregate and propagate features between different neighboring nodes. After each layer of convolution processing extracts the features of a layer, it needs to pass through an activation function, which can give the graph convolution operator the ability to fit nonlinear boundaries. Optionally, the activation function can be an Elu activation function.

[0048] It can be seen that this optional embodiment first aggregates and propagates features between different neighbor nodes, and then gives the graph convolution operator the ability to fit nonlinear boundaries through an activation function, thereby obtaining embeddings of all intermediate nodes corresponding to the convolution processing of this layer. After the convolution processing, the intermediate node embeddings obtain the main features of the high-level integrated design to be analyzed that can be used for quality analysis, and the intermediate node embeddings are also adapted to the nonlinear fitting of the graph convolution operator, thereby improving the accuracy of the quality analysis of the high-level integrated design.

[0049] In this optional embodiment, further optional, such as Figure 5As shown, in order to cope with different high-level integrated design quality analysis scenarios of graph neural networks, such as the prediction scenarios of LUT, FF, and DSP usage and delay. In this optional embodiment, the GNN encoder is used to perform multi-layer convolution processing on the preprocessed node features and the preprocessed edge features to obtain the embedding of all target nodes after the multi-layer convolution processing, and the convolution processing is performed in the GNN convolution layer. Optionally, in the GNN encoder, the GNN convolution layer uses six representative graph convolution operator models: GCN, GAT, GraphSAGE, TransformerConv, DGCNN and TAG. The main difference between different graph convolution operations lies in how to aggregate and propagate features between different neighboring nodes.

[0050] (1) GCN (Graph Convolutional Network) is an early representative work of graph convolution operations. GCN statically describes and processes the aggregation and flow of information between nodes by obtaining deterministic information from the adjacency matrix and weight matrix of the graph. The network structure of GCN is simple and efficient, and it can well fit the operation of convolution operations on small and regular graph structure data. On the other hand, the relative importance between neighbor nodes is statically determined according to the connectivity information described by the adjacency matrix and degree matrix of the graph. This approach cannot well describe the importance of nodes in the entire graph in many cases. For example, in the design scenario of HLS, optimization instructions (UNROLL, PIPELINE, etc.) often greatly change the quality of the final design. Therefore, the importance of the icmp instruction node responsible for carrying the optimization instruction information will be very high. However, in the traditional GCN convolution operator, its relative importance will only be determined based on the connectivity of the icmp instruction node, which will undoubtedly greatly underestimate the importance of the icmp node and ultimately affect the accuracy of the prediction results. On the other hand, since the calculation process of the classic GCN operator depends on the static characteristics of the graph, the GCN model is considered to be a transductive model. This means that the topology of the graph structure data used in the training set and the test set of the classic GCN model should be consistent. For the problem scenario faced by this optional embodiment, the predictor should be able to have good generalization for the HLS design quality prediction abstracted into different graph structures, which requires the graph neural network to be an inductive model. Therefore, as a comparison benchmark for the GNN convolution operator, the present invention uses GCN as one of the graph convolution operators tested.

[0051] (2) GAT is the abbreviation of Graph Attention Network. Compared with the classic GCN model, the biggest feature of GAT is that it avoids relying on the static features of the graph to determine the importance of neighbor nodes during information transmission, and turns the importance between different nodes and their neighbors into learnable parameters. The expression of GAT completing a layer of convolution operation is as follows:

[0052] in is the feature representation of this layer, and It represents the characteristics of nodes i and j, N(i) is the set of neighbor nodes of node i, Represents the attention coefficient between node i and node j, which is related to the weight matrix are all learnable parameters. The emergence of GAT overcomes the drawback of the classic GCN statically determining the importance of neighbor nodes, allowing nodes to dynamically adjust the attention weights of neighbor nodes during training, thereby effectively improving the information aggregation ability of graph neural networks. Since GAT only needs to pay attention to the interconnection relationship between the local subgraph where the node and its neighbors are located during the information transmission process, it also has good prediction capabilities for graph structures with new topologies. Therefore, GAT is regarded as an inductive model, which meets the requirements of the present invention for predictors. Therefore, GAT is taken into consideration as an evaluation object.

[0053] (3) GraphSAGE improves the sampling and aggregation methods compared to the original GCN model. For a specific node Ni, GraphSAGE first extracts a certain number of samples from Ni's 1-K order neighbors, and then uses a set of aggregators to aggregate the features of each order of neighbors until the embedding of the last layer of the target node is generated. Therefore, GraphSAGE is essentially different from GCN and GAT. The latter two are specific ways to generate node embeddings, while GraphSAGE learns the specific method of generating node embeddings during training. Therefore, GraphSAGE can easily generate embeddings for new nodes, so GraphSAGE also has the advantages of an inductive model. Another advantage of GraphSAGE is that due to the introduction of neighbor sampling and aggregation methods, GraphSAGE can be more easily expanded to large-scale graphs than GCN, which is crucial for quality prediction of large HLS designs. Based on this consideration, GraphSAGE is also considered as an alternative model.

[0054] (4) TransformerConv introduces the multi-head self-attention mechanism into the message passing process of graph neural networks. The formula for TransformerConv to complete a layer of convolution operation is as follows:

[0055] Among them, similar to GAT, It is also a trainable parameter. Its formula is as follows:

[0056] Where W1, W2, and W3 are all trainable parameters, and d represents the number of hidden neurons in the multi-head attention. It is worth noting that TransformerConv takes into account the features on the edge when calculating the correlation coefficient between nodes i and j. , which is a significant improvement over the previously introduced models.

[0057] (5) DGCNN uses the nearest neighbor algorithm to organize the scattered points in the point cloud into local subgraphs, and then constructs edge features for the organized local subgraphs. The edge features focus on the local neighborhood features and global features of the nodes. Therefore, the graph convolution operator proposed by DGCNN is also called edge convolution (EdgeConv). The expression for DGCNN to complete a layer of convolution operation is as follows:

[0058] in, It represents the characteristics of the node itself, also called global features in DGCNN. represents the local characteristics of the neighbors relative to the central node. These two pieces of information describe the central position of node i and the influence of neighbor node j on the central node. Before further processing, these two pieces of information will be spliced ​​together and then sent to a multi-layer perceptron. , in order to continuously learn the optimal way of feature aggregation, the neighbor features learned in the end will be passed through the max operator to obtain the most representative features. DGCNN has achieved very good results in the feature extraction task of point cloud.

[0059] (6) TAG is the abbreviation of Topological Adaptive Graph Convolutional Network. As a simple variant model of GCN, it expands the perception range of local node features from the 1-nearest neighbor of the classic GCN model to the K-nearest neighbor, and trains independent filters for neighborhoods of different sizes. This makes the perception range of node features wider and more accurate when aggregating. The computational complexity of TAG is not much different from that of traditional GCN. It is a simple and efficient model. The expression of TAG completing a layer of convolution operation is as follows:

[0060] In the above formula, k represents the size of the perception range. Represents an independent filter corresponding to the range of k-nearest neighbors. The advantage of TAG is that the use of multi-scale filters can more flexibly capture the most valuable neighborhood information and has lower computational complexity. Note that for existing work and selected network models, the perception range of the GNN convolution operator is fixed. For complex HLS large designs abstracted into fine-grained, fixed receptive field sizes may not be able to capture the most valuable information in the neighborhood. In order to solve the above problem, this optional embodiment specifically uses the TAG model as a supplementary test model to determine the impact of multi-scale receptive fields on prediction accuracy.

[0061] In yet another optional embodiment, obtaining all target node embeddings after multi-layer convolution processing according to all intermediate node embeddings corresponding to all layers of convolution processing may include: Filter out the target convolution processing with the most significant features of the corresponding intermediate node embedding from all layers of convolution processing, and determine all the intermediate node embeddings corresponding to the target convolution processing as all the target node embeddings after the multi-layer convolution processing, or After concatenating all the intermediate node embeddings corresponding to each layer of convolution processing, we can obtain the target node embedding after multi-layer convolution processing, or According to the embedding of all intermediate nodes corresponding to all layers of convolution processing, the attention scores of all intermediate node embeddings corresponding to each layer of convolution processing are determined, and the weight of each layer of convolution processing is determined according to the attention scores of all intermediate node embeddings corresponding to each layer of convolution processing; according to the weight of each layer of convolution processing and the embedding of all intermediate nodes corresponding to each layer of convolution processing, the target node embedding after multi-layer convolution processing is obtained.

[0062] In addition to the selection of the GNN model and activation function used in the embodiment of the present invention, the number of layers of the GNN encoder will also affect the accuracy of the prediction to a certain extent. If the depth of the GNN encoder is too shallow, the nodes in the graph will lose the information of distant neighbors during the process of information transmission and aggregation, resulting in a decrease in the ability to extract features. However, the depth of the GNN encoder should not be too large, because the convolution action of each layer of the graph neural network in the message passing mechanism will enable the local node to perceive the features of the more distant first-level neighbors. If the number of layers of the GNN model is too deep, it will cause the "over-smoothing" problem, that is, the average features finally aggregated to each node will show a high degree of convergence. The essence of "over-smoothing" is that the noise signal caused by excessive information aggregation masks the originally important features. Therefore, for the scenario of HLS design quality analysis, the depth of the GNN encoder is also an object worth weighing. However, the appropriate depth of the GNN encoder varies greatly for different scenarios, so it is not a wise approach to blindly enumerate and test the depth of the GNN encoder. In fact, even for the same task scenario, the optimal convolution depth of different nodes is different. This situation becomes more prominent for the HLS design quality prediction scenario targeted by the embodiment of the present invention. A simple example is Figure 6 As shown, Figure 6 The Add instruction node will be implemented as an adder circuit under the action of the HLS compiler. The resource overhead of the adder is closely related to the bit width of the operand. Figure 6 The i32 data node with a distance of 1 from the Add instruction node indicates the relevant information of the operand, and this information can be obtained by performing one layer of graph convolution operation. However, multiple layers of convolution will aggregate information from more distant neighbors. For example, the second layer of convolution operation will record the information of the i32 data node, which indicates the address of the operand loaded from the memory. Therefore, the existence of this information is essentially a noise for the embedding of the Add node. As the number of convolution layers continues to increase, the noise will increase, which will lead to a significant decrease in the convergence speed and accuracy of the model. However, it is obviously an inappropriate solution to set the number of layers of the graph neural network to 1 so that the node only aggregates the information of 1-neighbors. Therefore, considering the versatility and generalization of the predictor, an embodiment of the present invention proposes a method for allowing the predictor to capture the importance of node features extracted by convolution layers of different depths. Optionally, a Jumping Knowledge Network (JKN) layer can be introduced, which allows the graph neural network to adaptively learn the importance of each layer output during the information aggregation process, and finally adopt the most valuable convolution layer output, which improves the robustness of the graph neural network to deep convolution.

[0063] This optional implementation is for example Figure 7As shown, Figure 7 A simple example of a skip knowledge network layer is shown, assuming that there are only two GNN convolutional layers and the features of the nodes consist of a single dimension. Figure 7 The squares in represent the node embeddings generated after the convolution operation. The skip knowledge network obtains the node embeddings "bypassed" from multiple convolutional layers, and completes the adaptation of the information obtained by each layer of convolution internally. There are three knowledge fusion methods for the skip knowledge network: max pooling, concatenation, and long short-term memory-based attention weighted sum (LSTM). The three aggregation methods will be taken into consideration as a variable parameter set for the JKN layer. The max pooling fusion method will find the most characteristic and significant one from the output of multiple layers of convolution as the final result, the concatenation fusion method will directly splice the results of multiple layers of convolution, and the LSTM fusion method will calculate a weighted sum based on the attention score as the fusion result of the features of each layer.

[0064] It can be seen that this optional embodiment proposes a method of allowing the predictor to capture the importance of node features extracted by convolutional layers of different depths by itself. Through three methods of obtaining the embedding of all target nodes after multi-layer convolution processing, the graph neural network can adaptively learn the importance of each layer output during the information aggregation process, and finally adopt the most valuable convolution layer output, thereby improving the robustness of the graph neural network to deep convolution.

[0065] In yet another optional embodiment, converting all target node embeddings into target graph embeddings may include: Determine the node weight corresponding to each target node embedding according to the preset attention mechanism, and obtain the target graph embedding according to all target node embeddings and the node weight corresponding to each target node embedding, or All target nodes are input and embedded into a pre-trained LSTM model that is invariant to the permutation of set elements, and the final hidden state of the LSTM model is embedded as the target graph.

[0066] In an embodiment of the present invention, after multi-layer convolution operations and aggregation of jump knowledge networks, each node will obtain a final embedding containing local information and neighborhood information. Since the HLS design quality analysis is essentially a full-graph attribute prediction, it is finally necessary to convert the obtained node embedding into a graph embedding. Optionally, this process can be completed using a global pooling layer. Taking into account the characteristics of the HLS design, this optional embodiment introduces an attention-based pooling mechanism, because the final quality of the entire HLS design will be asymmetrically affected by some key nodes, such as the icmp instruction node carrying optimization instruction-related information and some key operation nodes (such as add and mul). The importance of these nodes to the final prediction accuracy is significantly higher than that of other nodes, so the key nodes should be given a higher importance in the process of downsampling the node embedding to the whole graph embedding. Early classic pooling schemes (such as sum pooling, maximum pooling, and average pooling) lack a learning process for the importance of different nodes. On the one hand, the whole graph embedding obtained in this way will suppress a large amount of effective information, and on the other hand, it is easy to introduce too much noise, resulting in poor final prediction accuracy.

[0067] Specifically, in this optional embodiment, the global pooling layer designs two attention-based global pooling methods, GlobalAttention and Set2Set, as variable parameters.

[0068] The essence of GlobalAttention is to give each node participating in global pooling an independent attention score, that is, node weight. This makes the originally fixed weight become a trainable parameter. The expression of GlobalAttention to complete global pooling is as follows:

[0069] In the above formula represents the embedding of node i, and Represent two multi-layer perceptrons respectively. First, the embedding of the node will be sent to a multi-layer perceptron, and then the attention score of this node will be obtained through the softmax function. Then, the weighted sum is made with the transformed embedding of the node itself, and the embedding of the whole graph is obtained. The introduction of multi-layer perceptron makes the weight of the node a learnable parameter, which improves the perception of important nodes. Set2Set pooling is also an attention-based pooling method. It trains an LSTM model with permutation invariance to the elements of the set to generate the final embedding of the whole graph. Using Set2Set to complete global pooling will use the final hidden state of the LSTM as the embedding of the global graph.

[0070] It can be seen that this optional embodiment adopts two different modes in the process of converting all target node embeddings into target graph embeddings, which can give higher importance to key nodes, thereby further improving the accuracy of the high-level integrated design quality analysis method.

[0071] In yet another optional embodiment, the original node features include a function number, a basic block number, a node type, a node text, a loop unrolling instruction, a pipelining instruction, and a loop slicing instruction; The original edge features include the start point of the edge, the end point of the edge, and the category of the edge.

[0072] In this optional embodiment, if Figure 8 As shown, Figure 8 The overall process of converting the HLS design described in a high-level language into the corresponding graph structure data is described. The LLVM intermediate code compiled from the native HLS design can be processed by the open source ProGraML tool and converted into the corresponding ProgramGraph object, which fully describes the nodes and corresponding connection relationships of the graph structure data corresponding to the LLVM intermediate code, and can be converted to multiple data types (such as Json and Dot) for further processing. On this basis, the basic information in the LLVM intermediate code and the optimization instruction information in the native HLS design are further encoded into the graph, and the graph structure data containing the complete HLS design information can be obtained, which can then be used for the multi-layer perceptron to obtain the quality analysis results of the high-level synthesis design to be analyzed output by the multi-layer perceptron.

[0073] The relevant ProGraML interface is introduced in Table 1. The method for converting HLS design to graph structure data can first use the llvm2graph interface to convert the LLVM intermediate language obtained from the native HLS design through the HLS compiler front end into the ProgramGraph object in the ProGraML tool, and then use the graph2json interface to further convert it into a Json format file that describes the corresponding graph hierarchy. At this time, the Json file already contains some important features in the LLVM intermediate code, but it is necessary to further add relevant information about the optimization instructions to fully characterize the complete features of the native HLS design.

[0074] Table 1 Related interfaces provided by ProGraML tools

[0075] The ProgramGraph object describes the overall backbone architecture of the graph structure data corresponding to the LLVM intermediate code corresponding to the HLS design. On this basis, it is also necessary to abstract the important information in the HLS design into the original features of nodes and edges and retain them. These features will gradually propagate and learn in the graph neural network, and finally generate representative graph embeddings and use them to perform design quality prediction tasks. Therefore, the selected original features must have representative significance.

[0076] The step of extracting graph node features refers to the process described by ProgramGraph, where variables, constants and assembly instructions are described as nodes, and each node has features such as basic block number, function number, type, text information, etc. These features are extracted from the LLVM intermediate code.

[0077] For all nodes, the function number identifies the HLS function where the node is located, that is, the hardware module in the final generated RTL level circuit, so it is retained as a node feature. The basic block number indicates the set of branchless instruction sequences where the node is located. Branchless instruction sequences are common in the innermost layer of the loop body and are generally used to represent basic operation logic in HLS design, so the basic block number will also be saved in the node feature. The type of the node implies the role of the node in the entire design and its possible impact on the final design quality. For example, a variable node may affect the on-chip cache (BRAM) or operation logic usage in the FPGA resource, while a constant node may correspond to the ROM on the FPGA chip, and the instruction node dominates the complex control logic and calculation logic of the entire circuit, so these three types of nodes should be distinguished, so the node type information will also be retained. The text information records the specific information of the node. For variable nodes and constant nodes, the text information records the type and bit width of the variable (such as i32, i32*, etc.), which affects the bit width of the operation device when the final circuit is implemented. For instruction nodes, branch instructions (such as br) and calculation instructions (such as add) imply relevant information about the control logic and calculation logic in the hardware circuit, so the text information of the node describes the behavior of the node in great detail, and can be regarded as a further refinement of the node type information, and is therefore also retained.

[0078] Finally, considering the information implied by the HLS design optimization instructions that have a significant impact on the design quality, the loop expansion instruction UNROLL, the pipeline instruction PIPELINE and the loop slicing instruction TILE are focused. When the HLS compiler generates RTL-level code at the back end, it will generate RTL-level code in a targeted manner according to the hardware structure specified by these instructions. For example, the UNROLL instruction will copy the hardware structure multiple times according to the expansion factor FACTOR specified in the instruction, which significantly improves the computational parallelism while also significantly increasing the hardware resource overhead. The pipeline instruction PIPELINE will insert pipeline segment registers into the computational logic to streamline the internal computational logic as much as possible. The loop slicing instruction TILE will disassemble a single-layer loop into multiple layers of nested loops to alleviate the on-chip memory access pressure of the computing core. These three instructions are all used for loop blocks in HLS design, so the present invention encodes them into the node features of the icmp assembly instruction.

[0079] It is worth further explaining that when the PIPELINE instruction acts on a specific loop, the HLS tool chain will do its best to pipeline the loop at this level, and the sub-loops within the loop at this level will be fully expanded. Therefore, for the pipeline instruction PIPELINE, this work only considers whether to enable pipeline for a specific icmp node, and thus encodes this dimension feature as a Boolean value. For the loop expansion instruction UNROLL and the tiling instruction TILE, the legal sizes of their expansion and tiling factors are a set of discrete positive integer values ​​between [1, TC] (TC represents the number of loop passes), so the legal value range of the loop expansion factor F is as shown in the formula As shown, the loop expansion and the slice factor value can be regarded as the characteristics of discrete positive integer types.

[0080] In summary, in order to retain the important features in the HLS design to the greatest extent, this optional embodiment ultimately retains 7 original features from the LLVM intermediate code and the HLS design optimization instructions as the feature vectors of the nodes, as shown in Table 2. This part of the feature information will be used to generate subsequent initial node embeddings.

[0081] Table 2 Node features extracted from HLS design

[0082] The step of extracting the graph edge features refers to the information in the ProgramGraph object also including the interconnection relationship between the nodes, which is described in the Json file in the form of a data structure in the form of a link. The link information includes the starting point of the edge, the end point of the edge, and the category of the edge. The starting point of the edge is related to the position of the edge in the graph, so it is retained. There are three types of edges: control flow (the two nodes connected by this edge are both instruction nodes), data flow (at least one of the nodes connected by this edge is a data node) and call flow (one of the nodes connected by this edge is a call instruction node). The functional positioning of these three types of edges in the graph is different, so the type characteristics of the edges are retained. In summary, in the ProgramGraph object, this optional embodiment extracts the edge features shown in Table 3.

[0083] Table 3 Edge features extracted from ProgramGraph object

[0084] It can be seen that the original node features and original edge features selected in this optional embodiment can retain the important features in the high-level integrated design to a great extent, thereby providing efficient data for a series of subsequent data processing steps.

[0085] In order to verify the technical advantages of the embodiments of the present invention, the embodiments of the present invention present and analyze the experimental results of GNN predictor combinations with different configurations. First, the basic settings and evaluation indicators of the experiment will be introduced, and then the effects of different variable parameters and their combinations will be widely discussed, as well as the comparison with related work.

[0086] The data set used in the experiment is 3935 different design samples generated by 22 HLS native designs in the Machsuite benchmark data set and the Polyhedral benchmark data set after different optimization instruction settings. The 22 native computing cores are summarized in Table 4. The hardware target platform uses the Xilinx VirtexUltraScale+ XCVU9P FPGA board. All designs are synthesized by Vitis HLS 2020.2 and implemented by Vitis2020.2. Considering that the design synthesis takes too long, the embodiment of the present invention extracts the true value of the design quality from the existing data set and re-encodes the design features locally.

[0087] Table 4. Names of HLS design kernels that make up the dataset

[0088] The prediction objects are the ratio of the HLS design to the hardware resources (FF, LUT, DSP) on the target platform, and the design delay counted in cycles. Considering that the delay is in the number of clock cycles, there is a large difference between the numerical scale and the hardware resource occupancy rate (the value range is [0,1]), so the delay is first counted and the range is scaled. The maximum design delay in the entire data set is , so the delay is handled as follows: Where L represents the delay before processing, It is a normalization factor selected after considering the range of delay values. It can ensure the delay after normalization The value of is greater than 0, and the logarithm is taken to make the distribution between the design values ​​of different delays more uniform and smooth. The processed delay data is more evenly distributed in the numerical range close to the utilization rate of each resource, so it is more convenient to intuitively display and measure the results. In terms of the error index for measuring the predicted value and the standard result, the embodiment of the present invention selects the root mean square error (RMSE) as the measurement index, which can well characterize the error between the predicted value and the true value, and is easy to compare with related work.

[0089] To ensure fairness during the experiment, the prediction scheme proposed in the related work used the same training rounds as the work in this chapter. Fig. 9 The error comparison results of the best performing models (TransformerConv-M1, DGCNN-M5 and TAG-M3) in various prediction indicators in the comparative experiment and the operation of the embodiment of the present invention are plotted. Among them, the comparative experiment uses the T-Conv convolution operator and the graph neural network structure with attention pooling to analyze the HLS design quality. The baseline data (Baseline) represents the preliminary design quality report obtained by the HLS backend. From Fig. 9It can be seen intuitively that the prediction method proposed in the embodiment of the present invention and the three best predictor structures obtained through the above discussion have surpassed the prediction scheme proposed in the comparative experiment in terms of prediction accuracy of resource utilization, and have been greatly improved compared to the baseline. Among them, the DGCNN-M5 proposed in this chapter has achieved the best results in the prediction performance of FF utilization, DSP utilization and design delay. Although it is slightly inferior to the predictor structure of T-Conv-M1 in the prediction performance of LUT utilization, the difference is very small. The predictor structure in the related work also achieved better performance than TAG-M3 and T-Conv-M1 in the prediction of design delay, but performed slightly worse in the prediction of the three resources. Overall, the DGCNN-M5 predictor using the embodiment of the present invention achieved the best prediction effect, which will bring better prediction accuracy to designers.

[0090] In terms of inference speed, the inference speed of the three best performing models in the embodiment of the present invention is compared with the HLS backend baseline time as shown below: Fig.10 As shown. For fairness, the CPU is uniformly used here to perform the design quality assessment. It can be seen that the predictor based on the graph neural network can obtain a report on a design point in less than 1 second, which is more than 10 times shorter than the time for the traditional HLS backend to obtain a preliminary design quality assessment, and the prediction effect is more accurate. Due to the limited scale of designs in the test set, it is expected that the reasoning speed advantage of the graph neural network over the traditional HLS backend will be further increased in larger-scale HLS designs. The above experimental results fully demonstrate the advantages of the high-level integrated design quality analysis based on the graph neural network designed in the embodiment of the present invention in terms of reasoning speed and prediction accuracy.

[0091] Embodiment 3 See also Fig.11 , Fig.11 Schematic diagram of a high-level integrated design quality analysis system based on a graph neural network disclosed in an embodiment of the present invention. Fig.11 As shown, the high-level integrated design quality analysis system based on graph neural network may include: A memory 301 storing executable program codes; a processor 302 coupled to the memory 301; The processor 302 calls the executable program code stored in the memory 301 to execute the steps of the high-level integrated design quality analysis method based on graph neural network described in the second embodiment of the present invention.

[0092] Embodiment 4 An embodiment of the present invention discloses a computer storage medium, which stores computer instructions. When the computer instructions are called, they are used to execute the steps of the high-level integrated design quality analysis method based on graph neural network described in the second embodiment of the present invention.

[0093] Embodiment 5 An embodiment of the present invention discloses a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to enable a computer to execute the steps of the high-level integrated design quality analysis method based on graph neural network described in Example 2.

[0094] The device embodiments described above are only illustrative, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, i.e., they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative work.

[0095] Through the specific description of the above embodiments, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on such an understanding, the above technical solution can be essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, and the storage medium includes a read-only memory (ROM), a random access memory (RAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a one-time programmable read-only memory (OTPROM), an electronically erasable rewritable read-only memory (EEPROM), a compact disc (CD-ROM) or other optical disc storage, magnetic disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0096] Finally, it should be noted that the high-level integrated design quality analysis method and device based on graph neural network disclosed in the embodiment of the present invention only discloses the preferred embodiment of the present invention, which is only used to illustrate the technical scheme of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical schemes recorded in the aforementioned embodiments can still be modified, or some of the technical features therein can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical schemes from the spirit and scope of the technical schemes of the embodiments of the present invention.

Claims

1. A high-level integrated design quality analysis method based on graph neural network, characterized in that: The method comprises: Encoding the original node features and the original edge features obtained from the high-level integrated design to be analyzed, mapping the original node features into numerical preprocessed node features, and mapping the original edge features into numerical preprocessed edge features; Performing multi-layer convolution processing on the pre-processed node features and the pre-processed edge features to obtain embeddings of all target nodes after the multi-layer convolution processing; Convert all the target node embeddings into target graph embeddings, where the target graph embeddings are used to describe the information in the corresponding target nodes through a graph structure; The target graph is input and embedded into a preset multi-layer perceptron, and a quality analysis result of the high-level integrated design to be analyzed output by the multi-layer perceptron is obtained.

2. The high-level integrated design quality analysis method based on graph neural network according to claim 1 is characterized in that: The encoding of the original node features and the original edge features obtained from the high-level integrated design to be analyzed, mapping the original node features into numerical preprocessed node features, and mapping the original edge features into numerical preprocessed edge features, includes: Count all feature values ​​of the original node features and original edge features obtained in the high-level integrated design to be analyzed, and obtain all possible values ​​corresponding to each feature dimension; For each of the feature dimensions, construct a unique hot encoding corresponding to the feature dimension according to all possible values ​​corresponding to the feature dimension; According to the original node features, the original edge features and the one-hot encodings corresponding to all the feature dimensions, the original node features are mapped to numerical preprocessed node features, and the original edge features are mapped to numerical preprocessed edge features.

3. The high-level integrated design quality analysis method based on graph neural network according to claim 2 is characterized in that: The statistics of all feature values ​​in the original node features and original edge features obtained in the high-level integrated design to be analyzed are used to obtain all possible values ​​corresponding to each feature dimension, including: De-duplication is performed on all feature values ​​of the original node features and the original edge features obtained in the statistical high-level integrated design to be analyzed in each feature dimension to obtain a set of non-repeated feature values ​​corresponding to all feature dimensions; A hash table without repeated elements is used to record the non-repeated feature value sets corresponding to all feature dimensions, and all possible values ​​corresponding to each feature dimension are obtained.

4. The high-level integrated design quality analysis method based on graph neural network according to claim 1 is characterized in that: The performing multi-layer convolution processing on the pre-processed node features and the pre-processed edge features to obtain all target node embeddings after the multi-layer convolution processing includes: Performing multi-layer convolution processing on the preprocessed node features and the preprocessed edge features, wherein for each layer of the convolution processing, the convolution processing includes: aggregating and propagating features between different neighboring nodes according to the preprocessed node features and the preprocessed edge features, and giving the graph convolution operator the ability to fit nonlinear boundaries through an activation function, so as to obtain all intermediate node embeddings corresponding to the convolution processing of this layer; According to all the intermediate node embeddings corresponding to the convolution processing of all layers, all the target node embeddings after the multi-layer convolution processing are obtained.

5. The high-level integrated design quality analysis method based on graph neural network according to claim 4 is characterized in that: The embedding of all the intermediate nodes corresponding to the convolution processing of all the layers to obtain the embedding of all the target nodes after the multi-layer convolution processing includes: Filter out the target convolution processing with the most significant features of the corresponding intermediate node embedding from all the convolution processings at all layers, and determine all the intermediate node embeddings corresponding to the target convolution processing as all the target node embeddings after the multi-layer convolution processing, or After concatenating all the intermediate node embeddings corresponding to each layer of the convolution processing, the target node embedding after the multi-layer convolution processing is obtained, or According to the embeddings of all the intermediate nodes corresponding to the convolution processing of all layers, the attention scores of all the intermediate node embeddings corresponding to the convolution processing of each layer are determined, and according to the attention scores of all the intermediate node embeddings corresponding to the convolution processing of each layer, the weight of the convolution processing of each layer is determined; according to the weight of the convolution processing of each layer and the embeddings of all the intermediate nodes corresponding to the convolution processing of each layer, the target node embeddings after the multi-layer convolution processing are obtained.

6. The high-level integrated design quality analysis method based on graph neural network according to claim 1 is characterized in that: The converting all the target node embeddings into a target graph embedding comprises: Determine the node weight corresponding to each target node embedding according to a preset attention mechanism, and obtain the target graph embedding according to all the target node embeddings and the node weight corresponding to each target node embedding, or All the target nodes are input and embedded into a pre-trained LSTM model that is invariant to the arrangement of set elements, and the final hidden layer state of the LSTM model is embedded as the target graph.

7. The high-level integrated design quality analysis method based on graph neural network according to claim 1 is characterized in that: The original node features include function number, basic block number, node type, node text, loop unrolling instruction, pipeline instruction and loop slicing instruction; The original edge features include the start point of the edge, the end point of the edge and the category of the edge.

8. A high-level integrated design quality analysis device based on graph neural network, characterized in that: The device comprises: A numerical encoder, used for encoding the original node features and the original edge features obtained from the high-level synthesis design to be analyzed, mapping the original node features into numerical preprocessed node features, and mapping the original edge features into numerical preprocessed edge features; A GNN encoder is used to perform multi-layer convolution processing on the pre-processed node features and the pre-processed edge features to obtain embeddings of all target nodes after the multi-layer convolution processing; A global pooler converts all the target node embeddings into a target graph embedding, where the target graph embedding is used to describe the information in the corresponding target node through a graph structure; The multi-layer perceptron is used to input the target graph and embed it into a preset multi-layer perceptron to obtain the quality analysis result of the high-level integrated design to be analyzed output by the multi-layer perceptron.

9. A high-level integrated design quality analysis system based on graph neural network, characterized in that: The system includes: a memory storing executable program code; a processor coupled to the memory; the processor calls the executable program code stored in the memory to execute the high-level synthesis design quality analysis method based on graph neural network as described in any one of claims 1-7.

10. A computer storage medium, characterized in that: The computer storage medium stores computer instructions, which, when called, are used to execute the high-level integrated design quality analysis method based on graph neural network as described in any one of claims 1-7.

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