Multiplexer and leakage current control method thereof

Abstract

The invention discloses a multiplexer and a leakage current control method thereof, and relates to the technical field of multiplexers. The multiplexer comprises a first selection circuit, a second selection circuit and a leakage current control circuit. The first selection circuit is selectively conducted according to the first selection signal so as to transmit a first input signal to an output node to generate an output voltage. The second selection circuit comprises a first switch and a second switch. The first switch is selectively turned on according to a second selection signal, and the second switch is turned on according to the first and second control signals so as to transmit a second input signal to the output node when the first switch is turned on. The leakage current control circuit compares the output voltage with a plurality of reference voltages to generate a plurality of detection signals when the first selection circuit is turned on, and selectively adjusts the level of the first control signal or the second control signal according to the plurality of detection signals and the second selection signal.

Description

Technical Field

[0001] The present application relates to the technical field of multiplexers, and in particular to a multiplexer and a leakage current control method thereof. Background Art

[0002] Multiplexers are often used in various electronic devices to support multi-channel or multi-input usage requirements. Each channel is equipped with a corresponding switch circuit to implement the selection function. In practical applications, the switch circuit is usually implemented by one or more transistors. With the advancement of process technology, the size of transistors is getting smaller and smaller, causing the problem of leakage current to become more serious. In particular, when the reverse bias voltage at either end of the transistor is large, it will cause leakage current to appear at the two ends of the transistor. In practical applications, if the transistors in the multiple channels that are not selected in the multiplexer have leakage current, these leakage currents may cause deviations in the output of the multiplexer (the deviation will increase as the number of channels increases), thereby making the output of the multiplexer inaccurate. Summary of the invention

[0003] One of the purposes of the present application is to provide a multiplexer capable of controlling leakage current according to the current output of the multiplexer and a leakage current control method thereof, so as to improve the deficiencies of the prior art.

[0004] In some embodiments, the multiplexer includes a first selection circuit, a second selection circuit, and a leakage current control circuit. The first selection circuit is selectively turned on according to a first selection signal to transmit a first input signal to an output node to generate an output voltage. The second selection circuit includes a first switch and a second switch. The first switch is selectively turned on according to a second selection signal, and the second switch is turned on according to a first control signal and a second control signal to transmit a second input signal to the output node when the first switch is turned on. The leakage current control circuit compares the output voltage with multiple reference voltages to generate multiple detection signals when the first selection circuit is turned on, and selectively adjusts the level of the first control signal or the second control signal according to the multiple detection signals and the second selection signal.

[0005] In some embodiments, a leakage current control method is applied to a multiplexer, the multiplexer comprising a first selection circuit, a second selection circuit and a leakage current control circuit, the method comprising the following operations: selectively turning on the first selection circuit according to a first selection signal to transmit a first input signal to an output node to generate an output voltage; selectively turning on a first switch in the second selection circuit according to a second selection signal, and turning on a second switch in the second selection circuit according to a first control signal and a second control signal to transmit a second input signal to the output node when the first switch is turned on; and comparing the output node with multiple reference voltages based on the leakage current control circuit when the first selection circuit is turned on to generate multiple detection signals, and selectively adjusting the level of the first control signal or the second control signal according to the multiple detection signals and the second selection signal.

[0006] The features, implementation and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram of a multiplexer drawn according to some embodiments of the present application;

[0008] Figure 2 According to some embodiments of the present application, Figure 1 A schematic diagram of a selection circuit;

[0009] Figure 3 According to some embodiments of the present application, Figure 1 A schematic diagram of a leakage current control circuit; and

[0010] Figure 4 A flow chart of a leakage current control method is drawn according to some embodiments of the present application.

[0011] Reference numerals:

[0012] 100: Multiplexer;

[0013] 110, 120: select circuit;

[0014] 130: leakage current control circuit;

[0015] 210, 220, 332, 334, 336, 338, 370, 372, 380: inverter;

[0016] 310, 320: comparator;

[0017] 330: logic gate;

[0018] 340, 350, 360: switching circuit;

[0019] 400: Leakage current control method;

[0020] AVDD, AVSS: power supply voltage;

[0021] C2, C2B: control signal;

[0022] CN, CP: detection signal;

[0023] EN2, EN2B: switching signal;

[0024] IN1, IN2: input signal;

[0025] MN1, MN2, MN3, MN4: N-type transistors;

[0026] MP1, MP2, MP3, MP4, MP5, MP6, MP7: P-type transistors;

[0027] N1: node;

[0028] NO: output node;

[0029] PW1, PW2, PW3: supply voltage;

[0030] S1: signal;

[0031] S2, S3, S4, S5: switching signals;

[0032] S410, S420, S430: operation;

[0033] SEL1, SEL2: selection signal;

[0034] SW1, SW2, SW3: switches;

[0035] V1, V2: voltage;

[0036] VH, VL: reference voltage;

[0037] VO: output voltage;

[0038] VX: Preset voltage. DETAILED DESCRIPTION

[0039] All words used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries, including any use examples of the words discussed herein in the content of this application are only examples and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0040] As used herein, "coupled" or "connected" may refer to two or more elements making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or may refer to two or more elements operating or acting on each other. As used herein, the term "circuit" may refer to a device composed of at least one transistor and / or at least one active and passive element connected in a certain manner to process signals.

[0041] Figure 1 1 is a schematic diagram of a multiplexer 100 drawn according to some embodiments of the present application. The multiplexer 100 includes a selection circuit 110, a selection circuit 120, and a leakage current control circuit 130. The selection circuit 110 is selectively turned on according to a selection signal SEL1 to transmit the input signal IN1 to the output node NO to generate an output voltage VO (i.e., the input signal IN1 is output as the output voltage). Similarly, the selection circuit 120 is selectively turned on according to a selection signal SEL2 to transmit the input signal IN2 to the output node NO to generate an output voltage VO. In some embodiments, the selection circuit 110 and the selection circuit 120 may have the same circuit structure, but the present application is not limited thereto.

[0042] The leakage current control circuit 130 can compare the output voltage VO with a plurality of reference voltages VL and VH to generate a plurality of detection signals (eg, Figure 3 The control signal (e.g., CP) input to the other one of the selection circuits 110 and 120 (i.e., the non-conducting selection circuit) is selectively adjusted according to a corresponding one of the selection signals SEL1 and SEL2 and the detection signals. Figure 2 or Figure 3 The levels of the control signals C2 and C2B in the output circuit are adjusted to reduce the leakage current in the non-conducting selection circuit and prevent the leakage current from affecting the level of the output voltage VO.

[0043] Figure 2 According to some embodiments of the present application, Figure 1 Schematic diagram of a selection circuit 120. The selection circuit 120 includes a switch SW1, a switch SW2, and a switch SW3. The switch SW1 is selectively turned on according to a selection signal SEL2 to transmit the input signal IN2 to the node N1. The switch SW2 is selectively turned on according to a control signal C2 and a control signal C2B to transmit the input signal IN2 to the output node NO when the switch SW1 is turned on.

[0044] Specifically, the switch SW1 includes a P-type transistor MP1 and an N-type transistor MN1. A first end (e.g., source) of the N-type transistor MN1 and a first end (e.g., drain) of the P-type transistor MP1 receive an input signal IN2, and a second end (e.g., drain) of the N-type transistor MN1 and a second end (e.g., source) of the P-type transistor MP1 are coupled to a node N1. A control end (e.g., gate) of the N-type transistor MN1 receives a switching signal EN2, and a control end (e.g., gate) of the P-type transistor MP1 receives a switching signal EN2B. In some embodiments, the switching signal EN2 and the switching signal EN2B are related to the selection signal SEL2. For example, the switching signal EN2B may be the logical inversion of the selection signal SEL2, and the switching signal EN2 may be the logical inversion of the switching signal EN2B. In some embodiments, the selection circuit 120 may further include an inverter 210 and an inverter 220, wherein the inverter 210 may generate the switching signal EN2B according to the selection signal SEL2, and the inverter 220 may generate the switching signal EN2 according to the switching signal EN2B. Based on the above configuration, when the selection signal SEL2 is a logic value of 1, it means that the multiplexer 100 turns on the selection circuit 120 to select the input signal IN2 to be output as the output voltage VO via the selection circuit 120. Under this condition, the switching signal EN2B is a logic value of 0, and the switching signal EN2 is a logic value of 1, thereby turning on the P-type transistor MP1 and the N-type transistor MN1 (i.e., turning on the switch SW1) to transmit the input signal IN2 to the node N1.

[0045] Similarly, the switch SW2 includes a P-type transistor MP2 and an N-type transistor MN2. The first end of the N-type transistor MN2 and the first end of the P-type transistor MP2 are coupled to the node N1, and the second end of the N-type transistor MN2 and the second end of the P-type transistor MP2 are coupled to the output node NO to output the output voltage VO. The control end of the N-type transistor MN2 receives the control signal C2, and the control end of the P-type transistor MP2 receives the control signal C2B. In some embodiments, the control signal C2 and the control signal C2B are related to the selection signal SEL2 and can be generated by the leakage current control circuit 130. For example, when the switch SW1 is not turned on according to the selection signal SEL2, the P-type transistor MP2 and the N-type transistor MN2 are not turned on according to the control signal C2B and the control signal C2, respectively. Alternatively, when the switch SW1 is turned on according to the selection signal SEL2, the P-type transistor MP2 and the N-type transistor MN2 are turned on according to the control signal C2B and the control signal C2, respectively, so as to transmit the input signal IN2 to the output node NO, thereby generating the output voltage VO.

[0046] The switch SW3 may be implemented by an N-type transistor MN3, but the present application is not limited thereto. Specifically, a first end of the switch SW3 is coupled to the node N1, a second end of the switch SW3 receives a preset voltage VX, and a control end of the switch SW3 receives a switching signal EN2B. Thus, the switch SW3 may be turned on according to the switching signal EN 2B (i.e., the logical inversion of the selection signal SEL2) to transmit the preset voltage VX to the node N1. When the switch SW1 and the switch SW2 are not turned on (i.e., the selection circuit 120 is not selected), the switch SW3 in the selection circuit 120 may be turned on accordingly to transmit the preset voltage VX to the node N1, so that the voltage across the two ends of the switch SW2 will not be too high. Thus, the leakage current between the drain and the source of the transistor in the switch SW2 (e.g., may include a P-type transistor MP2 and an N-type transistor MN2) may be reduced. In some embodiments, the level of the preset voltage VX may be determined based on the input range of the multiplexer 100. For example, the level of the preset voltage VX may be set to half of the highest level of the input signal IN1 (or the input signal IN2 ), but the present application is not limited thereto.

[0047] Figure 3 According to some embodiments of the present application, Figure 1 Schematic diagram of leakage current control circuit 130. Leakage current control circuit 130 includes comparator 310, comparator 320, logic gate 330, inverter 332, inverter 334, inverter 336, inverter 338, switching circuit 340, switching circuit 350, switching circuit 360, inverter 370, inverter 372 and inverter 380.

[0048] The comparator 310 compares the output voltage VO with the reference voltage VH to generate a detection signal CN. The comparator 320 compares the output voltage VO with the reference voltage VL to generate a detection signal CP. For example, when the selection circuit 110 is selected and turned on, the selection circuit 110 outputs the input signal IN1 as the output voltage VO. The comparator 310 can compare the output voltage VO with the reference voltage VH to confirm whether the output voltage VO (equivalent to the input signal IN1) at this time is higher than the reference voltage VH, so as to generate a corresponding detection signal CN. Similarly, the comparator 320 can compare the output voltage VO with the reference voltage VL to confirm whether the output voltage VO (equivalent to the input signal IN1) at this time is lower than the reference voltage VL, so as to generate a corresponding detection signal CP. In some embodiments, the comparator 310 and the comparator 320 can be continuous time comparators. In other embodiments, the comparator 310 and the comparator 320 can be discontinuous time comparators, which can be compared within a specific period according to a clock signal (not shown) to reduce overall power consumption.

[0049] In some embodiments, the reference voltage VH is the highest reference voltage of the reference voltage VH and the reference voltage VL, and the reference voltage VL is the lowest reference voltage of the reference voltage VH and the reference voltage VL. In some embodiments, the reference voltage VH can be set to be approximately two-thirds of the highest power supply voltage in the system (for example, the power supply voltage AVDD described later), and the reference voltage VL can be set to be approximately one-third of the highest power supply voltage, but the present application is not limited thereto.

[0050] The logic gate 330 generates a signal S1 according to the switching signal EN2B and the detection signal CN. In some embodiments, the logic gate 330 may be, but is not limited to, a NAND gate. The inverter 332 generates a switching signal S2 according to the signal S1. The inverter 334 generates a switching signal S3 according to the switching signal S2. That is, the switching signal S2 is the logical inversion of the signal S1, and the switching signal S3 is the logical inversion of the switching signal S2. The switching circuit 340 outputs the power supply voltage AVDD and the power supply voltage AVSS as a supply voltage PW1 according to the switching signal S2, wherein the power supply voltage AVDD is higher than the power supply voltage AVSS. Specifically, the switching circuit 340 includes a P-type transistor MP3 and an N-type transistor MN4. The first end of the P-type transistor MP3 receives the power supply voltage AVDD, the second end of the P-type transistor MP3 is coupled to the second end of the N-type transistor MN4 to output the supply voltage PW1, and the control end of the P-type transistor MP3 receives the switching signal S2. A first terminal of the N-type transistor MN4 receives the power voltage AVSS, and a control terminal of the N-type transistor MN4 receives the switching signal S2 .

[0051] The switching circuit 350 outputs the voltage V1 and the power supply voltage AVDD as the supply voltage PW2 according to the switching signal S3 and the switching signal S2. Specifically, the switching circuit 350 may include a P-type transistor MP4 and a P-type transistor MP5. The first end of the P-type transistor MP4 receives the voltage V1, the second end of the P-type transistor MP4 is coupled to the second end of the P-type transistor MP5 to output the supply voltage PW2, and the control end of the P-type transistor MP4 receives the switching signal S3. The first end of the P-type transistor MP5 receives the power supply voltage AVDD, and the control end of the P-type transistor MP5 receives the switching signal S2. In some embodiments, the voltage V1 is set to be higher than the power supply voltage AVSS.

[0052] The inverter 336 generates a switching signal S4 according to the detection signal CP, and the inverter 338 generates a switching signal S5 according to the switching signal S4. In other words, the switching signal S4 is the logical inversion of the detection signal CP and the switching signal S5 is the logical inversion of the switching signal S4. The switching circuit 360 outputs the voltage V2 and the power supply voltage AVDD as the supply voltage PW3 according to the switching signal S4 and the switching signal S5. Specifically, the switching circuit 360 may include a P-type transistor MP6 and a P-type transistor MP7. The first end of the P-type transistor MP6 receives the voltage V2, the second end of the P-type transistor MP6 is coupled to the second end of the P-type transistor MP7 to output the supply voltage PW3, and the control end of the P-type transistor MP6 receives the switching signal S5. The first end of the P-type transistor MP7 receives the power supply voltage AVDD, and the control end of the P-type transistor MP7 receives the switching signal S4. In some embodiments, the voltage V2 is set to be lower than the power supply voltage AVDD.

[0053] The inverter 370 is coupled in series with the inverter 372, and generates the control signal C2 according to the switching signal EN2. For example, the inverter 370 is powered by the supply voltage PW1 and the power supply voltage AVSS to generate a corresponding output according to the switching signal EN2. The inverter 372 is powered by the supply voltage PW2 and the power supply voltage AVSS, and generates the control signal C2 according to the output of the inverter 370. Similarly, the inverter 380 generates the control signal C2B according to the switching signal EN2. For example, the inverter 380 is powered by the supply voltage PW2 and the power supply voltage AVSS to generate the control signal C2B according to the switching signal EN2.

[0054] The following describes the related operations of the leakage current control circuit 130 in sequence according to different comparison results of the output voltage VO with the reference voltage VL and the reference voltage VH. In the first case, when the output voltage VO is higher than the reference voltage VL but lower than the reference voltage VH (i.e., the input signal IN1 transmitted by the selected selection circuit 110 is between the reference voltage VL and the reference voltage VH), the leakage current control circuit 130 does not adjust the levels of the control signal C2 and the control signal C2B according to the detection signal CP, the detection signal CN and the selection signal SEL2. That is, in the first case, the leakage current control circuit 130 will output the control signal C2B with a first preset level (e.g., the highest power supply voltage AVDD in the system) and the control signal C2 with a second preset level (e.g., the lowest power supply voltage AVSS in the system).

[0055] Specifically, when the output voltage VO is between the reference voltage VL and the reference voltage VH, the detection signal CP is a logic value 1, and the detection signal CN is a logic value 0. Under this condition, the signal S1 is a logic value 1, so that the switching signal S2 is a logic value 0, the switching signal S3 is a logic value 1, the switching signal S4 is a logic value 0, and the switching signal S5 is a logic value 1. In this way, the switching circuit 340 outputs the power supply voltage AVDD as the supply voltage PW1, the switching circuit 350 outputs the power supply voltage AVDD as the supply voltage PW2, and the switching circuit 360 outputs the power supply voltage AVDD as the supply voltage PW3, so that the inverter 372 generates the control signal C2B with a first preset level, and the inverter 380 generates the control signal C2 with a second preset level.

[0056] In the second case, when the output voltage VO is higher than the reference voltage VH (i.e., the input signal IN1 transmitted by the selected selection circuit 110 is higher than the reference voltage VH), the leakage current control circuit 130 increases the level of the control signal C2 (compared to the aforementioned second preset level) according to the detection signal CP, the detection signal CN and the selection signal SEL2. Specifically, when the output voltage VO is higher than the reference voltage VH, the detection signal CP is a logic value 1, and the detection signal CN is a logic value 1. Under this condition, the signal S1 is a logic value 0, so that the switching signal S2 is a logic value 1, the switching signal S3 is a logic value 0, the switching signal S4 is a logic value 0, and the switching signal S5 is a logic value 1. In this way, the switching circuit 340 outputs the power supply voltage AVSS as the supply voltage PW1, the switching circuit 350 outputs the voltage V1 as the supply voltage PW2, and the switching circuit 360 outputs the power supply voltage AVDD as the supply voltage PW3. Accordingly, the inverter 372 will output the control signal C2 having a level of voltage V1 to reduce Figure 2 The reverse bias voltage between the gate and the drain (or the source) of the N-type transistor MN2 in the selection circuit 120 is reduced, thereby reducing the base leakage current of the N-type transistor MN2.

[0057] In the third case, when the output voltage VO is lower than the reference voltage VL (i.e., the input signal IN1 transmitted by the selected selection circuit 110 is lower than the reference voltage VL), the leakage current control circuit 130 reduces the level of the control signal C2B (compared to the aforementioned first preset level) according to the detection signal CP, the detection signal CN and the selection signal SEL2. Specifically, when the output voltage VO is lower than the reference voltage VL, the detection signal CP and the detection signal CN are both logic values ​​0. Under this condition, the signal S1 is logic value 1, so that the switching signal S2 is logic value 0, the switching signal S3 is logic value 1, the switching signal S4 is logic value 1, and the switching signal S5 is logic value 0. In this way, the switching circuit 340 outputs the power supply voltage AVDD to supply the voltage PW1, the switching circuit 350 outputs the power supply voltage AVDD as the supply voltage PW2, and the switching circuit 360 outputs the voltage V2 as the supply voltage PW3. Accordingly, the inverter 380 will output the control signal C2 having a level of voltage V2 to reduce Figure 2 The reverse bias voltage between the gate and the drain (or the source) of the P-type transistor MP2 in the selection circuit 120 is reduced, thereby reducing the base leakage current of the P-type transistor MP2.

[0058] On the other hand, if the selection circuit 120 is selected (i.e., the selection signal SEL2 is switched to logic value 1), the switching signal EN2B is logic value 0, and the switching signal EN2 is logic value 1. Under this condition, the level of the control signal C2B is fixed to the power supply voltage AVDD, and the level of the control signal C2 is fixed to the power supply voltage AVSS (or ground).

[0059] Based on the above operation, it should be understood that the leakage current control circuit 130 can adjust the level of the control signal (such as the aforementioned control signal C2B and control signal C2) used by other unselected channels (such as the selection circuit 120) according to the current output of the multiplexer 100, thereby reducing the leakage current of the unselected channels to prevent the leakage current from affecting the output voltage VO.

[0060] For clarity and brevity, Figure 3The circuit portion shown mainly shows the relevant circuit portion for controlling the selection circuit 120. It should be understood that the leakage current control circuit 130 may also include the relevant circuit portion for controlling the selection circuit 110. In other words, the leakage current control circuit 130 may also include additional logic gates 330, inverters 332, inverters 334, inverters 336, inverters 338, switching circuits 340, switching circuits 350, switching circuits 360, inverters 370, inverters 372, and inverters 380 to control the leakage current of the selection circuit 110. In some embodiments, the relevant circuit portion for controlling the selection circuit 110 and the relevant circuit portion for controlling the selection circuit 120 in the leakage current control circuit 130 share the same set of comparators 310 and comparators 320.

[0061] Figure 4 A flow chart of a leakage current control method 400 is drawn according to some embodiments of the present application. In some embodiments, the leakage current control method 400 may be, but is not limited to, Figure 1 The multiplexer 100 is executed.

[0062] In operation S410, a first selection circuit is selectively turned on according to a first selection signal to transmit a first input signal to an output node to generate an output voltage. In operation S420, a first switch in a second selection circuit is selectively turned on according to a second selection signal, and a second switch in the second selection circuit is turned on according to a first control signal and a second control signal to transmit a second input signal to the output node when the first switch is turned on. In operation S430, based on a leakage current control circuit, the output node is compared with multiple reference voltages to generate multiple detection signals when the first selection circuit is turned on, and the level of the first control signal or the second control signal is selectively adjusted according to the multiple detection signals and the second selection signal.

[0063] The description of the multiple operations of the leakage current control method 400 can refer to the aforementioned multiple embodiments, so it will not be repeated here. The above multiple operations are only examples and are not limited to being performed in the order in this example. Without violating the operation mode and scope of each embodiment of the present application, the various operations under the leakage current control method 400 can be appropriately increased, replaced, omitted or performed in a different order. Alternatively, one or more operations under the leakage current control method 400 can be performed simultaneously or partially simultaneously.

[0064] In summary, the multiplexer and leakage current control method provided in some embodiments of the present application can control the leakage current of the circuits in the unselected channels in the multiplexer according to the current output of the multiplexer, so as to avoid the leakage of the unselected channel circuits affecting the output of the multiplexer. In this way, the output accuracy of the multiplexer can be improved.

[0065] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Technicians in this technical field may change the technical features of the present application based on the explicit or implicit contents of the present application. All these changes may fall within the scope of patent protection sought by the present application. The scope of patent protection of the present application shall be based on the scope of the patent application of this specification.

Claims

1. A multiplexer, characterized in that: include: a first selection circuit, selectively turned on according to a first selection signal to transmit a first input signal to an output node to generate an output voltage; a second selection circuit, comprising a first switch and a second switch, wherein the first switch is selectively turned on according to a second selection signal, and the second switch is turned on according to a first control signal and a second control signal, so as to transmit a second input signal to the output node when the first switch is turned on; as well as A leakage current control circuit compares the output voltage with a plurality of reference voltages to generate a plurality of detection signals when the first selection circuit is turned on, and selectively adjusts the level of the first control signal or the second control signal according to the plurality of detection signals and the second selection signal.

2. The multiplexer according to claim 1, wherein: The second switch comprises: a P-type transistor, turned on according to the first control signal, so as to receive the second input signal when the first switch is turned on; and an N-type transistor, turned on according to the second control signal, to receive the second input signal when the first switch is turned on.

3. The multiplexer according to claim 2, wherein: When the output voltage is higher than a highest reference voltage among the plurality of reference voltages, the leakage current control circuit increases the level of the second control signal according to the plurality of detection signals and the second selection signal.

4. The multiplexer according to claim 2, wherein: When the output voltage is lower than a lowest reference voltage among the plurality of reference voltages, the leakage current control circuit reduces a level of the first control signal according to the plurality of detection signals and the second selection signal.

5. The multiplexer according to claim 2, wherein: When the output voltage is between the multiple reference voltages, the leakage current control circuit outputs the first control signal having a first preset level and the second control signal having a second preset level according to the multiple detection signals and the second selection signal, wherein the first preset level is a level of a highest power supply voltage, and the second preset level is a level of a lowest power supply voltage.

6. The multiplexer according to claim 1, wherein: The leakage current control circuit comprises: a first comparator, comparing the output voltage with a first reference voltage among the plurality of reference voltages to generate a first detection signal among the plurality of detection signals; and A second comparator compares the output voltage with a second reference voltage among the plurality of reference voltages to generate a second detection signal among the plurality of detection signals.

7. The multiplexer according to claim 1, wherein: The leakage current control circuit comprises: a logic gate, generating a first signal according to a first switching signal and a first detection signal among the plurality of detection signals, wherein the first switching signal is a logic inversion of the second selection signal; a first switching circuit, outputting a first power supply voltage or a second power supply voltage as a first supply voltage according to a second switching signal, wherein the second switching signal is a logic inversion of the first signal, and the first power supply voltage is higher than the second power supply voltage; a second switching circuit, outputting a first voltage or the first power supply voltage as a second supply voltage according to a third switching signal and the second switching signal, wherein the third switching signal is a logical inversion of the second switching signal, and the first voltage is higher than the second power supply voltage; a third switching circuit, outputting a second voltage or the first power supply voltage as a third supply voltage according to a fourth switching signal and a fifth switching signal, wherein the fourth switching signal is a logic inversion of a second detection signal among the plurality of detection signals, the fifth switching signal is a logic inversion of the fourth switching signal, and the second voltage is lower than the first power supply voltage; a plurality of first inverters, the plurality of first inverters are coupled in series and generate the first control signal according to a sixth switching signal, wherein the sixth switching signal is a logic inversion of the first switching signal, a first one of the plurality of first inverters is powered by the first supply voltage and the second power supply voltage, and a second one of the plurality of first inverters is powered by the second supply voltage and the second power supply voltage; and a second inverter, generating the second control signal according to the sixth switching signal, wherein the second inverter is powered by the third supply voltage and the second power supply voltage.

8. The multiplexer according to claim 1, wherein: The second selection circuit further includes: a third switch is turned on according to the logic inversion of the second selection signal to transmit a preset voltage to a first node, wherein the second switch is coupled between the first node and the output node.

9. The multiplexer according to claim 8, wherein: The level of the preset voltage is half of the highest level of the first input signal.

10. A leakage current control method, characterized in that: Applied to a multiplexer, the multiplexer includes a first selection circuit, a second selection circuit and a leakage current control circuit, the method includes: Selectively turning on the first selection circuit according to a first selection signal to transmit a first input signal to an output node to generate an output voltage; selectively turning on a first switch in the second selection circuit according to a second selection signal, and turning on a second switch in the second selection circuit according to a first control signal and a second control signal, so as to transmit a second input signal to the output node when the first switch is turned on; and The leakage current control circuit compares the output node with a plurality of reference voltages to generate a plurality of detection signals when the first selection circuit is turned on, and selectively adjusts the level of the first control signal or the second control signal according to the plurality of detection signals and the second selection signal.

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