Method for measuring DC bias aging characteristics of multilayer capacitor

Abstract

The present disclosure provides a method for measuring DC bias aging characteristics of a multilayer capacitor, the method comprising: applying a first polarization voltage to the multilayer capacitor, the multilayer capacitor comprising a body and an external electrode, a body having a dielectric layer including a plurality of dielectric grains and internal electrodes disposed alternately with the dielectric layer in a first direction, the external electrodes disposed on the body; maintaining the first polarization voltage for a first time period (t1); applying a DC bias voltage lower than the first polarization voltage; maintaining the DC bias voltage for a second time period (t2); and measuring a saturation capacitance after the DC bias voltage is applied.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0102170 filed on August 4, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a method for measuring direct current (DC) bias aging characteristics of a multilayer capacitor. Background Art

[0003] Multilayer capacitors have been widely used as components of electronic devices such as computers and mobile phones due to their small size, high capacitance, and ease of installation, and have also been widely used as components of electrical devices including vehicles due to their high reliability and high strength characteristics.

[0004] Therefore, due to the diversity of electronic devices / electrical devices in which the multilayer capacitor is used, the multilayer capacitor can be evaluated by many guarantee indicators (such as capacitance characteristics, temperature characteristics, and operating voltage characteristics).

[0005] Multilayer capacitors can be used for a long period of time (e.g., 10 years or more). Therefore, among many guarantee indicators, the DC bias aging characteristic may be an indicator of the minimum capacitance value. Therefore, the time period required to measure the DC bias aging characteristic may be relatively increased compared to other guarantee indicators. When the required time period is excessively reduced, the accuracy of measuring the DC bias aging characteristic may be reduced. Summary of the invention

[0006] An aspect of the present disclosure is to quickly and accurately measure the DC bias aging characteristics of a multilayer capacitor.

[0007] Another aspect of the present disclosure is to accurately predict the saturation capacitance of a multilayer capacitor at different temperatures due to DC bias aging.

[0008] According to one aspect of the present disclosure, a method for measuring the DC bias aging characteristics of a multilayer capacitor is provided, the method comprising: applying a first polarization voltage to the multilayer capacitor, the multilayer capacitor comprising a main body and an external electrode, the main body having a dielectric layer comprising a plurality of dielectric grains and an internal electrode alternately arranged with the dielectric layer in a first direction, the external electrode being arranged on the main body; maintaining the first polarization voltage for a first time period (t1); applying a DC bias voltage lower than the first polarization voltage; maintaining the DC bias voltage for a second time period (t2); and measuring the saturation capacitance after applying the DC bias voltage.

[0009] According to another aspect of the present disclosure, a method for measuring the DC bias aging characteristics of a multilayer capacitor is provided, the method comprising: applying a first polarization voltage to the multilayer capacitor, the multilayer capacitor comprising a main body and a first external electrode and a second external electrode, the main body having a capacitance region, in which at least one first internal electrode and at least one second internal electrode are alternately stacked in a first direction, and at least one dielectric layer is interposed between the at least one first internal electrode and the at least one second internal electrode, the first external electrode and the second external electrode are arranged on the main body spaced apart from each other, the first external electrode and the second external electrode are respectively connected to the at least one first internal electrode and the at least one second internal electrode; measuring the first capacitance of the multilayer capacitor after applying the first polarization voltage and applying a DC bias voltage lower than the first polarization voltage; applying a second polarization voltage different from the first polarization voltage to the multilayer capacitor; measuring the second capacitance of the multilayer capacitor after applying the second polarization voltage and applying the DC bias voltage lower than the second polarization voltage; and determining the DC bias aging characteristics of the multilayer capacitor based on the first polarization voltage and the second polarization voltage and the first capacitance and the second capacitance.

[0010] According to another aspect of the present disclosure, a method for measuring DC bias aging characteristics of a multilayer capacitor is provided, the multilayer capacitor comprising a main body having a dielectric layer comprising a plurality of dielectric grains and internal electrodes alternately arranged with the dielectric layer, the method comprising repeating the following series of operations two or more times, each time using a different polarization voltage: applying the polarization voltage to the multilayer capacitor to polarize the dielectric layer; applying a DC bias voltage to the multilayer capacitor to depolarize the polarized dielectric layer, and after depolarizing the dielectric layer, measuring the saturation capacitance of the multilayer capacitor; and predicting the saturation capacitance of the multilayer capacitor after aging using the measured saturation capacitance and an exponential decay function.

[0011] The method for measuring the DC bias aging characteristics of a multilayer capacitor according to an example embodiment of the present disclosure can quickly and accurately measure the DC bias aging characteristics of the multilayer capacitor, and can quickly and accurately provide a guaranteed indicator of the minimum capacitance value of the multilayer capacitor.

[0012] The method can quickly predict the saturation capacitance of a multilayer capacitor due to DC bias aging at different temperatures.

[0013] The method according to the example embodiment of the present disclosure can reduce the existing required measurement time period of at least 100 hours to 1 hour or less, thereby not only reducing the space and tangible costs required to expand the measurement facilities, but also achieving intangible effects (such as reducing product development time). BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0015] Figure 1 is a diagram illustrating a system for performing a method of measuring a DC bias aging characteristic of a multilayer capacitor according to an example embodiment of the present disclosure;

[0016] Figure 2 is a flow chart illustrating a method for measuring DC bias aging characteristics of a multilayer capacitor according to an example embodiment of the present disclosure;

[0017] Figure 3 is a schematic perspective view showing a multilayer capacitor (measurement target) in a method for measuring DC bias aging characteristics of a multilayer capacitor according to an example embodiment of the present disclosure;

[0018] Figure 4 is an exploded perspective view showing a multi-layer structure of an inner electrode;

[0019] Figure 5 is along Figure 3 A cross-sectional view and a partially enlarged view taken along line II';

[0020] Figure 6 is a schematic diagram showing changes in domain walls due to aging of a multilayer capacitor;

[0021] Figure 7 is a graph showing the result of measuring the voltage-current characteristics of the multilayer capacitor for each temperature;

[0022] Fig. 8A is a graph showing capacitance change due to aging when a DC bias voltage is not applied to the multilayer capacitor;

[0023] Figure 8B is a graph showing a change in capacitance due to aging when a DC bias voltage is applied to a multilayer capacitor;

[0024] 9A to 9E is a TEM image showing the microstructure of the domain wall according to the temperature of the multilayer capacitor;

[0025] Fig.10 is a graph showing a capacitance change due to aging for each temperature when a DC bias voltage is applied to a multilayer capacitor;

[0026] Fig.11is a graph showing the capacitance of the multilayer capacitor when a polarization voltage of 30 V to 70 V is applied to the multilayer capacitor and the capacitance of the multilayer capacitor when a DC bias voltage of 3.3 V is applied at 25° C.;

[0027] Fig.12 is a graph showing the result of fitting a change in saturation capacitance of a multilayer capacitor due to a polarization voltage using an exponential decay function; and

[0028] FIG. 13A to FIG. 13C is a graph showing the capacitance of the multilayer capacitor when a polarization voltage of 30 V to 70 V is applied to the multilayer capacitor and the capacitance of the multilayer capacitor when a DC bias voltage of 3.3 V is applied to the multilayer capacitor under various temperature conditions. DETAILED DESCRIPTION

[0029] Hereinafter, example embodiments of the present disclosure are described with reference to the accompanying drawings. However, the present disclosure may be illustrated in many different forms and should not be construed as being limited to the specific example embodiments set forth herein. In addition, in order to more completely describe the present disclosure, example embodiments of the present disclosure may be provided to those skilled in the art. Therefore, for clarity of description, the shapes and sizes of the elements in the accompanying drawings may be exaggerated, and the elements represented by the same reference numerals in the accompanying drawings may be the same elements.

[0030] In order to clearly illustrate the present disclosure, parts irrelevant to the description are omitted and sizes (eg, thickness) are exaggerated to clearly indicate layers and regions, and similar parts having the same function in the same scope are denoted by similar reference numerals throughout the specification.

[0031] Throughout the specification, unless particularly stated otherwise, when an element is referred to as “comprising” or “including,” it means that it may also include other elements, rather than excluding other elements.

[0032] The directions of the hexahedron may be defined to clearly illustrate the exemplary embodiments of the present disclosure. The first to third directions shown in the drawings may refer to the thickness direction, the length direction, and the width direction, respectively. Here, the thickness direction may be used interchangeably with the stacking direction (or first direction) of the stacked dielectric layers.

[0033] Hereinafter, a multilayer capacitor according to an exemplary embodiment of the present disclosure will be described. Specifically, a multilayer ceramic capacitor (MLCC) will be described, but the present disclosure is not limited thereto.

[0034] Method for measuring DC bias aging characteristics of multilayer capacitors

[0035] In the present specification, the DC bias aging characteristics of the multilayer capacitor may be one of the reliability assurance indicators of the multilayer capacitor 100, and may refer to the minimum capacitance value after the multilayer capacitor 100 has been used for a long period of time (for example, 10 years or more) under operating conditions where a specific DC bias voltage is applied at various temperatures.

[0036] According to the prior art, in order to measure the DC bias aging characteristics of the above-mentioned multilayer capacitor, a DC bias voltage is applied to the multilayer capacitor for a relatively long period of time (e.g., 100 hours to 3000 hours) to measure the final saturation capacitance. In this example embodiment, the DC bias aging characteristics of the above-mentioned multilayer capacitor can be measured in a short period of time, while obtaining a measurement value with high accuracy close to the measurement value according to the prior art.

[0037] Hereinafter, a system and a measuring method for measuring a DC bias aging characteristic of a multilayer capacitor according to the present example embodiment will be described in detail.

[0038] Figure 1 is a diagram illustrating a system for performing a method of measuring a DC bias aging characteristic of a multilayer capacitor according to an example embodiment of the present disclosure.

[0039] Reference Figure 1 The system for performing the method of measuring the DC bias aging characteristics of a multilayer capacitor according to the present exemplary embodiment may include at least some of the following components: a temperature control unit 10 accommodating a multilayer capacitor 100 (measurement target), a power supply unit 20 supplying power to the system, a measurement unit 30 measuring the capacitance of the multilayer capacitor 100, and a biaser 40 applying a DC voltage to the multilayer capacitor 100 based on the power supplied from the power supply unit 20, the biaser 40 circuit being isolated to prevent interference with the measurement of the measurement unit 30. In addition, the system may further include a control unit (or controller) 50.

[0040] The temperature control unit 10 may be configured to control the temperature of the internal space in which the multilayer capacitor 100 is accommodated so that the temperature always falls within a predetermined temperature range and adjust the temperature, which may be less than or equal to the Curie temperature of the dielectric layer of the multilayer capacitor 100 .

[0041] The power supply unit 20 may include a DC power supply. Alternatively, the power supply unit 20 may include a converter for converting an AC voltage into a DC voltage or changing a DC voltage. For example, a DC voltage applied to the multilayer capacitor 100 may be changed by the power supply unit 20.

[0042] The biaser 40 may control a DC voltage applied between the first and second external electrodes of the multilayer capacitor 100 such that the DC voltage is maintained equal to a target DC voltage.

[0043] For example, the measuring unit 30 may apply an AC signal to the multilayer capacitor 100 to measure the capacitance of the multilayer capacitor 100, and the bias device 40 may be configured to prevent interference between the AC signal and the DC voltage. Therefore, the DC voltage application and the capacitance measurement may be performed simultaneously. For example, a DC blocking capacitor may be connected in series between the bias device 40 and the measuring unit 30, and the bias device 40 may include a low-pass filter, a high-pass filter, or a switch.

[0044] The control unit (or controller) 50 may control each of the temperature control unit 10, the power supply unit 20, and the measuring unit 30, and may record the measurement data. In addition, the control unit 50 may calculate a predicted value of the saturation capacitance of the multilayer capacitor 100 based on the recorded data, but the present disclosure is not limited thereto.

[0045] Figure 2 is a flow chart illustrating a method for measuring DC bias aging characteristics of a multilayer capacitor according to an example embodiment of the present disclosure.

[0046] Reference Figure 2 , the multilayer capacitor 100 (measurement target) according to the present exemplary embodiment may be set in the temperature control unit 10 (S110), and the inside of the temperature control unit 10 may be maintained at a specific temperature (S120). The inside of the temperature control unit 10 may be set and maintained at a specific temperature based on a control signal from the control unit 50.

[0047] Here, the specific temperature of the internal space of the temperature control unit 10 may be a temperature less than or equal to the Curie temperature (Tc) of the dielectric layer 111 of the multilayer capacitor 100 (measurement target). For example, in the present exemplary embodiment, the specific temperature of the internal space of the temperature control unit 10 may be less than 180°C, and may preferably be a specific temperature within a range of 25°C to 125°C, but the present disclosure is not limited thereto.

[0048] Subsequently, a polarization voltage may be applied to the multilayer capacitor 100 using the power supply unit 20 and the biaser 40 ( S210 ). The control unit 50 may be configured to control the power supply unit 20 to adjust the polarization voltage applied to the multilayer capacitor 100 through the biaser 40 .

[0049] Here, the polarization voltage may be a voltage capable of polarizing the dielectric of the multilayer capacitor 100 , and may be a voltage at a level at which domains are aligned in one direction and the domain wall DW expands.

[0050] The polarization voltage may be a voltage lower than the breakdown voltage of the multilayer capacitor 100 (measurement target). For example, the polarization voltage may be a voltage equal to or less than 70% of the breakdown voltage of the multilayer capacitor 100 (measurement target), and may be greater than or equal to 30V and less than or equal to 70V, but the present disclosure is not limited thereto.

[0051] Subsequently, the polarization voltage applied to the multilayer capacitor 100 may be maintained for a first period of time ( t1 ) ( S220 ).

[0052] The first time period (t1) may be a time period sufficient to cause polarization in the dielectric layer 111 of the multilayer capacitor 100, and may be a time period of 1 minute or longer. However, when the first time period (t1) is increased, it may be advantageous in terms of the accuracy of measuring the DC bias aging characteristics of the multilayer capacitor. The first time period (t1) may preferably be 20 minutes, but the present disclosure is not limited thereto.

[0053] Subsequently, a DC bias voltage may be applied to the multilayer capacitor 100 using the power supply unit 20 and the biaser 40 ( S230 ). The control unit 50 may be configured to control the power supply unit 20 to adjust the DC bias voltage applied to the multilayer capacitor 100 through the biaser 40 .

[0054] The DC bias voltage applied to the multilayer capacitor 100 may be a voltage similar to a DC bias voltage applied when the multilayer capacitor 100 is surface-mounted on a PCB board and used, and may be lower than the first polarization voltage.

[0055] For example, the DC bias voltage may be greater than or equal to 1.8 V and less than or equal to 3.3 V, but the present disclosure is not limited thereto.

[0056] Subsequently, the DC bias voltage applied to the multilayer capacitor 100 may be maintained for a second period of time (t2) (S240).

[0057] The second time period (t2) may be a time period sufficient to cause depolarization in the dielectric layer 111 of the multilayer capacitor 100, and may be a time period of 1 minute or longer. However, when the second time period (t2) is increased, it may be advantageous in terms of the accuracy of measuring the DC bias aging characteristics of the multilayer capacitor. The second time period (t2) may preferably be 20 minutes, but the present disclosure is not limited thereto.

[0058] Subsequently, the saturation capacitance of the multilayer capacitor 100 (measurement target) may be measured using the measurement unit 30 and the control unit 50 ( S250 ).

[0059] The method for measuring the DC bias aging characteristics of a multilayer capacitor according to this example embodiment may include applying a polarization voltage as a first operation. Therefore, compared with the case where the capacitance is measured by immediately applying a DC bias voltage, the saturation capacitance can be measured in a much shorter period of time.

[0060] Subsequently, the changed polarization voltage may be applied to the multilayer capacitor 100 using the control unit 50 , the power supply unit 20 , and the bias unit 40 ( S310 ).

[0061] For example, when a polarization voltage first applied to the multilayer capacitor 100 is referred to as a first polarization voltage and a polarization voltage applied again after operation S310 is referred to as a second polarization voltage, the first polarization voltage and the second polarization voltage may have a voltage difference of 10V.

[0062] In addition, the first polarization voltage and the second polarization voltage may be selected within a range of greater than or equal to 30 V and less than or equal to 70 V, respectively, but the present disclosure is not limited thereto.

[0063] The above operation can be performed repeatedly to obtain multiple saturation capacitance measurements for various polarization voltages.

[0064] Subsequently, the saturation capacitance of the multilayer capacitor after DC bias aging may be predicted using comparative analysis of multiple saturation capacitance measurements for various polarization voltages and an exponential decay function ( S410 ).

[0065] The detailed experimental data and their error results are described below.

[0066] Multilayer Capacitor According to the Present Example Embodiment (Measurement Target)

[0067] Figure 3 is a schematic perspective view showing a multilayer capacitor (measurement target) in a method for measuring DC bias aging characteristics of a multilayer capacitor according to an example embodiment of the present disclosure. Figure 4 is an exploded perspective view showing a multi-layer structure of an internal electrode. Figure 5 is along Figure 3 A cross-sectional view and a partially enlarged view taken along line II'.

[0068] Reference Figures 3 to 5 , the multilayer capacitor 100 (measurement target) may include: a main body 110, the main body 110 includes a dielectric layer 111 and internal electrodes 121 and 122 arranged alternately with the dielectric layer 111 in a first direction, the dielectric layer 111 includes a plurality of dielectric grains G; and external electrodes 131 and 132, which are arranged on the main body 110.

[0069] In the body 110 , dielectric layers 111 and internal electrodes 121 and 122 may be alternately stacked.

[0070] The body 110 may include a capacitor forming portion or capacitor region forming a capacitor, the capacitor forming portion or capacitor region including a first internal electrode 121 and a second internal electrode 122, the first internal electrodes 121 and the second internal electrodes 122 are alternately arranged with a dielectric layer 111 interposed between the first internal electrode 121 and the second internal electrode 122.

[0071] The multiple dielectric layers 111 included in the body 110 may be in a sintered state, and adjacent dielectric layers 111 may be integrated with each other such that the boundary between adjacent dielectric layers 111 is not easily visible without using a scanning electron microscope (SEM).

[0072] Referring Figure 5 to the enlarged view of Figure 6 , dielectric grains G may be included in the dielectric layer 111, and referring

[0073] to

[0074] , polarizations in different directions may be formed within the dielectric grains G, so that domain walls DW (boundaries between polarizations in different directions) may be observed.

[0075] The raw materials included in the dielectric layer 111 are not limited as long as sufficient capacitance can be obtained using them. Generally, perovskite (ABO3)-based materials may be used. In the chemical formula ABO3, A may include one of barium (Ba), strontium (Sr), and calcium (Ca), and B may include one of titanium (Ti) and zirconium (Zr), but the present disclosure is not limited thereto.

[0076] The raw materials included in the dielectric layer 111 may be barium titanate-based materials, lead composite perovskite-based materials, or strontium titanate-based materials. The barium titanate-based materials may include BaTiO3-based ceramic powder particles. Examples of the BaTiO3-based ceramic powder particles may include (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), or Ba(Ti 1-y Zr y )O3 (0 < y < 1).

[0077] In addition, depending on the purpose of the present disclosure, a raw material included in the dielectric layer 111 may be obtained by adding various ceramic additives, an organic solvent, a binder, a dispersant, etc. to powder particles such as barium titanate (BaTiO 3 ).

[0078] Reference Figure 4 , the internal electrodes 121 and 122 may be alternately stacked with the dielectric layers 111 .

[0079] The internal electrodes 121 and 122 may include a first internal electrode 121 and a second internal electrode 122, and the first internal electrode 121 and the second internal electrode 122 may be alternately arranged opposite to each other, and the dielectric layer 111 included in the body 110 is interposed between the first internal electrode 121 and the second internal electrode 122, and the first internal electrode 121 and the second internal electrode 122 may be exposed to the third surface 3 and the fourth surface 4 of the body 110, respectively.

[0080] The first internal electrode 121 may be connected to the first external electrode 131 without being connected to the second external electrode 132, and the second internal electrode 122 may be connected to the second external electrode 132 without being connected to the first external electrode 131. In this case, the first internal electrode 121 and the second internal electrode 122 may be electrically isolated from each other by the dielectric layer 111 disposed therebetween.

[0081] The body 110 may be formed by alternately stacking ceramic green sheets having the first internal electrode patterns printed thereon and ceramic green sheets having the second internal electrode patterns printed thereon and then sintering them.

[0082] The material included in the internal electrodes 121 and 122 is not particularly limited, and any material having excellent conductivity may be used. For example, the internal electrodes 121 and 122 may include at least one of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0083] The capacitance of the multilayer capacitor 100 may be proportional to the overlapping area between the first internal electrode 121 and the second internal electrode 122 in the stacking direction (first direction), may be proportional to the total number of stackings of the first internal electrode 121 and the second internal electrode 122, and may be inversely proportional to the distance between the first internal electrode 121 and the second internal electrode 122.

[0084] When the distance between the first inner electrode 121 and the second inner electrode 122 is reduced, the multilayer capacitor 100 may have a higher capacitance without changing its thickness. Conversely, when the distance between the first inner electrode 121 and the second inner electrode 122 is increased, the multilayer capacitor 100 may have a higher withstand voltage. Therefore, the distance between the inner electrodes may be adjusted according to the specifications required for the multilayer capacitor 100 (e.g., miniaturization and / or high capacitance required for capacitors for electronic devices, high withstand voltage characteristics and / or excellent strength required for capacitors for electrical devices, etc.).

[0085] The body 110 may include cover portions 112 and 113 disposed on both surfaces of the capacitance forming portion in the first direction.

[0086] More specifically, the body 110 may include an upper cover portion 112 disposed on an upper portion of the capacitance forming portion in the first direction and a lower cover portion 113 disposed on a lower portion of the capacitance forming portion in the first direction.

[0087] The upper cover portion 112 and the lower cover portion 113 may be formed by stacking a single dielectric layer 111 or two or more dielectric layers 111 on the upper surface and the lower surface of the capacitor forming portion in the first direction, respectively, and may be mainly used to prevent damage to the internal electrodes 121 and 122 caused by physical stress or chemical stress.

[0088] The upper and lower cover portions 112 and 113 do not include the internal electrodes 121 and 122, and may include the same material as the dielectric layer 111. That is, the upper and lower cover portions 112 and 113 may include a ceramic material (eg, a barium titanate (BaTiO3)-based ceramic material).

[0089] The external electrodes 131 and 132 may be disposed on the body 110 and connected to the internal electrodes 121 and 122 .

[0090] More specifically, the external electrodes 131 and 132 may be disposed on the third surface 3 and the fourth surface 4 of the body 110, respectively, and may include a first external electrode 131 and a second external electrode 132 respectively connected to the first internal electrode 121 and the second internal electrode 122. That is, the first external electrode 131 may be disposed on the third surface 3 of the body and connected to the first internal electrode 121, and the second external electrode 132 may be disposed on the fourth surface 4 of the body and connected to the second internal electrode 122.

[0091] The external electrodes 131 and 132 may include any material having conductivity such as metal, etc. A specific material may be determined in consideration of electrical characteristics, structural stability, etc. The external electrodes 131 and 132 may have a multi-layered structure.

[0092] For example, the external electrodes 131 and 132 may include electrode layers 131 a and 132 a disposed on the body 110 and plating layers 131 b and 132 b disposed on the electrode layers 131 a and 132 a .

[0093] As more specific examples of the electrode layers 131 a and 132 a , the electrode layers 131 a and 132 a may be sintered electrodes including a conductive metal and glass, or may be resin-based electrodes including a conductive metal and resin.

[0094] In addition, the electrode layers 131 a and 132 a may be formed by sequentially forming a sintered electrode and a resin-based electrode on the body 110 .

[0095] In addition, the electrode layers 131 a and 132 a may be formed by transferring a sheet including a conductive metal onto the body 110 or by transferring a sheet including a conductive metal onto a sintered electrode.

[0096] The conductive metal used for the electrode layers 131a and 132a is not particularly limited as long as the conductive metal is a material that can be electrically connected to the internal electrodes 121 and 122 to form a capacitor. For example, the conductive metal may include at least one selected from the group consisting of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof. The electrode layers 131a and 132a may be formed by applying a conductive paste prepared by adding glass frit to conductive metal powder particles and then sintering the same.

[0097] Measurement Principle and Experimental Results of DC Bias Aging Characteristics of Multilayer Capacitors

[0098] Figure 6 is a schematic diagram showing changes in domain walls due to aging of a multilayer capacitor.

[0099] Reference Figure 6 , the dielectric grains G of the multilayer capacitor 100 may form domain walls DW by spontaneous polarization. After a long period of time at a temperature less than or equal to the Curie temperature (Tc) of the dielectric layer 111, the 180° domain walls DW may be rearranged into 90° domain walls DW' (a more stable form), resulting in a lower capacitance of the multilayer capacitor 100 due to a decrease in the dielectric constant.

[0100] This example embodiment may have the purpose of accurately predicting the saturation capacitance (which decreases after aging over a long period of time) of the multilayer capacitor 100 and utilizing the predicted saturation capacitance as a guarantee indicator, and may utilize the following principle: pre-applying a polarization voltage higher than the DC bias voltage for a predetermined period of time to expand the domain wall DW, and then applying a DC bias voltage to shrink the domain wall DW, so that the saturation capacitance is quickly reached under the actual use environment of the multilayer capacitor 100.

[0101] Figure 7 is a graph showing the results of measuring the voltage-current characteristics of the multilayer capacitor for each temperature.

[0102] Reference Figure 7 , when a DC voltage is applied to a multilayer capacitor at a specific temperature, in addition to aging characteristics under high voltage or high temperature conditions, variables caused by mechanical defects, insulation resistance (IR) degradation, or oxygen vacancies may also occur. Therefore, in the method for measuring the DC bias aging characteristics of a multilayer capacitor according to this example embodiment, the polarization voltage and temperature range are appropriately controlled to focus on the aging characteristics.

[0103] For example, the polarization voltage applied to the multilayer capacitor 100 is set to a DC voltage of less than 100 V, and the temperature is controlled to be less than 180°C.

[0104] Fig. 8A is a graph showing capacitance change due to aging when no DC bias voltage is applied to the multilayer capacitor.

[0105] Reference Fig. 8A , the capacitance of the multilayer capacitor when no DC bias voltage is applied to the multilayer capacitor can be described by an exponential decay function having the following formula.

[0106] [Formula 1]

[0107]

[0108] (t: aging time; A: measured variable (temperature, voltage, etc.); C t : capacitance at time t; C0: initial capacitance; k: aging rate).

[0109] Here, when measuring the aging rate k, the capacitance value for a specific period of time (usually 1000 hours to 2000 hours) may be used.

[0110] Figure 8B is a graph showing capacitance change due to aging when a DC bias voltage is applied to a multilayer capacitor.

[0111] When the general Figure 8B and Fig. 8A In comparison, since a DC bias voltage of 3.3 V is applied to the multilayer capacitor 100 , the capacitance may deviate from exponential decay and may be saturated at a certain point in time.

[0112] Such a result can be assumed to be because the domain walls DW within the dielectric grains G of the multilayer capacitor 100 are continuously combined with each other due to the application of the DC electric field or high temperature.

[0113] However, even when the time period required for the capacitance saturation of the multilayer capacitor 100 is reduced due to the application of a DC bias voltage or a high temperature, it may take 100 hours or more. Therefore, in order to predict the saturation capacitance in a short period of time, it may be necessary to observe changes in aging characteristics related to the DC bias voltage and temperature.

[0114] 9A to 9E is a TEM image showing the microstructure of the domain wall according to the temperature of the multilayer capacitor.

[0115] 9A to 9C The objects indicated by arrows are domain walls. 9A to 9E , it is observed that at temperatures greater than or equal to 100 °C, the number of domain walls decreases.

[0116] This phenomenon is related to the phase transition of the crystal structure of barium titanate (BaTiO3) included in the dielectric layer from tetrahedral to cubic. In the case of BaTiO3-based perovskite oxide (material included in the dielectric layer 111 of the multilayer capacitor 100 according to the present exemplary embodiment), some domain walls were observed even at 180°C.

[0117] Fig.10 is a graph showing capacitance change due to aging for each temperature when a DC bias voltage is applied to the multilayer capacitor.

[0118] Reference Fig.10 , the DC bias aging characteristics of multilayer capacitors were measured under various temperature conditions from 25°C to 180°C.

[0119] The time point at which the capacitance of the multilayer capacitor is saturated is measured for each temperature. At 180°C, the saturation characteristics of the capacitance are different compared to the remaining temperatures below 180°C. Therefore, when the DC bias aging characteristics of the multilayer capacitor are measured according to the present exemplary embodiment, 180°C is excluded and the experiment is performed under lower temperature conditions.

[0120] Fig.11 is a graph showing the capacitance of the multilayer capacitor when a polarization voltage of 30 V to 70 V is applied to the multilayer capacitor and the capacitance of the multilayer capacitor when a DC bias voltage of 3.3 V is applied at 25°C.

[0121] Reference Fig.11 , when the polarization voltage was applied to the multilayer capacitor 100, the capacitance of the multilayer capacitor 100 had a small value of less than 1 μF. When a DC bias voltage of 3.3 V was applied immediately after the polarization voltage was maintained for 20 minutes, the capacitance of the multilayer capacitor 100 was observed to be rapidly saturated.

[0122] The experiment was conducted at 25° C. When a polarization voltage of 30 V to 70 V was applied, the capacitance of the multilayer capacitor 100 (measurement target) rapidly aged in a short period of time without IR degradation.

[0123] Thereafter, the voltage was lowered and a DC bias voltage of 3.3 V was applied to measure the capacitance after depolarization, and it was observed that a saturation state was quickly reached within about 1000 seconds.

[0124] Fig.12 : is a graph showing the result of fitting the change in saturation capacitance of the multilayer capacitor due to the polarization voltage using an exponential decay function.

[0125] Reference Fig.12 , Fig.12 The exponential decay function is shown. Fig.11 The results of fitting the measured values ​​in , and the measured values ​​of the saturation capacitance of the multilayer capacitor according to the polarization voltage at a temperature of 25°C are shown. It can be seen from the curve that the saturation capacitance decreases as the polarization voltage increases. The saturation capacitance can be predicted by fitting an exponential decay function, thereby measuring the DC bias aging characteristics of the multilayer capacitor.

[0126] For example, in the method of measuring the DC bias aging characteristics of a multilayer capacitor according to a comparative example, after a DC bias voltage of 3.3V is applied to a multilayer capacitor having a capacitance of 9.19μF, the capacitance of the multilayer capacitor is immediately 5.66μF, and 100 hours after applying the DC bias voltage of 3.3V, the capacitance of the multilayer capacitor is 3.58μF.

[0127] In contrast, in the method of measuring the DC bias aging characteristics of the multilayer capacitor according to the present exemplary embodiment, when a polarization voltage of 40 V is applied for 20 minutes and then a DC bias voltage of 3.3 V is applied, the capacitance of the multilayer capacitor is saturated to 3.50 μF within 1000 seconds. Compared with the above comparative example, such a result can be an error rate of 2.23%.

[0128] Therefore, compared with the capacitance measured after applying the DC bias voltage for 100 hours in the above-mentioned comparative example, in the method of measuring the DC bias aging characteristics of the multilayer capacitor according to the present example embodiment, the saturation capacitance of the multilayer capacitor can be measured with high accuracy within a short period of time of 1 hour or less.

[0129] FIG. 13A to FIG. 13C Graph showing the capacitance of the multilayer capacitor when a polarization voltage of 30V to 70V is applied to the multilayer capacitor and the capacitance of the multilayer capacitor when a DC bias voltage of 3.3V is applied to the multilayer capacitor under various temperature conditions. FIG. 13A to FIG. 13CIn the figure, the solid curve represents the capacitance of the multilayer capacitor when a DC bias voltage of 3.3V is applied to the multilayer capacitor after a polarization voltage of 30V to 70V is applied to the multilayer capacitor, and the hollow curve represents the capacitance of the multilayer capacitor when a polarization voltage of 30V to 70V is applied to the multilayer capacitor.

[0130] Reference FIG. 13A to FIG. 13C , it was observed that the capacitance of the multilayer capacitor saturated faster as the temperature increased to 25° C., 75° C., and 125° C. This is because depolarization occurred rapidly due to the application of the DC bias voltage as the temperature increased.

[0131] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A method for measuring DC bias aging characteristics of a multilayer capacitor, the method comprising: applying a first polarization voltage to the multilayer capacitor, the multilayer capacitor comprising a body and an outer electrode, the body having a dielectric layer including a plurality of dielectric grains and inner electrodes arranged alternately with the dielectric layer in a first direction, the outer electrode being arranged on the body; maintaining the first polarization voltage for a first period of time; applying a DC bias voltage lower than the first polarization voltage to the multilayer capacitor; maintaining the DC bias voltage for a second period of time; and The saturation capacitance of the multilayer capacitor is measured.

2. The method according to claim 1, further comprising: After measuring the saturation capacitance of the multilayer capacitor, applying a second polarization voltage different from the first polarization voltage to the multilayer capacitor; maintaining the second polarization voltage for the first period of time; applying the DC bias voltage lower than the second polarization voltage to the multilayer capacitor; maintaining the DC bias voltage for the second time period; as well as The saturation capacitance of the multilayer capacitor is measured again.

3. The method according to claim 2, further comprising: The measured saturation capacitance and an exponential decay function are used to predict the saturation capacitance of the multilayer capacitor after DC bias aging.

4. The method according to claim 2, wherein: The first polarization voltage and the second polarization voltage are respectively greater than or equal to 30V and less than or equal to 70V.

5. The method according to claim 2, wherein: The first polarization voltage and the second polarization voltage have a voltage difference of 10V.

6. The method according to claim 1, wherein: The first polarization voltage is lower than a breakdown voltage of the multilayer capacitor.

7. The method according to claim 6, wherein: The first polarization voltage is 70% or less of the breakdown voltage of the multilayer capacitor.

8. The method according to claim 1, wherein: The DC bias voltage is greater than or equal to 1.8V and less than or equal to 3.3V.

9. The method according to claim 1, wherein: The first time period and the second time period are respectively 1 minute or longer.

10. The method according to claim 8, wherein: The first time period is 20 minutes.

11. The method according to claim 1, further comprising: Before applying the first polarization voltage to the multilayer capacitor, placing the multilayer capacitor in a temperature control unit; as well as The internal temperature of the temperature control unit is maintained at a specific temperature.

12. The method according to claim 11, wherein: The specific temperature is less than or equal to the Curie temperature of the dielectric layer.

13. The method according to claim 11, wherein: The specific temperature is less than 180°C.

14. The method according to claim 13, wherein: The specific temperature is greater than or equal to 25° C. and less than or equal to 125° C.

15. The method according to claim 1, wherein: The domain wall within the dielectric layer is expanded by applying the first polarization voltage to the multilayer capacitor.

16. The method according to claim 15, wherein: The domain walls within the dielectric layer are contracted by applying the DC bias voltage that is lower than the first polarization voltage.

17. The method according to claim 1, wherein: The dielectric layer includes a perovskite-based material having a crystal structure represented by a chemical formula ABO 3 .

18. The method according to claim 17, wherein: In the chemical formula ABO3, A includes one of barium, strontium and calcium.

19. The method according to claim 17, wherein: In the chemical formula ABO3, B includes one of titanium and zirconium.

20. A method for measuring DC bias aging characteristics of a multilayer capacitor, the method comprising: applying a first polarization voltage to the multilayer capacitor, the multilayer capacitor comprising a body and a first external electrode and a second external electrode, the body having a capacitance region, in which at least one first internal electrode and at least one second internal electrode are alternately stacked in a first direction, and at least one dielectric layer is interposed between the at least one first internal electrode and the at least one second internal electrode, the first external electrode and the second external electrode being disposed on the body at a distance from each other, and the first external electrode and the second external electrode being connected to the at least one first internal electrode and the at least one second internal electrode, respectively; measuring a first capacitance of the multilayer capacitor to which a DC bias voltage lower than the first polarization voltage is applied after applying the first polarization voltage; applying a second polarization voltage different from the first polarization voltage to the multilayer capacitor; measuring a second capacitance of the multilayer capacitor to which the DC bias voltage lower than the second polarization voltage is applied after applying the second polarization voltage; as well as A DC bias aging characteristic of the multilayer capacitor is determined based on the first polarization voltage and the second polarization voltage and the first capacitance and the second capacitance.

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