Artificial intelligence chip test system

Abstract

The embodiment of the invention provides an artificial intelligence chip test system. The artificial intelligence chip test system comprises a to-be-tested chip core board, a multifunctional test mainboard and a test case, the to-be-tested chip core board comprises a to-be-tested artificial intelligence chip; the multifunctional test mainboard is connected with the to-be-tested chip core board through an adaptive connector; and the test case is connected with the multifunctional test mainboard and is used for providing a test signal for the to-be-tested artificial intelligence chip through the multifunctional test mainboard and receiving a test result of the to-be-tested artificial intelligence chip for the test signal through the multifunctional test mainboard. The system can realize the test functions of various types of artificial intelligence chips, improve the test efficiency, and meet the test requirements of the chips in thermal and mechanical environments.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of artificial intelligence technology, and in particular, to an artificial intelligence chip testing system. Background Art

[0002] Artificial intelligence chips are the core of artificial intelligence technology. In the field of high-reliability applications, the performance and environmental adaptability evaluation of artificial intelligence chips has important research value. The current artificial intelligence chip testing system is generally only applicable to specific chips. Different chips require different test systems. It is not universal and the test efficiency is low. At the same time, it can only test the performance of the chip in a laboratory environment, and cannot test the adaptability of the chip in thermal, mechanical and other environments. Summary of the invention

[0003] In view of this, the purpose of the embodiments of the present application is to propose an artificial intelligence chip testing system to solve the testing problem of artificial intelligence chips.

[0004] Based on the above purpose, the embodiment of the present application provides an artificial intelligence chip testing system, including: a core board of a chip to be tested, a multi-function test mainboard and a test chassis;

[0005] The chip core board to be tested includes an artificial intelligence chip to be tested;

[0006] The multifunctional test mainboard is connected to the core board of the chip to be tested via an adapter connector;

[0007] The test chassis is connected to the multi-functional test mainboard, and is used to provide a test signal to the artificial intelligence chip to be tested through the multi-functional test mainboard, and to receive the test result of the artificial intelligence chip to be tested for the test signal through the multi-functional test mainboard.

[0008] Optionally, the test chassis includes a main controller and an interface test module, the main controller includes a test sequence editing module and a test program template management module, the test sequence editing module is used to generate a test sequence for testing the artificial intelligence chip to be tested, and the test program template management module is used to generate a test program for testing the artificial intelligence chip to be tested; the test chassis transmits the test sequence and test program to the core board of the chip to be tested through the interface test module and the test interface of the multi-functional test mainboard, so that the artificial intelligence chip to be tested executes the test sequence and test program, and transmits the execution result to the test chassis through the multi-functional test mainboard.

[0009] Optionally, the test sequence includes an upper electronic sequence, a computing power performance evaluation subsequence, an interface function test subsequence and a lower electronic sequence executed in sequence, and the test program includes an interface test program and a computing power test program; the upper electronic sequence is used to perform a power-on test on the multi-functional test mainboard and the core board of the chip to be tested, the computing power performance evaluation subsequence and the computing power test program are used to perform a computing power performance test on the artificial intelligence chip to be tested, the interface function test subsequence and the interface test program are used to perform an interface function test on the artificial intelligence chip to be tested, and the lower electronic sequence is used to perform a power-off test on the multi-functional test mainboard and the core board of the chip to be tested.

[0010] Optionally, the execution steps of the computing power performance evaluation subsequence include: transmitting the configured computing parameters and computing power test program to the artificial intelligence chip to be tested through the multi-functional test mainboard; if successful, controlling the oscilloscope card of the test chassis to start collecting the current signal of the artificial intelligence chip to be tested; if successful, sending a start test instruction to the computing power test program, the computing power test program feeds back the start test status, executes the computing task according to the computing parameters, and obtains the test results after execution from the artificial intelligence chip to be tested.

[0011] Optionally, the execution step of the computing power performance evaluation subsequence also includes: if unsuccessful, executing the next electronic sequence.

[0012] Optionally, the test chassis includes a power board, and the test chassis supplies power to the artificial intelligence chip to be tested through the power board, the power board connector of the multi-function test mainboard, and the power interface of the core board of the chip to be tested.

[0013] Optionally, the test chassis includes a data acquisition card, and the current signal and voltage signal during the operation of the artificial intelligence chip to be tested are transmitted to the data acquisition card through the data acquisition interface of the multifunctional test mainboard.

[0014] Optionally, the test interface of the multifunctional test mainboard includes multiple types, and the test chassis transmits a specific type of interface test signal through the interface test module to the corresponding type of interface of the artificial intelligence chip to be tested via the corresponding type of test interface.

[0015] Optionally, the core board of the chip to be tested is connected to the multifunctional test board via a high temperature resistant soft wire, and the core board of the chip to be tested is arranged in a temperature box.

[0016] Optionally, the core board of the chip to be tested is provided with a fixing hole for connecting to a vibration table.

[0017] From the above, it can be seen that in the artificial intelligence chip testing system provided by the embodiment of the present application, the test chassis provides a test signal for the artificial intelligence chip to be tested through a multifunctional test mainboard, and receives the test result of the artificial intelligence chip to be tested for the test signal through the multifunctional test mainboard. The system can support the testing of various types of artificial intelligence chips through hardware expansion and software platform configuration, has strong versatility and scalability, improves test efficiency, and can meet the test requirements of chips in thermal and mechanical environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A structural block diagram of a test system according to an embodiment of the present application;

[0020] Figure 2 A schematic diagram of the structure of a test system according to another embodiment of the present application;

[0021] Figure 3 This is a schematic diagram of the structure of a multifunctional test mainboard according to an embodiment of the present application;

[0022] Figure 4 This is a schematic diagram of the structure of the core board of the chip to be tested according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0024] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connecting" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to represent relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0025] like Figure 1 As shown, the embodiment of the present application provides an artificial intelligence chip testing system, including: a core board of a chip to be tested, a multi-functional testing mainboard and a testing chassis;

[0026] The core board of the chip to be tested, including the artificial intelligence chip to be tested;

[0027] The multifunctional test main board is connected to the core board of the chip to be tested through an adapter connector;

[0028] The test chassis is connected to the multi-functional test mainboard, and is used to provide a test signal to the artificial intelligence chip to be tested through the multi-functional test mainboard, and receive the test result of the artificial intelligence chip to be tested through the multi-functional test mainboard.

[0029] The artificial intelligence chip testing system provided in this embodiment includes a test chassis, a multi-functional test mainboard and a core board of the chip to be tested. The test chassis is connected to the core board of the chip to be tested through the multi-functional test mainboard. During the test, the test chassis provides relevant test signals to the artificial intelligence chip to be tested on the core board of the chip to be tested through the multi-functional test mainboard. The test results of the artificial intelligence chip to be tested are transmitted to the test chassis through the multi-functional test mainboard, and the test chassis further processes the test results. The test chassis can test different types of artificial intelligence chips to be tested.

[0030] like Figure 2 As shown, in some implementations, the test chassis uses a PXI test chassis, which is equipped with hardware units such as a main controller, a power board, a data acquisition card, an interface test module, a signal generator, an oscilloscope, and reserved slots, and each hardware unit is connected to the PXI bus backplane. The test chassis is used to provide power, clock signals, various interface test signals, various functional test signals, etc. to the core board of the chip to be tested through a multi-functional test mainboard, and at the same time receive the interface test signal results, functional test results, etc. of the artificial intelligence chip to be tested through the multi-functional test mainboard.

[0031] like Figure 3As shown, the multifunctional test mainboard includes a power board connector, a data acquisition interface, various types of test interfaces, etc.; the test chassis supplies power to the artificial intelligence chip to be tested through the power board card, the power board connector of the multifunctional test mainboard, and the power interface 10 of the core board of the chip to be tested. The clock board of the test chassis generates a clock signal, and the clock signal is input into the clock signal end of the artificial intelligence chip to be tested through the clock signal input end of the multifunctional test mainboard to provide a synchronous clock signal for the chip. The current signal and voltage signal during the operation of the artificial intelligence chip to be tested are transmitted to the data acquisition card through the data acquisition interface of the multifunctional test mainboard. The main controller can calculate the power consumption and other performance parameters of the chip based on the collected current signal and voltage signal, and the test chassis can use an oscilloscope to display the collected current signal waveform and voltage signal waveform.

[0032] The test chassis transmits a specific type of interface test signal to the corresponding type of interface 20 of the artificial intelligence chip to be tested through the interface test module via the corresponding type of test interface. In some embodiments, the interface types of the artificial intelligence chip to be tested include but are not limited to UART, SPI, IIC, PCIE, USB, ETH, HDMI, SATA, MIPI, RapidIO, etc. Correspondingly, the test interface of the multi-functional test motherboard includes a multi-functional IO card connector (supporting low-speed UART, IIC, SPI interface), PCIE test card interface, high-speed interface (supporting PCIE, HDMI, SATA, RapidIO, MIPI, etc.), USB interface, ETH interface and other types. The interface test module of the test chassis can perform relevant tests on the interface test items such as data input and output, input control signal, and read control results on the corresponding type of interface of the artificial intelligence chip to be tested through the corresponding type of test interface.

[0033] like Figure 4 As shown, in some embodiments, the core board of the chip to be tested is designed and configured according to the principle of the artificial intelligence chip to be tested, the connection relationship with the multifunctional test mainboard, etc., and the core board of the chip to be tested includes the minimum system composed of the artificial intelligence chip to be tested and its peripheral circuits. The adapter connector between the core board of the chip to be tested and the multifunctional test mainboard can be customized or universally designed according to the characteristics and test requirements of the artificial intelligence chip to be tested, so as to meet the test requirements of different chips to be tested.

[0034] In some methods, the test chassis adopts a modular design, which is universal and scalable. When the hardware resources of the test chassis and the multi-function test motherboard cannot meet the test requirements of the new type of artificial intelligence chip, the reserved slots of the chassis can be used to expand the hardware resources. Specifically, a test board for testing the new type of artificial intelligence chip is added to the reserved slots of the chassis, and the multi-function test motherboard for the new type of artificial intelligence chip is expanded at the same time. The core board of the chip to be tested is designed and configured for the new type of artificial intelligence chip, so as to meet the test requirements of the new type of artificial intelligence chip.

[0035] In some embodiments, in a laboratory environment, the core board of the chip to be tested is connected to the multifunctional test mainboard via an adapter connector (e.g., a board-to-board connector). When the artificial intelligence chip to be tested needs to be tested in a high temperature environment, the core board of the chip to be tested is connected to the multifunctional test mainboard via a high temperature resistant soft wire, and the core board of the chip to be tested is set in an incubator, the temperature of the incubator is adjustable, and the artificial intelligence chip to be tested is set in different temperature environments, so as to perform performance tests, functional tests, reliability tests, etc. on the artificial intelligence chip to be tested in different temperature environments, and test the environmental adaptability and reliability of the artificial intelligence chip to be tested.

[0036] In some embodiments, a fixing hole 30 for connecting to a vibration table is provided on the core board of the chip to be tested, and the core board of the chip to be tested can be fixedly connected to the vibration table through the fixing hole 30. The vibration frequency and vibration intensity of the vibration table can be adjusted, that is, the artificial intelligence chip to be tested is set in different mechanical environments, so as to realize performance testing, functional testing, reliability testing, etc. of the artificial intelligence chip to be tested under different force environments, and test the environmental adaptability and reliability of the artificial intelligence chip to be tested.

[0037] In some implementations, an operating system is installed on the main controller, and a software testing platform is installed on the system. The software testing platform includes a test sequence editing module, a test sequence execution module, a test program template management module, a tested chip management module, an SDK management module, a model and data set management module, a test report management module, a hardware test panel, a user management module and a database, etc.

[0038] Among them, the test sequence editing module provides a graphical editing and debugging environment for the test sequence. The test sequence editing module can be used to edit and generate a test sequence for testing the artificial intelligence chip under test. A complete test sequence consists of a sequence, a subsequence, a test item, and an execution step. According to the specific test item, the corresponding test sequence is configured in the debugging environment, and each step can be controlled to jump to the next step, a certain step, or stop execution according to the execution result or monitoring data after the execution is completed.

[0039] The test sequence execution module is used to control the hardware test platform (including various hardware units of the test chassis, the multi-functional test main board and the core board of the chip to be tested) to perform tests according to the test steps configured in the test sequence, obtain test result data (including the test results of the artificial intelligence chip to be tested, the test processing results after the main controller processes the test results, etc.), and generate a test report based on the test result data.

[0040] The test program template management module is used to download and manage different types of test program templates for different artificial intelligence chips. Different artificial intelligence chips may have different programming methods and operating environments. The test program template is used to provide basic program code and framework for artificial intelligence chips to be tested with similar architecture, the same programming environment, and the same test method, such as Python-based program templates, FPGA+C++-based program templates, etc. Based on the test program template, a test program can be written to generate a test program for testing artificial intelligence chips, thereby ensuring the unification of test programs for similar artificial intelligence chips, reducing the impact of code writing on test results, shortening development time, and improving test efficiency.

[0041] Among them, the test program written using the test program template is deployed in the artificial intelligence chip to be tested, and cooperates with the test sequence as a test item to complete the specific test function. The role of the test program template is to provide test procedures and basic codes for similar test items. Users can achieve the purpose of rapid development of test items by fine-tuning based on the model. For example, the computing power test program template performs operations based on operation parameters such as batch size, accuracy, framework, model, and data set, and the test obtains test result parameters such as inference delay, inference rate, throughput, accuracy, and computing power utilization. The test process includes data preprocessing, model inference, and parameter calculation. The basic code includes functions such as dataloader, dataprocessor, Loadmodel, Runmodel, and Caculate.

[0042] In some implementations, in order to implement computing power performance evaluation and interface function testing of artificial intelligence chips, the configured test sequence includes an upper electronic sequence, a computing power performance evaluation subsequence, an interface function test subsequence, and a lower electronic sequence that are executed in sequence, and the configured test program includes an interface test program and a computing power test program; the upper electronic sequence is used to perform a power-on test on the multifunctional test mainboard and the core board of the chip to be tested, the computing power performance evaluation subsequence and the computing power test program are used to perform a computing power performance test on the artificial intelligence chip to be tested, the interface function test subsequence and the interface test program are used to perform an interface function test on the artificial intelligence chip to be tested, and the lower electronic sequence is used to perform a power-off test on the multifunctional test mainboard and the core board of the chip to be tested. The specific test process includes:

[0043] Subsequence 1: Execute the electronic sequence, specifically the multi-function test mainboard and the core board of the chip to be tested. The steps are: set the power board parameters to 12V, 5A, the next step, enable the output, and if it is successful, jump to the next step (subsequence 2), otherwise stop the test sequence execution;

[0044] Subsequence 2: Computing performance evaluation subsequence, specifically for the configured operation parameters, including batch size, data set, precision, deep learning framework, neural network type, etc., for example, batch size is 8, int8 precision, Pytorch framework, Resnet50 network, Imagenet data set to perform chip performance test, the steps are: Step 1 deploys the operating parameters and computing power test program to the specified path of the file system of the artificial intelligence chip to be tested, and jumps to Step 2 if successful, otherwise jumps to subsequence 4; Step 2 controls the oscilloscope card to start collecting the current signal of the artificial intelligence chip to be tested, and jumps to S successfully tep3, otherwise jump to subsequence 4; Step 3 sends a start test instruction to the computing power test program in the artificial intelligence chip to be tested through the network port, and the computing power test program in the chip feedbacks the start test status, and the computing power test program performs the calculation task according to the specified calculation parameters; Step 4 obtains the forward reasoning delay, average reasoning rate, reasoning accuracy, throughput, computing power, computing power utilization and other test results of the model from the artificial intelligence chip to be tested through the network port, and sets a timeout of 60000ms. If the result is fed back within the timeout, Step 4 is performed. If there is no feedback within the timeout, jump to subsequence 4; Step 4 calculates the energy efficiency ratio according to the test results and current signal;

[0045] Subsequence 3: Interface function test subsequence, according to the interface type and test method of the artificial intelligence chip to be tested, transmits the interface test signal through the interface test module of the test chassis through the corresponding type of test interface to the corresponding interface of the artificial intelligence chip to be tested, and completes the interface test through the interface test program in the artificial intelligence chip to be tested and the interface function subsequence cooperates with each other.

[0046] Subsequence 4: the next electronic sequence, specifically, the multi-function test main board is powered on and the core board of the chip to be tested is powered off, the power board is set to disable output, and the power supply is stopped.

[0047] The chip management module under test is used to manage the relevant information of the artificial intelligence chip under test, including model specifications, manufacturer, packaging, detailed specifications, user manual, SDK version, test sequence and other information. The operations that can be performed on the relevant information include adding, editing, deleting, etc.

[0048] The model and dataset management module is used to manage the artificial intelligence models required for testing, the model's weight files, version information, computational complexity and other related information. The operations that can be performed on the model's related information include adding, editing, deleting, etc., and it can be uploaded and downloaded.

[0049] The SDK management module is used to manage SDK packages of different artificial intelligence chips, including uploading, downloading, and managing SDK package related information. It supports version control to ensure that users can easily switch to the required version of the SDK package. The relevant information of each SDK package includes the version number, release date, and update instructions. Users can choose the appropriate version according to their needs.

[0050] The test report management module is used to configure test report templates, export test reports, etc. The test report module is configured to ensure that the report content is accurate and well-structured. The report content includes the execution status of test cases, error information, performance indicators, summary and suggestions, etc. The export function allows users to export test reports to the required format.

[0051] The hardware test panel is used to test and debug hardware resources. For example, relevant control software is used to calibrate and test the core board of the chip to be tested, any hardware unit in the test chassis, and the multi-function test mainboard.

[0052] The user management module is used to manage account information and user permissions. Users can create, modify and delete account information, including user name, password, permission level, etc. Administrators can assign different permission levels to users (administrators, testers, ordinary users) to ensure system security and data confidentiality. Different permission levels have different system operation permissions. For example, ordinary users can only view test reports, while administrators can edit and delete reports.

[0053] The database is used to save various data files, including account information, AI chip-related information, tests and other structured data. For unstructured data such as files and SDK packages, a mapping relationship between database tables and physical addresses is established for storage and management.

[0054] In some embodiments, the steps of testing using the artificial intelligence chip testing system of the present application include: designing and configuring the core board of the chip to be tested according to the chip manual of the artificial intelligence chip to be tested and the connection relationship between the chip and the multi-functional test mainboard; connecting the core board of the chip to be tested to the test chassis through the multi-functional test mainboard, and if the artificial intelligence chip to be tested needs to be tested in a high temperature environment or a mechanical environment, placing the core board of the chip to be tested in an incubator or installing it on a vibration table; downloading and installing a suitable SDK package for the artificial intelligence chip to be tested to ensure the normal operation of the chip; setting the relevant information of the artificial intelligence chip to be tested on the software platform, configuring the corresponding test sequence according to the test requirements, executing the test sequence, and generating a test report based on the test result data fed back by the hardware test platform.

[0055] The artificial intelligence chip testing system provided in the embodiment of the present application includes a test chassis, a multi-functional test mainboard and a core board of the chip to be tested. The core board of the chip to be tested and the multi-functional test mainboard can be designed and configured according to the principles and characteristics of the artificial intelligence chip to be tested. The test chassis supports hardware expansion, which can not only realize the test of existing types of artificial intelligence chips to be tested, but also realize the test of new types of artificial intelligence chips to be tested through hardware expansion, thereby supporting the testing requirements of various types of artificial intelligence chips in hardware, and having strong versatility and expansibility; using the software testing platform, the operating environment and programming methods that support different types of artificial intelligence chips to be tested can be configured, thereby supporting the testing functions of various types of artificial intelligence chips in software, and at the same time, it can realize the automatic execution of the test sequence, improve the test efficiency, and meet the testing requirements of the chip in thermal and mechanical environments, which is of great significance to the application of artificial intelligence chips in the field of high reliability.

[0056] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0057] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented in the embodiments of the present application (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present disclosure, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0058] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description.

[0059] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present disclosure.

Claims

1. An artificial intelligence chip testing system, characterized in that: include: The core board of the chip to be tested, the multi-functional test mainboard and the test chassis; The chip core board to be tested includes an artificial intelligence chip to be tested; The multifunctional test mainboard is connected to the core board of the chip to be tested via an adapter connector; The test chassis is connected to the multi-functional test mainboard, and is used to provide a test signal to the artificial intelligence chip to be tested through the multi-functional test mainboard, and to receive the test result of the artificial intelligence chip to be tested for the test signal through the multi-functional test mainboard.

2. The system according to claim 1, characterized in that The test chassis includes a main controller and an interface test module. The main controller includes a test sequence editing module and a test program template management module. The test sequence editing module is used to generate a test sequence for testing the artificial intelligence chip to be tested. The test program template management module is used to generate a test program for testing the artificial intelligence chip to be tested. The test chassis transmits the test sequence and test program to the core board of the chip to be tested through the interface test module and the test interface of the multi-functional test mainboard, so that the artificial intelligence chip to be tested executes the test sequence and test program, and transmits the execution result to the test chassis through the multi-functional test mainboard.

3. The system according to claim 2, characterized in that The test sequence includes an upper electronic sequence, a computing power performance evaluation subsequence, an interface function test subsequence and a lower electronic sequence which are executed in sequence, and the test program includes an interface test program and a computing power test program; the upper electronic sequence is used to perform a power-on test on the multi-functional test mainboard and the core board of the chip to be tested, the computing power performance evaluation subsequence and the computing power test program are used to perform a computing power performance test on the artificial intelligence chip to be tested, the interface function test subsequence and the interface test program are used to perform an interface function test on the artificial intelligence chip to be tested, and the lower electronic sequence is used to perform a power-off test on the multi-functional test mainboard and the core board of the chip to be tested.

4. The system according to claim 3, characterized in that The execution steps of the computing power performance evaluation subsequence include: transmitting the configured computing parameters and computing power test program to the artificial intelligence chip to be tested through the multi-functional test mainboard; if successful, controlling the oscilloscope card of the test chassis to start collecting the current signal of the artificial intelligence chip to be tested; if successful, sending a start test instruction to the computing power test program, the computing power test program feeds back the start test status, executes the computing task according to the computing parameters, and obtains the test results after execution from the artificial intelligence chip to be tested.

5. The system according to claim 4, characterized in that The execution step of the computing power performance evaluation subsequence also includes: if unsuccessful, executing the next electronic sequence.

6. The system according to claim 1, characterized in that The test chassis includes a power board, and the test chassis supplies power to the artificial intelligence chip to be tested through the power board, the power board connector of the multi-functional test mainboard, and the power interface of the core board of the chip to be tested.

7. The system according to claim 1, characterized in that The test chassis includes a data acquisition card, and the current signal and voltage signal of the artificial intelligence chip to be tested during operation are transmitted to the data acquisition card through the data acquisition interface of the multifunctional test mainboard.

8. The system according to claim 2, characterized in that The test interfaces of the multifunctional test mainboard include multiple types, and the test chassis transmits a specific type of interface test signal through the interface test module to the corresponding type of interface of the artificial intelligence chip to be tested via the corresponding type of test interface.

9. The system according to claim 1, characterized in that The core board of the chip to be tested is connected to the multifunctional testing board via a high temperature resistant soft wire, and the core board of the chip to be tested is arranged in a temperature box.

10. The system according to claim 1, characterized in that The core board of the chip to be tested is provided with a fixing hole for connecting with the vibration table.

Images