WSTRB signal generation method and device, VIP and medium

Abstract

The invention discloses a WSTRB signal generation method and device, a VIP and a medium, and belongs to the field of signal processing. The method comprises the following steps: acquiring a first WSTRB signal, an AWADDR signal and an AWSIZE signal, wherein the first WSTRB signal is a WSTRB signal meeting address alignment and non-narrow transmission conditions; on the basis of the AWADDR signal, it is determined that write data transmission is carried out by the current write operation in a first transmission mode, and the first transmission mode comprises address alignment or address non-alignment; on the basis of the AWSIZE signal, it is determined that write data transmission is conducted in a second transmission mode in the current write operation, and the second transmission mode comprises non-narrow transmission or narrow-band transmission; and based on the first transmission mode and the second transmission mode, assigning a bit value on the first WSTRB signal to an effective bit position of the second WSTRB signal to obtain the second WSTRB signal. The invention provides a generation scheme of the WSTRB signal.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of signal processing, and in particular to a method, device, VIP and medium for generating a WSTRB signal. Background Art

[0002] AXI (Advanced Extensible Interface) bus is a high-performance bus of AMBA (Advanced Microcontroller Bus Architecture). AMBA bus defines the communication standard of system on chip (SoC chip). Verification IP (Verification Intellectual Property, VIP) is a verification component used to verify whether the function of the design under test (DUT) is correct.

[0003] When the user uses AXI VIP to issue a write operation to the DUT, the user needs to provide the WSTRB signal of the write data (WriteData) channel to the AXI VIP. One bit of the WSTRB signal indicates whether a byte in the write data bus carries valid data. A bit value of 0 indicates that the corresponding byte does not carry valid data, and a bit value of 1 indicates that the corresponding byte carries valid data.

[0004] In the related art, users need to calculate the WSTRB signal by themselves, which is cumbersome and error-prone. Summary of the invention

[0005] The present application provides a method, device, VIP and medium for generating a WSTRB signal, and provides a WSTRB signal generation solution. The technical solution is as follows:

[0006] According to one aspect of the present application, a method for generating a WSTRB signal is provided, the method comprising:

[0007] Acquire a first WSTRB signal, an AWADDR signal, and an AWSIZE signal, wherein the first WSTRB signal is a WSTRB signal that satisfies address alignment and non-narrow transmission conditions, and one bit of the WSTRB signal is used to determine whether a byte in a write data bus carries valid data or does not carry valid data;

[0008] Based on the AWADDR signal, determining that the current write operation adopts a first transmission mode for write data transmission, the first transmission mode includes address alignment or address non-alignment; and based on the AWSIZE signal, determining that the current write operation adopts a second transmission mode for write data transmission, the second transmission mode includes non-narrow transmission or narrowband transmission;

[0009] Based on the first transmission mode and the second transmission mode, assigning a bit value on the first WSTRB signal to a valid bit position of the second WSTRB signal to obtain the second WSTRB signal, wherein a bit at the valid bit position is used to determine that a byte in the write data bus carries valid data;

[0010] Among them, the AWADDR signal is used to indicate the first transmission address of a write operation, the AWSIZE signal is used to indicate the data size of each transmission, the non-narrow transmission indicates that the data size of each transmission is not less than the bit width of the write data bus, and the narrowband transmission indicates that the data size of each transmission is less than the bit width of the write data bus.

[0011] According to another aspect of the present application, a method for generating a WSTRB signal is provided, the method being performed by a verification intellectual property VIP, the method comprising:

[0012] Acquire a first WSTRB signal, an AWADDR signal, and an AWSIZE signal, wherein the first WSTRB signal is a WSTRB signal that satisfies address alignment and non-narrow transmission conditions, and one bit of the WSTRB signal is used to determine whether a byte in a write data bus carries valid data or does not carry valid data;

[0013] Based on the AWADDR signal, determining that the current write operation adopts a first transmission mode for write data transmission, the first transmission mode includes address alignment or address non-alignment; and based on the AWSIZE signal, determining that the current write operation adopts a second transmission mode for write data transmission, the second transmission mode includes non-narrow transmission or narrowband transmission;

[0014] Based on the first transmission mode and the second transmission mode, assigning a bit value on the first WSTRB signal to a valid bit position of the second WSTRB signal to obtain the second WSTRB signal, wherein a bit at the valid bit position is used to determine that a byte in the write data bus carries valid data;

[0015] Sending the second WSTRB signal to the design under test to verify the design under test;

[0016] Among them, the AWADDR signal is used to indicate the first transmission address of a write operation, the AWSIZE signal is used to indicate the data size of each transmission, the non-narrow transmission indicates that the data size of each transmission is not less than the bit width of the write data bus, and the narrowband transmission indicates that the data size of each transmission is less than the bit width of the write data bus.

[0017] According to another aspect of the present application, a device for generating a WSTRB signal is provided, the device comprising:

[0018] an acquisition module, used for acquiring a first WSTRB signal, an AWADDR signal and an AWSIZE signal, wherein the first WSTRB signal is a WSTRB signal satisfying address alignment and non-narrow transmission conditions, and one bit of the WSTRB signal is used for determining whether a byte in a write data bus carries valid data or does not carry valid data;

[0019] a determination module, configured to determine, based on the AWADDR signal, that a current write operation adopts a first transmission mode for write data transmission, wherein the first transmission mode includes address alignment or address non-alignment; and, based on the AWSIZE signal, determine that the current write operation adopts a second transmission mode for write data transmission, wherein the second transmission mode includes non-narrow transmission or narrowband transmission;

[0020] a processing module, configured to assign a bit value on the first WSTRB signal to a valid bit position of the second WSTRB signal based on the first transmission mode and the second transmission mode to obtain the second WSTRB signal, wherein a bit at the valid bit position is used to determine that a byte in the write data bus carries valid data;

[0021] Among them, the AWADDR signal is used to indicate the first transmission address of a write operation, the AWSIZE signal is used to indicate the data size of each transmission, the non-narrow transmission indicates that the data size of each transmission is not less than the bit width of the write data bus, and the narrowband transmission indicates that the data size of each transmission is less than the bit width of the write data bus.

[0022] According to another aspect of the present application, a device for generating a WSTRB signal is provided, the device comprising:

[0023] an acquisition module, used for acquiring a first WSTRB signal, an AWADDR signal and an AWSIZE signal, wherein the first WSTRB signal is a WSTRB signal satisfying address alignment and non-narrow transmission conditions, and one bit of the WSTRB signal is used for determining whether a byte in a write data bus carries valid data or does not carry valid data;

[0024] a determination module, configured to determine, based on the AWADDR signal, that a current write operation adopts a first transmission mode for write data transmission, wherein the first transmission mode includes address alignment or address non-alignment; and, based on the AWSIZE signal, determine that the current write operation adopts a second transmission mode for write data transmission, wherein the second transmission mode includes non-narrow transmission or narrowband transmission;

[0025] a processing module, configured to assign a bit value on the first WSTRB signal to a valid bit position of the second WSTRB signal based on the first transmission mode and the second transmission mode to obtain the second WSTRB signal, wherein a bit at the valid bit position is used to determine that a byte in the write data bus carries valid data;

[0026] A sending module, used for sending the second WSTRB signal to the design under test to verify the design under test;

[0027] Among them, the AWADDR signal is used to indicate the first transmission address of a write operation, the AWSIZE signal is used to indicate the data size of each transmission, the non-narrow transmission indicates that the data size of each transmission is not less than the bit width of the write data bus, and the narrowband transmission indicates that the data size of each transmission is less than the bit width of the write data bus.

[0028] According to one aspect of the present application, a VIP is provided, and the VIP is loaded and executed by a computer device to implement the WSTRB signal generation method as described above.

[0029] According to one aspect of the present application, a computer device is provided. The computer device includes a processor and a memory. The memory stores a computer program. The processor of the computer device loads and executes the computer program to implement the WSTRB signal generation method as described above.

[0030] According to another aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and the computer program is loaded and executed by a processor to implement the WSTRB signal generation method as described above.

[0031] According to another aspect of the present application, a computer program product is provided, the computer program product comprising computer instructions, the computer instructions being stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the WSTRB signal generation method provided in the above aspect.

[0032] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

[0033] By acquiring the first WSTRB signal corresponding to non-narrow transmission and address alignment conditions, and determining the first transmission mode of the current write operation based on the acquired AWADDR signal, determining the second transmission mode of the current write operation based on the acquired AWSIZE signal, and performing an assignment operation based on the first transmission mode and the second transmission mode in combination with the first WSTRB signal to generate a real second WSTRB signal.

[0034] The above provides a solution for generating a real second WSTRB signal through an assignment operation, and the user does not need to calculate the WSTRB signal by himself, thereby solving the problem of cumbersome operation and prone to errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 A schematic diagram showing a principle of generating a WSTRB signal provided by an exemplary embodiment;

[0037] Figure 2 A flowchart of a method for generating a WSTRB signal provided by an exemplary embodiment is shown;

[0038] Figure 3 A schematic diagram of transmitting in a manner of non-narrow transmission, address alignment, and burst type FIXED provided by an exemplary embodiment is shown;

[0039] Figure 4 A schematic diagram of an exemplary embodiment providing transmission in a manner of non-narrow transmission, address alignment, and a burst type of INCR is shown;

[0040] Figure 5 A schematic diagram of an exemplary embodiment providing transmission in a manner of non-narrow transmission, address alignment, and burst type WRAP is shown;

[0041] Figure 6 A schematic diagram of transmitting in a non-narrow transmission, non-aligned address, and FIXED burst type manner provided by an exemplary embodiment is shown;

[0042] Figure 7 A schematic diagram of an exemplary embodiment providing transmission in a manner of non-narrow transmission, non-aligned addresses, and a burst type of INCR is shown;

[0043] Figure 8 A schematic diagram of transmission in a manner of narrowband transmission, address alignment, and burst type FIXED provided by an exemplary embodiment is shown;

[0044] Fig. 9 A schematic diagram of transmission using narrowband transmission, address alignment, and a burst type of INCR provided by an exemplary embodiment is shown;

[0045] Fig.10 A schematic diagram of transmission using narrowband transmission, address alignment, and a burst type of WRAP is shown in an exemplary embodiment;

[0046] Fig.11 A schematic diagram of transmission using narrowband transmission, non-aligned addresses, and a burst type of FIXED is shown in an exemplary embodiment;

[0047] Fig.12 A schematic diagram of transmission using narrowband transmission, non-aligned addresses, and a burst type of INCR is shown in an exemplary embodiment;

[0048] Fig.13 A flowchart of a method for generating a WSTRB signal provided by another exemplary embodiment is shown;

[0049] Fig.14 A schematic diagram showing a method for generating a WSTRB signal provided by another exemplary embodiment;

[0050] Fig.15 A structural block diagram of a WSTRB signal generating device provided by an exemplary embodiment is shown;

[0051] Fig.16 A structural block diagram of a device for generating a WSTRB signal provided by another exemplary embodiment is shown. DETAILED DESCRIPTION

[0052] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0053] It should be understood that the "several" mentioned in this article refers to one or more, and "multiple" refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0054] First, the nouns involved in the embodiments of the present application are briefly introduced:

[0055] The AXI (Advanced Extensible Interface) bus is a high-performance bus of AMBA (Advanced Microcontroller Bus Architecture). The AMBA bus defines the communication standard for the system on chip (SoC chip). The AMBA bus includes AHB (Advanced High-performance Bus), ASB (Advanced System Bus), APB (Advanced Peripheral Bus), and AXI (Advanced eXtensible Interface). The above buses define a set of high-performance on-chip communication standards. The AXI bus defines the WSTRB signal, AWADDR signal, AWSIZE signal, AWBURST signal, and AWLEN signal in this application.

[0056] The WSTRB signal is defined in the AXI protocol as "Write strobes, indicating which byte lanes hold valid data", that is, one bit of the WSTRB signal is used to determine whether a byte in the write data bus carries valid data or does not carry valid data.

[0057] The AWADDR signal is defined in the AXI protocol as "The address of the first transfer in a write transaction", that is, the AWADDR signal is used to indicate the first transfer address of a write operation.

[0058] The AWSIZE signal is defined in the AXI protocol as "Size, the number of bytes in each data transfer in a write transaction", that is, the AWSIZE signal is used to indicate the data size (the number of bytes of data transferred) of each transfer in a write operation.

[0059] The AWBURST signal is defined in the AXI protocol as "Burst type, indicates how address changes between each transfer in a write transaction", that is, the AWBURST signal is used to indicate how the address changes between each burst transfer in a write operation.

[0060] The AWLEN signal is defined in the AXI protocol as "Length, the eaxct number of data transfers in a write transaction", that is, the AWLEN signal is used to indicate the number of transfers in a write operation.

[0061] VIP (Verification Intellectual Property) components, also referred to as Verification IP below, are used to verify the correctness of complex system-on-chip (SoC) design functions. VIP is used to verify whether the communication of the system-on-chip complies with the protocol standard. Common commercial VIPs include Synopsys and Cadence. This application provides a self-developed VIP that can automatically generate WSTRB signals.

[0062] Figure 1 FIG. 1 is a schematic diagram showing a principle of a method for generating a WSTRB signal provided by an exemplary embodiment of the present application. Figure 1 A verification IP (ie, VIP) 101 and a design under test (DUT) 102 are shown.

[0063] The user inputs the first WSTRB signal 103, the AWADDR signal 104 and the AWSIZE signal 105 to the verification IP 101. The verification IP 101 assigns the bit value of the first WSTRB signal 103 to the second WSTRB signal 106 to obtain the second WSTRB signal 106. The verification IP 101 sends the second WSTRB signal 106 to the design under test 102.

[0064] The first WSTRB signal 103 is a WSTRB signal that satisfies the address alignment and non-narrow transmission conditions, that is, the first WSTRB signal 103 is all 1. One bit of the WSTRB signal is used to determine whether a byte in the write data bus carries valid data or does not carry valid data. For example, the write data bus contains 32 bits (that is, 4 bytes), and the WSTRB signal is 4'b1000, which means that the first byte (counting from high to low) in the write data bus carries valid data, and the next three bytes (counting from high to low) do not carry valid data.

[0065] The AWADDR signal 104 is used to indicate the first transmission address of a write operation. For example, the AWADDR signal 104 is used to indicate that the first transmission address of the write operation is 0x01. Therefore, the AWADDR signal 104 can be used to indicate that the transmission is performed in an address-aligned or address-unaligned manner. The natural starting address is 0x00, and the first transmission address is 0x01, indicating that the transmission is performed in an address-unaligned manner.

[0066] AWSIZE signal 105 is used to indicate the data size of each transmission. For example, AWSIZE signal 105 is used to indicate that the data size of each transmission is 32 bits (i.e., 4 bytes). Therefore, AWSIZE signal 105 can be used to indicate whether to use narrowband transmission or non-narrowband transmission for transmission. For example, if the bit width of the write data bus is 32 bits and the data size of each transmission is 32 bits, it indicates that non-narrowband transmission is used for transmission. Non-narrow transmission indicates that the data size of each transmission is not less than the bit width of the write data bus, and narrowband transmission indicates that the data size of each transmission is less than the bit width of the write data bus.

[0067] Combined with reference Figure 1 , the verification IP 101 obtains the AWADDR signal 104, determines whether the current write operation is transmitted in an address-aligned or address-unaligned manner, and the verification IP 101 obtains the AWSIZE signal 105, determines whether the current write operation is transmitted in a narrowband transmission or a non-narrowband transmission manner. The verification IP 101 uses a corresponding assignment method according to the transmission mode used by the current write operation, and obtains a second WSTRB signal 106. Optionally, the user also inputs an AWBURST signal and an AWLEN signal to the verification IP 101, and the verification IP 101 determines whether to use or not use the AWBURST signal and the AWLEN signal to participate in the assignment calculation according to the transmission mode used by the current write operation. The AWBURST signal is used to indicate the burst type of the transmission. The AWLEN signal is used to indicate the number of transmissions (transmission beats).

[0068] It is understandable that the present application will determine the first transmission mode of the current write operation based on the acquired AWADDR signal, determine the second transmission mode of the current write operation based on the acquired AWSIZE signal, and perform an assignment operation based on the first transmission mode and the second transmission mode in combination with the first WSTRB signal to generate a real second WSTRB signal. The present application provides a solution for generating a real second WSTRB signal through an assignment operation, and the user does not need to calculate the WSTRB signal by himself, thereby solving the problem of cumbersome operation and easy error.

[0069] Figure 2 A flowchart of a method for generating a WSTRB signal provided by an exemplary embodiment of the present application is shown. The method can be performed by Figure 1 The following is an example of the method being executed by the verification IP, and the method includes:

[0070] Step 220, obtaining a first WSTRB signal, an AWADDR signal, and an AWSIZE signal, wherein the first WSTRB signal is a WSTRB signal that satisfies address alignment and non-narrow transmission conditions;

[0071] The AXI bus defines five independent channels: read address channel, read data channel, write address channel, write data channel and write response channel. The AXI bus currently supports bus widths of 8, 16, 32, 64, 128, 256, 512, and 1024 bits. The write data channel also transmits a data enable signal.

[0072] The WSTRB signal is a definition signal of the write data channel. One bit of the WSTRB signal is used to determine whether a byte in the write data bus carries valid data or does not carry valid data. For example, the write data bus contains 32 bits (i.e., 4 bytes), and the WSTRB signal is 4'b1000, which means that the first byte in the write data bus carries valid data, and the next three bytes do not carry valid data.

[0073] The first WSTRB signal is a WSTRB signal under non-narrowband transmission and address alignment conditions. The first WSTRB signal is all 1s. For example, if the write data bus width is 32 bits, the first WSTRB signal is 4'b1111; for example, if the write data bus width is 64 bits, the first WSTRB signal is 8'b1111 1111.

[0074] The AWADDR signal is a definition signal of the write address channel. The AWADDR signal is used to indicate the first transmission address of a write operation. For example, the AWADDR signal is used to indicate that the first transmission address of the write operation is 0x01. Therefore, the AWADDR signal can be used to indicate that the transmission is carried out in an address-aligned or address-unaligned manner. The natural starting address is 0x00, and the first transmission address is 0x01, which indicates that the transmission is carried out in an address-unaligned manner.

[0075] The AWSIZE signal is a definition signal of the write address channel. The AWSIZE signal is used to indicate the data size of each transmission. For example, the AWSIZE signal is used to indicate that the data size of each transmission is 32 bits (i.e., 4 bytes). Therefore, the AWSIZE signal can be used to indicate whether to use narrowband transmission or non-narrowband transmission. For example, if the bit width of the write data bus is 32 bits and the data size of each transmission is 32 bits, it indicates that non-narrowband transmission is used for transmission.

[0076] Step 240, based on the AWADDR signal, determining that the current write operation adopts a first transmission mode for write data transmission, the first transmission mode includes address alignment or address non-alignment; and based on the AWSIZE signal, determining that the current write operation adopts a second transmission mode for write data transmission, the second transmission mode includes non-narrow transmission or narrowband transmission;

[0077] The current write transaction includes multiple write transfers, for example, one write transaction includes four write transfers. Based on the AWADDR signal, it is determined whether the current write transaction is transmitted in an address-aligned or address-unaligned manner. Based on the AWSIZE signal, it is determined whether the current write transaction is transmitted in a narrowband transmission or a non-narrowband transmission manner. Among them, the non-narrowband transmission indicates that the data size of each transmission is not less than the bit width of the write data bus, and the narrowband transmission indicates that the data size of each transmission is less than the bit width of the write data bus.

[0078] Step 260, based on the first transmission mode and the second transmission mode, assign the bit value on the first WSTRB signal to the valid bit position of the second WSTRB signal to obtain the second WSTRB signal, and a bit at the valid bit position is used to determine whether a byte in the write data bus carries valid data.

[0079] According to the determined four transmission modes of non-narrowband transmission and address alignment, non-narrowband transmission and address non-alignment, narrowband transmission and address alignment, and narrowband transmission and address non-alignment, the bit value on the first WSTRB signal is assigned to the valid bit position of the second WSTRB signal.

[0080] To summarize, by acquiring the first WSTRB signal corresponding to the non-narrow transmission and address alignment conditions, and determining the first transmission mode of the current write operation based on the acquired AWADDR signal, and determining the second transmission mode of the current write operation based on the acquired AWSIZE signal, an assignment operation is performed based on the first transmission mode and the second transmission mode in combination with the first WSTRB signal to generate a real second WSTRB signal.

[0081] The above provides a solution for generating a real second WSTRB signal through an assignment operation, and the user does not need to calculate the WSTRB signal by himself, thereby solving the problem of cumbersome operation and prone to errors.

[0082] The following will introduce the assignment method performed based on the first transmission mode and the second transmission mode.

[0083] First, the first transmission mode is non-narrow transmission, and the second transmission mode is address alignment;

[0084] The current write operation includes multiple write transfers, and the multiple write transfers correspond to multiple second WSTRB signals one by one. For any one of the multiple write transfers, the first WSTRB signal is determined as the second WSTRB signal of the write transfer to obtain multiple second WSTRB signals of the multiple write transfers.

[0085] For the burst type of FIXED, refer to Figure 3 , Figure 3 The transmission diagram when the burst type is FIXED is shown, and FIXED indicates that the address of each write transmission is fixed. At this time, the bit width of the write data bus is 32 bits, and the current write operation includes four transmissions, that is, the burst length is 4, the first transmission address is 0x00, and the transmission size is 32 bits. Figure 3 The blank spaces in the WRITE DATA BUS indicate the bit positions that are used to transfer valid data.

[0086] For the burst type INCR, refer to Figure 4 , Figure 4 The transmission diagram when the burst type is INCR is shown, and INCR indicates that the address of each write transmission gradually increases. At this time, the bit width of the write data bus is 32 bits, and the current write operation includes four transmissions, that is, the burst length is 4, the first transmission address is 0x00, and the transmission size is 32 bits. Figure 4 The blank spaces in the WRITE DATA BUS indicate the bit positions that are used to transfer valid data.

[0087] For the burst type of WRAP, refer to Figure 5 , Figure 5The transmission diagram when the burst type is WRAP is shown. WRAP indicates that the address change mode is wrapping increment. At this time, the bit width of the write data bus is 32 bits, and the current write operation includes four transmissions, that is, the burst length is 4, the first transmission address is 0x04, and the transmission size is 32 bits. Figure 5 The blank spaces in the WRITE DATA BUS indicate the bit positions that are used to transfer valid data.

[0088] Through the above Figure 3 , 4 ,5. It can be observed that no matter the burst type is FIXED, INCR or WRAP, each write transfer occupies all the bit positions of the write data bus. Among them, the burst type FIXED, INCR or WRAP is indicated by the AWBURST signal, and the number of write transfers included in the current write operation is indicated by the AWLEN signal. Both signals are defined in the AXI protocol.

[0089] Therefore, for non-narrow transfers and address alignment, for any write transfer in multiple write transfers, the first WSTRB signal can be directly determined as the second WSTRB signal of the write transfer to obtain multiple second WSTRB signals of the multiple write transfers. For example, if the first WSTRB signal is 4'b1111, then the multiple second WSTRB signals of the multiple write transfers are all 4'b1111.

[0090] Second, the first transmission mode is non-narrow transmission, and the second transmission mode is address non-alignment;

[0091] The current write operation includes multiple write transfers, and the multiple write transfers correspond to multiple second WSTRB signals one by one. Due to address non-alignment, the multiple write transfers need to be divided into the first write transfer and other write transfers for separate consideration.

[0092] For the first write transfer in the multiple write transfers, based on the corresponding position of the valid bit on the write data bus on the second WSTRB signal of the first write transfer, combined with the bit value on the first WSTRB signal, the second WSTRB signal of the first write transfer is assigned, and the valid bit on the write data bus carries all the valid data in the first write transfer;

[0093] For any other write transfer except the first write transfer in the multiple write transfers, based on the burst type of the current write operation and in combination with the bit value of the first WSTRB signal, a second WSTRB signal of the other write transfer is assigned.

[0094] For the burst type of FIXED, refer to Figure 6 , Figure 6The transmission diagram under the burst type of FIXED is shown, and FIXED indicates that the address of each write transmission is fixed. At this time, the bit width of the write data bus is 32 bits, and the current write operation includes four transmissions, that is, the burst length is 4, the first transmission address is 0x01, and the transmission size is 32 bits. Figure 6 A blank cell in the middle indicates that the bit position of the write data bus is used to transmit valid data, and a gray cell indicates that the bit position of the write data bus is not used to transmit valid data.

[0095] At this time, for the first write transfer under the burst type of FIXED, the following assignment process is performed:

[0096] ① According to the AWADDR signal, determine the effective starting address of the first write transfer;

[0097] ② Determine the number of bytes that the write data bus can carry;

[0098] ③ Subtract the effective starting address from the number of bytes that can be carried to get the number of assignments;

[0099] ④ Starting from the 0th bit of the first WSTRB signal, corresponding to the effective starting address on the second WSTRB signal, the assignment is performed one byte at a time and the assignment is executed the number of times to obtain the second WSTRB signal of the first write transfer.

[0100] Illustratively, the effective starting address of the first write transfer is 0x01, and the number of bytes that can be carried by the write data bus is 4 (the bit width of the write data bus is 32 bits), then the number of bytes that can be carried by the write data bus minus the effective starting address, and the number of assignments is 3. The first WSTRB signal is 4'b1111, then starting from the rightmost "1", corresponding to the effective starting address 0x01 on the second WSTRB signal, one byte is assigned at a time and the assignment is performed 3 times, and the second WSTRB signal 4'b1110 of the first write transfer is obtained.

[0101] At this time, for other write transfers with the burst type of FIXED, the second WSTRB signal of the first write transfer is determined as the second WSTRB signal of other write transfers.

[0102] Therefore, multiple second WSTRB signals of multiple write transfers can be generated when the transfer is not narrow, the address is not aligned, and the burst transfer type is FIXED. The burst type FIXED is indicated by the AWBURST signal, and the number of write transfers included in the current write operation is indicated by the AWLEN signal, both of which are defined in the AXI protocol.

[0103] For the burst type INCR, refer to Figure 7 , Figure 7The transmission diagram under the burst type of INCR is shown, and INCR indicates that the address of each write transmission gradually increases. At this time, the bit width of the write data bus is 32 bits, and the current write operation includes four transmissions, that is, the burst length is 4, the first transmission address is 0x01, and the transmission size is 32 bits. Figure 7 A blank cell in the middle indicates that the bit position of the write data bus is used to transmit valid data, and a gray cell indicates that the bit position of the write data bus is not used to transmit valid data.

[0104] At this time, for the first write transfer under the burst type INCR, the following assignment process is performed:

[0105] ① According to the AWADDR signal, determine the effective starting address of the first write transfer;

[0106] ② Determine the number of bytes that the write data bus can carry;

[0107] ③ Subtract the effective starting address from the number of bytes that can be carried to get the number of assignments;

[0108] ④ Starting from the 0th bit of the first WSTRB signal, corresponding to the effective starting address on the second WSTRB signal, the assignment is performed one byte at a time and the assignment is executed the number of times to obtain the second WSTRB signal of the first write transfer.

[0109] Illustratively, the effective starting address of the first write transfer is 0x01, and the number of bytes that can be carried by the write data bus is 4 (the bit width is 32 bits), then the number of bytes that can be carried by the write data bus minus the effective starting address, and the number of assignments is 3. The first WSTRB is 4'b1111, then starting from the rightmost "1", corresponding to the effective starting address 0x01 on the second WSTRB signal, one byte is assigned at a time and the assignment is performed 3 times, and the second WSTRB signal 4'b1110 of the first write transfer is obtained.

[0110] At this time, for other write transfers with the burst type INCR, the first WSTRB signal is determined as the second WSTRB signal of other write transfers. If the first WSTRB is 4'b1111, the second WSTRB signals of other write transfers are all 4'b1111.

[0111] Therefore, multiple second WSTRB signals of multiple write transfers can be generated when the transfer is not narrow, the address is not aligned, and the burst transfer type is INCR. The burst type INCR is indicated by the AWBURST signal, and the number of write transfers included in the current write operation is indicated by the AWLEN signal, both of which are defined in the AXI protocol.

[0112] For the burst type of WRAP, the AXI protocol stipulates that the address must be aligned. Therefore, there is no need to consider the generation of the WSTRB signal in the case of non-narrow transfer, non-aligned address and WRAP burst transfer type.

[0113] Third, the first transmission mode is narrowband transmission, and the second transmission mode is address alignment;

[0114] The current write operation includes multiple write transfers, and the multiple write transfers correspond to multiple second WSTRB signals one by one. For any one of the multiple write transfers, based on the corresponding position of the valid bit group on the write data bus on the second WSTRB signal of the write transfer, combined with the bit value on the first WSTRB signal, the second WSTRB signal of the write transfer is assigned, and the valid bit group on the write data bus carries all valid data of the write transfer, and the valid bit group includes bytes of the narrow transfer byte number.

[0115] The write data bus is divided into multiple bit groups, each bit group includes bytes of the narrow transfer byte number. For example, if the bit width of the write data bus is 64 bits and the narrow transfer byte number is 4, the write data bus is divided into the upper 32 bits (as one bit group) and the lower 32 bits (as another bit group). For another example, if the bit width of the write data bus is 128 bits and the narrow transfer byte number is 4, the bit width of the write data bus is divided from low to high into the first bit group (including 32 bits), the second bit group (including 32 bits), the third bit group (including 32 bits) and the fourth bit group (including 32 bits).

[0116] Assume that the bit width of the write data bus is 64 bits, the lower 32 bits are used as a bit group, and the upper 32 bits are used as a bit group. Each bit group contains the bytes of the narrow transfer byte number, and the narrow transfer byte number is 4. The narrow transfer byte number indicates the data size of the write transfer (narrow transfer). In a write transfer, the bit group carrying all the valid data of the write transfer is the lower 32-bit bit group, which is called the valid bit group, and the valid bit group contains 4 bytes. The lower 32-bit group of the write data bus corresponds to the position of the lower 32 bits on the second WSTRB, and the lower 32 bits on the second WSTRB are assigned.

[0117] For the burst type of FIXED, refer to Figure 8 , Figure 8 The transmission diagram under the burst type of FIXED is shown, and FIXED indicates that the address of each write transmission is fixed. At this time, the bit width of the write data bus is 64 bits, and the current write operation includes four transmissions, that is, the burst length is 4, the first transmission address is 0x00, and the transmission size is 32 bits (that is, the number of narrow transmission bytes is 4). Figure 8A blank cell in the middle indicates that the bit position of the write data bus is used to transmit valid data, and a gray cell indicates that the bit position of the write data bus is not used to transmit valid data.

[0118] At this time, for any write transfer in multiple write transfers, determine the valid bit group on the write data bus corresponding to the valid bit group on the second WSTRB signal of the write transfer; and transparently transmit the bit value on the first WSTRB signal to the valid bit group on the second WSTRB signal.

[0119] Specifically, for the first write transfer, the valid bit group corresponding to the first write transfer is determined according to the first transfer address, and the bit value on the first WSTRB signal is transparently transmitted to the valid bit group on the second WSTRB signal. Since the valid bit group of each write transfer is the same under the FIXED type, the second WSTRB signal of the first write transfer is determined as the second WSTRB signal of other write transfers.

[0120] In one embodiment, the first transmission address is calculated and divided by the integer of the narrow transmission byte number to obtain the index number of the valid bit group, the valid bit group indicated by the same index number on the second WSTRB signal is determined, and the value transparent transmission is performed on the valid bit group.

[0121] For example, the first transmission address is 0x00, which is divided by the narrow transmission byte number 4 and rounded to obtain index number 0. The valid bit group indicated by index number 0 on the second WSTRB signal is determined, and value transparent transmission is performed on the valid bit group.

[0122] Therefore, multiple second WSTRB signals of multiple write transfers can be generated when narrow transfers are address aligned and the burst transfer type is FIXED. The burst type FIXED is indicated by the AWBURST signal, and the number of write transfers included in the current write operation is indicated by the AWLEN signal, both of which are defined in the AXI protocol.

[0123] For the burst type INCR, refer to Fig. 9 , Fig. 9 The transmission diagram under the burst type of INCR is shown, and INCR indicates that the address of each write transmission is gradually increased. At this time, the bit width of the write data bus is 64 bits, and the current write operation includes four transmissions, that is, the burst length is 4, the first transmission address is 0x00, and the transmission size is 32 bits (that is, the number of narrow transmission bytes is 4). Fig. 9 A blank cell in the middle indicates that the bit position of the write data bus is used to transmit valid data, and a gray cell indicates that the bit position of the write data bus is not used to transmit valid data.

[0124] At this time, for any write transfer in multiple write transfers, determine the valid bit group on the write data bus corresponding to the valid bit group on the second WSTRB signal of the write transfer; and transparently transmit the bit value on the first WSTRB signal to the valid bit group on the second WSTRB signal.

[0125] Specifically, for the first write transfer, the index number of the valid bit group corresponding to the first write transfer is calculated according to the first transfer address, and the bit value on the first WSTRB signal is transparently transmitted to the valid bit group corresponding to the index number of the first write transfer on the second WSTRB signal. In one embodiment, the first transfer address is calculated and divided by the integer of the number of narrow transfer bytes to obtain the index number of the valid bit group.

[0126] For the second write transfer, add 1 to the index number of the valid bit group of the first write transfer to obtain the index number of the valid bit group of the second write transfer, and determine the valid bit group of the second write transfer according to the index number; transparently transmit the bit value on the first WSTRB signal to the valid bit group on the second WSTRB signal of the second write transfer. And so on, until the index number value reaches the target value, which is equal to the number of bytes that can be accommodated by the write data bus divided by the transfer size (bytes) minus one, the index number value is counted as 0, and the assignment of the next write transfer is continued.

[0127] Indicative, Fig. 9 If the first transfer address is 0x00, the index number of the valid bit group (lower 32 bits) is 0, and the first write transfer is assigned to the lower 32 bits of the second WSTRB signal. For the second write transfer, the calculated index number is 1, and the second write transfer is assigned to the upper 32 bits of the second WSTRB signal. The number of bytes that the write data bus can accommodate (8) is calculated and divided by the transfer size (4) and then subtracted by 1, and the target value is 1. Therefore, it is determined that the index number value reaches the target value, and the index number value is counted as 0, and the third write transfer is assigned to the lower 32 bits of the second WSTRB signal.

[0128] Therefore, multiple second WSTRB signals of multiple write transfers can be generated when narrow transfers are address aligned and the burst transfer type is INCR. The burst type INCR is indicated by the AWBURST signal, and the number of write transfers included in the current write operation is indicated by the AWLEN signal, both of which are defined in the AXI protocol.

[0129] For the burst type of WRAP, refer to Fig.10 , Fig.10The transmission diagram under the burst type of WRAP is shown, and WRAP indicates that the address change mode is wrapping increment. At this time, the bit width of the write data bus is 64 bits, and the current write operation includes four transmissions, that is, the burst length is 4, the first transmission address is 0x04, and the transmission size is 32 bits (that is, the number of narrow transmission bytes is 4). Fig.10 A blank cell in the middle indicates that the bit position of the write data bus is used to transmit valid data, and a gray cell indicates that the bit position of the write data bus is not used to transmit valid data.

[0130] At this time, for any write transfer in multiple write transfers, determine the valid bit group on the write data bus corresponding to the valid bit group on the second WSTRB signal of the write transfer; and transparently transmit the bit value on the first WSTRB signal to the valid bit group on the second WSTRB signal.

[0131] Specifically, for the first write transfer, the index number of the valid bit group corresponding to the first write transfer is calculated according to the first transfer address, and the bit value on the first WSTRB signal is transparently transmitted to the valid bit group corresponding to the index number of the first write transfer on the second WSTRB signal. In one embodiment, the first transfer address is calculated and divided by the integer of the number of narrow transfer bytes to obtain the index number of the valid bit group.

[0132] For the second write transfer, add 1 to the index number of the valid bit group of the first write transfer to obtain the index number of the valid bit group of the second write transfer, and determine the valid bit group of the second write transfer according to the index number; transparently transmit the bit value on the first WSTRB signal to the valid bit group on the second WSTRB signal of the second write transfer. And so on, until the index number value reaches the target value, which is equal to the number of bytes that can be accommodated by the write data bus divided by the transfer size (bytes) minus one, the index number value is counted as 0, and the assignment of the next write transfer is continued.

[0133] Indicative, Fig.10 The first transfer address is 0x04, so the index number of the valid bit group (upper 32 bits) is 1, and the first write transfer is assigned to the upper 32 bits of the second WSTRB signal. The number of bytes that can be accommodated by the write data bus (8) is calculated and divided by the transfer size (4) and then minus 1, and the target value is 1. Therefore, it is determined that the index number value reaches the target value, the index number value is counted as 0, and the second write transfer is assigned to the lower 32 bits of the second WSTRB signal.

[0134] Therefore, multiple second WSTRB signals of multiple write transfers can be generated when narrowband transfer, address alignment and burst transfer type are WRAP. The burst type WRAP is indicated by the AWBURST signal, and the number of write transfers included in the current write operation is indicated by the AWLEN signal, both of which are defined in the AXI protocol.

[0135] In summary, the above text divides the bits contained in the write data bus into bit groups for narrowband transmission and address alignment, such as the upper 32 bits as a bit group and the lower 32 bits as a bit group. For any write transmission, the assignment operation will be performed according to the index number of the bit group, and one bit group will be assigned at a time. The above provides a generation scheme for the second WSTRB signal in the complex case of narrowband transmission and address alignment.

[0136] Fourth, the first transmission mode is narrowband transmission, and the second transmission mode is address non-alignment.

[0137] The current write operation includes multiple write transfers, and the multiple write transfers correspond to multiple second WSTRB signals one by one. Due to the non-alignment of the address, the first write transfer and the other write transfers need to be considered separately.

[0138] For the first write transfer in the multiple write transfers, based on the corresponding position of the valid bit on the write data bus on the second WSTRB signal of the first write transfer, combined with the bit value on the first WSTRB signal, the second WSTRB signal of the first write transfer is assigned, and the valid bit on the write data bus carries all the valid data in the first write transfer;

[0139] For any other write transfer except the first write transfer in multiple write transfers, the second WSTRB signal of the other write transfer is assigned based on the corresponding position of the valid bit group on the write data bus on the second WSTRB signal of the other write transfer and the bit value on the first WSTRB signal. The valid bit group on the write data bus carries all valid data of one other write transfer, and the valid bit group includes bytes of the narrow transfer byte number.

[0140] For the burst type of FIXED, refer to Fig.11 , Fig.11 The transmission diagram under the burst type of FIXED is shown, and FIXED indicates that the address of each write transmission is fixed. At this time, the bit width of the write data bus is 64 bits, and the current write operation includes four transmissions, that is, the burst length is 4, the first transmission address is 0x07, and the transmission size is 32 bits (that is, the number of narrow transmission bytes is 4). Fig.11A blank cell in the middle indicates that the bit position of the write data bus is used to transmit valid data, and a gray cell indicates that the bit position of the write data bus is not used to transmit valid data.

[0141] At this time, the assignment process for the first write transfer under the burst type of FIXED is as follows:

[0142] ① For the first write transfer in multiple write transfers, determine the effective starting address of the first transfer according to the AWADDR signal;

[0143] ② According to the AWSIZE signal, determine the number of narrow transfer bytes of the current write operation;

[0144] ③ Calculate the effective start address divided by the integer of the number of narrow transfer bytes to obtain the index of the first effective bit group of the write data bus. The effective bits on the write data bus are part of the bits in the first effective bit group. The first effective bit group includes bytes of the number of narrow transfer bytes.

[0145] ④ Calculate the modulus of the effective starting address divided by the number of narrow transfer bytes to obtain the effective starting position of the first effective bit group within the group; multiply the index of the first effective bit group by the number of narrow transfer bytes, and add the effective starting position within the group to obtain the assignment starting position;

[0146] ⑤ Subtract the effective starting position in the group from the number of narrow transmission bytes to obtain the number of assignments;

[0147] ⑥ Starting from the 0th bit of the first WSTRB signal, corresponding to the assignment start position on the second WSTRB signal, the assignment is performed one byte at a time and the assignment is executed the number of times to obtain the second WSTRB signal of the first write transfer.

[0148] Indicatively, the effective starting address of the first write transfer is 0x07, the number of narrow transfer bytes (i.e., transfer size) is 4 bytes, the index of the first effective bit group obtained by division and rounding is 1, and the effective starting position within the group of the first effective bit group obtained by division and modulo is 3. The calculated assignment starting position is 7. The number of narrow transfer bytes 4 minus the effective starting position within the group 3, the number of assignments is 1. The first WSTRB is 8'b 1111 1111, then starting from the rightmost "1", corresponding to the assignment starting address 0x07 on the second WSTRB signal, one byte is assigned at a time and the assignment is performed once, and the second WSTRB signal of the first write transfer is 8'b1000 0000.

[0149] At this time, for other write transfers with the burst type of FIXED, the second WSTRB signal of the first write transfer is determined as the second WSTRB signal of other write transfers.

[0150] Therefore, multiple second WSTRB signals of multiple write transfers can be generated when narrowband transfer, address non-alignment and burst transfer type is FIXED. The burst type FIXED is indicated by the AWBURST signal, and the number of write transfers included in the current write operation is indicated by the AWLEN signal, both of which are defined in the AXI protocol.

[0151] For the burst type INCR, refer to Fig.12 , Fig.12 The transmission diagram under the burst type of INCR is shown, and INCR indicates that the address of each write transmission is gradually increased. At this time, the bit width of the write data bus is 64 bits, and the current write operation includes five transmissions, that is, the burst length is 5, the first transmission address is 0x07, and the transmission size is 32 bits (that is, the number of narrow transmission bytes is 4). Fig.12 A blank cell in the middle indicates that the bit position of the write data bus is used to transmit valid data, and a gray cell indicates that the bit position of the write data bus is not used to transmit valid data.

[0152] At this time, the assignment process for the first write transfer under the burst type of FIXED is as follows:

[0153] ① For the first write transfer in multiple write transfers, determine the effective starting address of the first transfer according to the AWADDR signal;

[0154] ② According to the AWSIZE signal, determine the number of narrow transfer bytes of the current write operation;

[0155] ③ Calculate the effective start address divided by the integer of the number of narrow transfer bytes to obtain the index of the first effective bit group of the write data bus. The effective bits on the write data bus are part of the bits in the first effective bit group. The first effective bit group includes bytes of the number of narrow transfer bytes.

[0156] ④ Calculate the modulus of the effective starting address divided by the number of narrow transfer bytes to obtain the effective starting position of the first effective bit group within the group; multiply the index of the first effective bit group by the number of narrow transfer bytes, and add the effective starting position within the group to obtain the assignment starting position;

[0157] ⑤ Subtract the effective starting position in the group from the number of narrow transmission bytes to obtain the number of assignments;

[0158] ⑥ Starting from the 0th bit of the first WSTRB signal, corresponding to the assignment start position on the second WSTRB signal, the assignment is performed one byte at a time and the assignment is executed the number of times to obtain the second WSTRB signal of the first write transfer.

[0159] Indicatively, the effective starting address of the first write transfer is 0x07, the number of narrow transfer bytes (i.e., transfer size) is 4 bytes, the index of the first effective bit group obtained by division and rounding is 1, and the effective starting position of the first effective bit group obtained by division and modulo is 3. The calculated assignment starting position is 7. The number of narrow transfer bytes 4 minus the effective starting position 3 in the group, the number of assignments is 1. The first WSTRB is 8'b 1111 1111, then starting from the rightmost "1", corresponding to the assignment starting address 0x07 on the second WSTRB signal, one byte is assigned at a time and the assignment is performed once, and the second WSTRB signal of the first write transfer is 8'b1000 0000.

[0160] At this time, for other write transfers under the burst type of INCR, determine the valid bit group on the write data bus that corresponds to the valid bit group on the second WSTRB signal of other write transfers; starting from the 0th bit of the first WSTRB signal, corresponding to the 0th bit of the valid bit group on the second WSTRB signal, assign one byte at a time and execute the number of assignments indicated by the narrow transfer byte number to obtain the second WSTRB signal of other write transfers.

[0161] Specifically, the index number of the valid bit group corresponding to the first write transfer is calculated.

[0162] For the second write transfer, add 1 to the index number of the valid bit group of the first write transfer to obtain the index number of the valid bit group of the second write transfer, and determine the valid bit group of the second write transfer according to the index number; transparently transmit the bit value on the first WSTRB signal to the valid bit group on the second WSTRB signal of the second write transfer. And so on, until the index number value reaches the target value, which is equal to the number of bytes that can be accommodated by the write data bus divided by the transfer size (bytes) minus one, the index number value is counted as 0, and the assignment of the next write transfer is continued.

[0163] Indicative, Fig.12 The first transfer address is 0x07, so the index number of the valid bit group (upper 32 bits) of the first write transfer is 1, and the number of bytes that can be accommodated by the write data bus (8) is divided by the transfer size (4) and then minus 1, and the target value is 1. Therefore, it is determined that the index number value reaches the target value, the index number value is counted as 0, and the second write transfer is assigned to the lower 32 bits of the second WSTRB signal.

[0164] Therefore, multiple second WSTRB signals of multiple write transfers can be generated when narrowband transfer, address non-alignment and burst transfer type INCR are used. The burst type INCR is indicated by the AWBURST signal, and the number of write transfers included in the current write operation is indicated by the AWLEN signal, both of which are defined in the AXI protocol.

[0165] For the burst type of WRAP, the AXI protocol stipulates that the address must be aligned. Therefore, there is no need to consider the generation of the WSTRB signal when the narrow transfer, the address is not aligned, and the burst transfer type is WRAP.

[0166] In summary, the above text divides the bits contained in the write data bus into bit groups for narrowband transmission and address non-alignment, such as the upper 32 bits as a bit group and the lower 32 bits as a bit group, and the assignment operation is performed according to the index number of the bit group during calculation.

[0167] For the first write transfer, the assignment start position is calculated based on the index number and the valid start position in the group, and the number of assignments is calculated based on the valid start position in the group, and the assignment is performed in combination with the assignment start position and the number of assignments. For other write transfers, the bit group for each assignment is determined based on the index number. The above provides a generation scheme for the second WSTRB signal in the complex case of narrowband transmission and non-aligned addresses.

[0168] Fig.13 A flowchart of a method for generating a WSTRB signal provided by an exemplary embodiment of the present application is shown. Figure 1 The VIP execution shown is used as an example to illustrate that the method includes:

[0169] Step 1301, obtaining AWADDR, AWLEN, AWSIZE, and AWBURST signals;

[0170] VIP receives AWADDR, AWLEN, AWSIZE, and AWBURST signals. After receiving the write operation provided by the user, VIP parses the AWADDR signal to determine whether the current write operation is transmitted in an address non-aligned manner. If so, execute step 1302. If not, execute step 1303.

[0171] Step 1302, address non-alignment processing;

[0172] VIP obtains the effective byte address according to the AWADDR signal.

[0173] Step 1303, determining whether narrow transmission is required;

[0174] VIP parses the AWSIZE signal to determine whether the current write operation is transmitted in a narrow transmission mode. If not, execute step 1304. If yes, execute step 1307.

[0175] Step 1304, determine the burst type;

[0176] VIP parses the AWBURST signal and determines the burst type. If the burst type is FIXED, execute step 1305; if the burst type is non-FIXED (ie, INCR and WRAP), execute step 1306.

[0177] Step 1305, generation and processing of WSTRB under FIXED type;

[0178] If the address is aligned, the WSTRB provided by the user is directly passed through.

[0179] If the address is not aligned, the WSTRB value of each beat is the same, starting from the 0th bit of the WSTRB provided by the user, it is assigned to the new WSTRB, corresponding to the valid starting position of the unaligned address of the new WSTRB, and the number of assignments is the burst byte size minus the valid starting position of the unaligned address. The burst byte size is the number of bytes that the write data bus can accommodate. For example, if the bit width of the write data bus is 32 bits, the number of bytes that can be accommodated is 4.

[0180] Step 1306, generating and processing WSTRB under non-FIXED type;

[0181] If the address is aligned, the WSTRB provided by the user is directly passed through.

[0182] If the address is not aligned, the WSTRB corresponding to the first beat of data considers the address alignment, and starts from the 0th bit of the WSTRB provided by the user, and assigns it to the new WSTRB, corresponding to the valid starting position of the unaligned address of the new WSTRB. The number of assignments is the burst byte size minus the valid starting position of the unaligned address. The burst byte size is the number of bytes that the write data bus can accommodate. For example, if the bit width of the write data bus is 32 bits, the number of bytes that can be accommodated is 4. The WSTRBs of the remaining beats are the same, and the WSTRBs provided by the user are transparently transmitted.

[0183] Step 1307, narrow transmission processing;

[0184] VIP obtains the number of narrow transfer bytes according to the AWSIZE signal. For example, if the narrow transfer size is 32 bits, the number of narrow transfer bytes is 4.

[0185] Step 1308, determine the burst type;

[0186] VIP parses the AWBURST signal and determines the burst type. If the burst type is FIXED, execute step 1309; if the burst type is INCR, execute step 1310; if the burst type is WRAP, execute step 1311.

[0187] Step 1309, generation and processing of WSTRB under FIXED type;

[0188] If the address is aligned, the WSTRB provided by the user is directly passed through.

[0189] If the address is not aligned, when the burst type is FIXED, the WSTRB value of each beat is the same, starting from the 0th bit of the WSTRB provided by the user, and assigned to the new WSTRB, corresponding to the index number of its current narrow transfer plus the effective starting position of the current narrow transfer, and the number of assignments is the current narrow transfer size minus the effective starting position of the current narrow transfer.

[0190] Step 1310, generation and processing of WSTRB under INCR type;

[0191] If the address is aligned, the WSTRB provided by the user is directly passed through.

[0192] If the address is not aligned, the WSTRB corresponding to the first beat of data considers the address misalignment and is handled in the same way as the WSTRB of the FIXED type. Starting from the 0th bit of the WSTRB provided by the user, the value is assigned to the new WSTRB, corresponding to the index number of the current narrow transfer plus the valid starting position of the current narrow transfer, and the number of assignments is the current narrow transfer size minus the valid starting position of the current narrow transfer. The WSTRBs of the other beats of data are the same, starting from the 0th bit of the WSTRB provided by the user, the value is assigned to the 0th bit of the new WSTRB, and the number of assignments is the current narrow transfer size.

[0193] Step 1311, generation and processing of WSTRB under WRAP type.

[0194] If the addresses are aligned, the WSTRB value is the same for each beat. For the first beat, starting from the 0th bit of the WSTRB provided by the user, the value is assigned to the new WSTRB, corresponding to the index number position of its current narrow transfer, and the number of assignments is the current narrow transfer size.

[0195] Fig.14 A schematic diagram of an application environment provided by an exemplary embodiment of the present application is shown. Fig.14 A user input layer 1401 , an internal processing layer 1402 , and an output layer 1403 are shown.

[0196] User input layer 1401, the user provides the corresponding AWADDR, AWLEN, AWSIZE, and AWBURST values ​​according to the requirements of the write operation. In any case, the value of WSTRB is given according to the conditions of address alignment and non-narrow transfer. This step is completed by the personnel using the self-developed AXI VIP.

[0197] The internal processing layer 1402 completes the transparent transmission processing of WSTRB under the conditions of address alignment and non-narrow transmission, completes the automatic calculation of WSTRB under the conditions of address non-alignment and narrow transmission, and gives the real value. This part is implemented internally by the solution and is not perceived by the user.

[0198] The output layer 1403 generates a correct WSTRB value for the self-developed AXI VIP, and connects it to the AXI interface of the DUT (design under test) through the interface of the AXI VIP (verification IP) for use in the environment that calls the self-developed AXI VIP.

[0199] Some codes for implementing the method for generating the WSTRB signal provided by this application are given below.

[0200] The first section of code defines the bit width of the write data bus and calculates the number of bytes that the write data bus can accommodate.

[0201]

[0202]

[0203] The second code segment shows the assignment process of burst types FIXED and INCR when non-narrow transmission and non-aligned address are used for transmission.

[0204]

[0205]

[0206] The third code segment calculates the number of bit groups written to the data bus, the number of narrow transfer bytes, the index number of the valid bit group, and the valid starting position within the group.

[0207] beat_narrow_num = cfg.data_width / burst_bit_size; the number of bit groups of the write data bus

[0208] narrow_size = burst_bit_size / 8; narrow transmission byte number

[0209] beat_narrow_idx=unaligned_idx / narrow size; index of the valid bit group

[0210] beat_narrow_start=unaligned_idx%narrow_size; effective starting position within the group

[0211] The fourth code segment shows the assignment process of burst types FIXED and INCR when narrow transmission and non-aligned address are used for transmission.

[0212]

[0213]

[0214] The fifth code segment shows the assignment process of burst type WRAP when narrow transmission and address alignment are used for transmission.

[0215]

[0216]

[0217] Fig.15 A device for generating a WSTRB signal provided by an exemplary embodiment of the present application is shown, and the device includes:

[0218] An acquisition module 1501 is used to acquire a first WSTRB signal, an AWADDR signal and an AWSIZE signal, wherein the first WSTRB signal is a WSTRB signal that satisfies address alignment and non-narrow transmission conditions, and one bit of the WSTRB signal is used to determine whether a byte in a write data bus carries valid data or does not carry valid data;

[0219] The determination module 1502 is used to determine, based on the AWADDR signal, that the current write operation adopts a first transmission mode for write data transmission, where the first transmission mode includes address alignment or address non-alignment; and, based on the AWSIZE signal, determine that the current write operation adopts a second transmission mode for write data transmission, where the second transmission mode includes non-narrow transmission or narrowband transmission;

[0220] A processing module 1503 is used to assign the bit value on the first WSTRB signal to the valid bit position of the second WSTRB signal based on the first transmission mode and the second transmission mode to obtain the second WSTRB signal, wherein a bit at the valid bit position is used to determine that a byte in the write data bus carries valid data;

[0221] Among them, the AWADDR signal is used to indicate the first transmission address of a write operation, the AWSIZE signal is used to indicate the data size of each transmission, the non-narrow transmission indicates that the data size of each transmission is not less than the bit width of the write data bus, and the narrowband transmission indicates that the data size of each transmission is less than the bit width of the write data bus.

[0222] In an optional embodiment, the current write operation includes multiple write transfers, and the multiple write transfers correspond one-to-one to the multiple second WSTRB signals; the processing module 1503 is also used to, when the first transmission mode is narrowband transmission and the second transmission mode is address non-alignment, for the first write transfer in the multiple write transfers, based on the corresponding position of the valid bit on the write data bus on the second WSTRB signal of the first write transfer, combined with the bit value on the first WSTRB signal, assign the second WSTRB signal of the first write transfer, and the valid bit on the write data bus carries all valid data in the first write transfer;

[0223] For any other write transfer except the first write transfer in the multiple write transfers, the second WSTRB signal of the other write transfer is assigned based on the corresponding position of the valid bit group on the write data bus on the second WSTRB signal of the other write transfer and the bit value on the first WSTRB signal. The valid bit group on the write data bus carries all valid data of the other write transfers, and the valid bit group includes bytes of the narrow transfer byte number.

[0224] In an optional embodiment, the processing module 1503 is further configured to determine, for a first write transfer among multiple write transfers, a valid starting address of the first transfer according to the AWADDR signal;

[0225] According to the AWSIZE signal, determine the number of narrow transfer bytes of the current write operation;

[0226] Calculate the effective start address divided by the integer of the number of narrow transfer bytes to obtain the index of the first effective bit group of the write data bus, the effective bits on the write data bus are part of the bits in the first effective bit group, and the first effective bit group includes bytes of the number of narrow transfer bytes;

[0227] Calculate the modulus of the effective start address divided by the number of narrow transfer bytes to obtain the effective start position of the first effective bit group within the group; multiply the index of the first effective bit group by the number of narrow transfer bytes, and add the index to the effective start position within the group to obtain the assignment start position;

[0228] Subtract the effective starting position in the group from the number of narrow transfer bytes to get the number of assignments;

[0229] Starting from the 0th bit of the first WSTRB signal, corresponding to the assignment start position on the second WSTRB signal, the assignment is performed one byte at a time and the assignment is performed a number of times to obtain the second WSTRB signal of the first write transfer.

[0230] In an optional embodiment, the processing module 1503 is further configured to obtain an AWBURST signal for any other write transfer except the first write transfer among the multiple write transfers;

[0231] Determine the burst type of the current write operation based on the AWBURST signal;

[0232] When the burst type of the current write operation is FIXED, the second WSTRB signal of the first write transfer operation is determined as the second WSTRB signal of other write transfers, and FIXED indicates that the address of each write transfer is fixed;

[0233] When the burst type of the current write operation is INCR, determine the valid bit group on the write data bus that corresponds to the valid bit group on the second WSTRB signal of other write transfers; starting from the 0th bit of the first WSTRB signal, corresponding to the 0th bit of the valid bit group on the second WSTRB signal, assign one byte at a time and execute the number of assignments indicated by the narrow transfer byte number to obtain the second WSTRB signal of other write transfers, and INCR indicates that the address of each write transfer gradually increases.

[0234] In an optional embodiment, the current write operation includes multiple write transfers, and the multiple write transfers correspond one-to-one to multiple second WSTRB signals; the processing module 1503 is also used to, when the first transmission mode is narrowband transmission and the second transmission mode is address alignment, for any one of the multiple write transfers, based on the corresponding position of the valid bit group on the write data bus on the second WSTRB signal of the write transfer, combined with the bit value on the first WSTRB signal, assign the second WSTRB signal of the write transfer, the valid bit group on the write data bus carries all valid data of the write transfer, and the valid bit group includes bytes of the narrow transmission byte number.

[0235] In an optional embodiment, the current write operation includes multiple write transfers, and the multiple write transfers correspond one-to-one to multiple second WSTRB signals; the processing module 1503 is also used to, when the first transmission mode is non-narrow transmission and the second transmission mode is address alignment, for any write transfer among the multiple write transfers, determine the first WSTRB signal as the second WSTRB signal of the write transfer, and obtain multiple second WSTRB signals of the multiple write transfers.

[0236] In an optional embodiment, the current write operation includes multiple write transfers, and the multiple write transfers correspond one-to-one to the multiple second WSTRB signals; the processing module 1503 is also used to, when the first transmission mode is non-narrow transmission and the second transmission mode is address non-aligned, for the first write transfer in the multiple write transfers, based on the corresponding position of the valid bit on the write data bus on the second WSTRB signal of the first write transfer, combined with the bit value on the first WSTRB signal, assign the second WSTRB signal of the first write transfer, and the valid bit on the write data bus carries all valid data in the first write transfer;

[0237] For any other write transfer except the first write transfer in the multiple write transfers, based on the burst type of the current write operation and in combination with the bit value of the first WSTRB signal, a second WSTRB signal of the other write transfer is assigned.

[0238] In an optional embodiment, the processing module 1503 is further configured to determine, for a first write transfer among multiple write transfers, a valid starting address of the first write transfer according to the AWADDR signal;

[0239] Determine the number of bytes that can be carried by the write data bus; subtract the effective starting address from the number of bytes that can be carried to obtain the number of assignments;

[0240] Starting from the 0th bit of the first WSTRB signal, corresponding to the effective starting address on the second WSTRB signal, the value is assigned one byte at a time and the assignment is performed the number of times to obtain the second WSTRB signal of the first write transfer.

[0241] In an optional embodiment, the processing module 1503 is further configured to obtain an AWBURST signal for any other write transfer except the first write transfer among the multiple write transfers;

[0242] Determine the burst type of the current write operation based on the AWBURST signal;

[0243] When the burst type of the current write operation is FIXED, the second WSTRB signal of the first write transfer is determined as the second WSTRB signal of other write transfers, and FIXED indicates that the address of each write transfer is fixed;

[0244] In the case that the burst type of the current write operation is the INCR type, the first WSTRB signal is determined as the second WSTRB signal of other write transfers, and INCR indicates that the address of each write transfer is gradually increased.

[0245] To summarize, by acquiring the first WSTRB signal corresponding to the non-narrow transmission and address alignment conditions, and determining the first transmission mode of the current write operation based on the acquired AWADDR signal, and determining the second transmission mode of the current write operation based on the acquired AWSIZE signal, an assignment operation is performed based on the first transmission mode and the second transmission mode in combination with the first WSTRB signal to generate a real second WSTRB signal.

[0246] The above provides a device for generating a real second WSTRB signal through an assignment operation, and the user does not need to calculate the WSTRB signal by himself, thereby solving the problem of cumbersome operation and easy error.

[0247] Fig.16 A device for generating a WSTRB signal provided by an exemplary embodiment of the present application is shown, the device is loaded with VIP, and the device includes:

[0248] An acquisition module 1601 is used to acquire a first WSTRB signal, an AWADDR signal and an AWSIZE signal, wherein the first WSTRB signal is a WSTRB signal that satisfies address alignment and non-narrow transmission conditions, and one bit of the WSTRB signal is used to determine whether a byte in a write data bus carries valid data or does not carry valid data;

[0249] The determination module 1602 is used to determine, based on the AWADDR signal, that the current write operation adopts a first transmission mode for write data transmission, where the first transmission mode includes address alignment or address non-alignment; and, based on the AWSIZE signal, determine that the current write operation adopts a second transmission mode for write data transmission, where the second transmission mode includes non-narrow transmission or narrowband transmission;

[0250] A processing module 1603 is used to assign the bit value on the first WSTRB signal to the valid bit position of the second WSTRB signal based on the first transmission mode and the second transmission mode to obtain the second WSTRB signal, wherein a bit at the valid bit position is used to determine that a byte in the write data bus carries valid data;

[0251] The sending module 1604 is used to send the second WSTRB signal to the design under test to verify the design under test;

[0252] Among them, the AWADDR signal is used to indicate the first transmission address of a write operation, the AWSIZE signal is used to indicate the data size of each transmission, the non-narrow transmission indicates that the data size of each transmission is not less than the bit width of the write data bus, and the narrowband transmission indicates that the data size of each transmission is less than the bit width of the write data bus.

[0253] To summarize, by acquiring the first WSTRB signal corresponding to the non-narrow transmission and address alignment conditions, and determining the first transmission mode of the current write operation based on the acquired AWADDR signal, and determining the second transmission mode of the current write operation based on the acquired AWSIZE signal, an assignment operation is performed based on the first transmission mode and the second transmission mode in combination with the first WSTRB signal to generate a real second WSTRB signal.

[0254] The above provides a device for generating a real second WSTRB signal through an assignment operation, and the user does not need to calculate the WSTRB signal by himself, thereby solving the problem of cumbersome operation and easy error.

[0255] The present application also provides a VIP, which is loaded and executed by a computer device to implement the WSTRB signal generation method provided by the above method embodiment.

[0256] The present application also provides a computer device, which includes a processor and a memory. The memory stores a computer program, and the computer program is loaded and executed by the processor to implement the WSTRB signal generation method provided in the above method embodiment.

[0257] The present application also provides a computer-readable storage medium, in which at least one instruction, at least one program, code set or instruction set is stored. The at least one instruction, the at least one program, the code set or instruction set is loaded and executed by a processor to implement the WSTRB signal generation method provided in the above method embodiment.

[0258] The present application provides a computer program product, which includes a computer-readable storage medium. A processor of a computer device reads computer instructions from the computer-readable storage medium, and the processor of the computer device executes the computer instructions, so that the computer device executes the WSTRB signal generation method provided by the above method embodiment.

[0259] The serial numbers of the embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments. A person skilled in the art can understand that all or part of the steps of implementing the above embodiments can be completed by hardware, or can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium, and the above-mentioned storage medium can be a read-only memory, a disk or an optical disk, etc.

[0260] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for generating a WSTRB signal, characterized in that: The method comprises: Acquire a first WSTRB signal, an AWADDR signal, and an AWSIZE signal, wherein the first WSTRB signal is a WSTRB signal that satisfies address alignment and non-narrow transmission conditions, and one bit of the WSTRB signal is used to determine whether a byte in a write data bus carries valid data or does not carry valid data; Based on the AWADDR signal, determining that the current write operation adopts a first transmission mode for write data transmission, the first transmission mode includes address alignment or address non-alignment; and based on the AWSIZE signal, determining that the current write operation adopts a second transmission mode for write data transmission, the second transmission mode includes non-narrow transmission or narrowband transmission; Based on the first transmission mode and the second transmission mode, assigning a bit value on the first WSTRB signal to a valid bit position of the second WSTRB signal to obtain the second WSTRB signal, wherein a bit at the valid bit position is used to determine that a byte in the write data bus carries valid data; Among them, the AWADDR signal is used to indicate the first transmission address of a write operation, the AWSIZE signal is used to indicate the data size of each transmission, the non-narrow transmission indicates that the data size of each transmission is not less than the bit width of the write data bus, and the narrowband transmission indicates that the data size of each transmission is less than the bit width of the write data bus.

2. The method according to claim 1, characterized in that: The current write operation includes multiple write transfers, and the multiple write transfers correspond one-to-one to multiple second WSTRB signals; The step of assigning the bit value of the first WSTRB signal to the valid bit position of the second WSTRB signal based on the first transmission mode and the second transmission mode to obtain the second WSTRB signal includes: In the case where the first transmission mode is the narrowband transmission and the second transmission mode is the address non-alignment, for the first write transmission in the multiple write transmissions, based on the corresponding position of the valid bit on the write data bus on the second WSTRB signal of the first write transmission, combined with the bit value on the first WSTRB signal, the second WSTRB signal of the first write transmission is assigned, and the valid bit on the write data bus carries all valid data in the first write transmission; For any other write transfer except the first write transfer in the multiple write transfers, based on the corresponding position of the valid bit group on the write data bus on the second WSTRB signal of the other write transfer and combined with the bit value on the first WSTRB signal, the second WSTRB signal of the other write transfer is assigned, the valid bit group on the write data bus carries all valid data of the other write transfer, and the valid bit group includes bytes of the narrow transfer byte number.

3. The method according to claim 2, characterized in that For the first write transfer of the multiple write transfers, assigning a second WSTRB signal of the first write transfer based on a corresponding position of a valid bit on the write data bus on the second WSTRB signal of the first write transfer in combination with a bit value on the first WSTRB signal includes: For a first write transfer among the multiple write transfers, determining a valid starting address of the first transfer according to the AWADDR signal; Determine the number of narrow transfer bytes of the current write operation according to the AWSIZE signal; Calculate the effective start address divided by the integer of the narrow transfer byte number to obtain the index of the first effective bit group of the write data bus, the effective bits on the write data bus are part of the bits in the first effective bit group, and the first effective bit group includes bytes of the narrow transfer byte number; Calculate the modulus of the effective start address divided by the number of narrow transmission bytes to obtain the effective start position of the first effective bit group within the group; multiply the index of the first effective bit group by the number of narrow transmission bytes, and add the index to the effective start position within the group to obtain the assignment start position; Subtract the effective starting position in the group from the number of narrow transmission bytes to obtain the number of assignments; Starting from the 0th bit of the first WSTRB signal, corresponding to the assignment start position on the second WSTRB signal, the assignment is performed one byte at a time and the assignment times are performed to obtain the second WSTRB signal of the first write transfer.

4. The method according to claim 2, characterized in that: For any other write transfer except the first write transfer in the multiple write transfers, assigning a second WSTRB signal of the other write transfer based on a corresponding position of a valid bit group on the write data bus on the second WSTRB signal of the other write transfer in combination with a bit value on the first WSTRB signal, comprises: For any other write transfer except the first write transfer in the multiple write transfers, obtaining an AWBURST signal; Determining a burst type of the current write operation based on the AWBURST signal; In a case where the burst type of the current write operation is FIXED, determining the second WSTRB signal of the first write transfer operation as the second WSTRB signal of the other write transfers, wherein the FIXED indicates that the address of each write transfer is fixed; In the case where the burst type of the current write operation is INCR, determine the valid bit group on the write data bus that corresponds to the valid bit group on the second WSTRB signal of the other write transfer; starting from the 0th bit of the first WSTRB signal, corresponding to the 0th bit of the valid bit group on the second WSTRB signal, assign one byte at a time and execute the number of assignments indicated by the narrow transfer byte number to obtain the second WSTRB signal of the other write transfer, and the INCR indicates that the address of each write transfer gradually increases.

5. The method according to claim 1, characterized in that: The current write operation includes multiple write transfers, and the multiple write transfers correspond one-to-one to multiple second WSTRB signals; The step of assigning the bit value of the first WSTRB signal to the valid bit position of the second WSTRB signal based on the first transmission mode and the second transmission mode to obtain the second WSTRB signal includes: In the case where the first transmission mode is the narrowband transmission and the second transmission mode is the address alignment, for any one of the multiple write transmissions, based on the corresponding position of the valid bit group on the write data bus on the second WSTRB signal of the write transmission, combined with the bit value on the first WSTRB signal, the second WSTRB signal of the write transmission is assigned; the valid bit group on the write data bus carries all valid data of the write transmission, and the valid bit group includes bytes of the narrow transmission byte number.

6. The method according to claim 1, characterized in that The current write operation includes multiple write transfers, and the multiple write transfers correspond one-to-one to multiple second WSTRB signals; The step of assigning the bit value of the first WSTRB signal to the valid bit position of the second WSTRB signal based on the first transmission mode and the second transmission mode to obtain the second WSTRB signal includes: When the first transmission mode is the non-narrow transmission and the second transmission mode is the address alignment, for any one of the multiple write transmissions, the first WSTRB signal is determined as the second WSTRB signal of the write transmission to obtain multiple second WSTRB signals of the multiple write transmissions.

7. The method according to claim 1, characterized in that The current write operation includes multiple write transfers, and the multiple write transfers correspond one-to-one to multiple second WSTRB signals; The step of assigning the bit value of the first WSTRB signal to the valid bit position of the second WSTRB signal based on the first transmission mode and the second transmission mode to obtain the second WSTRB signal includes: In the case where the first transmission mode is the non-narrow transmission and the second transmission mode is the address non-alignment, for the first write transmission in the multiple write transmissions, based on the corresponding position of the valid bit on the write data bus on the second WSTRB signal of the first write transmission, combined with the bit value on the first WSTRB signal, the second WSTRB signal of the first write transmission is assigned, and the valid bit on the write data bus carries all valid data in the first write transmission; For any other write transfer except the first write transfer in the multiple write transfers, a second WSTRB signal of the other write transfer is assigned based on the burst type of the current write operation and in combination with the bit value of the first WSTRB signal.

8. The method according to claim 7, characterized in that For the first write transfer of the multiple write transfers, assigning a second WSTRB signal of the first write transfer based on a corresponding position of a valid bit on the write data bus on the second WSTRB signal of the first write transfer in combination with a bit value on the first WSTRB signal includes: For a first write transfer among the multiple write transfers, determining a valid starting address of the first write transfer according to the AWADDR signal; Determine the number of bytes that the write data bus can carry; subtract the effective start address from the number of bytes that can carry to obtain the number of assignments; Starting from the 0th bit of the first WSTRB signal, corresponding to the effective start address on the second WSTRB signal, the second WSTRB signal of the first write transfer is obtained by assigning one byte at a time and performing the assignment times.

9. The method according to claim 7, characterized in that: For any other write transfer except the first write transfer in the multiple write transfers, based on the burst type of the current write operation and in combination with the bit value on the first WSTRB signal, assigning a second WSTRB signal of the other write transfer includes: For any other write transfer except the first write transfer in the multiple write transfers, obtaining an AWBURST signal; Determining a burst type of the current write operation based on the AWBURST signal; In a case where the burst type of the current write operation is FIXED, determining the second WSTRB signal of the first write transfer as the second WSTRB signal of the other write transfers, wherein the FIXED indicates that the address of each write transfer is fixed; In the case that the burst type of the current write operation is an INCR type, the first WSTRB signal is determined as the second WSTRB signal of the other write transfers, and the INCR indicates that the address of each write transfer gradually increases.

10. A method for generating a WSTRB signal, characterized in that: The method is performed by verifying intellectual property rights VIP, and the method includes: Acquire a first WSTRB signal, an AWADDR signal, and an AWSIZE signal, wherein the first WSTRB signal is a WSTRB signal that satisfies address alignment and non-narrow transmission conditions, and one bit of the WSTRB signal is used to determine whether a byte in a write data bus carries valid data or does not carry valid data; Based on the AWADDR signal, determining that the current write operation adopts a first transmission mode for write data transmission, the first transmission mode includes address alignment or address non-alignment; and based on the AWSIZE signal, determining that the current write operation adopts a second transmission mode for write data transmission, the second transmission mode includes non-narrow transmission or narrowband transmission; Based on the first transmission mode and the second transmission mode, assigning a bit value on the first WSTRB signal to a valid bit position of the second WSTRB signal to obtain the second WSTRB signal, wherein a bit at the valid bit position is used to determine that a byte in the write data bus carries valid data; Sending the second WSTRB signal to the design under test to verify the design under test; Among them, the AWADDR signal is used to indicate the first transmission address of a write operation, the AWSIZE signal is used to indicate the data size of each transmission, the non-narrow transmission indicates that the data size of each transmission is not less than the bit width of the write data bus, and the narrowband transmission indicates that the data size of each transmission is less than the bit width of the write data bus.

11. A device for generating a WSTRB signal, characterized in that: The device comprises: an acquisition module, used for acquiring a first WSTRB signal, an AWADDR signal and an AWSIZE signal, wherein the first WSTRB signal is a WSTRB signal satisfying address alignment and non-narrow transmission conditions, and one bit of the WSTRB signal is used for determining whether a byte in a write data bus carries valid data or does not carry valid data; a determination module, configured to determine, based on the AWADDR signal, that a current write operation adopts a first transmission mode for write data transmission, wherein the first transmission mode includes address alignment or address non-alignment; and, based on the AWSIZE signal, determine that the current write operation adopts a second transmission mode for write data transmission, wherein the second transmission mode includes non-narrow transmission or narrowband transmission; a processing module, configured to assign a bit value on the first WSTRB signal to a valid bit position of the second WSTRB signal based on the first transmission mode and the second transmission mode to obtain the second WSTRB signal, wherein a bit at the valid bit position is used to determine that a byte in the write data bus carries valid data; Among them, the AWADDR signal is used to indicate the first transmission address of a write operation, the AWSIZE signal is used to indicate the data size of each transmission, the non-narrow transmission indicates that the data size of each transmission is not less than the bit width of the write data bus, and the narrowband transmission indicates that the data size of each transmission is less than the bit width of the write data bus.

12. A device for generating a WSTRB signal, characterized in that: The device is loaded with VIP, and the device comprises: an acquisition module, used for acquiring a first WSTRB signal, an AWADDR signal and an AWSIZE signal, wherein the first WSTRB signal is a WSTRB signal satisfying address alignment and non-narrow transmission conditions, and one bit of the WSTRB signal is used for determining whether a byte in a write data bus carries valid data or does not carry valid data; a determination module, configured to determine, based on the AWADDR signal, that a current write operation adopts a first transmission mode for write data transmission, wherein the first transmission mode includes address alignment or address non-alignment; and, based on the AWSIZE signal, determine that the current write operation adopts a second transmission mode for write data transmission, wherein the second transmission mode includes non-narrow transmission or narrowband transmission; a processing module, configured to assign a bit value on the first WSTRB signal to a valid bit position of the second WSTRB signal based on the first transmission mode and the second transmission mode to obtain the second WSTRB signal, wherein a bit at the valid bit position is used to determine that a byte in the write data bus carries valid data; A sending module, used for sending the second WSTRB signal to the design under test to verify the design under test; Among them, the AWADDR signal is used to indicate the first transmission address of a write operation, the AWSIZE signal is used to indicate the data size of each transmission, the non-narrow transmission indicates that the data size of each transmission is not less than the bit width of the write data bus, and the narrowband transmission indicates that the data size of each transmission is less than the bit width of the write data bus.

13. A VIP for verifying intellectual property rights, characterized in that: The VIP is loaded and executed by a computer device to implement the WSTRB signal generation method according to any one of claims 1 to 10.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is loaded and executed by a processor to implement the method for generating a WSTRB signal according to any one of claims 1 to 10.

15. A computer program product, characterized in that The computer program product comprises computer instructions, which are stored in a computer-readable storage medium. The computer instructions are loaded and executed by a processor to implement the method for generating a WSTRB signal according to any one of claims 1 to 10.

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