Interconnection device, host, host interconnection assembly, imaging system and acquisition method

Abstract

The embodiment of the invention provides an interconnection device, a host, a host interconnection assembly, an imaging system and an acquisition method, and the interconnection device comprises a first connector which is detachably inserted into a first interface of a first fnirs host; the second connector is detachably inserted into a second interface of the second fnirs host, and the second connector and the first connector have different dominant physical attributes; the cable connecting part is electrically connected with the first joint and the second joint, and under the condition that the first joint is inserted into a first interface of a first fnIRs host and the second joint is inserted into a second interface of a second fnIRs host, the first joint receives a first acquisition time sequence signal which is synchronously acquired from a first processing circuit part of the first fnIRs host; and the signal is transmitted to a second processing circuit part of the second fnirs host through the cable connecting part and the second joint. According to the scheme, the first connector and the second connector can be distinguished, and the main control host is specified by inserting the first connector.

Description

Technical Field

[0001] The present application relates to the field of near-infrared spectroscopy technology, and in particular to an interconnection device, a host, a host interconnection component, an imaging system and an acquisition method. Background Art

[0002] Functional near-infrared spectroscopy (fNIRS) uses the good scattering properties of the main components of blood to near-infrared light of 600-900nm to obtain the changes in oxygenated hemoglobin and deoxygenated hemoglobin (brain blood oxygen data) during brain activity.

[0003] This technology has begun to be used in the study of advanced cognition, developmental psychology, abnormal psychology and other fields in natural situations. As fNIRS equipment is more widely used in brain research, the number of brain locations and sites that are focused on for different application scenarios will also be different. Sometimes researchers will focus on fewer SD channels, and sometimes researchers will focus on more SD channels. Many users already have several low-channel fNIRS systems with low SD channels, such as Figure 1 As shown, a fNIRS system includes a head cap, an SD probe and cable, a fNIRS host also called an acquisition machine, and a host computer for receiving the acquired data and presenting the acquisition and analysis software interface.

[0004] When facing the application scenario of high SD channel count, instead of purchasing a new system with high SD channel count, users expect to be able to simply operate several existing low-channel fNIRS systems with low SD channel count to achieve the collection of brain detection data with high SD channel count. Moreover, users expect that this operation can be widely applicable to various existing low-channel fNIRS systems with low SD channel count, and minimize the cost of updating and modifying the existing low-channel fNIRS systems.

[0005] Multiple fNIRS systems can be interconnected via daisy chaining, for example, 2, 3, or 4 fNIRS mainframes can be connected to each other in a daisy chain mode, thereby measuring larger brain areas of interest, achieving higher density configurations, and realizing hyperscanning fNIRS measurements. The dorsal side of the fNIRS mainframe has cascade ports (flared ports A and B) such as Figure 2 As shown, one is connected to the upstream fnirs host and the other is connected to the downstream fnirs host to expand the number of SD detectors and channels.

[0006] At present, the interconnection device used for interconnecting FNIRS hosts in multiple FNIRS systems has the following defects. The interconnection device has two identical connectors and wires, that is, the two connectors connected by the interconnection device look the same, and the user cannot determine which FNIRS host is the master host, nor can he determine which corresponding host computer to go to to view the signal acquisition and analysis results. In addition, when a large number of FNIRS hosts are connected in series in daisy chain mode, the time delay between FNIRS hosts that are far away will be significantly increased. Summary of the invention

[0007] In view of this, the embodiments of the present application provide an interconnect device, a host, a host interconnect component, an imaging system and an acquisition method, so that a user can autonomously determine a master host among multiple interconnected fnirs hosts by plugging and unplugging the connectors of the interconnect device.

[0008] According to a first aspect of the present application, an interconnection device for an FNIRS host is provided, the interconnection device comprising a first connector, a second connector and a cable connection portion. The first connector is arranged at a first end of the interconnection device, and the first connector is configured to be removably plugged into a first interface of a first FNIRS host to be interconnected. The second connector is arranged at an opposite end of the first end, and the second connector has different dominant physical properties from the first connector, and the second connector is configured to be removably plugged into a second interface of a second FNIRS host to be interconnected. The cable connection portion is used to electrically connect the first connector and the second connector. Wherein, when the first connector is plugged into the first interface of the first FNIRS host and the second connector is plugged into the second interface of the second FNIRS host, the first connector receives a first acquisition timing signal of synchronous acquisition from a first processing circuit portion of the first FNIRS host, and transmits it to a second processing circuit portion of the second FNIRS host via the cable connection portion and the second connector, and the first acquisition timing signal at least indicates the start time of a series of acquisition cycles of synchronous acquisition.

[0009] According to a second aspect of the present application, a FNIRS host is provided. The FNIRS host includes a main processor, at least one interface, and a processing circuit unit separate from the main processor. The main processor is configured to control the acquisition of FNIRS detection signals. The at least one interface is configured to be inserted into a first connector or a second connector of an interconnection device for the FNIRS host. The processing circuit unit is configured to identify whether the connector inserted into the at least one interface is the first connector or the second connector. In the case of identifying that the inserted connector is the first connector, the processing circuit unit transmits a synchronously collected acquisition timing signal to the corresponding processing circuit unit of another interconnected FNIRS host via the at least one interface. In the case of identifying that the inserted connector is the second connector, the processing circuit unit receives another synchronously collected acquisition timing signal from the corresponding processing circuit unit of another interconnected FNIRS host via the at least one interface.

[0010] The main processor is further configured to: when the processing circuit unit receives the other acquisition timing signal, receive the other acquisition timing signal from the processing circuit unit, and use the other acquisition timing signal to perform synchronous acquisition of the FNIRS detection signal. The main processor is further configured to: when the processing circuit unit transmits the acquisition timing signal for synchronous acquisition to the outside, use the acquisition timing signal for synchronous acquisition transmitted to the outside to perform synchronous acquisition of the FNIRS detection signal, and the acquisition timing signal at least indicates the start time of a series of acquisition cycles of synchronous acquisition.

[0011] According to a third aspect of the present application, a fnirs host interconnection component is provided, the fnirs host interconnection component comprising: at least two fnirs hosts of any one of the various embodiments of the present application; and an interconnection device of any one of the various embodiments of the present application, wherein the interconnection device is configured to interconnect the at least two fnirs hosts.

[0012] According to a fourth aspect of the present application, a fnirs imaging system is provided, the fnirs imaging system comprising: any one of the fnirs host interconnection components in the various embodiments of the present application; and a probe group connected to and used in conjunction with each fnirs host, the probe group comprising a transmitting probe and a receiving probe. Each probe group matched with each fnirs host has a first number of channels, wherein each fnirs host is configured to control the corresponding probe group to synchronously collect detection data of a second number of channels based on a first acquisition timing signal of the first fnirs host connected to the first connector, and the second number of channels is greater than the first number of channels.

[0013] According to a fifth aspect of the present application, a method for collecting detection data with a higher number of channels by interconnecting at least two FNIRS devices is provided, wherein each FNIRS device includes a probe group and any one of the FNIRS hosts in the various embodiments of the present application connected to and used in conjunction with the probe group, and each probe group matched with each FNIRS host includes a transmitting probe and a receiving probe. The method includes the following steps.

[0014] The at least two FNIRS devices are interconnected by any one of the interconnection devices in the various embodiments of the present application, wherein the first connector of the interconnection device is inserted into the first interface of the FNIRS host serving as the master host in the at least two FNIRS devices, and the second connector of the interconnection device is inserted into the second interface of the FNIRS host serving as the slave host in the at least two FNIRS devices.

[0015] Each probe group is put on the subject's head through the same head cap. Please note that the order of the fNIRS host interconnection operation and the head cap wearing operation is not restricted.

[0016] Each fnirs host as the master host and the slave host controls the transmitting probe and the receiving probe of the corresponding probe group to synchronously collect detection data based on the first acquisition timing signal of the fnirs host of the master host, so as to obtain detection data with a higher number of channels.

[0017] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the embodiments of the present application are as follows. Through the different explicit physical properties of the second connector and the first connector of the interconnection device, the user can distinguish which connector is the first connector and which connector is the second connector, and the first connector is configured to be detachably plugged into the first interface of the first fnirs host to be interconnected, that is, the user plugs the first connector into which fnirs host, which fnirs host is used as the master host, and the second connector is configured to be detachably plugged into the second interface of the second fnirs host to be interconnected, that is, the user plugs the second connector into which fnirs host, which fnirs host is used as the slave host. In other words, the user can autonomously plug the first connector into the fnirs host that needs to be the master host according to the distinguished first connector and the second connector, according to different interconnection requirements, so as to realize that the fnirs host that needs to be the master host can be flexibly specified or clarified by plugging the first connector, which is conducive to knowing and clarifying the master host, and then it is conducive to clarifying which fnirs host is connected to the host computer to view the signal acquisition and analysis results. Through the hardware transmission between the first connector and the processing circuit part of the master host, and the hardware transmission between the second connector and the processing circuit part of the slave host, the transmitted acquisition timing signal may at least only include the start time of a series of acquisition cycles of synchronous acquisition (the start time of the first acquisition cycle), or may include the start time of each acquisition cycle. The amount of transmitted data is very small and it is hardware transmission, which can significantly reduce the delay between the interconnected fnirs hosts (for example, controlling the delay to less than 10 microseconds). BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 is a schematic diagram of an existing fNIRS system provided in an embodiment of the present application; Figure 2 It is a schematic diagram of the back side of an existing fNIRS host provided by an embodiment of the present application; Figure 3 It is a structural schematic diagram of an interconnection device for an fnirs host provided in an embodiment of the present application; Figure 4 It is a structural block diagram of an FNIRS host interconnected through an interconnection device provided in an embodiment of the present application; Figure 5It is a timing diagram of a synchronous acquisition timing signal between interconnected FNIRS hosts provided in an embodiment of the present application; Figure 6 It is a schematic diagram of the docking structure of an interface-connector when an explicit physical attribute is a circuit parameter provided in an embodiment of the present application; Figure 7 It is a structural schematic diagram of an interconnection device with multiple second connectors for an fnirs host provided by an embodiment of the present application; Figure 8 It is a schematic diagram of a star topology structure of an FNIRS host interconnection component provided by an embodiment of the present application; Fig. 9 It is a flow chart of a method for collecting detection data with a higher number of channels by interconnecting at least two FNIRS devices provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0021] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0022] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "said" and "the" used in the various embodiments of the present application are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in the various embodiments of the present application refers to and includes any or all possible combinations of one or more associated listed items.

[0023] It should be understood that although the terms first, second, third, etc. may be used to describe various information in various embodiments of the present application, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this specification, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "under the circumstances of..." or "when..." or "determined in response to...".

[0024] Furthermore, the drawings are schematic illustrations only and are not necessarily drawn to scale. The block diagrams shown in the drawings are merely functional entities and do not necessarily correspond to physically independent entities unless the context makes physical independence clear. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0025] In an embodiment of the present application, an interconnection device for an fnirs host is provided. Figure 3 As shown, the interconnection device for the fnirs host includes a first connector 401, a second connector 402 and a cable connecting portion 403 for electrically connecting the first connector 401 and the second connector 402.

[0026] The first connector 401 is arranged at the first end of the interconnection device, and the first connector 401 is configured to be detachably plugged into the first interface of the first fnirs host to be interconnected. The user expects which host to be the master host in the interconnection, and the host is used as the first fnirs host.

[0027] The second connector 402 is arranged at the opposite end of the first end, and the second connector 402 has different dominant physical properties from the first connector 401, and the second connector 402 is configured to be detachably plugged into the second interface of the second FNIRS host to be interconnected. The user expects which host to be the slave host in the interconnection, and the host is used as the second FNIRS host.

[0028] When the first connector 401 is plugged into the first interface of the first FNIRS host and the second connector 402 is plugged into the second interface of the second FNIRS host, the first connector 401 receives a first acquisition timing signal of synchronous acquisition from the first processing circuit unit of the first FNIRS host, and transmits it to the second processing circuit unit of the second FNIRS host via the cable connection unit 403 and the second connector 402, wherein the first acquisition timing signal at least indicates the start time of a series of acquisition cycles of synchronous acquisition.

[0029] In some embodiments, Figure 4 As shown, the first fnirs host 700a and the second fnirs host 700b are connected via Figure 3 The interconnection device for the FNIRS host is interconnected, the first FNIRS host 700a includes a first main processor 701a, a first processing circuit unit 702a and at least one first interface 703a, the second FNIRS host 700b includes a second main processor 701b, a second processing circuit unit 702b and at least one second interface 703b, the first connector 401 of the interconnection device is inserted into the first interface 703a, so that the first FNIRS host 700a is used as a master host, and the second connector 402 of the interconnection device is inserted into the second interface 703b, so that the second FNIRS host 700b is used as a slave host, the first connector 401 receives the first acquisition timing signal of synchronous acquisition from the first processing circuit unit 702a of the first FNIRS host 700a, and transmits it to the second processing circuit unit 702b of the second FNIRS host 700b via the cable connection unit 403 and the second connector 402, and then the second main processor 701b receives the first acquisition timing signal from the second processing circuit unit 702b, and uses the first acquisition timing signal to start acquisition according to the respective SD sub-arrangement timing configuration information, so as to start acquisition synchronously with the first FNIRS host 700a.

[0030] In some embodiments, after multiple fnirs hosts are interconnected through an interconnection device for interconnecting devices, the host computer interacts with each interconnected fnirs host so that each fnirs host knows the SD sub-arrangement timing configuration information connected to each fnirs host (i.e., which transmitting probe of all interconnected SD channels the light source of each fnirs host is connected to, the timing of lighting each light source, the lighting duration of each light source, etc.) Figure 5 As shown, Figure 5 The timing information of the thin lines in the middle is the SD sub-arrangement timing configuration information of each fnirs host, and it is known that the synchronous acquisition should be run according to this interconnection mode, that is, the acquisition timing signal transmitted by the master host in the interconnection is used as the synchronous acquisition instruction to start the respective synchronous acquisition mode. Therefore, after each slave host knows its own SD sub-arrangement timing configuration information, as long as it knows the synchronous acquisition start instruction (such as the "first acquisition timing signal" mentioned above), it can autonomously start to execute the lighting / detection of its own S / D probe. When the upper computer sends the first acquisition timing signal of synchronous acquisition to the master host, the processing circuit part of the master host transmits the first acquisition timing signal ( Figure 5The dotted line in the figure is a first acquisition timing signal in the form of a rising edge, the timing signal in the bold line is a periodic first acquisition timing signal including a rising edge, and the moment shown by the dotted line is also the moment when the master host sends the acquisition timing signal) which is transmitted to the processing circuit part of each slave host, so that each slave host can start acquisition based on the first acquisition timing signal according to its own SD sub-arrangement timing configuration information, so as to start acquisition at the same time as the master host to achieve synchronous acquisition.

[0031] In some embodiments, the first connector 401 is configured to be detachably plugged into the first interface 703a of the first fnirs host 700a to be interconnected, that is, which fnirs host the first connector 401 is plugged into is the master host among the multiple fnirs hosts to be interconnected, and the second connector 402 is configured to be detachably plugged into the second interface 703b of the second fnirs host 700b to be interconnected, that is, which fnirs host the second connector 402 is plugged into is the slave host among the multiple fnirs hosts to be interconnected. It is proposed that which fnirs host is the master host and which fnirs host is the slave host can be flexibly and freely determined by inserting the first connector 401 or the second connector 402, without the need to specify or determine which fnirs host is the master host or the slave host in advance on the fnirs host or the host computer. In order to facilitate the distinction between the first connector 401 and the second connector 402, and then determine how to insert the first connector 401 and the second connector 402, the first connector 401 and the second connector 402 have different explicit physical properties, so that the first connector 401 and the second connector 402 can be distinguished based on the explicit physical properties. For example, the explicit physical properties may include physical properties on the appearance (for example, Figure 3 The first connector 401 and the second connector 402 are different in shape, different in appearance, different in color, etc., so that the user can distinguish the first connector 401 and the second connector 402 by observing the difference in appearance. The explicit physical attribute also allows the processing circuit unit in the FNIRS host to distinguish whether the first connector 401 or the second connector 402 is inserted, so that the FNIRS host can autonomously identify whether it is a master host or a slave host by identifying whether the first connector 401 or the second connector 402 is inserted. In addition, through the hardware transmission between the first connector 401 and the processing circuit unit of the master host, the hardware transmission between the second connector 402 and the processing circuit unit of the slave host, and the transmitted acquisition timing signal can at least only include the start time of a series of acquisition cycles of synchronous acquisition (the start time of the first acquisition cycle), or can include the start time of each acquisition cycle, the amount of transmitted data is very small and it is hardware transmission, which can significantly reduce the delay between the interconnected FNIRS hosts (for example, controlling the delay to less than 10 microseconds).

[0032] In some embodiments, the processing circuit unit may be a hardware circuit capable of realizing information recognition and data transmission, so as to realize identification of whether the first connector 401 or the second connector 402 is inserted, and realize transmission and acquisition timing signals.

[0033] In some embodiments, the explicit physical attribute may be physical contact, the first connector 401 is configured to form a first physical contact when inserted into the first interface, so that the first processing circuit unit 702a recognizes the insertion of the first connector 401, and the second connector 402 is configured to form a second physical contact when inserted into the second interface, so that the first processing circuit unit 702b recognizes the insertion of the second connector 402. The physical contact may be any form of different physical contact that is easy for the processing circuit unit to identify, for example, different numbers of contact pieces, different shapes of contact pieces, etc. may be provided on the first connector 401 and the second connector 402, so that the processing circuit unit can identify whether the first connector 401 or the second connector 402 is inserted by identifying the different numbers and shapes of the contact pieces.

[0034] In some embodiments, when the explicit physical attribute is a physical attribute used by the processing circuit unit in the FNIRS host to distinguish whether the first connector 401 and the second connector 402 are inserted, the explicit physical attribute can also be a circuit parameter, and the first connector 401 is configured to generate a first circuit parameter when inserted into the first interface, so that the first processing circuit unit 702a recognizes the insertion of the first connector 401, and the second connector 402 is configured to generate a different second circuit parameter when inserted into the second interface, so that the first processing circuit unit 702b recognizes the insertion of the second connector 402. The circuit parameter can be a voltage, a current, etc., by setting different resistors, cables, contacts and other circuit components on the first connector 401 and the second connector 402, and then electrically connecting the pins, cables and other circuit contact components in the processing circuit unit when the first connector 401 and the second connector 402 are plugged into the interface of the FNIRS host, so that different circuit parameters are formed, and the processing circuit unit distinguishes whether the first connector 401 or the second connector 402 is inserted based on different circuit parameters.

[0035] In some embodiments, taking voltage as an example, the circuit parameter can be maintained at different voltages by setting internal sites on the first connector 401 and the second connector 402, and electrically connecting the internal sites within the processing circuit portion to form different voltages to distinguish whether the first connector 401 or the second connector 402 is inserted into the interface. For example, the first internal site of the first connector 401 is maintained at a first voltage, the second internal site of the second connector 402 is maintained at a second voltage, the first voltage is different from the second voltage (can be different single-point voltage values, or can be different voltage ranges), and the first internal site of the first connector 401 is electrically connected to the third internal site in the first processing circuit unit 702a when plugged into the first interface to form a third voltage, so that the first processing circuit unit 702a can identify whether the first connector 401 or the second connector 402 is inserted based on the third voltage; the second internal site of the second connector 402 is electrically connected to the fourth internal site in the first processing circuit unit 702b when plugged into the second interface to form a fourth voltage, and the third voltage is different from the fourth voltage, so that the first processing circuit unit 702b can identify whether the first connector 401 or the second connector 402 is inserted based on the fourth voltage.

[0036] For example, the first internal position of the first connector 401 and the second internal position of the second connector 402 can be realized by setting cables, contacts, etc. with different voltages. When setting cables, one or more cables can be set. In the case of setting one cable, the cable at the first internal position of the first connector 401 and the cable at the second internal position of the second connector 402 can maintain different voltage values ​​respectively by means of grounding or resistance. In the case of setting multiple cables, the first internal position of the first connector 401 and the second internal position of the second connector 402 can be cables with different serial numbers and different voltages, such as Figure 6As shown, taking the setting of three cables as an example, the first internal point of the first connector 401 is connected to the first cable, and the first cable is grounded, the second internal point of the second connector 402 is connected to the second cable 1, and the second cable 2 is grounded, and three cables ID1, ID2, and ID3 are also set in the processing circuit part of the fnirs host, and the states of the cables ID1, ID2, and ID3 are pulled up to a high level (taking 5V voltage as an example) through internal resistors respectively. When the first connector 401 is connected to the interface, the cable ID1 of the processing circuit part is connected to the first cable of the first connector 401, and the cable ID1 is pulled to a low level, that is, ID1=low level (GND), ID2=high level, and ID3=high level; when the second connector 402 is connected to the interface, the cable ID2 of the processing circuit part is connected to the second cable of the second connector 402, and the cable ID2 is pulled to a low level, that is, ID1=high level, ID2=low level (GND), and ID3=high level. Therefore, due to the different internal wiring methods of the first connector 401 and the second connector 402 (or the connection methods of the contacts), the voltage values ​​of ID1, ID2, and ID3 of the processing circuit unit will change differently after the connector is inserted. The processing circuit unit can identify whether the first connector 401 or the second connector 402 is inserted based on the different changes in the voltage. In some embodiments, when the explicit physical attribute is a physical attribute used by the processing circuit unit in the fnirs host to distinguish between the first connector 401 and the second connector 402 that are inserted, the explicit physical attribute can also be a visual feature, the first connector 401 has a first visual feature so that the first processing circuit unit 702a recognizes the insertion of the first connector 401 based on a visual sensor, and the second connector 402 has a second visual feature so that the second processing circuit unit 702b recognizes the insertion of the second connector 402 based on the visual sensor.

[0037] In some embodiments, when the explicit physical attribute is a physical attribute used by the processing circuit unit in the fnirs host to distinguish between the first connector 401 and the second connector 402 that are inserted, the explicit physical attribute may also be a magnetic mark, and the first connector 401 has a first magnetic mark so that the first processing circuit unit 702a recognizes the insertion of the first connector 401 based on a magnetic sensor, and the second connector 402 has a second magnetic mark so that the second processing circuit unit 702b recognizes the insertion of the second connector 402 based on the magnetic sensor.

[0038] In some embodiments, the magnetic identification may be a barcode, a magnetic tag, etc. The magnetic sensor may include any one of a Hall effect sensor, a magnetoresistive sensor, and a coil.

[0039] In some embodiments, the first connector 401 and the second connector 402 are detachably plugged into the same interface of the same FNIRS host, that is, for the same interface of the same FNIRS host, the first connector 401 can be inserted to make the FNIRS host become the master host among the interconnected FNIRS hosts (that is, used as the first interface 703a), and the second connector 402 can be inserted to make the FNIRS host become the slave host among the interconnected FNIRS hosts (that is, used as the second interface 703b).

[0040] In some embodiments, various types of FNIRS hosts generally have at least one interface, which is a basic configuration. In other words, the interconnection device for the FNIRS host of the present application can be applicable to the interconnection of the FNIRS host with a basic configuration of only a single interconnection interface. Of course, it is also applicable to the interconnection of the FNIRS host with a first interface and a second interface.

[0041] In some embodiments, if the interconnected fnirs hosts are connected in series one by one in a daisy chain, the delay of transmitting data from the fnirs host at the beginning of the daisy chain to the fnirs host at the end will be superimposed, and the closer to the end, the greater the deviation from the beginning. As the number of interconnected fnirs hosts increases, the delay deviation will further increase. In order to avoid the problem of delay superposition of multiple interconnected fnirs hosts, it is proposed that the interconnection device includes a single first connector 401 and a plurality of second connectors 402, so that the interconnected multiple fnirs hosts can realize a master host connecting multiple slave hosts in parallel. For example, Figure 7 ( Figure 7 , taking three second connectors 402 as an example, the specific number of the second connectors 402 is not limited and can be determined according to specific usage requirements), the interconnection device includes a single first connector 401 and a plurality of second connectors 402, the cable connecting portion 403 includes a first cable portion 4031, an expansion portion 4032 and a plurality of second cable portions 4033, the expansion portion 4032 is electrically connected to the first connector 401 via the first cable portion 4031, and is connected to the corresponding plurality of second connectors 402 via the plurality of second cable portions 4033.

[0042] In some embodiments, the expansion unit 4032 may be any device capable of implementing data relay, for example, an expansion dock, a synchronization relay box, etc.

[0043] In some embodiments, when the first connector 401 is plugged into the first interface 703a of the first FNIRS host 700a and the second connector 402 is plugged into the second interface 703b of the second FNIRS host 700b, the first acquisition timing signal of synchronous acquisition transmitted outwardly by the first connector 401 via the cable connection portion 403 and the second connector 402 at least indicates the start time of a series of acquisition cycles of synchronous acquisition, that is, the first acquisition timing signal indicates that the acquisition cycles of the interconnected multiple FNIRS hosts start synchronous acquisition based on the same start time. The first acquisition timing signal can indicate the start time of the first acquisition cycle in a series of acquisition cycles of synchronous acquisition, and can also indicate the start time of each acquisition cycle in a series of acquisition cycles of synchronous acquisition.

[0044] In some embodiments, the first acquisition timing signal may also include the identification of each cycle of synchronous acquisition, so that the master host and the slave host can identify each acquisition cycle based on the identification. After the collected detection data is transmitted to the host computer, the host computer can summarize the detection data collected by multiple groups of channels with the same acquisition cycle identification based on the identification, and can also determine which acquisition cycle has a poor acquisition status of the slave host based on the identification. If there is a slave host with a poor acquisition status in a certain acquisition cycle, the host computer can discard the detection data of other slave hosts with good acquisition status in this acquisition cycle together, and no longer summarize and use them, so that the detection data retained in each acquisition cycle are of good quality.

[0045] In some embodiments, the identifiers of each period of synchronous acquisition included in the first acquisition timing signal may be any identifier that can distinguish the order or the existence of a difference, for example, identifiers in the form of numbers, letters, strings, etc.

[0046] In some embodiments, in order to avoid the problem that individual slave hosts cannot synchronize acquisition due to the main processor being occupied, when the first connector 401 is plugged into the first interface 703a of the first FNIRS host 700a and the second connector 402 is plugged into the second interface 703b of the second FNIRS host 700b, the first connector 401 transmits the first acquisition timing signal to the second processing circuit part 702b of the second FNIRS host 700b via the cable connection part 403 and the second connector 402 only when the second main processor 701b of the second FNIRS host 700b is idle. For example, before the master host (i.e., the fnirs host plugged into the first connector 401) sends the start time of each cycle, it can pre-determine whether the main processor of the slave host is busy. If it is busy, the master processor cannot perform synchronous acquisition. At this time, the master host can temporarily not send the start time of that acquisition cycle (i.e., temporarily not send the first acquisition timing signal), because it cannot be executed even if it is sent. When it is pre-determined that the main processors of each slave host are not busy, the first acquisition timing signal including the start time of the acquisition cycle is sent to each slave host, so that the master host and each slave host can start synchronous acquisition at the same time.

[0047] In some embodiments of the present application, a fnirs host is also provided, which can be used as a master host (i.e. Figure 4 The first fnirs host 700a) can be used as a slave host (i.e. Figure 4 Note that the use of component designation x without suffixes a and b in the following text is intended to include both xa and xb. For example, when referring to the fnirs host 700 or another fnirs host 700, both can be used as the first fnirs host 700a or the second fnirs host 700b.

[0048] The FNIRS host 700 may include: a main processor 701, configured to control the acquisition of the FNIRS detection signal; at least one interface 703, configured to be inserted into the first connector 401 or the second connector 402 of the interconnection device for the FNIRS host; a processing circuit unit 702 separate from the main processor, configured to identify whether the connector inserted into the at least one interface 703 is the first connector 401 or the second connector 402; when the inserted connector is identified as the first connector 401, transmitting an acquisition timing signal of synchronous acquisition to a corresponding processing circuit unit 702 of another interconnected FNIRS host 700 via the at least one interface 703; when the inserted connector is identified as the second connector 402, receiving another acquisition timing signal of synchronous acquisition from the corresponding processing circuit unit 702 of another interconnected FNIRS host 700 via the at least one interface 703.

[0049] The main processor 701 is further configured to: when the processing circuit unit 702 receives the other acquisition timing signal (at this time, it acts as a slave host), receive the other acquisition timing signal from the processing circuit unit 702, and use the other acquisition timing signal to perform synchronous acquisition of the FNIRS detection signal. When the processing circuit unit 702 transmits an acquisition timing signal for synchronous acquisition to the outside (at this time, it acts as a master host), the main processor 701 uses the acquisition timing signal for synchronous acquisition transmitted to the outside to perform synchronous acquisition of the FNIRS detection signal, and the acquisition timing signal at least indicates the start time of a series of acquisition cycles of synchronous acquisition.

[0050] In some embodiments, the main processor 701 may be any processor chip of a CPU, an MPU, a GPU, or a SOC. The processing circuit unit may be a hardware circuit capable of realizing information recognition and data transmission, for example, an ASIC circuit or an FPGA circuit.

[0051] In some embodiments, in order to achieve lower cost and more flexibility in modifying the FNIRS host, preferably, the processing circuit unit 702 can be an FPGA circuit. If the existing FNIRS host is to be modified, the built-in FPGA circuit of the chassis is opened, and the FPGA is programmed to perform the tasks of access identification of the connector and mutual transmission of the acquisition timing signal, and then interconnected with the main processor, and the application program of the main processor is updated.

[0052] In some embodiments, in order to further reduce the delay between FNIRS hosts caused by interconnection, the processing circuit unit 702 is configured to identify the insertion connector and transmit the corresponding acquisition timing signal without relying on the main processor 701. That is, the processing circuit unit 702 is configured to centrally handle the processing tasks of the FNIRS host interconnection (such as identifying the insertion connector, transmitting the corresponding acquisition timing signal, etc.), without relying on the main processor 701, and all are processed by the hardware circuit, so that the delay between FNIRS hosts caused by interconnection can be minimized, for example, the delay can be controlled at 10μs, 8μs, 6μs, or even 4μs and below.

[0053] In some embodiments, the processing circuit unit 702 is further configured to identify whether the inserted connector is the first connector 401 or the second connector 402 by detecting any one or any combination of the following explicit physical properties: Physical contact, circuit parameters generated by the inserted connector, and visual features. Here, the processing circuit unit 702 identifies whether the inserted connector is the first connector 401 or the second connector 402 based on the explicit physical attributes, based on the case where the explicit physical attributes of the inserted connector are any one or any combination of physical contact, circuit parameters generated by the inserted connector, and visual features. This is similar to the description of the explicit physical attributes of the interconnection device for the fNIRS host in the aforementioned embodiment, and will not be repeated here.

[0054] In some embodiments, the at least one interface 703 may be a single interface, and the single interface may be a lemo interface or a DB square connector of the fnirs host.

[0055] In some embodiments, the acquisition timing signal also includes the identification of each period of synchronous acquisition. That is, the acquisition timing signal transmitted by the processing circuit unit of the master host to the processing circuit unit of each slave host through the interconnection device for the fnirs host can also include the identification of each acquisition period of synchronous acquisition, so that the master host and the slave host can identify each acquisition period based on the identification, and after the collected detection data is transmitted to the host computer, the host computer can summarize the detection data collected by multiple groups of channels with the same acquisition period identification based on the identification, and can also judge which acquisition period has a poor acquisition status of the slave host based on the identification, so that the detection data of other slave hosts with good acquisition status in this acquisition period can be discarded together and no longer summarized and used, so that the detection data retained in each acquisition period are of good quality.

[0056] In some embodiments, the acquisition timing signal of synchronous acquisition transmitted by the master host to the processing circuit part of each slave host through the interconnection device for the fnirs host at least indicates the start time of a series of acquisition cycles of synchronous acquisition, that is, the acquisition timing signal indicates that the acquisition cycles of multiple interconnected fnirs hosts start synchronous acquisition based on the same start time. The acquisition timing signal can indicate the start time of the first acquisition cycle in a series of acquisition cycles of synchronous acquisition, such as Figure 5 As shown ( Figure 5 The timing information of the thin lines in the middle is the SD sub-arrangement timing configuration information of each fnirs host. Figure 5 The dotted line in the figure is an acquisition timing signal in the form of a rising edge, and the timing signal in the bold line is a periodic acquisition timing signal including a rising edge. The moment indicated by the dotted line is also the moment when the master host sends the acquisition timing signal); it can also indicate the start time of each acquisition cycle in a series of acquisition cycles of synchronous acquisition, that is, in each acquisition cycle, the master host transmits the acquisition timing signal of synchronous acquisition to the processing circuit part of each slave host through the interconnection device used for the fnirs host, so that each slave host can start acquisition with the master host based on the acquisition timing signal and according to their respective SD sub-arrangement timing configuration information (the SD sub-arrangement timing configuration information of each fnirs host includes the serial number of the SD probe of each fnirs host, which timing signal in the total timing cycle of synchronous acquisition is used to light up / detect, etc.), so as to realize synchronous acquisition. The acquisition timing signal of synchronous acquisition can be a rising edge signal or a periodic timing signal including a rising edge. Please note that in this application, the expression "total timing cycle of synchronous acquisition" is intended to mean Figure 5 Each complete acquisition timing cycle (including thick lines and thin lines) contains when the S / D of each serial number is lit / detected, which is distinguished from the "first acquisition timing signal" and the "acquisition timing signal".

[0057] In some embodiments, various methods can be used to let each fnirs host know the SD sub-arrangement timing configuration information of the S / D probes connected to each of them (i.e., the timing of lighting up each S probe of each fnirs host, the duration of lighting up each S probe, the timing and duration of detection of each D probe, the order between each other and the simultaneous lighting / detection relationship, etc.). Once the configuration information is known, as long as the synchronous acquisition start instruction (such as the "first acquisition timing signal" mentioned above) is known, it can autonomously start to execute the lighting / detection of its own S / D probe, thereby realizing the synchronous acquisition of high-channel detection data.

[0058] In some embodiments, each interconnected fnirs host can learn its own SD sub-arrangement timing configuration information through interaction with the host computer. There are many ways of interaction, which are not specifically limited in this application. For example, it can be implemented in the following different ways.

[0059] a. Connect multiple fnirs hosts to be interconnected to the same host computer, either wirelessly or by wire. The high-channel detection data collected by the subsequent multiple fnirs hosts are also analyzed and displayed on a single host computer. The host computer can identify how many fnirs hosts are connected and their connected SD configurations (such as 8S8D). In the host computer operation, inform each fnirs host to operate in accordance with this low-channel integration to form a high-channel interconnection mode, and configure the position allocation of the SD probe group connected to each fnirs host in the target high-channel arrangement. This configuration can be automatically generated by the host computer, or the host computer can provide multiple options for the user to choose.

[0060] b. Connect multiple fnirs hosts to be interconnected to the same host computer. According to the number of fnirs hosts, SD configuration and expected target high-channel arrangement, the user queries the position allocation of SD probes connected to each host in the operation manual, completes the plugging of each group of SD probes accordingly, and interactively confirms the position allocation of the SD probe group of each host and the target high-channel SD arrangement formed on the operation interface of the same host computer. The host computer then informs each fnirs host of the position allocation of its SD probe group.

[0061] Each fnirs host knows its own SD position allocation, that is, it knows which position (serial number) S (transmitting probe) and which position (serial number) D (receiving probe) it corresponds to in the target high channel arrangement, so it also knows which time segments of the total synchronous acquisition timing cycle instruct its own light source to light up and the detection probe to receive. Therefore, it determines when the total synchronous acquisition timing cycle starts. For example, if the start of the cycle is known through the "(first) acquisition timing signal", it can complete the lighting / detection operation in the time domain responsible for synchronous acquisition by itself.

[0062] In some embodiments, the processing circuit unit 702 is further configured to: when the main processor 701 of the other fnirs host 700 is occupied, the acquisition timing signal of synchronous acquisition is not transmitted externally via the at least one interface 703. That is, among the interconnected multiple fnirs hosts, if the main processor of an individual slave host is occupied, the master host temporarily does not transmit the acquisition timing signal of synchronous acquisition to each slave host via the at least one interface, that is, temporarily does not send the acquisition timing signal of synchronous acquisition to each slave host, and when the main processors of each slave host are not occupied, the acquisition timing signal of synchronous acquisition is transmitted externally to each slave host via the at least one interface to ensure that each slave host can perform synchronous acquisition with the master host based on the acquisition timing signal.

[0063] In some embodiments of the present application, a fnirs host interconnection component is also provided, including: at least two fnirs hosts of any one of the embodiments of the present application; and Any one of the interconnection devices for the fnirs host in the various embodiments of the present application is configured to connect the at least two fnirs hosts to each other.

[0064] In some embodiments, when the fnirs host is multiple, see Figure 7 The interconnection device includes a single first connector 401 and a plurality of second connectors 402, the cable connection portion 403 includes a first cable portion 4031, an expansion portion 4032 and a plurality of second cable portions 4033, the expansion portion 4032 is electrically connected to the first connector 401 via the first cable portion 4031, and is connected to a corresponding plurality of second connectors 402 via a plurality of second cable portions 4033. Figure 4 , a single first connector 401 is inserted into the first interface 703a of a fnirs host 700a (the one fnirs host is used as the master host), and a plurality of second connectors 402 are respectively inserted into the second interfaces 703b of the remaining fnirs hosts 700b (the remaining fnirs hosts are used as slave hosts), so as to realize the parallel interconnection of a master host and multiple slave hosts, avoid the superposition of the delay of the interconnected fnirs hosts, and avoid the delay accumulation. Figure 8 As shown, a master host 700a is connected to multiple slave hosts 700b ( Figure 8 7 fnirs hosts 700b are shown as slave hosts as an example) and are interconnected in parallel to form a link in a star topology.

[0065] In some embodiments of the present application, an fNIRS imaging system is also provided, the system comprising: Any one of the fnirs host interconnection components in the various embodiments of the present application; and A probe group including a transmitting probe (i.e., S) and a receiving probe (i.e., D) connected to and used in conjunction with each fnirs host, each of the probe groups has a first number of channels, wherein each fnirs host is configured to control the corresponding probe group to synchronously collect detection data of a second number of channels based on a first acquisition timing signal of a first fnirs host 700a connected to the first connector 401, wherein the second number of channels is greater than the first number of channels.

[0066] In some embodiments, the first channel number is the channel number of each interconnected fnirs host to realize detection data collection, and the second channel number is the channel number of detection data collection realized by all interconnected interconnected devices through synchronous collection.

[0067] In some embodiments, the fNIRS imaging system further comprises: The host computer receives the detection data of the second channel number collected synchronously by each fnirs host, and displays and analyzes the detection data. That is, the detection data of the second channel number collected synchronously by all interconnected fnirs hosts is displayed and analyzed by the same host computer.

[0068] In some embodiments, each interconnected FNIRS host can be connected to a host computer respectively, but whichever FNIRS host is used as the master host, the host computer connected to which FNIRS host will be used to uniformly display and analyze the detection data of the second channel number synchronously collected by all interconnected FNIRS hosts. All interconnected FNIRS hosts can also be connected to one host computer, and the one host computer will be used to uniformly display and analyze the detection data of the second channel number synchronously collected by all interconnected FNIRS hosts.

[0069] In some embodiments, each fnirs host to be interconnected can be connected to the host computer through a wireless transmitter or a wired connection, and the host computer determines what kind of high-channel SD total arrangement to be formed, and each S / D probe connected to each fnirs host is used as the S / D probe (or S / D serial number) at which position in the total arrangement. Each fnirs host can learn the S / D serial number and synchronous acquisition of each S / D probe connected to it in the total arrangement from the host computer in various ways.

[0070] After the interconnected FNIRS hosts in the FNIRS host interconnection component are interconnected through the interconnection device for interconnection devices, the host computer interacts with the interconnected FNIRS hosts so that each FNIRS host knows the timing configuration information of the SD sub-arrangement connected to each of them (that is, which transmitting probe of all SD channels of the interconnection is connected to the light source of each FNIRS host, the timing of lighting each light source, the lighting duration of each light source, etc.), and knows to run the synchronous acquisition according to this interconnection mode, that is, to use the acquisition timing signal transmitted by the master host in the interconnection as the synchronous acquisition instruction to start the respective synchronous acquisition modes, and the host computer sends the acquisition timing signal of the synchronous acquisition to the master host, and then the processing circuit part of the master host transmits the acquisition timing signal to the processing circuit part of each slave host through the interconnection device, so that each slave host can start the acquisition at the same time as the master host based on the acquisition timing signal to achieve synchronous acquisition.

[0071] In some embodiments of the present application, a method for collecting detection data with a higher number of channels by interconnecting at least two FNIRS devices is also provided, wherein each FNIRS device includes a probe group and any one of the FNIRS hosts in the various embodiments of the present application connected to and used in conjunction with the probe group, wherein the probe group includes a transmitting probe and a receiving probe, such as Fig. 9 As shown, the method includes: Step S901: connecting the at least two FNIRS devices to each other through any one of the interconnection devices for the FNIRS host in the various embodiments of the present application, wherein the first connector 401 of the interconnection device is inserted into the first interface 703a of the FNIRS host 700a as the master host of the at least two FNIRS devices, and the second connector 402 of the interconnection device is inserted into the second interface 703b of the FNIRS host 700b as the slave host of the at least two FNIRS devices; Step S902: putting each probe group on the head of the subject through the same head cap; Step S903: Using each fnirs host as the master host and the slave host, based on the first acquisition timing signal of the synchronous acquisition of the fnirs host from the master host, to control the transmitting probe and the receiving probe of the corresponding probe group to synchronously acquire detection data, so as to obtain detection data with a higher number of channels.

[0072] The embodiment of the present application achieves the following technical effects: it is realized that through the different explicit physical properties of the second connector 402 and the first connector 401, it is possible to distinguish which connector is the first connector 401 and which connector is the second connector 402, and the first connector 401 is configured to be detachably plugged into the first interface 703a of the first fnirs host 700a to be interconnected, that is, which fnirs host the first connector 401 is plugged into is the master host, and the second connector 402 is configured to be detachably plugged into the second interface 703b of the second fnirs host 700b to be interconnected, that is, the first connector 401 is plugged into the first interface 703a of the first fnirs host 700a to be interconnected. The fnirs host to which the second connector 402 is plugged is the slave host. In this case, the user can arbitrarily and independently plug the first connector 401 into the fnirs host that needs to be the master host according to the distinguished first connector 401 and the second connector 402 according to different interconnection requirements, so as to flexibly and arbitrarily specify or clarify the fnirs host that needs to be the master host by plugging the first connector 401, which is conducive to knowing and clarifying the master host, and then to clarifying which fnirs host is connected to the host computer to view the signal acquisition and analysis results.

[0073] Obviously, those skilled in the art should understand that the modules or steps of the above-mentioned embodiments of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. In this way, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0074] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the embodiments of the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An interconnect device for an fnirs host, characterized in that: include: A first connector is arranged at a first end of the interconnection device, and the first connector is configured to be detachably plugged into a first interface of a first fnirs host to be interconnected; A second connector is disposed at an end opposite to the first end, and the second connector has different dominant physical properties from the first connector, and the second connector is configured to be detachably plugged into a second interface of a second fnirs host to be interconnected; as well as A cable connection portion, the cable connection portion is used to electrically connect the first connector and the second connector, wherein, when the first connector is plugged into the first interface of the first FNIRS host and the second connector is plugged into the second interface of the second FNIRS host, the first connector receives a first acquisition timing signal of synchronous acquisition from the first processing circuit portion of the first FNIRS host, and transmits it to the second processing circuit portion of the second FNIRS host via the cable connection portion and the second connector, and the first acquisition timing signal at least indicates the start time of a series of acquisition cycles of synchronous acquisition.

2. The interconnect device for the fnirs host as claimed in claim 1, characterized in that The first connector and the second connector are detachably plugged into the same interface of the same fnirs host.

3. The interconnect device for the fnirs host as claimed in claim 1 or 2, characterized in that, The explicit physical attribute is physical contact, the first connector is configured to form a first physical contact when inserted into the first interface, so that the first processing circuit unit recognizes the insertion of the first connector, and the second connector is configured to form a second physical contact when inserted into the second interface, so that the second processing circuit unit recognizes the insertion of the second connector.

4. The interconnect device for the fnirs host as claimed in claim 1 or 2, characterized in that, The explicit physical property is a circuit parameter, the first connector is configured to generate a first circuit parameter when inserted into the first interface, so that the first processing circuit unit recognizes the insertion of the first connector, and the second connector is configured to generate a different second circuit parameter when inserted into the second interface, so that the second processing circuit unit recognizes the insertion of the second connector.

5. The interconnect device for the fnirs host as claimed in claim 1 or 2, characterized in that, The explicit physical attribute is a visual feature, the first connector has a first visual feature so that the first processing circuit unit recognizes the insertion of the first connector based on a visual sensor, and the second connector has a second visual feature so that the second processing circuit unit recognizes the insertion of the second connector based on the visual sensor.

6. The interconnect device for the fnirs host as claimed in claim 4, characterized in that The first internal point of the first connector is maintained at a first voltage, the second internal point of the second connector is maintained at a second voltage, the first internal point of the first connector is electrically connected to a third internal point within the first processing circuit part when plugged into the first interface, and the second internal point of the second connector is electrically connected to a fourth internal point within the second processing circuit part when plugged into the second interface.

7. The interconnect device for the fnirs host as claimed in claim 1 or 2, characterized in that, The interconnection device includes a single first connector and several second connectors, the cable connection portion includes a first cable portion, an expansion portion and several second cable portions, the expansion portion is electrically connected to the first connector via the first cable portion, and is connected to the corresponding several second connectors via the several second cable portions.

8. The interconnect device for the fnirs host as claimed in claim 1 or 2, characterized in that: The first acquisition timing signal also includes identifiers of each period of synchronous acquisition.

9. The interconnect device for the fnirs host as claimed in claim 1 or 2, characterized in that, When the first connector is plugged into the first interface of the first FNIRS host and the second connector is plugged into the second interface of the second FNIRS host, the first connector transmits the first acquisition timing signal to the second processing circuit part of the second FNIRS host via the cable connection part and the second connector only when the main processor of the second FNIRS host is idle.

10. A fnirs host, characterized in that: include: A main processor configured to control the acquisition of the fNIRS detection signal; at least one interface configured to be plugged into a first connector or a second connector of an interconnect device for an fnirs host; A processing circuit unit separate from the main processor is configured to identify whether the connector inserted into the at least one interface is the first connector or the second connector; when the inserted connector is identified as the first connector, transmit a synchronously collected acquisition timing signal to a corresponding processing circuit unit of another interconnected FNIRS host via the at least one interface; when the inserted connector is identified as the second connector, receive another synchronously collected acquisition timing signal from a corresponding processing circuit unit of another interconnected FNIRS host via the at least one interface; The main processor is further configured to: when the processing circuit unit receives the other acquisition timing signal, receive the other acquisition timing signal from the processing circuit unit, and use the other acquisition timing signal to synchronously acquire the FNIRS detection signal; when the processing circuit unit transmits the acquisition timing signal for synchronous acquisition externally, use the acquisition timing signal for synchronous acquisition transmitted externally to synchronously acquire the FNIRS detection signal, and the acquisition timing signal at least indicates the start time of a series of acquisition cycles of synchronous acquisition.

11. The fnirs host according to claim 10, characterized in that The processing circuit part is an FPGA circuit.

12. The fnirs host according to claim 10 or 11, characterized in that: The processing circuit unit is configured to identify the inserted connector and transmit the corresponding acquisition timing signal independently of the main processor.

13. The fnirs host according to claim 10 or 11, characterized in that: The processing circuit unit is further configured to identify whether the inserted connector is the first connector or the second connector by detecting any one or any combination of the following dominant physical properties: Physical contacts, circuit parameters generated by inserting connectors, and visual features.

14. The fnirs host according to claim 10 or 11, characterized in that: The at least one interface is a single interface, and the single interface is a Lemo interface or a DB square connector of the fnirs host.

15. The fnirs host according to claim 10 or 11, characterized in that: The acquisition timing signal also includes identification of each cycle of synchronous acquisition.

16. The fnirs host according to claim 10 or 11, characterized in that: The processing circuit unit is further configured to temporarily not transmit the synchronously collected acquisition timing signal to the outside via the at least one interface when the main processor of the other fnirs host is occupied.

17. A fnirs host interconnection component, characterized in that include: At least two fnirs hosts according to any one of claims 10 to 16; as well as The interconnect device according to any one of claims 1 to 9, wherein the interconnect device is configured to interconnect the at least two fnirs hosts.

18. The fnirs host interconnect component of claim 17, wherein: In the case where there are multiple fnirs hosts, the interconnection device includes a single first connector and several second connectors, the cable connection portion includes a first cable portion, an expansion portion and several second cable portions, the expansion portion is electrically connected to the first connector via the first cable portion, and is connected to the corresponding several second connectors via several second cable portions, the single first connector is inserted into the first interface of one fnirs host, and the several second connectors are respectively inserted into the second interfaces of the remaining fnirs hosts.

19. An fNIRS imaging system, characterized in that: include: The fnirs host interconnect assembly of claim 17 or 18; and A probe group including a transmitting probe and a receiving probe connected to and used in conjunction with each fnirs host, each of the probe groups having a first number of channels, wherein each fnirs host is configured to control the corresponding probe group to synchronously acquire detection data of a second number of channels based on a first acquisition timing signal of a first fnirs host connected to the first connector, wherein the second number of channels is greater than the first number of channels.

20. The fNIRS imaging system of claim 19, wherein: Also includes: The host computer receives the detection data of the second channel number synchronously collected by each fnirs host, and displays and analyzes the detection data.

21. A method for collecting detection data with a higher number of channels by interconnecting at least two FNIRS devices, each of which comprises a probe group and a FNIRS host as claimed in any one of claims 10 to 16 connected to and used in conjunction with the probe group, the probe group comprising a transmitting probe and a receiving probe, the method comprising: The at least two FNIRS devices are interconnected by the interconnection device according to any one of claims 1 to 9, wherein a first connector of the interconnection device is inserted into a first interface of a FNIRS host serving as a master host in the at least two FNIRS devices, and a second connector of the interconnection device is inserted into a second interface of a FNIRS host serving as a slave host in the at least two FNIRS devices; Wearing each probe set on the subject's head via the same head cap; Each fnirs host as the master host and the slave host controls the transmitting probe and the receiving probe of the corresponding probe group to synchronously collect detection data based on the first acquisition timing signal of the fnirs host of the master host, so as to obtain detection data with a higher number of channels.

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