Double-peak current control strategy of four-switch Buck-Boost converter

Abstract

The invention provides a double-peak-value current control strategy of a four-switch Buck-Boost converter, belongs to the technical field of converter control, and solves the problems that an existing control algorithm is relatively large in delay during high-frequency real-time calculation, and the control method still needs to switch algorithms under light-load and heavy-load conditions. Comprising the following steps: dividing a switching period into four stages: an energy storage stage D-A, a direct connection stage A-B, an energy release stage B-C and a clamping stage C-D according to on and off states of a switching tube of the FSBB converter; a voltage regulator is introduced to the point B to output Vc1, so that the point B is related to the point A, and the FSBB is limited to control the degree of freedom; and the specific value information of the input voltage and the output voltage is detected, the inductive current working state of the FSBB in the step-up / step-down state is determined according to the magnitude relation of the input voltage and the output voltage, and a control logic circuit is constructed to complete double-peak current control.

Description

Technical Field

[0001] The invention relates to a dual-peak current control strategy of a four-switch Buck-Boost converter, and belongs to the technical field of converter control. Background Art

[0002] The Four Switch Buck-Boost (FSBB) converter is very suitable as a voltage stabilization link in scenarios such as distributed power supply in data centers and low-voltage DC-DC in electric vehicles because it is easy to implement soft switching and can have both boost and buck functions.

[0003] With the continuous increase of switching frequency and power density, the hard switch control method can no longer meet the current needs due to the large turn-on loss. However, due to the high degree of freedom of the four-switch Buck-Boost converter, it is difficult to realize soft switching control. The current control method that can realize the soft switching of the four-switch Buck-Boost converter is mainly based on quadrilateral current control, and optimizes the RMS of the inductor current, limits it by deriving the expression that minimizes the inductor current, and calculates the duty cycle and phase shift accordingly. However, the current control algorithm is relatively complex, so there will be a large delay problem in high-frequency real-time calculation. Although the table lookup method can avoid real-time calculation, it takes up a lot of storage resources and reduces the control accuracy. The increase in data volume is not conducive to real-time control. At the same time, the existing control method still needs to switch the algorithm under light load and heavy load conditions, and a large number of real-time calculations are required to obtain the corresponding duty cycle and phase shift angle. Therefore, it is necessary to innovate the control strategy for the four switches to reduce the complexity of control, avoid complex real-time calculations or 3D / 2D lookup tables, avoid frequent switching of the converter working state under light load and heavy load conditions, and improve the control speed and accuracy of the system. Summary of the invention

[0004] In order to solve the problem that the existing control algorithm will have a large delay in high-frequency real-time calculation, and the control method still needs to switch the algorithm under light load and heavy load conditions, the present invention further proposes a dual peak current control strategy for a four-switch Buck-Boost converter.

[0005] The technical solution adopted by the present invention to solve the above problems is:

[0006] According to the on and off states of the switch tube of the FSBB converter, the switching cycle is divided into four stages: energy storage stage DA, direct connection stage AB, energy release stage BC and clamping stage CD;

[0007] When the inductor current rises / falls to the output of the voltage regulator and the coefficient k and V in / V oThe product of The converter enters the energy release stage BC from the direct connection stage AB;

[0008] By introducing the voltage regulator output V to point B c1 Point B is related to point A to limit the control freedom of FSBB; and the ratio information of input voltage to output voltage is detected. According to the relationship between the input voltage and the output voltage, the inductor current working state of FSBB boost / buck state is determined, and a control logic circuit is constructed to complete the dual peak current control.

[0009] Optionally, when the input voltage V in Less than the output voltage V o When the inductor current I B A , the circuit naturally works in the boost state;

[0010] Input voltage V in Greater than the output voltage V o When the inductor current I B >I A , the circuit naturally works in a step-down state;

[0011] Build I A and I B The relationship between points A and B is used to control the current at points A and B at the same time by using the output of the voltage loop, and the current inductance expressions at points A and B are obtained;

[0012] Combining the current inductance expressions at points A and B, when the output voltage V o , output voltage V o When the inductance L is fixed, I A and I B The size of V c1 Related, obtain the expressions of optimized energy storage time T1, direct time T2 and energy release time T3;

[0013] The current inductance expression at point A is:

[0014] I A =V c1 (1);

[0015] The current inductance expression at point B is:

[0016]

[0017] The expression of the optimized energy storage time T1 is:

[0018]

[0019] The expression of the optimized through time T2 is: ​

[0020]

[0021] The expression of the optimized energy release time T3 is:

[0022]

[0023] Optionally, the control logic circuit includes:

[0024] Module A, module B, module C and module D;

[0025] Module A is responsible for switching the inductor current at point B;

[0026] Module B is responsible for switching the inductor current at point A;

[0027] Module C is responsible for the switching point C, where the inductor current is less than -I during the switching process z ;

[0028] Module D is used to receive the constant frequency f sent by the sampling device s pulses, wherein the sampling device is used to sample the input voltage and the output voltage.

[0029] Optionally, module A is responsible for switching the inductor current at point B, specifically including:

[0030] When any of the switching conditions 1, 2 and 3 is met, the inductor current is switched at point B, where the switching condition 1 is that the inductor current is not equal to the voltage loop output V c2 The second switching condition is that the inductor current is reduced to the current I required to achieve ZVS. z , switching condition three is that T2 reaches T 2_max And T≤T s ;

[0031] Module B is responsible for the switching of the inductor current at point A, specifically including:

[0032] When any of the switching conditions 4 and 5 is met, the inductor current is switched at point A. The switching condition 4 is that the inductor current is greater than the voltage loop output V c1 , switching condition five is that the inductor current is greater than I z .

[0033] Optionally, in the switching condition 3, T≤T s Specifically include:

[0034] According to T1, T2, T3 and V c1 Get the expression of power transfer stage T;

[0035] When the converter output power is maximum, T4 = 0, and only when Q3 is turned on, the inductor current i L The flow into the load, combined with the power transfer stage T, limits the maximum value of the inductance L;

[0036] When the input voltage V in Equal to the output voltage V o , I A The value is equal to I B When the value of T2 tends to infinity, the power transfer stage T will be greater than the switching period. Limiting the maximum value of T2 ensures that the converter can work normally in the entire range and ensures that T≤T in all working conditions. s ;

[0037] The expression of power transfer stage T is:

[0038]

[0039] The expression for limiting the maximum value of the inductance L is:

[0040]

[0041] The expression that limits the maximum value of T2 is:

[0042]

[0043] The beneficial effects of the present invention are:

[0044] 1. The advantage of the control strategy proposed in the present invention is that the digital controller only needs to detect the input and output voltages. By comparing these voltages with the inductor current i L By comparison, the T1 and T2 time periods of the FSBB converter can be automatically adjusted according to changes in the input voltage and load, thereby avoiding the traditional real-time calculation or table lookup method and making full use of system resources. Compared with the real-time calculation method, the present invention reduces the calculation delay and calculation load; compared with the table lookup method, the present invention improves the control accuracy and saves the memory of the controller.

[0045] 2. In order to achieve wide input range and full load range ZVS and meet transient requirements, the present invention proposes a dual peak current control strategy for a four-switch Buck-Boost converter to avoid complex real-time calculations or the need for large amounts of data storage. This mode introduces the input and output voltages to associate the two peak inflection points of the inductor current to achieve the functions of boost and buck. At the same time, the working principle of the proposed strategy is analyzed and the effective value current minimization optimization design process of the inductor is derived, thereby improving the overall efficiency. In addition, a maximum duration limit is imposed for situations where the input and output voltages are close. The control strategy proposed in the present invention can be implemented by high-speed comparators and low-latency logic gates, thereby saving storage and computing resources of the controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A schematic diagram of the overall architecture of the FSBB dual-peak control strategy provided by the present invention;

[0047] Figure 2 A schematic diagram of the FSBB double peak control logic provided by the present invention;

[0048] Figure 3 Equivalent circuit diagram of the energy storage stage DA, direct connection stage AB, energy release stage BC and clamping stage CD provided by the present invention;

[0049] Figure 3 In the figure, (a) is the equivalent circuit diagram of the energy storage stage DA, (b) is the equivalent circuit diagram of the direct connection stage AB, (c) is the equivalent circuit diagram of the energy release stage BC, and (d) is the equivalent circuit diagram of the clamping stage CD.

[0050] Figure 4 A schematic diagram of the inductor current waveform of the FSBB converter provided by the present invention;

[0051] Figure 4 In the figure, (a) is V in <V o Schematic diagram of the inductor current waveform when (b) is V in =V o Schematic diagram of the inductor current waveform when (c) is V in >V o Schematic diagram of the inductor current waveform when .

[0052] Figure 5 The V provided by the present invention in = 36V FSBB converter steady-state waveform diagram;

[0053] Figure 5In the figure, (a) is a schematic diagram of the steady-state waveform of the FSBB converter under 25% load when the input voltage is 36V, (b) is a schematic diagram of the steady-state waveform of the FSBB converter under 50% load when the input voltage is 36V, and (c) is a schematic diagram of the steady-state waveform of the FSBB converter under full load when the input voltage is 36V;

[0054] Figure 6 The V provided by the present invention in = Schematic diagram of steady-state waveform of FSBB converter when 48V;

[0055] Figure 6 In the figure, (a) is a schematic diagram of the steady-state waveform of the FSBB converter under 25% load when the input voltage is 48V, (b) is a schematic diagram of the steady-state waveform of the FSBB converter under 50% load when the input voltage is 48V, and (c) is a schematic diagram of the steady-state waveform of the FSBB converter under full load when the input voltage is 48V;

[0056] Figure 7 The V provided by the present invention in = Schematic diagram of steady-state waveform of FSBB converter when 60V;

[0057] Figure 7 In the figure, (a) is a schematic diagram of the steady-state waveform of the FSBB converter under the condition of 25% load when the input voltage is 60V, (b) is a schematic diagram of the steady-state waveform of the FSBB converter under the condition of 50% load when the input voltage is 60V, and (c) is a schematic diagram of the steady-state waveform of the FSBB converter under the condition of full load when the input voltage is 60V;

[0058] Figure 8 A schematic diagram of a dynamic waveform of the FSBB converter provided by the present invention when the load suddenly changes from 25% to 75%;

[0059] Figure 8 In the figure, (a) is a schematic diagram of the dynamic waveform of the FSBB converter when the input voltage is 36V and the load suddenly changes from 25% to 75%; (b) is a schematic diagram of the dynamic waveform of the FSBB converter when the input voltage is 48V and the load suddenly changes from 25% to 75%; (c) is a schematic diagram of the dynamic waveform of the FSBB converter when the input voltage is 60V and the load suddenly changes from 25% to 75%;

[0060] Fig. 9 A schematic diagram of the efficiency curve of the FSBB converter provided by the present invention;

[0061] Fig.10 A schematic diagram of an inductor current waveform in a boost state under the dual-peak current control strategy provided by the present invention;

[0062] Fig.11 A schematic diagram of an inductor current waveform in a boost state under the dual-peak current control strategy provided by the present invention;

[0063] Fig.12 A schematic diagram of the waveform when the inductor current cannot be reset provided by the present invention;

[0064] Fig.13 A schematic diagram of the inductor current waveform when the converter output power reaches the maximum provided by the present invention;

[0065] Fig.14 The present invention provides that when the input voltage V in Equal to the output voltage V o Schematic diagram of inductor current waveform;

[0066] Fig.15 The present invention provides different load currents I rms Schematic diagram of the relationship with k;

[0067] Fig.15 In the figure, (a) is V in =36V, the output voltage is constant at 48V, different load current I o Next I rms Schematic diagram of the relationship between V and k, (b) is V in =60V, the output voltage is constant at 48V, different load current I o Next I rms Schematic diagram of the relationship with k. DETAILED DESCRIPTION

[0068] Specific implementation method 1: Combination Figure 3 and Figure 4 This embodiment is described. The FSBB double peak control strategy provided by the present invention described in this embodiment specifically includes:

[0069] According to the on and off states of the switch tube of the FSBB converter, the switching cycle is divided into four stages: energy storage stage DA, direct connection stage AB, energy release stage BC and clamping stage CD;

[0070] like Figure 3 As shown in the figure, for the four-switch Buck-Boost converter, there are three control degrees of freedom, namely, the on-time T1 of Q1 and Q4, the on-time T2 of Q1 and Q3, the on-time T3 of Q2 and Q3, and the on-time T4 of the uncontrolled quantity Q2 and Q4. Figure 3 As shown in (a), during the energy storage phase DA: Q1 and Q4 are turned on, V in Applied to the inductor L, so that i L Linear increase; e.g. Figure 3(b) As shown in the direct connection stage AB: Q1 and Q3 are turned on, V in -V o is applied to the inductor L. If V in >V o , then i L Increases linearly; if V in <V o ,i L Linear decrease; such as Figure 3 As shown in (c), Q2 and Q3 are turned on, and the voltage applied to the inductor L is -V o , so that i L Linear decrease; such as Figure 3 (d) shows the clamping stage CD: Q2 and Q4 are turned on, the voltage applied to the inductor L is zero, i L Remain unchanged.

[0071] The traditional peak current control is to compare the inductor current with the output of the voltage regulator and turn off the main switch when the inductor current exceeds the output of the voltage regulator. That is, the output of the voltage loop is used as the peak value of the given inductor current. This method is not suitable for the FSBB converter because there are two sets of complementary switches in the FSBB, and when the FSBB works in different states, the maximum point of the inductor current will change with the mode conversion, such as Figure 4 As shown in the figure, in the boost state, the peak value of the inductor current appears at point A, and in the buck state, the peak value of the inductor current appears at point B. When the input voltage and the output voltage are equal, the currents at points A and B are equal.

[0072] The energy storage time T1 is determined by the input voltage and I A The through time T2 is determined by the input voltage, output voltage and I A ,I B The energy release time T3 is determined by the output voltage and I B The clamping time T4 is determined by the duty cycle. According to the relationship between the input and output voltages, the inductor current, and the inductor value, the expressions (1)(2)(3) for the energy storage phase (DA) time interval T1, the direct connection phase (AB) time interval T2, and the energy release phase time interval (BC) T3 can be derived. It can be seen that the lack of a control relationship limits the freedom of converter control. Therefore, it is necessary to establish I A with I B The relationship between the two points is obtained by using the output of the voltage loop to control the current at the two points at the same time.

[0073] The expression of energy storage time T1 is:

[0074]

[0075] In formula (1), I A is the inductor current at point A, I Z The current required to achieve ZVS, L is the inductance;

[0076] The expression of the through time T2 is:

[0077]

[0078] In formula (2), I B is the inductor current at point B

[0079] The expression of energy release time T3 is:

[0080]

[0081] Based on the traditional peak current control, dual peak current control is proposed. That is, the moment of node A is determined by the inductor current and the output V c1 The comparison result determines that when the inductor current exceeds V c1 When Q3 is turned on and Q4 is turned off, the converter enters the direct connection stage T2 (AB) from the energy storage stage T1 (DA), and the size of node B is V c2 The output of the voltage regulator V c1 , input voltage and output voltage V in / V o And the optimization coefficient k. From this, we can get the expression of the inductor current at point A and point B:

[0082] The current inductance expression at point A is:

[0083] I A =V c1 (4);

[0084] The current inductance expression at point B is:

[0085]

[0086] According to formulas (4) and (5), when the input voltage V in Less than the output voltage V o That is V in / V o When it is less than 1, the inductor current I B A , and V in With V o The greater the difference B The value relative to I A The smaller the voltage is, the circuit will naturally work in the boost state. in / V o When it is greater than 1, the inductor current I​B >I A , at this time the circuit naturally works in a step-down state. From the expression, it can be seen that when V in 、V o When L is constant, I A and I B The size of V c1 related.

[0087] According to formula (4) and (5), the above formula can be expressed as:

[0088]

[0089] According to the volt-second balance across the inductor L in steady state, the voltage gain of the FSBB converter can be obtained as:

[0090]

[0091] From the above formula, we can know that the inductance value L and the current required for soft switching I z Under certain conditions, the voltage gain is only related to the voltage regulator output V c1 By establishing a relationship between the inductor current point A and point B, the voltage regulator output V is adjusted according to the input voltage and load size. c1 It naturally works in a certain state, so this control method is called "dual peak current control".

[0092] In summary, the advantage of the control strategy proposed in the present invention is that the digital controller only needs to detect the input and output voltages. L By comparison, the T1 and T2 time periods of the FSBB converter can be automatically adjusted according to the changes in input voltage and load, thus avoiding the traditional real-time calculation or lookup table method. This method makes full use of system resources, reduces calculation delay and calculation load compared to the real-time calculation method; and improves control accuracy and saves controller memory compared to the lookup table method.

[0093] Specific implementation method 2: Combination Fig.10 and Fig.11 This embodiment is explained. This embodiment analyzes the working state of the converter. Under the dual peak current control strategy, the inductor current of the FSBB mainly works in an unclamped discontinuous current mode (UDCM) or a clamped discontinuous current mode (CDCM). Figure 8 The figure shows different inductor current waveforms when the FSBB works in UDCM and CDCM respectively in the boost state. The dotted line ① represents the continuous current mode (CCM) of the inductor current, that is, the state in which the maximum energy can be transmitted at a constant frequency.

[0094] The increment of T2 and Vc1 The expression of the relationship between is:

[0095]

[0096] In formula (10), ΔT2 and ΔV c1 They are T2 and V c1 increment.

[0097] In order to ensure that FSBB can maintain good regulation performance when the load increases, that is, the energy delivered to the output side increases with the load increase, I B and T2 increase accordingly. According to formula (5), in dual peak control, I B Obviously, it will increase with the increase of load. For T2, if T2 decreases with the increase of load, the RMS value of the inductor current will increase sharply, which is not conducive to improving the efficiency of FSBB. Therefore, the k value should satisfy formula (11), and ΔT2 and ΔV c1 There is a positive correlation;

[0098] The expression of k value in boost state is:

[0099]

[0100] In formula (11), V in_min is the minimum input voltage.

[0101] When the load decreases, when I B =I z , FSBB starts to work in CDCM (clamped discontinuous current mode), such as Fig.10 To meet the ZVS (zero voltage switching) condition of Q2, when the load is low, I B needs to be clamped at I z In CDCM, T 2_CDCM The time interval is determined by the following equation:

[0102]

[0103] exist Fig.10 In the case shown, T 2_CDCM Become the dependent variable in CDCM, using only a single variable I A To adjust the output voltage, the dual peak current control strategy degenerates into peak current control.

[0104] Fig.11The figure shows different inductor current waveforms when FSBB works in UDCM and CDCM respectively in the buck state. The dotted line ① represents the continuous current mode (CCM). If T2 decreases with the increase of load, the increase of the RMS value of the inductor current will be aggravated, which is not good for the efficiency of FSBB. Therefore, the k value should satisfy formula (16), and ΔT2 and ΔV c1 There is a positive correlation;

[0105] The expression of k value in the step-down state is:

[0106]

[0107] In formula (13), V in_max is the maximum input voltage.

[0108] When the load is reduced to I A =I z , FSBB starts to work in CDCM (clamped discontinuous current mode), such as Fig.11 In order to meet the ZVS (zero voltage switching) condition of Q3, it is necessary to set I A Clamped at I z , in CDCM, T′ 2_CDCM The time interval is determined by formula (14):

[0109]

[0110] Considering I B =V c2 , T′ 2_CDCM Become the dependent variable in CDCM, and only use a single variable I B To adjust the output voltage, the dual peak current control strategy degenerates into peak current control. By analyzing the working state, it can be found that the proposed dual peak current control strategy always uses the voltage loop output V c1 To control the current amplitude I at point A A , and use V c2 To control the current amplitude I at point B B , whether it is light load or heavy load switching.

[0111] Specific implementation method three: Combination Figure 12-14 This embodiment is described. Under the dual peak control strategy, when T changes with the load, T1, T2 and T3 are all connected with V c1 The equation for the power transfer stage T can be derived from formula (6)(7)(8):

[0112]

[0113] As the load increases, V c1 Increase, the T value in the power transmission stage may increase, such as Fig.10 Therefore, some measures need to be taken to limit the T value during the power transfer phase and ensure that T ≤ T s Otherwise, T during the power transfer phase will be greater than the switching period, causing the inductor current to be unable to reset. Therefore, the inductor L must first be limited to meet the converter's requirements under heavy load conditions.

[0114] As the load increases, V c1 Increase, the T value in the power transmission stage may increase, such as Fig.12 Therefore, some measures need to be taken to limit the T value during the power transfer phase and ensure that T ≤ T s Otherwise, T during the power transfer phase will be greater than the switching period, causing the inductor current to be unable to reset.

[0115] First, the inductor L needs to be limited to meet the requirements of the converter under heavy load conditions. When the output power of the converter reaches the maximum, T4 = 0, and only when Q3 is turned on, the inductor current i L Inflow load, such as Fig.13 As shown in the shaded area, based on formulas (15) and (16), the maximum value of the inductance can be limited to:

[0116]

[0117] In the dual peak current control strategy, when the input voltage V in Equal to the output voltage V o When A The value is equal to I B The value of T2 tends to infinity, such as Fig.14 As shown, in this case, the power transfer stage T will be greater than the switching period. The maximum value of T2 needs to be limited to ensure that the converter can work normally in the entire range and to ensure that T ≤ T in all operating conditions. s The maximum value of T2 is T 2_max It can be derived from formula (17):

[0118]

[0119] Specific implementation method four: Combination Fig.15 This embodiment further describes the optimization design process of k:

[0120] The RMS value of the quadrilateral current is related to I A and I B When FSBB operates under the proposed dual peak current control strategy, formula (5) shows that IB The value of k and V c1 In order to minimize the peak and RMS values ​​of the inductor current, it is necessary to further calculate the optimal choice of the proportional factor k.

[0121] In UDCM (Unclamped Discontinuous Current Mode), the RMS value of the inductor current I rms Given by formula (18). At the same time, formula (16) provides the output current I o , k and V c1 Therefore, for a specific load current I o , we can get V corresponding to different k values c1 Substituting these values ​​into formula (18), we can obtain the corresponding current RMS value I rms :

[0122]

[0123] In addition, k should also satisfy the boundary conditions given in formula (20) and the restrictions in formulas (11) and (13). o is the output power, I A_max and I B_max isI A and I B The maximum value is usually related to the upper limit of the voltage loop PI output, f s is the operating frequency.

[0124]

[0125] Fig.15 The output voltage is constant at 48V and the load current I o Next I rms Relationship with K.

[0126] According to the restrictions of formulas (11) and (13), the value range of k is 0.8 to 1.3. in <V o , FSBB is in boost state, such as Fig.13 As shown in (a), as the k value increases, the RMS current I rms This is because the increase in k value leads to I B Therefore, the k value should be increased as much as possible to reduce I rms .

[0127] When V in >V o When FSBB is in a depressurized state (such as Fig. 9 (b) shows), at this time, the RMS current Irms As the k value increases, it decreases. This is because the increase in k value makes I B Therefore, the k value should be minimized in the step-down state to reduce I rms Comparing these two pictures, I rms The minimum value of is greater than the maximum value in the buck state. In order to make FSBB have good performance in both boost and buck voltage, k is selected as 0.8.

[0128] Specific implementation method five: Combination Figure 1-2 This embodiment is described. The control logic and method described in Specific Embodiments 1 to 4 involve current comparison and high switching frequency, which require high real-time performance and calculation speed of the control system. Therefore, this embodiment is realized by integrating STM32G474 with analog circuits. The overall architecture of the control system is as follows: Figure 1 As shown in the figure, the input and output voltages are sampled by the STM32G474, using two ADC channels and transmitted to the controller simultaneously through DMA. The controller performs PI compensation on the voltage signal to obtain the compensated voltage error signal V c1 , and calculate V c2 Both are converted into analog voltage signals by the controller's DAC, passed to the comparator module, and compared with the inductor current. The output of the comparator is passed to the logic control module, which controls the drive signal of the switch tube together with the STM32.

[0129] The implementation of the dual peak current control strategy of the four-switch Buck-Boost converter described in this embodiment uses a high-speed comparator to control the inductor current waveform in real time, thereby generating the corresponding power switch tube drive signal with high precision, avoiding the real-time calculation of the conduction time of each power switch tube and the front and rear bridge phase shift angle in the controller. In addition, compared with the control method using a 3D or 2D lookup table, this implementation is non-discrete and occupies almost no storage resources of the controller.

[0130] The control logic part is as follows Figure 2 As shown in the figure, module A is responsible for switching the inductor current at point B. Once one of the following three conditions is met, point B will be switched: First, the inductor current is greater than (or less than) the voltage loop output V c2 , which is the condition for dual peak current control; second, the inductor current is reduced to the current I required to achieve ZVS z , that is, the switch tube ZVS condition needs to be met; third, T2 reaches T 2_max , that is, it is necessary to ensure that T≤T s .

[0131] Module B is responsible for switching the inductor current at point A. Point A switches when one of the following two conditions is met: First, the inductor current is greater than the voltage loop output V c1 , which is the condition for dual peak current control; second, the inductor current needs to be greater than I z Module C is responsible for switching point C, requiring the inductor current to be less than -I z For point D, the STM32 sends a constant frequency f s pulse.

[0132] This embodiment Figure 2 An analog circuit is designed in the I part of module A to avoid the problem of output change when the NOR gate RS trigger is at a high level at the same time. The RC oscillator circuit can convert a long pulse signal into a narrow pulse to ensure the trigger level, so that the transistor of the subsequent circuit can be turned on normally. Once the narrow pulse is lower than the comparator output low level and the NOR gate RS trigger outputs a low level, the transistor is turned off; when the capacitor is charged to the upper limit comparator output is 0, the RS trigger outputs a high level to turn on the transistor. In this way, the narrow pulse is processed into a level signal with a fixed duration of 50ns to avoid signal conflict.

[0133] In order to achieve ZVS over a wide input range and full load range and meet transient requirements, the present invention proposes a dual-peak current control strategy for a four-switch Buck-Boost converter to avoid complex real-time calculations or the need for large amounts of data storage. This mode associates the two peak inflection points of the inductor current by introducing input and output voltages to achieve the functions of boost and buck. At the same time, the working principle of the proposed strategy is analyzed and the effective current minimization optimization design process of the inductor is derived, thereby improving the overall efficiency.

[0134] In addition, this embodiment also designs a time limit circuit to limit the maximum value of T2 at point A under specific conditions, such as Figure 2 As shown in the Ⅱ part of module A in the figure. The input of the NOT gate is high level and Q3 signal PWMC. Once Q3 is turned on, that is, starting from point A, the output of the NOT gate is low level, and the transistor is turned off to charge the capacitor. Once the threshold is reached, the OR gate outputs a high level to turn on the transistor to discharge, thereby achieving the maximum limit on T2.

[0135] In addition, a maximum time limit is set for the case where the input and output voltages are close. The control strategy proposed in the present invention can be implemented by high-speed comparators and low-latency logic gates, thereby saving storage and computing resources of the controller.

[0136] Example

[0137] Combination Figure 5-Figure 9This embodiment is explained. In order to verify the technical effect of the specific implementation of the present invention, this embodiment makes and tests a 300W prototype. The key parameters of the prototype are listed in Table 1. The prototype uses Infineon 120V MOSFET (BSC077N12NS3G) as a power switch, and the driver uses UCC21222DR of Texas Instruments (TI), and the dead time is controlled by an external resistor. The current detection uses the GS8092 350 MHz high-speed, low-distortion amplifier, which can accurately detect the inductor current. The high-speed, low-power comparator MX3502 and the low-latency American 74LVC series logic gate are also used.

[0138] Table 1

[0139]

[0140] like Figure 5 and Figure 7 As shown, in Figure 5 , Figure 6 and Figure 7 The steady-state experimental waveforms of the FSBB converter at 25% load, half load and full load are shown in Figure 2. in They are 36V, 48V and 60V respectively. gs1 and V ds1 are the gate drive signal and drain-source voltage of the power switch Q1, V ds3 is the drain-source voltage of the power switch Q3, i L is the inductor current. As shown in the figure, before turning on, the drain-source voltage of Q1 has decayed to zero, so Q1 achieves zero voltage turn-on. In fact, Q2, Q3, and Q4 also achieve zero voltage turn-on, but the waveforms here are not shown. As the load current decreases, the fluctuation of the inductor current also decreases, thereby reducing the light load loss. In addition, when the input voltage is 36V and 60V, the FSBB converter operates in discontinuous conduction mode (CDCM) under light load conditions. When the input voltage is 48V, T2 of the FSBB converter is in a constant duration state.

[0141] like Figure 8 As shown, Figure 8 The dynamic experimental waveforms are shown when the load changes from 25% to 75% when the input voltage is 36V, 48V and 60V, indicating that the FSBB converter has good dynamic performance. Fig. 9 The conversion efficiency of the FSBB converter was measured at input voltages of 36 V, 48 V, and 60 V. When Vin = 60 V, the maximum efficiency of the FSBB converter can reach 98.37%, and the full-load efficiency at different input voltages is higher than 97.13%.

[0142] As shown in Table 2, the main features of the proposed control strategy are compared with the existing control strategies. The contributions and innovations of the proposed dual-peak current control strategy can be summarized as follows:

[0143] 1. Compared with control schemes ② and ④, the control strategy proposed in the present invention does not require real-time calculation of complex conduction time and phase shift angle for each power switch to achieve optimal control of the four switches.

[0144] 2. Compared with control scheme ③, the strategy proposed in the present invention does not need to use a lookup table for data storage, thereby saving controller resources and improving control accuracy.

[0145] 3. Compared with control schemes ①, ②, ③ and ④, the control strategy proposed in the present invention does not require switching the control strategy when switching between light load and heavy load, thereby enhancing the stability of the converter during operation.

[0146] 4. Compared with control schemes ①, ②, and ③, the control strategy proposed in this invention has a larger |V in -V o |The higher efficiency of the FSBB converter is achieved under different conditions. Especially at full load, balanced efficiency is shown under different input voltages.

[0147] Table 2

[0148]

[0149] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A dual peak current control strategy for a four-switch Buck-Boost converter, characterized in that: Specifically include: According to the on and off states of the switch tube of the FSBB converter, the switching cycle is divided into four stages: energy storage stage DA, direct connection stage AB, energy release stage BC and clamping stage CD; When the inductor current rises / falls to the output of the voltage regulator and the coefficient k and V in / V o The product of The converter enters the energy release stage BC from the direct connection stage AB; By introducing the voltage regulator output V to point B c1 Point B is related to point A to limit the control freedom of FSBB; and the ratio information of input voltage to output voltage is detected. According to the relationship between the input voltage and the output voltage, the inductor current working state of FSBB boost / buck state is determined, and a control logic circuit is constructed to complete the dual peak current control.

2. The dual peak current control strategy of the four-switch Buck-Boost converter according to claim 1, characterized in that: When the input voltage V in Less than the output voltage V o When the inductor current I B A , the circuit naturally works in the boost state;​ Input voltage V in Greater than the output voltage V o When the inductor current I B >I A , the circuit naturally works in a step-down state; Build I A and I B The relationship between points A and B is used to control the current at points A and B at the same time by using the output of the voltage loop, and the current inductance expressions at points A and B are obtained; Combining the current inductance expressions at points A and B, when the output voltage V o , output voltage V o When the inductance L is fixed, I A and I B The size of V c1 Related, obtain the expressions of optimized energy storage time T1, direct time T2 and energy release time T3; The current inductance expression at point A is: I A =V c1 (1); The current inductance expression at point B is: The expression of the optimized energy storage time T1 is: The expression of the optimized through time T2 is: The expression of the optimized energy release time T3 is:

3. The dual peak current control strategy of the four-switch Buck-Boost converter according to claim 1, characterized in that: The control logic circuit comprises: Module A, module B, module C and module D; The module A is responsible for switching the inductor current at point B; The module B is responsible for switching the inductor current at point A; The module C is responsible for the switching point C, where the inductor current is less than -I z ; The module D is used to receive the constant frequency f sent by the sampling device s pulses, wherein the sampling device is used to sample the input voltage and the output voltage.

4. The dual peak current control strategy of the four-switch Buck-Boost converter according to claim 3, characterized in that: Module A is responsible for the switching of the inductor current at point B, specifically including: When any of the switching conditions 1, 2 and 3 is met, the inductor current is switched at point B, where the switching condition 1 is that the inductor current is not equal to the voltage loop output V c2 The second switching condition is that the inductor current is reduced to the current I required to achieve ZVS. z , switching condition three is that T2 reaches T 2_max And T≤T s ; Module B is responsible for the switching of the inductor current at point A, specifically including: When any of the switching conditions 4 and 5 is met, the inductor current is switched at point A. The switching condition 4 is that the inductor current is greater than the voltage loop output V c1 , switching condition five is that the inductor current is greater than I z .

5. The dual peak current control strategy of the four-switch Buck-Boost converter according to claim 4, characterized in that: Switching condition 3: T≤T s Specifically include: According to T1, T2, T3 and V c1 Get the expression of power transfer stage T; When the converter output power is maximum, T4 = 0, and only when Q3 is turned on, the inductor current i L The flow into the load, combined with the power transfer stage T, limits the maximum value of the inductance L; When the input voltage V in Equal to the output voltage V o , I A The value is equal to I B When the value of T2 tends to infinity, the power transfer stage T will be greater than the switching period. Limiting the maximum value of T2 ensures that the converter can work normally in the entire range and ensures that T≤T in all working conditions. s ; The expression of power transfer stage T is: The expression for limiting the maximum value of the inductance L is: The expression that limits the maximum value of T2 is:

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