Method for realizing client synchronization function in AS6802 protocol based on FPGA

Abstract

The invention discloses a method for realizing a synchronous client function in an AS6802 protocol based on an FPGA (Field Programmable Gate Array). The method comprises the following steps of: 1) receiving a PCF (Policy Control Function) sent by a switch; according to the method, the function of synchronizing the client in Ethernet time synchronization is achieved through the FPGA, and the method has the advantages of being low in delay, high in precision, high in fault tolerance, capable of improving system reliability and the like and is convenient to transplant and learn.

Description

Technical Field

[0001] The present invention relates to the field of network synchronization technology, and in particular to a method for realizing a synchronization client function in an AS6802 protocol based on FPGA. Background Art

[0002] With the widespread application of time-triggered Ethernet networks and their high real-time and deterministic performance, the open standard AS6802 clock synchronization protocol was promulgated in 2011. It has synchronization technology with deterministic, high fault tolerance and congestion-free communication. The design of the AS6802 synchronization client can be applied to time-triggered Ethernet systems in aerospace, automotive, medical and industrial applications, providing the ability to passively synchronize time-triggered Ethernet networks and detect the synchronization status of existing network synchronization members in real time.

[0003] The AS6802 clock synchronization protocol has three synchronization network roles, namely synchronization host-SM, synchronization client-SC and compression host-CM. How to achieve high precision, high real-time performance and high reliability of synchronization client-SC to solve the drawbacks of traditional Ethernet that cannot meet time requirements, so as to be applied to high-security and high-reliability application scenarios such as aerospace, industrial control and other fields is the focus of current research. To this end, this paper uses FPGA to independently design and implement the functions of the synchronization client-SC role through understanding the AS6802 protocol standard and studying the existing Ethernet time synchronization. Summary of the invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a method for implementing the synchronization client function in the AS6802 protocol based on FPGA, which implements the synchronization client function in Ethernet time synchronization through FPGA, which not only has the characteristics of low latency, high precision, high fault tolerance and improved system reliability, but also is easy to transplant and learn.

[0005] The present invention provides a method for realizing the synchronization client function in the AS6802 protocol based on FPGA. The state of the synchronization client includes an asynchronous stage and a synchronous stage. The asynchronous stage only includes an initial state; the synchronous stage includes a synchronous state and a stable synchronous state. The method includes the following steps: 1) The synchronization client receives the PCF frame sent by the switch, filters it, and solidifies the receiving time of the valid frame to form the local clock solidification time point and the device receiving time point, and saves it in the PCF frame; determines whether the PCF frame is an IN frame. If so and it is within the detection window of the synchronization client, the clock correction value is calculated based on the local clock solidification time point and its transparent clock is updated; the required information in the PCF frame is extracted and entered into the state machine of the synchronization client; Wherein, the number of members of the member vector in the PCF frame is the number of synchronous members if it is within the receiving window of the synchronous client, otherwise it is the number of asynchronous members; the frame types of the PCF frame include CS frame, CA frame and IN frame; 2) The synchronization client enters the initial state. If the received PCF frame is an IN frame and the number of synchronization members is greater than or equal to the state transition threshold from the initial state to the synchronization state, then it proceeds to step 3); otherwise, it remains in the current state and continues to judge; 3) The synchronization client enters the synchronization state, and the clock synchronization service maintains the synchronization update of the local clock and local integration cycle of the synchronization host, synchronization client and compression host in the time-triggered Ethernet; the group detection service maintains the change in the number of members to identify the loss of synchronization of the device in the time-triggered Ethernet executing the group detection service, and makes a state jump judgment in the current state according to the current state jump condition; At the asynchronous evaluation point, if the number of asynchronous members is greater than the preset minimum number of asynchronous members, return to step 2) and clear the synchronization state loop count; otherwise, keep the current state and continue to judge; At the synchronization evaluation point, if the number of synchronization members is less than the preset minimum number of synchronization members, then return to step 2), and clear the synchronization state cycle count; if the number of synchronization members is greater than or equal to the preset minimum number of synchronization members, and the synchronization state cycle count of the received PCF frame is greater than or equal to the preset synchronization state cycle number, and there is a synchronization state entering a stable synchronization state flag, then enter step 4), and clear the synchronization state cycle count; otherwise, keep judging in the current state, and the synchronization state cycle count +1; At the clock correction point, the current state is maintained and the local clock value is updated to the original local clock value + clock correction value; 4) The synchronization client enters the stable synchronization state, and the clock synchronization service maintains the synchronization update of the local clock and local integration cycle of the synchronization host, synchronization client and compression host in the time-triggered Ethernet; the group detection service maintains the change in the number of members to identify the synchronization loss of the device in the time-triggered Ethernet executing the group detection service, and makes a state jump judgment in the current state according to the current state jump condition; At the asynchronous evaluation point, if the number of asynchronous members is greater than or equal to the preset minimum number of asynchronous members, then return to step 2), and the stable synchronization state cycle count is reset to zero; otherwise, keep in the current state and continue to judge; At the synchronization evaluation point, if the number of synchronization members is less than the preset minimum number of synchronization members, and the stable synchronization state cycle count is greater than or equal to the preset stable synchronization state cycle count, then return to step 2), and the stable synchronization state cycle count is reset; if the number of synchronization members is less than the preset minimum number of synchronization members, and the stable synchronization state cycle count is less than the preset stable synchronization state cycle count, then maintain the current state, and the stable synchronization state cycle count + 1; if the number of synchronization members is greater than or equal to the preset minimum number of synchronization members, then maintain the current state, and the stable synchronization state cycle count is reset; otherwise, maintain the current state and continue to judge, and the stable synchronization state cycle count is also maintained; At the clock correction point, the current state is maintained and the local clock value is updated to the original local clock value + clock correction value.

[0006] Furthermore, in the step 1), the required information extracted from the PCF frame includes the frame type, member vector, integration period, synchronization member state threshold jump judgment, local clock solidification time point and device reception time point; Among them, the local clock solidification point is used to calculate the clock correction value; The synchronization state threshold jump judgment performs member detection in the initial state; If the synchronous membership vector is within the receiving window of the synchronous client, synchronous membership detection is performed in the synchronous state and the stable synchronous state, otherwise asynchronous membership detection is performed.

[0007] Compared with the prior art, the beneficial effects of the present invention are: The present invention replaces the existing IP core by using the function of the synchronization client-SC in the AS6802 protocol implemented by FPGA, so that the synchronization client is more flexible in processing Ethernet data frames, and can dynamically estimate and correct the reception delay of the PCF frame, thereby improving the synchronization accuracy of the synchronization client. At the same time, it also reduces dynamic delay and improves synchronization accuracy. In addition, it also has the characteristics of low cost and easy transplantation.

[0008] It should be understood that the contents described in the summary of the invention are not intended to limit the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 A flowchart of a method for implementing a synchronous client function in the AS6802 protocol based on FPGA; Figure 2Schematic diagram of the connection of synchronization clients in a time-triggered Ethernet network. DETAILED DESCRIPTION

[0010] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It should also be noted that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0011] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0012] Please refer to Figure 1~Figure 2 The embodiment of the present invention provides a method for implementing the synchronization client function in the AS6802 protocol based on FPGA, wherein the state of the synchronization client includes an asynchronous phase and a synchronous phase, wherein the asynchronous phase only includes an initial state; and the synchronous phase includes a synchronous state and a stable synchronous state, wherein the method includes the following steps: 1) The synchronization client receives the PCF frame sent by the switch, filters it, and solidifies the receiving time of the valid frame to form the local clock solidification time point and the device receiving time point, and saves it in the PCF frame; determines whether the PCF frame is an IN frame. If so and it is within the detection window of the synchronization client, the clock correction value is calculated based on the local clock solidification time point and its transparent clock is updated; the required information in the PCF frame is extracted and entered into the state machine of the synchronization client; Wherein, the number of members of the member vector in the PCF frame is the number of synchronous members if it is within the receiving window of the synchronous client, otherwise it is the number of asynchronous members; the frame types of the PCF frame include CS frame, CA frame and IN frame; Extract the required information in the PCF frame, including frame type, member vector, integration period, synchronous member state threshold jump judgment, local clock solidification time point and device reception time point; Among them, the local clock solidification point is used to calculate the clock correction value; The synchronization state threshold jump judgment performs member detection in the initial state; If the synchronous member vector is within the receiving window of the synchronous client, synchronous member detection is performed in the synchronous state and the stable synchronous state, otherwise asynchronous member detection is performed; 2) The synchronization client enters the initial state. If the received PCF frame is an IN frame and the number of synchronization members is greater than or equal to the state transition threshold from the initial state to the synchronization state, then it proceeds to step 3); otherwise, it remains in the current state and continues to judge; 3) The synchronization client enters the synchronization state, and the clock synchronization service maintains the synchronization update of the local clock and local integration cycle of the synchronization host, synchronization client and compression host in the time-triggered Ethernet; the group detection service maintains the change in the number of members to identify the loss of synchronization of the device in the time-triggered Ethernet executing the group detection service, and makes a state jump judgment in the current state according to the current state jump condition; At the asynchronous evaluation point, if the number of asynchronous members is greater than the preset minimum number of asynchronous members, return to step 2) and clear the synchronization state loop count; otherwise, keep the current state and continue to judge; At the synchronization evaluation point, if the number of synchronization members is less than the preset minimum number of synchronization members, then return to step 2), and clear the synchronization state cycle count; if the number of synchronization members is greater than or equal to the preset minimum number of synchronization members, and the synchronization state cycle count of the received PCF frame is greater than or equal to the preset synchronization state cycle number, and there is a synchronization state entering a stable synchronization state flag, then enter step 4), and clear the synchronization state cycle count; otherwise, keep judging in the current state, and the synchronization state cycle count +1; At the clock correction point, the current state is maintained and the local clock value is updated to the original local clock value + clock correction value; 4) The synchronization client enters the stable synchronization state, and the clock synchronization service maintains the synchronization update of the local clock and local integration cycle of the synchronization host, synchronization client and compression host in the time-triggered Ethernet; the group detection service maintains the change in the number of members to identify the synchronization loss of the device in the time-triggered Ethernet executing the group detection service, and makes a state jump judgment in the current state according to the current state jump condition; At the asynchronous evaluation point, if the number of asynchronous members is greater than or equal to the preset minimum number of asynchronous members, then return to step 2), and the stable synchronization state cycle count is reset to zero; otherwise, keep in the current state and continue to judge; At the synchronization evaluation point, if the number of synchronization members is less than the preset minimum number of synchronization members, and the stable synchronization state cycle count is greater than or equal to the preset stable synchronization state cycle count, then return to step 2), and the stable synchronization state cycle count is reset; if the number of synchronization members is less than the preset minimum number of synchronization members, and the stable synchronization state cycle count is less than the preset stable synchronization state cycle count, then maintain the current state, and the stable synchronization state cycle count + 1; if the number of synchronization members is greater than or equal to the preset minimum number of synchronization members, then maintain the current state, and the stable synchronization state cycle count is reset; otherwise, maintain the current state and continue to judge, and the stable synchronization state cycle count is also maintained; At the clock correction point, the current state is maintained and the local clock value is updated to the original local clock value + clock correction value. Example

[0013] Please refer to Figure 2 This case simulates a simple time-triggered Ethernet network formed by a synchronous client and TTTech's switches and end systems to implement and verify the content of this application.

[0014] In this embodiment, a group of configuration tables are called, and the content of the configuration table corresponds to the role one by one. That is, the switch-SW1 corresponds to the only switch configuration table in the group of configuration tables, the synchronization hosts ES1~ES3 correspond to the configuration tables of ES1~ES3, and the synchronization client-ES4 is configured as the SC-synchronization client role. Before forming a network, the TTTech end system and the switch are powered on and the configuration table is loaded. After the configuration is completed, the switch status display light is observed to see whether it is in the synchronization state, so as to determine whether the status display of the synchronization client is correct.

[0015] Now set the ES4 written by FPGA as a synchronization client, and calculate the relevant configuration of the synchronization client by using the end system configuration table. Since the synchronization client does not send PCF frames, the ILA capture signal in the FPGA and the synchronization client state machine display can be used to determine whether the PCF frame has reached the synchronization client and applied. The synchronization requirements for the synchronization client are as follows: 1. If the received PCF frame is an IN frame and the number of its local synchronization members is greater than the state transition threshold from the initial state to the synchronization state, the synchronization state can be reached; 2. If it is found in the synchronous state that the number of synchronous members is not enough to reach the minimum number of synchronous members or the number of asynchronous members reaches the minimum number of asynchronous members, it will return to the initial state for re-detection; 3. In the synchronization state and stable synchronization state, the number of local synchronization members and the number of local asynchronous members will be constantly detected to facilitate real-time status updates. At the same time, it will also ensure that the local clock and local inheritance cycle of the synchronization client can be synchronized and updated with the synchronization host and compression host in the network.

[0016] The method of the present invention realizes the function of the synchronization client in the AS6802 protocol based on FPGA, and realizes the function of the synchronization client in Ethernet time synchronization through FPGA. It not only has the characteristics of low delay, high precision, high fault tolerance and improved system reliability, but also is easy to transplant and learn.

[0017] In the description of this specification, the description of the terms "one embodiment", "some embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0018] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for implementing the synchronization client function in the AS6802 protocol based on FPGA, wherein the state of the synchronization client includes an asynchronous phase and a synchronous phase, wherein the asynchronous phase only includes an initial state; and the synchronous phase includes a synchronous state and a stable synchronous state, wherein: The method comprises the following steps: 1) The synchronization client receives the PCF frame sent by the switch, filters it, and solidifies the receiving time of the valid frame to form the local clock solidification time point and the device receiving time point, and saves it in the PCF frame; determines whether the PCF frame is an IN frame. If so and it is within the detection window of the synchronization client, the clock correction value is calculated based on the local clock solidification time point and its transparent clock is updated; the required information in the PCF frame is extracted and entered into the state machine of the synchronization client; Wherein, the number of members of the member vector in the PCF frame is the number of synchronous members if it is within the receiving window of the synchronous client, otherwise it is the number of asynchronous members; the frame types of the PCF frame include CS frame, CA frame and IN frame; 2) The synchronization client enters the initial state. If the received PCF frame is an IN frame and the number of synchronization members is greater than or equal to the state transition threshold from the initial state to the synchronization state, then it proceeds to step 3); otherwise, it remains in the current state and continues to judge; 3) The synchronization client enters the synchronization state, and the clock synchronization service maintains the synchronization update of the local clock and local integration cycle of the synchronization host, synchronization client and compression host in the time-triggered Ethernet; the group detection service maintains the change in the number of members to identify the loss of synchronization of the device in the time-triggered Ethernet executing the group detection service, and makes a state jump judgment in the current state according to the current state jump condition; At the asynchronous evaluation point, if the number of asynchronous members is greater than the preset minimum number of asynchronous members, return to step 2) and clear the synchronization state loop count; otherwise, keep the current state and continue to judge; At the synchronization evaluation point, if the number of synchronization members is less than the preset minimum number of synchronization members, then return to step 2), and clear the synchronization state cycle count; if the number of synchronization members is greater than or equal to the preset minimum number of synchronization members, and the synchronization state cycle count of the received PCF frame is greater than or equal to the preset synchronization state cycle number, and there is a synchronization state entering a stable synchronization state flag, then enter step 4), and clear the synchronization state cycle count; otherwise, keep judging in the current state, and the synchronization state cycle count +1; At the clock correction point, the current state is maintained and the local clock value is updated to the original local clock value + clock correction value; 4) The synchronization client enters the stable synchronization state, and the clock synchronization service maintains the synchronization update of the local clock and local integration cycle of the synchronization host, synchronization client and compression host in the time-triggered Ethernet; the group detection service maintains the change in the number of members to identify the synchronization loss of the device in the time-triggered Ethernet executing the group detection service, and makes a state jump judgment in the current state according to the current state jump condition; At the asynchronous evaluation point, if the number of asynchronous members is greater than or equal to the preset minimum number of asynchronous members, then return to step 2), and the stable synchronization state cycle count is reset to zero; otherwise, keep in the current state and continue to judge; At the synchronization evaluation point, if the number of synchronization members is less than the preset minimum number of synchronization members, and the stable synchronization state cycle count is greater than or equal to the preset stable synchronization state cycle count, then return to step 2), and the stable synchronization state cycle count is reset; if the number of synchronization members is less than the preset minimum number of synchronization members, and the stable synchronization state cycle count is less than the preset stable synchronization state cycle count, then maintain the current state, and the stable synchronization state cycle count + 1; if the number of synchronization members is greater than or equal to the preset minimum number of synchronization members, then maintain the current state, and the stable synchronization state cycle count is reset; otherwise, maintain the current state and continue to judge, and the stable synchronization state cycle count is also maintained; At the clock correction point, the current state is maintained and the local clock value is updated to the original local clock value + clock correction value.

2. The method for realizing the synchronization client function in the AS6802 protocol based on FPGA according to claim 1, characterized in that: In the step 1), the required information extracted from the PCF frame includes the frame type, member vector, integration period, synchronization member state threshold jump judgment, local clock solidification time point and device reception time point; Among them, the local clock solidification point is used to calculate the clock correction value; The synchronization state threshold jump judgment performs member detection in the initial state; If the synchronous membership vector is within the receiving window of the synchronous client, synchronous membership detection is performed in the synchronous state and the stable synchronous state, otherwise asynchronous membership detection is performed.

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