Method for realizing compression host function in AS6802 protocol based on FPGA

Abstract

The invention discloses a method for realizing a compression host function in an AS6802 protocol based on an FPGA. The method comprises the following steps: 1) receiving a PCF frame sent by a synchronization host; 2) judging a received IN frame; the group detection result carries the member number, the member vector and the synchronous judgment mark after being sorted and enters a state machine of the compression host; 3) entering an initial state; 4) entering an IN frame detection state with high integrity; 5) entering an asynchronous state; 6) the standard integrity enters a CA frame relay continuous state; according to the method, the function of compressing the host in Ethernet time synchronization is achieved through the FPGA, and the method has the advantages of being low in delay, high in precision, high in fault tolerance, capable of improving system reliability and the like and is convenient to transplant and learn.

Description

Technical Field

[0001] The present invention relates to the technical field of network synchronization, and in particular to a method for realizing a host compression function in an AS6802 protocol based on FPGA. Background Art

[0002] With the widespread application of time-triggered Ethernet networks and their high real-time and deterministic performance, the open standard AS6802 clock synchronization protocol was promulgated in 2011. It has synchronization technology with deterministic, high fault tolerance and congestion-free communication. The design of the AS6802 synchronization client can be applied to time-triggered Ethernet systems in aerospace, automotive, medical and industrial applications, providing the ability to passively synchronize time-triggered Ethernet networks and detect the synchronization status of existing network synchronization members in real time.

[0003] The AS6802 clock synchronization protocol has three synchronization network roles, namely, synchronization host-SM, synchronization client-SC and compression host-CM. How to establish a high-precision, high-real-time, high-reliability and high-fault-tolerant synchronization network under the high integrity or standard integrity of the compression host-CM, and perform flow control on the basis of the synchronization network to solve the problem that traditional Ethernet cannot meet the time requirements, so as to be applied to high-security and high-reliability application scenarios such as aerospace, industrial control and other fields is the focus of current research. To this end, this article uses FPGA to independently design and implement the functions of the compression host-CM role through the understanding of the AS6802 protocol standard and the study of existing Ethernet time synchronization. Summary of the invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a method for implementing the compression host function in the AS6802 protocol based on FPGA, which implements the function of the compression host in Ethernet time synchronization through FPGA, which not only has the characteristics of low latency, high precision, high fault tolerance and improved system reliability, but also is easy to transplant and learn.

[0005] The present invention provides a method for realizing a compression host function in an AS6802 protocol based on FPGA, wherein the state of the compression host includes an asynchronous stage and a synchronous stage; when the compression host is of standard integrity, its asynchronous stage includes an initial state, an asynchronous state, a CA frame relay continuous state and a waiting IN frame state, and the synchronous stage includes a synchronous state and a stable synchronous state; when the compression host is of high integrity, its asynchronous stage includes an initial state, an intermediate waiting state and an asynchronous state, and the synchronous stage includes a temporary synchronous state, a synchronous state and a stable synchronous state; the method comprises the following steps: 1) The compression host receives the PCF frame sent by the synchronization host. The PCF frame is compressed in the collection stage, calculation stage and delay stage. If the compressed PCF frame is an IN frame, it enters step 2). Otherwise, it enters the state machine of the compression host and enters step 3); 2) Determine whether the number of members of the received IN frame is within the receiving window of the compression host. If so, it is the number of synchronous members for synchronous group detection; otherwise, it is the number of asynchronous members for asynchronous group detection; if the received IN frame is within the receiving window and the number of members is greater than or equal to the preset optimal number of members, calculate the clock correction value for correcting the local clock; after the group detection result is sorted, it carries the number of members, member vector and synchronization judgment flag into the state machine of the compression host; 3) The compression host enters the initial state; When the compression host is of high integrity, within the preset time length, if no IN frame is received, or the number of synchronization members of the received IN frame is less than the preset minimum value for entering the IN frame detection state, then proceed to step 5); if an IN frame is received and the number of synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, then proceed to step 9); if an IN frame is received and the number of synchronization members is less than the preset minimum value for entering the synchronization state and greater than or equal to the preset minimum value for entering the IN frame detection state, then proceed to step 4); When the compression host is of standard integrity, within the preset time length, if an IN frame is received and the number of its synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, then go to step 9); otherwise, go to step 5); 4) The high integrity compression host enters the IN frame detection state. In the integration cycle after the IN frame is integrated, if the number of synchronization members of the received IN frame is less than the preset minimum number of synchronization members and is not 0, then go to step 8); if its number of synchronization members is 0, then go to step 5); if its number of synchronization members is greater than or equal to the preset minimum number of synchronization members, then remain in the current state and continue to judge the IN frame in the next integration cycle; 5) The compression host enters an asynchronous state; When the compression host is of standard integrity, if the number of synchronization members of the received CS frame or CA frame is greater than or equal to the preset minimum number of synchronization members, proceed to step 6); if the number of synchronization members of the received IN frame is greater than or equal to the preset minimum value for entering the synchronization state, proceed to step 9); When the compression host is of high integrity, if an IN frame is received and the number of its synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, then go to step 9); if an IN frame is received and the number of its synchronization members is less than the preset minimum value for entering the synchronization state, and greater than or equal to the preset minimum value for entering the temporary synchronization state, then go to step 8); otherwise, keep in the current state and continue to judge; 6) The standard integrity compression host enters the CA frame relay continuous state, relays the CA frame for a preset fixed duration, and then enters step 7); 7) The standard integrity compression host enters the waiting IN frame state. Within the preset waiting IN frame time, if an IN frame is received and the number of its synchronization members is greater than or equal to the minimum value for entering the synchronization state, then it enters step 9), otherwise it returns to step 5); 8) The high integrity compression host enters the temporary synchronization state and synchronizes with at least one group of synchronization hosts; At the asynchronous evaluation point, if the number of asynchronous members is greater than or equal to the preset minimum number of asynchronous members, return to step 5), otherwise continue to judge in the current state; At the synchronization evaluation point, if the number of synchronization members is less than the preset minimum value of the temporary synchronization state, return to step 5); otherwise, determine whether the number of synchronization members is greater than or equal to the state jump threshold from the temporary synchronization state to the synchronization state, if so, proceed to step 9), otherwise, maintain the current state and continue to judge; At the clock correction point, the current state is maintained and the local clock is updated to the original local clock value + clock correction value; 9) The compression host enters the synchronization state. If the number of synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, and there is a sign that the synchronization state has entered a stable synchronization state, then proceed to step 10); if the number of synchronization members is less than the preset minimum value for entering the synchronization state, return to step 3); otherwise, continue to judge in the current state; At the asynchronous evaluation point, if the number of asynchronous members is greater than or equal to the preset minimum number of asynchronous members, return to step 3), otherwise, continue to judge in the current state, and the synchronous state loop count is reset to zero; At the synchronization evaluation point: When the compression host is of standard integrity, if the number of synchronization members is less than the preset minimum value for entering the synchronization state, then return to step 3), and the synchronization state cycle count is reset; if the number of synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, then determine whether there is a synchronization state to stable synchronization state flag, if so and the synchronization state cycle count is greater than or equal to the preset synchronization state cycle number, then enter step 10), the synchronization state cycle count is reset; otherwise, keep in the current state, and the synchronization state cycle count +1; When the compression host is of high integrity, if the number of synchronization members is less than the preset minimum value for entering the synchronization state, then return to step 8), and the synchronization state cycle count is reset; if the number of synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, then determine whether there is a synchronization state to stable synchronization state flag, if so and the synchronization state cycle count is greater than or equal to the preset synchronization state cycle number, then enter step 10), the synchronization state cycle count is reset; otherwise, keep in the current state, and the synchronization state cycle count +1; At the clock correction point, the current state is maintained and the local clock is updated to the original local clock value + clock correction value; 10) The compression host enters a stable synchronization state, achieving the highest level of synchronization quality, configured to withstand temporary loss of all protocol control frames in the network; If the number of asynchronous members is greater than or equal to the preset minimum number of asynchronous members, return to step 3), otherwise keep judging in the current state, and reset the stable synchronization state cycle count; At the synchronization evaluation point, if the number of synchronization members is less than the preset minimum value for entering the stable synchronization state, and the stable synchronization state cycle count is greater than or equal to the preset number of stable synchronization cycles, then enter step 3), and the stable synchronization state cycle count is cleared; if the number of synchronization members is less than the preset minimum value for entering the stable synchronization state, and the stable synchronization state cycle count is less than the preset number of stable synchronization cycles, then maintain the current state, and the stable synchronization state cycle count is +1; if the number of synchronization members is greater than or equal to the preset minimum value for entering the stable synchronization state, then maintain the current state, and the stable synchronization state cycle count is cleared; At the clock correction point, the current state is maintained and the local clock is updated to the original local clock value + clock correction value.

[0006] Furthermore, the collection phase is: After the first observation window, if the number of collected and solidified PCF frames is 1, the collection of PCF frames will stop; if the number of collected and solidified PCF frames is greater than 1, the second observation window will be started to continue collecting solidified PCF frames; if at least one solidified PCF frame is received during the second observation window, the third observation window will be opened after the second observation window to continue collecting solidified PCF frames; and so on, until no solidified PCF frames are received in the next observation window, the collection is completed at the end of the observation window; The fixed PCF frame refers to a PCF frame that is not received in the first observation window and has the same frame type and integration period as the second PCF frame and becomes the fixed PCF frame.

[0007] Furthermore, in the collection phase, the compression host ends the collection process before the first fixed-line time point + the maximum observation window; Among them, the maximum observation window = (f+1)*observation window, f is a configurable parameter, which specifies the number of allowed faulty synchronization hosts. If the synchronization host has a single fault-tolerant feature, f=1; if it has a dual fault-tolerant feature, f=2.

[0008] Furthermore, the calculation stage is: The calculation stage mainly calculates the compression point by receiving the solidification time point in the PCF frame; that is, the compression correction value is calculated by the relative distance time between the solidification time point of the received PCF frame and the solidification time point of the first received PCF frame; If there is an input PCF frame, the compression correction value is 0; If there are two input PCF frames, the compression correction value = (solidification time point of the second PCF frame - solidification time point of the first PCF frame) / 2; If there are three input PCF frames, the compression correction value = the solidification time point of the second PCF frame - the solidification time point of the first PCF frame; If there are four input PCF frames, the compression correction value = ((the solidification time point of the second PCF frame - the solidification time point of the first PCF frame) + (the solidification time point of the third PCF frame - the solidification time point of the first PCF frame)) / 2; If there are five input PCF frames, the compression correction value = ((solidification time point of the second PCF frame - solidification time point of the first PCF frame) + (solidification time point of the fourth PCF frame - solidification time point of the first PCF frame)) / 2; 6) If there are more than five input PCF frames, the compression correction value = ((solidification time point of the Kth PCF frame - solidification time point of the first PCF frame) + (solidification time point of the second PCF frame - solidification time point of the first PCF frame)) / 2, K = f + 1; The compression function delay is: the maximum observation window + the static delay that can be calculated offline + the compression correction value; The compression point is: the first solidification time point + compression function delay; The first solidification time point refers to the solidification time point in the PCF frame where a given compression function is started.

[0009] Furthermore, the delay phase is: When the local clock reaches the fixed time point, the received PCF frame is compressed, and a maximum observation window time is delayed, and then the fixed time point of the PFC frame is updated.

[0010] Compared with the prior art, the beneficial effects of the present invention are: The present invention replaces the existing IP core by using the compression host-CM function in the AS6802 protocol implemented by FPGA, so that the compression host is more flexible in processing Ethernet data frames, and can dynamically estimate and correct the reception delay of the PCF frame, thereby improving the synchronization accuracy of the compression host. At the same time, it also reduces dynamic delay and improves synchronization accuracy. In addition, it also has the characteristics of low cost and easy transplantation.

[0011] It should be understood that the contents described in the summary of the invention are not intended to limit the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 A flowchart of a method for implementing a compression host function in the AS6802 protocol based on FPGA; Figure 2 Schematic diagram of the connection of compression host in time-triggered Ethernet network. DETAILED DESCRIPTION

[0013] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant inventions, rather than to limit the invention. It should also be noted that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0014] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0015] Please refer to Figure 1~Figure 2 The embodiment of the present invention provides a method for implementing the compression host function in the AS6802 protocol based on FPGA, wherein the state of the compression host includes an asynchronous stage and a synchronous stage; when the compression host is of standard integrity, its asynchronous stage includes an initial state, an asynchronous state, a CA frame relay continuous state, and a waiting IN frame state, and the synchronous stage includes a synchronous state and a stable synchronous state; when the compression host is of high integrity, its asynchronous stage includes an initial state, an intermediate waiting state, and an asynchronous state, and the synchronous stage includes a temporary synchronous state, a synchronous state, and a stable synchronous state; the method comprises the following steps: 1) The compression host receives the PCF frame sent by the synchronization host. The PCF frame is compressed in the collection stage, calculation stage and delay stage. If the compressed PCF frame is an IN frame, it enters step 2). Otherwise, it enters the state machine of the compression host and enters step 3); Wherein, the collection stage is: After the first observation window, if the number of collected and solidified PCF frames is 1, the collection of PCF frames will stop; if the number of collected and solidified PCF frames is greater than 1, the second observation window will be started to continue collecting solidified PCF frames; if at least one solidified PCF frame is received during the second observation window, the third observation window will be opened after the second observation window to continue collecting solidified PCF frames; and so on, until no solidified PCF frames are received in the next observation window, the collection is completed at the end of the observation window; A fixed PCF frame refers to a PCF frame that does not receive a second PCF frame with the same frame type and integration period in the first observation window and becomes a fixed PCF frame; In the collection phase, the compression host ends the collection process before the first fixed-line time point + the maximum observation window; Maximum observation window = (f+1) * observation window, f is a configurable parameter, which specifies the number of allowed faulty synchronization hosts. If the synchronization host has a single fault-tolerant feature, f=1; if it has a dual fault-tolerant feature, f=2; The calculation phases are: The calculation stage mainly calculates the compression point by receiving the solidification time point in the PCF frame; that is, the compression correction value is calculated by the relative distance time between the solidification time point of the received PCF frame and the solidification time point of the first received PCF frame; If there is an input PCF frame, the compression correction value is 0; If there are two input PCF frames, the compression correction value = (solidification time point of the second PCF frame - solidification time point of the first PCF frame) / 2; If there are three input PCF frames, the compression correction value = the solidification time point of the second PCF frame - the solidification time point of the first PCF frame; If there are four input PCF frames, the compression correction value = ((the solidification time point of the second PCF frame - the solidification time point of the first PCF frame) + (the solidification time point of the third PCF frame - the solidification time point of the first PCF frame)) / 2; If there are five input PCF frames, the compression correction value = ((solidification time point of the second PCF frame - solidification time point of the first PCF frame) + (solidification time point of the fourth PCF frame - solidification time point of the first PCF frame)) / 2; 6) If there are more than five input PCF frames, the compression correction value = ((solidification time point of the Kth PCF frame - solidification time point of the first PCF frame) + (solidification time point of the second PCF frame - solidification time point of the first PCF frame)) / 2, K = f + 1; The compression function delay is: the maximum observation window + the static delay that can be calculated offline + the compression correction value; The compression point is: the first solidification time point + compression function delay; The first solidification time point refers to the solidification time point in the PCF frame where the given compression function is started; The delay phase is: When the local clock reaches the fixed time point, the received PCF frame is compressed, and a maximum observation window time is delayed, and then the fixed time point of the PFC frame is updated; 2) Determine whether the number of members of the received IN frame is within the receiving window of the compression host. If so, it is the number of synchronous members for synchronous group detection; otherwise, it is the number of asynchronous members for asynchronous group detection; if the received IN frame is within the receiving window and the number of members is greater than or equal to the preset optimal number of members, calculate the clock correction value for correcting the local clock; after the group detection result is sorted, it carries the number of members, member vector and synchronization judgment flag into the state machine of the compression host; 3) The compression host enters the initial state; When the compression host is of high integrity, within the preset time length, if no IN frame is received, or the number of synchronization members of the received IN frame is less than the preset minimum value for entering the IN frame detection state, the compression host cannot be directly synchronized to the entire time-triggered Ethernet network, and proceeds to step 5); if an IN frame is received and the number of its synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, proceed to step 9); if an IN frame is received and the number of its synchronization members is less than the preset minimum value for entering the synchronization state and greater than or equal to the preset minimum value for entering the IN frame detection state, proceed to step 4); When the compression host is of standard integrity, within the preset time length, if an IN frame is received and the number of its synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, then go to step 9); otherwise, go to step 5); 4) The high integrity compression host enters the IN frame detection state. In the integration cycle after the IN frame is integrated, if the number of synchronization members of the received IN frame is less than the preset minimum number of synchronization members and is not 0, then go to step 8); if its number of synchronization members is 0, then go to step 5); if its number of synchronization members is greater than or equal to the preset minimum number of synchronization members, then remain in the current state and continue to judge the IN frame in the next integration cycle; 5) The compression host enters an asynchronous state; When the compression host is of standard integrity, if the number of synchronization members of the received CS frame or CA frame is greater than or equal to the preset minimum number of synchronization members, proceed to step 6); if the number of synchronization members of the received IN frame is greater than or equal to the preset minimum value for entering the synchronization state, proceed to step 9); When the compression host is of high integrity, if an IN frame is received and the number of its synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, then go to step 9); if an IN frame is received and the number of its synchronization members is less than the preset minimum value for entering the synchronization state, and greater than or equal to the preset minimum value for entering the temporary synchronization state, then go to step 8); otherwise, keep in the current state and continue to judge; 6) The standard integrity compression host enters the CA frame relay continuous state, relays the CA frame for a preset fixed duration, and then enters step 7); 7) The standard integrity compression host enters the waiting IN frame state. Within the preset waiting IN frame time, if an IN frame is received and the number of its synchronization members is greater than or equal to the minimum value for entering the synchronization state, then it enters step 9), otherwise it returns to step 5); 8) The high integrity compression host enters the temporary synchronization state and synchronizes with at least one group of synchronization hosts; At the asynchronous evaluation point, if the number of asynchronous members is greater than or equal to the preset minimum number of asynchronous members, return to step 5), otherwise continue to judge in the current state; At the synchronization evaluation point, if the number of synchronization members is less than the preset minimum value of the temporary synchronization state, return to step 5); otherwise, determine whether the number of synchronization members is greater than or equal to the state jump threshold from the temporary synchronization state to the synchronization state, if so, proceed to step 9), otherwise, maintain the current state and continue to judge; At the clock correction point, the current state is maintained and the local clock is updated to the original local clock value + clock correction value; 9) The compression host enters the synchronization state. If the number of synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, and there is a sign that the synchronization state has entered a stable synchronization state, then proceed to step 10); if the number of synchronization members is less than the preset minimum value for entering the synchronization state, return to step 3); otherwise, continue to judge in the current state; At the asynchronous evaluation point, if the number of asynchronous members is greater than or equal to the preset minimum number of asynchronous members, return to step 3), otherwise, continue to judge in the current state, and the synchronous state loop count is reset to zero; At the synchronization evaluation point: When the compression host is of standard integrity, if the number of synchronization members is less than the preset minimum value for entering the synchronization state, then return to step 3), and the synchronization state cycle count is reset; if the number of synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, then determine whether there is a synchronization state to stable synchronization state flag, if so and the synchronization state cycle count is greater than or equal to the preset synchronization state cycle number, then enter step 10), the synchronization state cycle count is reset; otherwise, keep in the current state, and the synchronization state cycle count +1; When the compression host is of high integrity, if the number of synchronization members is less than the preset minimum value for entering the synchronization state, then return to step 8), and the synchronization state cycle count is reset; if the number of synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, then determine whether there is a synchronization state to stable synchronization state flag, if so and the synchronization state cycle count is greater than or equal to the preset synchronization state cycle number, then enter step 10), the synchronization state cycle count is reset; otherwise, keep in the current state, and the synchronization state cycle count +1; At the clock correction point, the current state is maintained and the local clock is updated to the original local clock value + clock correction value; 10) The compression host enters a stable synchronization state, achieving the highest level of synchronization quality, configured to withstand temporary loss of all protocol control frames in the network; If the number of asynchronous members is greater than or equal to the preset minimum number of asynchronous members, return to step 3), otherwise keep judging in the current state, and reset the stable synchronization state cycle count; At the synchronization evaluation point, if the number of synchronization members is less than the preset minimum value for entering the stable synchronization state, and the stable synchronization state cycle count is greater than or equal to the preset number of stable synchronization cycles, then enter step 3), and the stable synchronization state cycle count is cleared; if the number of synchronization members is less than the preset minimum value for entering the stable synchronization state, and the stable synchronization state cycle count is less than the preset number of stable synchronization cycles, then maintain the current state, and the stable synchronization state cycle count is +1; if the number of synchronization members is greater than or equal to the preset minimum value for entering the stable synchronization state, then maintain the current state, and the stable synchronization state cycle count is cleared; At the clock correction point, the current state is maintained and the local clock is updated to the original local clock value + clock correction value. Example

[0016] Please refer to Figure 2 In this case, a simple time-triggered Ethernet network is formed using the TTTech end system to implement and verify the content of this application, and the Wireshark packet capture software is used to view the situation of its compression host sending synchronization frames.

[0017] In this embodiment, a group of configuration tables are called, and the content of the configuration table corresponds to its role one by one. That is, the compression host-SW1 corresponds to the only compression host configuration table in the group of configuration tables, while the synchronization host-ES1 corresponds to the ES1 configuration table, and the synchronization host-ES2 corresponds to the ES2 configuration table. Among them, the compression host-SW1 is the invention content of this application, so it should correctly load the compression host configuration table information and complete the corresponding functions. Before forming the network, the end system of TTTech and the compression host-SW1 are powered on first, and the configuration table is loaded. After the configuration is completed, the frame sending status of the compression host-SW1 is observed through the wireshark packet capture software, and it is found that the bit0 and bit1 of the synchronization member vector are 1, and the forwarding frame is an IN frame, which means that the network composed of the compression host and the end system of TTTech is currently in the synchronization stage. At the same time, by reading the status register, the current synchronization information is obtained. In addition, its offline situation is observed to check whether the entire network is stable.

[0018] The compression host will not actively initiate PCF frames, so you need to connect an end system to the corresponding node of the compression host first, so that you can use wireshark to observe whether the compression host forwards as designed. Now connect the idle port of the compression host to wireshark to observe whether it sends out PCF frames consistent with the TTTech end system. If they are consistent, observe what type of PCF frame the compression host forwards. The compression host needs to connect to the end system according to the configuration table to reach the stable synchronization stage.

[0019] The method of the present invention realizes the function of the compression host in the AS6802 protocol based on FPGA, and realizes the function of the compression host in Ethernet time synchronization through FPGA. It not only has the characteristics of low delay, high precision, high fault tolerance and improved system reliability, but also is easy to transplant and learn.

[0020] In the description of this specification, the description of the terms "one embodiment", "some embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0021] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for implementing the compression host function in the AS6802 protocol based on FPGA, wherein the state of the compression host includes an asynchronous stage and a synchronous stage; when the compression host is of standard integrity, its asynchronous stage includes an initial state, an asynchronous state, a CA frame relay continuous state, and a waiting IN frame state, and the synchronous stage includes a synchronous state and a stable synchronous state; when the compression host is of high integrity, its asynchronous stage includes an initial state, an intermediate waiting state, and an asynchronous state, and the synchronous stage includes a temporary synchronous state, a synchronous state, and a stable synchronous state; characterized in that, The method comprises the following steps: 1) The compression host receives the PCF frame sent by the synchronization host. The PCF frame is compressed in the collection stage, calculation stage and delay stage. If the compressed PCF frame is an IN frame, it enters step 2). Otherwise, it enters the state machine of the compression host and enters step 3); Among them, the frame types of PCF frames include CS frames, CA frames and IN frames; 2) Determine whether the number of members of the received IN frame is within the receiving window of the compression host. If so, it is the number of synchronous members for synchronous group detection; otherwise, it is the number of asynchronous members for asynchronous group detection; if the received IN frame is within the receiving window and the number of members is greater than or equal to the preset optimal number of members, calculate the clock correction value for correcting the local clock; after the group detection result is sorted, it carries the number of members, member vector and synchronization judgment flag into the state machine of the compression host; 3) The compression host enters the initial state; When the compression host is of high integrity, within the preset time length, if no IN frame is received, or the number of synchronization members of the received IN frame is less than the preset minimum value for entering the IN frame detection state, then proceed to step 5); if an IN frame is received and the number of synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, then proceed to step 9); if an IN frame is received and the number of synchronization members is less than the preset minimum value for entering the synchronization state and greater than or equal to the preset minimum value for entering the IN frame detection state, then proceed to step 4); When the compression host is of standard integrity, within the preset time length, if an IN frame is received and the number of its synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, then go to step 9); otherwise, go to step 5); 4) The high integrity compression host enters the IN frame detection state. In the integration cycle after the IN frame is integrated, if the number of synchronization members of the received IN frame is less than the preset minimum number of synchronization members and is not 0, then go to step 8); if its number of synchronization members is 0, then go to step 5); if its number of synchronization members is greater than or equal to the preset minimum number of synchronization members, then remain in the current state and continue to judge the IN frame in the next integration cycle; 5) The compression host enters an asynchronous state; When the compression host is of standard integrity, if the number of synchronization members of the received CS frame or CA frame is greater than or equal to the preset minimum number of synchronization members, proceed to step 6); if the number of synchronization members of the received IN frame is greater than or equal to the preset minimum value for entering the synchronization state, proceed to step 9); When the compression host is of high integrity, if an IN frame is received and the number of its synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, then proceed to step 9); if an IN frame is received and the number of its synchronization members is less than the preset minimum value for entering the synchronization state, and greater than or equal to the preset minimum value for entering the temporary synchronization state, then proceed to step 8); otherwise, maintain the current state and continue to judge; 6) The standard integrity compression host enters the CA frame relay continuous state, relays the CA frame for a preset fixed duration, and then enters step 7); 7) The standard integrity compression host enters the waiting IN frame state. Within the preset waiting IN frame time, if an IN frame is received and the number of its synchronization members is greater than or equal to the minimum value for entering the synchronization state, then it enters step 9), otherwise it returns to step 5); 8) The high integrity compression host enters the temporary synchronization state and synchronizes with at least one group of synchronization hosts; At the asynchronous evaluation point, if the number of asynchronous members is greater than or equal to the preset minimum number of asynchronous members, return to step 5), otherwise continue to judge in the current state; At the synchronization evaluation point, if the number of synchronization members is less than the preset minimum value of the temporary synchronization state, return to step 5); otherwise, determine whether the number of synchronization members is greater than or equal to the state jump threshold from the temporary synchronization state to the synchronization state, if so, proceed to step 9), otherwise, maintain the current state and continue to judge; At the clock correction point, the current state is maintained and the local clock is updated to the original local clock value + clock correction value; 9) The compression host enters the synchronization state. If the number of synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, and there is a sign that the synchronization state has entered a stable synchronization state, then proceed to step 10); if the number of synchronization members is less than the preset minimum value for entering the synchronization state, return to step 3); otherwise, continue to judge in the current state; At the asynchronous evaluation point, if the number of asynchronous members is greater than or equal to the preset minimum number of asynchronous members, return to step 3), otherwise, continue to judge in the current state, and the synchronous state loop count is reset to zero; At the synchronization evaluation point: When the compression host is of standard integrity, if the number of synchronization members is less than the preset minimum value for entering the synchronization state, then return to step 3), and the synchronization state cycle count is reset; if the number of synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, then determine whether there is a synchronization state to stable synchronization state flag, if so and the synchronization state cycle count is greater than or equal to the preset synchronization state cycle number, then enter step 10), the synchronization state cycle count is reset; otherwise, keep in the current state, and the synchronization state cycle count +1; When the compression host is of high integrity, if the number of synchronization members is less than the preset minimum value for entering the synchronization state, then return to step 8), and the synchronization state cycle count is reset; if the number of synchronization members is greater than or equal to the preset minimum value for entering the synchronization state, then determine whether there is a synchronization state to stable synchronization state flag, if so and the synchronization state cycle count is greater than or equal to the preset synchronization state cycle number, then enter step 10), the synchronization state cycle count is reset; otherwise, keep in the current state, and the synchronization state cycle count +1; At the clock correction point, the current state is maintained and the local clock is updated to the original local clock value + clock correction value; 10) The compression host enters a stable synchronization state, achieving the highest level of synchronization quality, configured to withstand temporary loss of all protocol control frames in the network; If the number of asynchronous members is greater than or equal to the preset minimum number of asynchronous members, return to step 3), otherwise keep judging in the current state, and reset the stable synchronization state cycle count; At the synchronization evaluation point, if the number of synchronization members is less than the preset minimum value for entering the stable synchronization state, and the stable synchronization state cycle count is greater than or equal to the preset number of stable synchronization cycles, then enter step 3), and the stable synchronization state cycle count is cleared; if the number of synchronization members is less than the preset minimum value for entering the stable synchronization state, and the stable synchronization state cycle count is less than the preset number of stable synchronization cycles, then maintain the current state, and the stable synchronization state cycle count is +1; if the number of synchronization members is greater than or equal to the preset minimum value for entering the stable synchronization state, then maintain the current state, and the stable synchronization state cycle count is cleared; At the clock correction point, the current state is maintained and the local clock is updated to the original local clock value + clock correction value.

2. The method for implementing the compression host function in the AS6802 protocol based on FPGA according to claim 1, characterized in that: The collection phase is: After the first observation window, if the number of collected and solidified PCF frames is 1, the collection of PCF frames will stop; if the number of collected and solidified PCF frames is greater than 1, the second observation window will be started to continue collecting solidified PCF frames; if at least one solidified PCF frame is received during the second observation window, the third observation window will be opened after the second observation window to continue collecting solidified PCF frames; and so on, until no solidified PCF frames are received in the next observation window, the collection is completed at the end of the observation window; The fixed PCF frame refers to a PCF frame that is not received in the first observation window and has the same frame type and integration period as the second PCF frame and becomes the fixed PCF frame.

3. The method for implementing the compression host function in the AS6802 protocol based on FPGA according to claim 2, characterized in that: In the collection phase, the compression host ends the collection process before the first fixed-line time point + the maximum observation window; Among them, the maximum observation window = (f+1)*observation window, f is a configurable parameter, which specifies the number of allowed faulty synchronization hosts. If the synchronization host has a single fault-tolerant feature, f=1; if it has a dual fault-tolerant feature, f=2.

4. The method for implementing the compression host function in the AS6802 protocol based on FPGA according to claim 3, characterized in that: The calculation phases are: The calculation stage mainly calculates the compression point by receiving the solidification time point in the PCF frame; that is, the compression correction value is calculated by the relative distance time between the solidification time point of the received PCF frame and the solidification time point of the first received PCF frame; If there is an input PCF frame, the compression correction value is 0; If there are two input PCF frames, the compression correction value = (solidification time point of the second PCF frame - solidification time point of the first PCF frame) / 2; If there are three input PCF frames, the compression correction value = the solidification time point of the second PCF frame - the solidification time point of the first PCF frame; If there are four input PCF frames, the compression correction value = ((the solidification time point of the second PCF frame - the solidification time point of the first PCF frame) + (the solidification time point of the third PCF frame - the solidification time point of the first PCF frame)) / 2; If there are five input PCF frames, the compression correction value = ((solidification time point of the second PCF frame - solidification time point of the first PCF frame) + (solidification time point of the fourth PCF frame - solidification time point of the first PCF frame)) / 2; 6) If there are more than five input PCF frames, the compression correction value = ((solidification time point of the Kth PCF frame - solidification time point of the first PCF frame) + (solidification time point of the second PCF frame - solidification time point of the first PCF frame)) / 2, K = f + 1; The compression function delay is: the maximum observation window + the static delay that can be calculated offline + the compression correction value; The compression point is: the first solidification time point + compression function delay; The first solidification time point refers to the solidification time point in the PCF frame where a given compression function is started.

5. The method for implementing the compression host function in the AS6802 protocol based on FPGA according to claim 4, characterized in that: The delay phase is: When the local clock reaches the fixed time point, the received PCF frame is compressed, and a maximum observation window time is delayed, and then the fixed time point of the PFC frame is updated.

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