Chip testing method

Abstract

According to the chip testing method provided by the invention, the single bare chip is tested after the wafer is cut, so that defects or unqualified products which may not be found in a wafer level test can be identified more accurately. The defects may be introduced in the wafer cutting process, such as cutting damage, pollution and the like. Therefore, the test method can effectively improve the yield of final products, and reduces resource waste and cost increase caused by the fact that unqualified bare chips flow into subsequent production links. The bare chips are placed in the chip carriers, then the chip carriers are placed on the tray, batch testing is carried out through the tray, the design enables the testing process to be more flexible, different chip carriers can be designed according to different bare chips, different chip carriers can be placed in the tray, and testing of different bare chips can be compatible. Moreover, the distance between the detection bonding pads of the chip carrier is relatively large, so that a tester can test the bare chip through the detection bonding pads.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip testing method. Background Art

[0002] The wafer-level testing of advanced process chips (such as HBM chips) is relatively mature, but there is no good solution for chip-level testing.

[0003] Take HBM chip as an example. HBM chip is a high-performance DRAM based on 3D stacking process, which is designed to meet the high demand for memory bandwidth and capacity in high-performance computing, artificial intelligence and graphics processing. HBM is a new type of memory chip technology that achieves high-speed and high-bandwidth memory access by vertically stacking multiple DRAM chips and using advanced packaging technologies such as through silicon vias (TSV) and micro bumps.

[0004] The manufacturing process of HBM chips mainly includes: thinning and bumping the memory core wafer, and then cutting it to obtain multiple bare dies; thinning and bumping the logic wafer; stacking multiple bare dies on the logic wafer to obtain a stacked wafer; cutting and wafer debonding or peeling the stacked wafer to obtain multiple stacked bare chips, which are then packaged in tape and reel and enter the subsequent process of batch shipment.

[0005] The existing technology for testing HBM chips mainly includes: testing of memory core wafers, testing of logic wafers, and testing of stacked wafers. However, in the manufacturing process of HBM chips, after obtaining the stacked wafers, wafer cutting and wafer debonding or peeling are also performed. This process may produce unqualified HBM units. These unqualified HBM units are assembled into 2.5D packages, resulting in a decrease in product yield. Summary of the invention

[0006] The purpose of the embodiments of the present application is to provide a chip testing method to solve the technical problem that the prior art only performs wafer-level testing and is unable to detect unqualified bare chips after wafer cutting, resulting in a decrease in product yield.

[0007] A chip testing method provided in an embodiment of the present application includes:

[0008] After the wafer is cut to obtain bare chips, each bare chip is placed in a corresponding chip carrier; wherein the spacing between bumps or test pads of the bare chip is smaller than the spacing between detection pads of the chip carrier;

[0009] placing at least one chip carrier on a placement area of ​​the tray;

[0010] The tray is moved to a tester, and the bare chips in each chip carrier on the tray are tested by the tester.

[0011] In the above technical solution, by testing a single bare chip after wafer cutting, defects or defective products that may not be discovered in wafer-level testing can be more accurately identified. These defects may be introduced during the wafer cutting process, such as cutting damage, contamination, etc. Therefore, this testing method can effectively improve the yield of the final product and reduce the waste of resources and increased costs caused by the flow of unqualified bare chips into subsequent production links. The bare chip is placed in a chip carrier, and then the chip carrier is placed on a tray, and batch testing is performed through the tray. This design makes the testing process more flexible. Different chip carriers can be designed according to different bare chips. Different chip carriers can be placed in the tray, which can be compatible with the testing of different bare chips. In addition, the spacing between the detection pads of the chip carrier is relatively large, so that the tester can test the bare chip through the detection pads.

[0012] In some optional implementations, after the bare chip in each chip carrier on the tray is tested by the test machine, the method further includes:

[0013] After testing, the chip carrier is removed from the tray, and then the bare chip is removed from the chip carrier. The qualified bare chip is directly packaged and then shipped in batches.

[0014] In the above technical solution, the chip carrier is placed on a tray, and the chip carrier can be easily taken out from the tray. Moreover, the bare chip is placed in the chip carrier, and the bare chip can also be taken out from the chip carrier. Both the tray and the chip carrier can be reused. The reusability of the tray and the chip carrier significantly reduces the material consumption and waste generation in the production process, conforms to the concept of sustainable development, helps to reduce production costs, and reduces the impact on the environment.

[0015] In some optional embodiments, after the wafer is cut to obtain bare chips, each bare chip is placed in a corresponding chip carrier, including:

[0016] After the wafer is cut to obtain bare chips, the untested bare chips are packaged with tape and reel to obtain a packaging structure;

[0017] At least one bare chip of the packaging structure is taken out, and each bare chip is placed in a corresponding chip carrier.

[0018] In the above technical solution, after the wafer is cut to obtain the bare chips, the bare chips are first packaged in a tape-and-reel manner to obtain a packaging structure, and then the bare chips are taken out of the packaging structure for testing. Taking out the bare chips from the packaging structure for testing can be flexibly arranged according to actual production needs and test plans. If some bare chips do not need to be tested temporarily, they can be kept in the packaging structure and wait for subsequent processing. This flexibility helps optimize production processes and resource utilization.

[0019] Among them, the packaging structure includes taping. Taping refers to packaging the chip on a tape carrier for automated handling and assembly during the production process. Taping is usually a long tape made of plastic or other materials with a series of chip packages on it, with each package arranged at a fixed spacing. Each package is connected to the tape through pins or pads for connection to other components (such as circuit boards). Taping not only improves production efficiency and reduces production costs, but also provides the function of protecting chip safety. Chip packaging in tape can prevent touching, collision and damage.

[0020] In some optional implementations, after the bare chip in each chip carrier on the tray is tested by the test machine, the method further includes:

[0021] After the test, the chip carrier is removed from the tray, and then the bare chip is removed from the chip carrier, and the qualified bare chip is returned to the packaging structure, or the qualified bare chip is placed on the corresponding tray or Frame film, and the subsequent batch shipment process is carried out.

[0022] In the above technical solution, by putting the qualified bare chips back into the packaging structure, the original packaging can be directly used for batch shipment, which not only simplifies the shipment process, but also avoids the additional cost and time consumption that may be introduced by repackaging.

[0023] In some optional embodiments, the bare chip in each chip carrier on the tray is tested by a test machine, including:

[0024] Perform at least one of the following tests on each bare die in a chip carrier:

[0025] Logic chip test, dynamic vector aging stress test, TSV test, high-speed performance test, PHY I / O test, 2.5D SIP test, Burn in test.

[0026] In the above technical solution, bare chips include HBM chips, 3D stacked chips or advanced process packaging chips, etc. The tests on HBM bare chips include: logic chip test, dynamic vector aging stress test, TSV test, high-speed performance test, PHYI / O test, 2.5D SIP test, and Burn in test.

[0027] Among them, logic chip test: As one of the core components of HBM KGSD, the performance of the logic chip directly affects the stability and reliability of the entire system. The test content includes functional test, timing test, power consumption test, etc. to ensure that the logic chip can work normally under various working conditions.

[0028] Dynamic vector aging stress test: Dynamic vector aging stress test is designed to simulate the aging of chips during long-term use to evaluate their lifespan and reliability. The specific test method includes: applying specific dynamic vectors to the chip, observing its performance changes under different stress conditions, and thus predicting its service life.

[0029] TSV test: TSV (Through Silicon Via) is a key technology for HBM to achieve vertical chip stacking, and its quality directly affects the speed and stability of data transmission. The test content includes the electrical performance test of TSV resistance, capacitance, inductance, etc., as well as the connection reliability test between TSV and micro bumps.

[0030] High-speed performance test: HBM is designed to provide extremely high data transmission speeds, so high-speed performance testing is an important indicator for evaluating its performance. Specific testing methods include: testing HBM's bandwidth, latency and other key performance indicators through dedicated high-speed testing equipment.

[0031] PHY I / O test: PHY I / O (physical layer input and output) is the interface for HBM to communicate with external devices. Its performance directly affects the quality and efficiency of data transmission. The test content includes the rate, timing, signal integrity and other tests of the I / O interface to ensure the accuracy and stability of data transmission.

[0032] 2.5D SIP test: 2.5D SIP (system-in-package) technology integrates multiple chips and components in one package to form a compact system-level solution. All chips and components in the package need to be fully tested, including functional testing, interconnect testing, thermal testing, etc., to ensure the performance and reliability of the entire system.

[0033] Burn-in test: Burn-in test is an accelerated aging test method designed to quickly expose potential manufacturing defects or early failure modes by simulating long-term operation of chips under extreme conditions.

[0034] NG chips that fail the above tests will enter the repair process, including screening and replacement, parameter adjustment, fault analysis, etc. Among them, screening and replacement: the bad chips found in the test are screened out from the production batch and replaced with qualified chips. Parameter adjustment: For some defects that can be optimized by software or firmware adjustment, the performance of the chip may be improved by adjusting the parameters. Fault analysis: Detailed analysis of the failed chip to find out the root cause of the failure so that improvements can be made in the subsequent production process.

[0035] In some optional embodiments, the chip carrier includes: a carrier body and a cover plate; the carrier body includes a base plate and a surrounding structure, and the base plate and the surrounding structure form a cavity with an opening;

[0036] Place each bare die in the corresponding chip carrier, including:

[0037] Place the bare chip into the cavity of the chip carrier through the opening, and then cover the opening with a cover plate to fix the bare chip.

[0038] In the above technical solution, the bare chip is directly exposed to the external environment and is easily affected by physical damage, contamination, and electrostatic discharge (ESD). By placing the bare chip in the cavity of the chip carrier and closing the opening with a cover plate, the direct impact of the external environment on the bare chip can be effectively isolated, the physical protection level of the chip can be improved, and the risk of damage can be reduced. In addition, the design of this chip carrier is also conducive to the subsequent step of removing the bare chip.

[0039] In some optional embodiments, a connector and a detection pad are provided on the base plate, the connector is provided on the inner side of the enclosing structure, and the detection pad is provided on the outer side of the enclosing structure; a probe head is provided on the connector, and is used for the bumps of the bare chip and the test pads to contact the corresponding probe heads when the bare chip is placed on the chip carrier; the connector is also connected to the detection pad, and the detection pad is used for the test machine to test the bare chip through the detection pad during testing.

[0040] In the above technical solution, the chip, such as the HBM chip, has a micro-bump pitch of 73um and a test pad pitch of about 165um. These extremely small pitches place extremely high demands on the accuracy during the test. Due to the extremely small pitch, the traditional test socket faces great challenges when trying to make accurate contact with the uBump or the test pad. Even a slight deviation or misalignment may lead to poor contact or failure. Therefore, in this embodiment, a connector is provided in the chip carrier, and the probe head of the connector contacts the micro-bump or the test pad of the HBM chip. The connector is also connected to the detection pad, and the detection pad is relatively large in size. The test machine can test the HBM chip by detecting the pad.

[0041] In some optional implementations, the connector includes: a MEMS pin or a Pogo pin.

[0042] Among them, MEMS pin: Due to the high precision of MEMS technology, MEMS pin can provide very small contact points to ensure accurate docking with bare chip bumps and test solder joints. This high-precision connection helps reduce test errors and improve the quality of signal transmission.

[0043] Pogo pin: Pogo pin is known for its unique spring structure, which allows the pin to automatically adjust its position when pressure is applied to ensure optimal contact with the contact point. This adaptive ability ensures a stable connection even with slight position deviations. The spring structure of the Pogo pin not only provides good contact performance, but also gives it excellent durability. The spring can withstand multiple plug-ins and compressions without being easily damaged, which is especially important for application scenarios that require frequent testing and replacement of bare chips.

[0044] In some optional embodiments, an alignment mark is also provided on the bottom plate;

[0045] Place the bare chip from the opening into the cavity of the chip carrier, including:

[0046] The bare chip is clamped by a robotic arm and hovered above the chip carrier. After positioning and aligning using alignment marks, the bare chip is placed vertically into the chip carrier.

[0047] In the above technical solution, the alignment mark provides a clear reference point for the robotic arm, which can quickly identify and locate the correct position. The robotic arm clamps, hovers, aligns and places the bare chip, thereby automating the entire process, improving production efficiency and reducing the uncertainty and errors caused by manual operation.

[0048] In some optional embodiments, the chip carrier further comprises: a locking device;

[0049] After the opening is covered with a cover plate to fix the bare chip, the method further includes:

[0050] The cover plate is fixedly connected to the carrier body by means of a locking device.

[0051] In the above technical solution, the locking device can ensure the tight connection between the cover plate and the carrier body, reducing the impact of the external environment on the chip carrier due to looseness or gaps, such as the intrusion of pollutants such as dust and moisture. In addition, during the test process, the chip carrier may be affected by various external forces. The locking device can effectively prevent the cover plate from accidentally falling off due to external forces such as vibration and impact, ensuring the stability and safety of the bare chip. At the same time, the design of the locking device is also easy to disassemble, which is convenient for the subsequent process of removing the bare chip.

[0052] In some optional embodiments, the locking device includes a back buckle or a bolt locking assembly.

[0053] In some optional embodiments, the bare chip includes an HBM chip, a 3D stacked chip, or an advanced process packaging chip, etc.

[0054] In some optional implementations, a plurality of placement areas are evenly distributed on the tray, and each placement area is used to place a chip carrier; the test machine performs simultaneous testing on the chip carriers on at least two placement areas.

[0055] In some optional implementations, the spacing between the bumps of the bare chip ranges from 10 to 200 um, the spacing between the test pads of the bare chip ranges from 40 to 250 um, and the spacing between the detection pads of the chip carrier ranges from 200 to 500 um.

[0056] In some optional implementations, the pressing stroke of the probe head is 2 to 100 um.

[0057] In some optional implementations, the diameter of the bare chip bump is 10-100 um; the bare chip test solder joint is rectangular, and its length and width are both 30-100 um; the detection pad is rectangular, and its length and width are both 100-200 um.

[0058] In some optional implementations, the surface of the detection pad is gold-plated; the detection pad is made of an alloy of one or more of Cu, Ni and Pd.

[0059] In some optional embodiments, an elastic material layer is disposed between the cover plate and the chip, and the elastic material layer is detachably fixed to the surface of the cover plate.

[0060] In some optional implementations, the thickness of the elastic material layer is 0.005-5 mm; the elastic material layer is made of organic resin, gel or flexible metal.

[0061] In some optional embodiments, the base plate includes a substrate; the probe head is grown on the substrate, and the probe head is connected to the detection pad through an internal circuit of the substrate; the substrate includes a silicon substrate, a ceramic substrate or a glass substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0063] Figure 1 A flowchart of a chip testing method provided in an embodiment of the present application;

[0064] Figure 2 A top view of a carrier body of a chip carrier provided in the first embodiment of the present application;

[0065] Figure 3 A top view of a chip carrier provided in the first embodiment of the present application;

[0066] Figure 4 A top view of a carrier body of a chip carrier provided in a second embodiment of the present application;

[0067] Figure 5 A top view of a chip carrier provided in the second embodiment of the present application.

[0068] Icon: 1-carrier body, 2-cover plate, 3-connector, 4-detection pad, 5-enclosing structure, 6-base plate. DETAILED DESCRIPTION

[0069] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0070] Please refer to Figure 1 , Figure 1 A chip testing method step flow chart provided in an embodiment of the present application specifically includes:

[0071] Step 100: After the wafer is cut to obtain bare chips, each bare chip is placed in a corresponding chip carrier; wherein the spacing between bumps or test pads of the bare chip is smaller than the spacing between detection pads of the chip carrier;

[0072] Step 200: placing at least one chip carrier on a placement area of ​​a tray;

[0073] Step 300: Move the tray to a testing machine, and use the testing machine to test the bare chip in each chip carrier on the tray.

[0074] In an embodiment of the present application, by testing a single bare chip after wafer cutting, defects or defective products that may not be discovered in wafer-level testing can be more accurately identified. These defects may be introduced during the wafer cutting process, such as cutting damage, contamination, etc. Therefore, this testing method can effectively improve the yield of the final product and reduce the waste of resources and increased costs caused by the flow of unqualified bare chips into subsequent production links. The bare chip is placed in a chip carrier, and then the chip carrier is placed on a tray, and batch testing is performed through the tray. This design makes the testing process more flexible. Different chip carriers can be designed according to different bare chips. Different chip carriers can be placed in the tray, which can be compatible with the testing of different bare chips. In addition, the spacing between the detection pads of the chip carrier is relatively large, so that the tester can test the bare chip through the detection pads.

[0075] In some optional implementations, after step 300, the method further includes:

[0076] Step 400: After the test, the chip carrier is removed from the tray, and then the bare chip is removed from the chip carrier. The qualified bare chip is directly packaged in tape and reel, or the qualified bare chip is placed on the corresponding tray or frame film for subsequent batch shipment process.

[0077] Among them, tape and reel packaging is a packaging method that arranges electronic components (such as chips, resistors, capacitors, etc.) at a certain interval on a continuous tape (Tape), and winds the tape on a reel (Reel). This packaging method has the advantages of high automation, convenient storage and transportation, and protection of components from damage. Tape and Reel is widely used in surface mount technology (SMT) and is an important material supply method on SMT production lines. In the SMT production process, the placement machine can directly pick up components from the Tape and Reel and mount them on the circuit board, greatly improving production efficiency and automation.

[0078] In the semiconductor industry, batch shipment refers to the process of packaging and labeling qualified products after a series of processes such as production, testing, and packaging according to order requirements and delivering them to customers by transportation. This process involves multiple links such as product packaging, logistics transportation, and delivery.

[0079] Among them, finished product testing: After the product is packaged, finished product testing is required to ensure that the quality and performance of the product meet customer requirements. This step usually includes functional testing, performance testing, reliability testing, etc.

[0080] Packaging: Products that pass the test need to be properly packaged to protect them from damage during transportation. The selection of packaging materials and the design of packaging methods need to take into account the characteristics of the product and transportation conditions.

[0081] Marking: The product model, specifications, quantity, production date, batch number and other information must be clearly marked on the packaging to facilitate customers to identify and track the source and flow of the product.

[0082] Logistics and transportation: Choose the appropriate logistics channels and transportation methods to deliver products to customers safely and on time. This step needs to take into account multiple factors such as transportation cost, transportation time, and transportation safety.

[0083] Delivery: After the product is delivered to the customer, a delivery inspection is required to ensure that the quantity, specifications, quality, etc. of the products meet the order requirements and complete the relevant delivery procedures.

[0084] In the embodiment of the present application, the chip carrier is placed on a tray, and the chip carrier can be easily taken out from the tray. Moreover, the bare chip is placed in the chip carrier, and the bare chip can also be taken out from the chip carrier. Both the tray and the chip carrier can be reused. The reusability of the tray and the chip carrier significantly reduces the material consumption and waste generation in the production process, conforms to the concept of sustainable development, helps to reduce production costs, and reduces the impact on the environment.

[0085] In some optional embodiments, the chip testing method can also be applied after tape packaging, that is: after cutting the wafer to obtain bare chips, the untested bare chips are tape packaged to obtain a packaging structure; at least one bare chip in the packaging structure is taken out, and each bare chip is placed in a corresponding chip carrier.

[0086] In the embodiment of the present application, after the wafer is cut to obtain the bare chips, the bare chips are first packaged by tape and reel to obtain a packaging structure, and then the bare chips are taken out of the packaging structure for testing. The bare chips are taken out from the packaging structure for testing, which can be flexibly arranged according to actual production needs and test plans. If some bare chips do not need to be tested temporarily, they can be kept in the packaging structure and wait for subsequent processing. This flexibility helps to optimize production processes and resource utilization.

[0087] Correspondingly, after step 300, this embodiment also includes: after testing, removing the chip carrier from the tray, then removing the bare chip from the chip carrier, putting the qualified bare chip back into the packaging structure, or placing the qualified bare chip on the corresponding tray or Frame film, and performing the subsequent batch shipping process.

[0088] In the embodiment of the present application, by putting the qualified bare chips back into the packaging structure, the original packaging can be directly used for batch shipment, which not only simplifies the shipment process, but also avoids the additional cost and time consumption that may be introduced by repackaging.

[0089] In some optional implementations, in step 300, the bare chip in each chip carrier on the tray is tested by using a testing machine, specifically including:

[0090] Perform at least one of the following tests on the bare die in each chip carrier: logic chip test, dynamic vector aging stress test, TSV test, high-speed performance test, PHY I / O test, 2.5D SIP test, Burn in test.

[0091] In the embodiment of the present application, the bare chip includes an HBM chip, a 3D stacked chip or an advanced process packaging chip, etc., and the tests on the HBM bare chip include: logic chip test, dynamic vector aging stress test, TSV test, high-speed performance test, PHYI / O test, 2.5D SIP test, and Burn in test.

[0092] Among them, logic chip test: As one of the core components of HBM KGSD, the performance of the logic chip directly affects the stability and reliability of the entire system. The test content includes functional test, timing test, power consumption test, etc. to ensure that the logic chip can work normally under various working conditions.

[0093] Dynamic vector aging stress test: Dynamic vector aging stress test is designed to simulate the aging of chips during long-term use to evaluate their lifespan and reliability. The specific test method includes: applying specific dynamic vectors to the chip, observing its performance changes under different stress conditions, and thus predicting its service life.

[0094] TSV test: TSV (Through Silicon Via) is a key technology for HBM to achieve vertical chip stacking, and its quality directly affects the speed and stability of data transmission. The test content includes the electrical performance test of TSV resistance, capacitance, inductance, etc., as well as the connection reliability test between TSV and micro bumps.

[0095] High-speed performance test: HBM is designed to provide extremely high data transmission speeds, so high-speed performance testing is an important indicator for evaluating its performance. Specific testing methods include: testing HBM's bandwidth, latency and other key performance indicators through dedicated high-speed testing equipment.

[0096] PHY I / O test: PHY I / O (physical layer input and output) is the interface for HBM to communicate with external devices. Its performance directly affects the quality and efficiency of data transmission. The test content includes the rate, timing, signal integrity and other tests of the I / O interface to ensure the accuracy and stability of data transmission.

[0097] 2.5D SIP test: 2.5D SIP (system-in-package) technology integrates multiple chips and components in one package to form a compact system-level solution. All chips and components in the package need to be fully tested, including functional testing, interconnect testing, thermal testing, etc., to ensure the performance and reliability of the entire system.

[0098] Burn-in test: Burn-in test is an accelerated aging test method designed to quickly expose potential manufacturing defects or early failure modes by simulating long-term operation of chips under extreme conditions.

[0099] After the above test process, repair is usually carried out, including screening and replacement, parameter adjustment, fault analysis, etc. Among them, screening and replacement: the bad chips found in the test are screened out from the production batch and replaced with qualified chips. Parameter adjustment: For some defects that can be optimized by software or firmware adjustment, the performance of the chip may be improved by adjusting the parameters. Fault analysis: Detailed analysis of the failed chip to find out the root cause of the failure so that improvements can be made in the subsequent production process.

[0100] Please refer to Figure 2 and Figure 3 , Figure 2 A top view of a carrier body of a chip carrier provided in the first embodiment of the present application, Figure 3 A top view of a chip carrier provided in the first embodiment of the present application.

[0101] In some optional embodiments, the chip carrier includes: a carrier body 1 and a cover plate 2; the carrier body 1 includes a base plate 6 and a surrounding structure 5, and the base plate 6 and the surrounding structure 5 form a cavity with an opening;

[0102] In step 100 of this embodiment, each bare chip is placed in a corresponding chip carrier, which specifically includes: placing the bare chip into the cavity of the chip carrier from the opening, and then covering the opening with a cover plate 2 to fix the bare chip.

[0103] In the embodiment of the present application, the bare chip is directly exposed to the external environment and is easily affected by physical damage, contamination, electrostatic discharge (ESD) and other problems. By placing the bare chip in the cavity of the chip carrier and closing the opening with the cover plate 2, the direct impact of the external environment on the bare chip can be effectively isolated, the physical protection level of the chip can be improved, and the risk of damage can be reduced. In addition, the design of this chip carrier is also conducive to the subsequent step of removing the bare chip.

[0104] In some optional embodiments, a connector 3 and a detection pad 4 are provided on the base plate 6, the connector 3 is provided on the inner side of the enclosing structure 5, and the detection pad 4 is provided on the outer side of the enclosing structure 5; a probe head is provided on the connector 3, which is used for the bumps of the bare chip and the test pads to contact the corresponding probe heads when the bare chip is placed on the chip carrier; the connector 3 is also connected to the detection pad 4, and the detection pad 4 is used for the test machine to test the bare chip through the detection pad 4 during testing.

[0105] In the embodiment of the present application, the chip, such as the HBM chip, has a micro-bump pitch of 73um and a test pad pitch of about 165um. These extremely small pitches place extremely high demands on the accuracy during the test. Due to the extremely small pitch, the traditional test socket faces great challenges when trying to make accurate contact with the uBump or the test pad. Even a slight deviation or misalignment may result in poor contact or failure. Therefore, in the present embodiment, a connector 3 is provided in the chip carrier, and the probe head of the connector 3 contacts the micro-bump or the test pad of the HBM chip. The connector 3 is also connected to the detection pad 4, and the detection pad 4 is relatively large in size. The test machine can test the HBM chip by detecting the pad 4.

[0106] In some optional implementations, the connector 3 includes: a MEMS pin or a Pogo pin.

[0107] Among them, MEMS pin: Due to the high precision of MEMS technology, MEMS pin can provide very small contact points to ensure accurate docking with bare chip bumps and test solder joints. This high-precision connection helps reduce test errors and improve the quality of signal transmission.

[0108] Pogo pin: Pogo pin is known for its unique spring structure, which allows the pin to automatically adjust its position when pressure is applied to ensure optimal contact with the contact point. This adaptive ability ensures a stable connection even with slight position deviations. The spring structure of the Pogo pin not only provides good contact performance, but also gives it excellent durability. The spring can withstand multiple plug-ins and compressions without being easily damaged, which is especially important for application scenarios that require frequent testing and replacement of bare chips.

[0109] In some optional embodiments, the bottom plate 6 is also provided with an alignment mark;

[0110] Correspondingly, the bare chip is placed into the cavity of the chip carrier from the opening, specifically including: using a mechanical arm to clamp the bare chip and hover it above the chip carrier, using an alignment mark to perform positioning and alignment, and then vertically placing the bare chip into the chip carrier.

[0111] In the embodiment of the present application, the alignment mark provides a clear reference point for the robotic arm, which can quickly identify and locate the correct position. The robotic arm clamps, hovers, aligns and places the bare chip, thereby automating the entire process, improving production efficiency and reducing the uncertainty and errors caused by manual operation.

[0112] In some optional embodiments, the chip carrier further includes: a locking device; after the opening is covered with the cover plate 2 to fix the bare chip, the method further includes: fixing the cover plate 2 to the carrier body 1 with the locking device.

[0113] In the embodiment of the present application, the locking device can ensure a tight connection between the cover plate 2 and the carrier body 1, reducing the impact of the external environment on the chip carrier due to looseness or gaps, such as the intrusion of pollutants such as dust and moisture. In addition, during the test process, the chip carrier may be affected by various external forces. The locking device can effectively prevent the cover plate 2 from accidentally falling off due to external forces such as vibration and impact, ensuring the stability and safety of the bare chip. At the same time, the design of the locking device is also easy to disassemble, which is convenient for the subsequent process of removing the bare chip.

[0114] In this embodiment, all the detection pads 4 are arranged close to one side of the bottom plate 6. It should be noted that the detection pads 4 may also be arranged close to other sides of the bottom plate 6, such as Figure 4 and Figure 5 As shown, Figure 4 A top view of a carrier body 1 of a chip carrier provided in a second embodiment of the present application, Figure 5 This is a top view of a chip carrier provided in a second embodiment of the present application. In the second embodiment, the detection pads 4 are arranged near two opposite sides of the base plate 6 .

[0115] In some optional implementations, a plurality of placement areas are evenly distributed on the tray, and each placement area is used to place a chip carrier; the test machine performs simultaneous testing on the chip carriers on at least two placement areas.

[0116] In some optional implementations, the spacing between the bumps of the bare chip ranges from 10 to 200 um, the spacing between the test pads of the bare chip ranges from 40 to 250 um, and the spacing between the detection pads of the chip carrier ranges from 200 to 500 um.

[0117] In some optional implementations, the pressing stroke of the probe head is 2 to 100 um.

[0118] In some optional implementations, the diameter of the bare chip bump is 10-100 um; the bare chip test solder joint is rectangular, and its length and width are both 30-100 um; the detection pad is rectangular, and its length and width are both 100-200 um.

[0119] In some optional implementations, the surface of the detection pad is gold-plated; the detection pad is made of an alloy of one or more of Cu, Ni and Pd.

[0120] In some optional embodiments, an elastic material layer is disposed between the cover plate and the chip, and the elastic material layer is detachably fixed to the surface of the cover plate.

[0121] In some optional implementations, the thickness of the elastic material layer is 0.005-5 mm; the elastic material layer is made of organic resin, gel or flexible metal.

[0122] In some optional embodiments, the base plate includes a substrate; the probe head is grown on the substrate, and the probe head is connected to the detection pad through an internal circuit of the substrate; the substrate includes a silicon substrate, a ceramic substrate or a glass substrate.

[0123] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0124] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0125] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0126] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0127] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip testing method, characterized in that: include: After the wafer is cut to obtain bare chips, each bare chip is placed in a corresponding chip carrier; wherein the spacing between bumps or test pads of the bare chip is smaller than the spacing between detection pads of the chip carrier; placing at least one of the chip carriers on a placement area of ​​the tray; The tray is moved to a testing machine, and the bare chip in each chip carrier on the tray is tested by the testing machine.

2. The method according to claim 1, characterized in that The spacing between the bumps of the bare chip ranges from 10 to 200 um, the spacing between the test solder joints of the bare chip ranges from 40 to 250 um, and the spacing between the detection pads of the chip carrier ranges from 200 to 500 um.

3. The method according to claim 1, characterized in that The chip carrier comprises: a carrier body and a cover plate; the carrier body comprises a bottom plate and a surrounding structure, and the bottom plate and the surrounding structure form a cavity with an opening; Placing each of the bare chips in a corresponding chip carrier includes: The bare chip is placed into the cavity of the chip carrier through the opening, and the opening is covered with the cover plate to fix the bare chip.

4. The method according to claim 3, characterized in that A connector and a detection pad are arranged on the bottom plate, the connector is arranged on the inner side of the surrounding structure, and the detection pad is arranged on the outer side of the surrounding structure; a probe head is arranged on the connector, which is used for the bumps of the bare chip and the test pads to contact the corresponding probe heads when the bare chip is placed on the chip carrier; the connector is also connected to the detection pad, and the detection pad is used for the test machine to test the bare chip through the detection pad during testing.

5. The method according to claim 4, characterized in that The pressing stroke of the probe head is 2 to 100 um.

6. The method according to claim 5, characterized in that The diameter of the bare chip bump is 10-100um; the bare chip test solder joint is rectangular, and its length and width are both 30-100um; the detection pad is rectangular, and its length and width are both 100-200um.

7. The method according to claim 5, characterized in that The surface of the detection pad is gold-plated; the detection pad is made of one or more alloys of Cu, Ni and Pd.

8. The method according to claim 5, characterized in that An elastic material layer is arranged between the cover plate and the chip, and the elastic material layer is detachably fixed on the surface of the cover plate.

9. The method according to claim 8, characterized in that The thickness of the elastic material layer is 0.005-5 mm; the elastic material layer is made of organic resin, gel or flexible metal.

10. The method according to claim 4, characterized in that The bottom plate includes a substrate; the probe head is grown on the substrate, and the probe head is connected to the detection pad through an internal circuit of the substrate; the substrate includes a silicon substrate, a ceramic substrate or a glass substrate.

11. The method according to claim 4, characterized in that The connector includes: a MEMS pin or a Pogo pin.

12. The method according to claim 4, characterized in that The bottom plate is also provided with an alignment mark; Placing the bare chip into the cavity of the chip carrier from the opening includes: The bare chip is clamped by a mechanical arm and suspended above the chip carrier. After positioning and aligning by using the alignment mark, the bare chip is vertically placed into the chip carrier.

13. The method according to claim 1, characterized in that The bare chip includes an HBM chip, a 3D stacked chip or an advanced process packaging chip.

14. The method according to claim 1, wherein: A plurality of placement areas are evenly distributed on the tray, and each placement area is used to place one chip carrier; the test machine performs simultaneous testing on the chip carriers on at least two placement areas.

15. The method according to claim 1, wherein: After the bare chip in each chip carrier on the tray is tested by the testing machine, the method further includes: After the test, the chip carrier is taken out from the tray, and then the bare chip is taken out from the chip carrier, and the qualified bare chip is directly packaged by tape and reel, or the qualified bare chip is placed on the corresponding tray or frame film.

16. The method according to claim 1, wherein: After the wafer is cut to obtain bare chips, each bare chip is placed in a corresponding chip carrier, including: After the bare chips are obtained by cutting the wafer, the untested bare chips are packaged with tape and reel to obtain a packaging structure; At least one of the bare chips in the packaging structure is taken out, and each of the bare chips is placed in a corresponding chip carrier.

17. The method according to claim 16, characterized in that After the bare chip in each chip carrier on the tray is tested by the testing machine, the method further includes: After the test, the chip carrier is taken out from the tray, the bare chip is taken out from the chip carrier, and the qualified bare chip is put back into the packaging structure.

18. The method of claim 1, wherein: The method of testing the bare chip in each chip carrier on the tray by using a testing machine includes: The bare die in each of the chip carriers is subjected to at least one of the following tests: Logic chip test, dynamic vector aging stress test, TSV test, high-speed performance test, PHYI / O test, 2.5DSIP test, Burn in test.

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