Programmable AES encryption module hardware accelerator, instruction set and operation method

Abstract

The invention provides a programmable AES (Advanced Encryption Standard) encryption module hardware accelerator, an instruction set and an operation method.The accelerator is connected with a bus, carries out data interaction with the bus and carries out AES encryption and decryption on data, the accelerator comprises a master device and a slave device which are connected with the bus, the main equipment is used for receiving and transmitting a data carrying instruction; the slave device communicates with other modules on the bus and receives the data carrying instruction and data of the master device; the slave device is connected with the decoder through an instruction stack and transmits an instruction to the decoder; the decoder decodes the instruction transmitted from the slave device and sends the decoded instruction to the calculation module or the carrying module connected with the decoder for corresponding operation or data transmission; the instruction set is used for controlling the accelerator; the operation method is realized by adopting the accelerator.

Description

Technical Field

[0001] The present invention relates to a hardware accelerator, an instruction set and an operating method, in particular to a programmable AES encryption module hardware accelerator, an instruction set and an operating method. Background Art

[0002] This section merely provides background information related to the present disclosure and is not necessarily prior art.

[0003] The AES (Advanced Encryption Standard) algorithm in the prior art uses too large an area for hardware implementation, and using a pure software method will cause the CPU to be occupied for a long time. Therefore, most of the existing AES use a combination of software and hardware technology to solve the above problem. The AES hardware accelerator and the CPU generally cooperate using an interrupt method, that is, the AES hardware accelerator notifies the CPU to perform the next operation after completing the calculation.

[0004] However, in the prior art, the above solutions require frequent interruptions to the CPU, resulting in low CPU working efficiency.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] Purpose of the invention: The technical problem to be solved by the present invention is to provide a programmable AES encryption module hardware accelerator, instruction set and operation method in view of the deficiencies in the prior art.

[0007] In order to solve the above technical problems, the present invention discloses a programmable AES encryption module hardware accelerator, an instruction set and an operation method;

[0008] The accelerator is connected to the bus, performs data exchange with the bus, and performs AES encryption and decryption on the data. The accelerator includes:

[0009] A master device and a slave device connected to the bus, wherein the master device is used to send and receive data transfer instructions; the slave device communicates with other modules on the bus and receives the data transfer instructions and data from the master device.

[0010] Furthermore, the accelerator further includes: an instruction stack and a decoder,

[0011] The slave device is connected to the decoder via an instruction stack and transmits its instructions to the decoder.

[0012] Furthermore, the accelerator further includes: a computing module and a transport module.

[0013] The decoder decodes the instruction transmitted from the slave device and sends the decoded instruction to the computing module or the transport module connected thereto;

[0014] The computing module is used to select different computing submodules to perform corresponding operations according to the instructions;

[0015] The transport module is used to transfer data in the calculation module and the register according to the data transport instruction issued by the main device.

[0016] Furthermore, the accelerator further includes: a register,

[0017] The register is used to store data in the accelerator.

[0018] Furthermore, the register includes:

[0019] Special registers and general registers, among which,

[0020] The dedicated register is used to store specific encryption and decryption data;

[0021] The general register is used to store conventional data, including intermediate calculation results and auxiliary data;

[0022] The dedicated registers include a domain operation result register GF, a verification information result register TAG, an initialization vector register IV, a key register H, an encryption key register KEY, a plaintext data register PTEXT, and a ciphertext data register CTEXT.

[0023] Furthermore, the register further includes:

[0024] A status register connected to the slave device is used to store the current status of the accelerator.

[0025] Furthermore, the computing submodule includes:

[0026] The inverse operation submodule INV is used to perform the inverse transformation step in the AES encryption and decryption process; the inverse operation submodule INV has four modes of inversion, namely byte-level inversion, word-level inversion, doubleword-level inversion and full inversion;

[0027] AES core submodule AES_CORE is used to perform the core operation steps of AES encryption and decryption, including byte substitution, row shift, column confusion and round key addition;

[0028] The Galois field operator G2F is used for multiplication operations on finite fields, and the calculation results are placed in the field operation result register GF;

[0029] XOR operation submodule XOR, used to perform XOR operation;

[0030] The addition operation submodule ADD is used to perform addition operation;

[0031] The dedicated DMA submodule DMA is only used to move data in SRAM to dedicated registers and general registers;

[0032] The transfer submodule MOV is used to transfer data between special registers and general registers.

[0033] Furthermore, the bus, the master device and the slave device are an AHB bus, an AHB master device and an AHB slave device.

[0034] The present invention also proposes a programmable AES hardware accelerator instruction set, which is used to control the computing module in the aforementioned accelerator to perform related calculations, and the instruction set includes:

[0035] XOR instruction, performs exclusive OR operation, the input and output are special registers or general registers, the input is 2 registers, and the output is 1 register;

[0036] AES_CORE instruction, performs AES encryption or decryption operation. Before executing this instruction, confirm that the initialization vector register IV, encryption key register KEY and plaintext data register PTEXT are configured, and the output value is stored in the ciphertext data register CTEXT; specify encryption or decryption mode before running;

[0037] G2F instruction, performs Galois encryption operation. Before executing this instruction, confirm that the domain operation result register GF and the encryption key register KEY have been configured. The output value is stored in the domain operation result register GF.

[0038] The INV instruction performs reverse operation and has four modes: byte-level inversion, word-level inversion, double word-level inversion, and full inversion.

[0039] ADD instruction performs addition operation, using a 32-bit adder to complete 128-bit addition operation. The input and output are special registers or general registers. The input also includes a selection bit constant value. The input is 2 registers and the output is 1 register.

[0040] DMA instruction, to carry out external data transfer, to complete the bidirectional data transfer operation from SRAM to the general register;

[0041] The MOV instruction moves data between registers. The data is moved to a register. The input is a constant, a general register, or a special register. The output is a general register or a special register.

[0042] The present invention also proposes a programmable AES hardware accelerator operation method, which is implemented using the above accelerator, and the method includes:

[0043] Step 1: Determine whether the current round of AES encryption or decryption operation has been completed. If not, execute step 2; otherwise, terminate the current round of operation.

[0044] Step 2, write the received new instruction into the instruction stack;

[0045] Step 3, pop the last instruction in the instruction stack;

[0046] Step 4, decode the popped instruction and assign it to the computing module or the transport module for processing;

[0047] Step 5, wait for the processing described in step 4 to be completed, check whether the instruction stack is empty, if it is empty, end the operation, otherwise return to execute step 1.

[0048] Beneficial effects:

[0049] 1. The present invention improves the AES encryption speed and significantly speeds up data processing compared to pure software solutions.

[0050] 2. The present invention reduces hardware costs and achieves a balance between speed and cost through the combination of hardware acceleration and software control.

[0051] 3. The present invention reduces the burden on the CPU and uses DMA for efficient instruction transfer.

[0052] 4. The present invention improves system flexibility and supports two instruction input modes: CPU and DMA.

[0053] 5. The present invention optimizes energy utilization and reduces system power consumption through precise configuration and efficient data interaction. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more clear.

[0055] Figure 1 This is a schematic diagram of the overall working principle of the programmable AES module.

[0056] Figure 2 It is a schematic diagram of the overall architecture of the AES hardware accelerator proposed in the present invention.

[0057] Figure 3 It is a schematic diagram of the overall operation flow of the AES hardware accelerator proposed in the present invention.

[0058] Figure 4 It is a flow chart of CBC encryption using the AES hardware accelerator proposed in the present invention.

[0059] Figure 5 It is a flow chart of applying the AES hardware accelerator proposed in the present invention to perform GCM encryption. DETAILED DESCRIPTION

[0060] The design idea of ​​the present invention is as follows: an AES hardware accelerator pre-fills AES instructions through the CPU, and triggers an interrupt when the instruction is about to be completed to allow the CPU to continue filling in the instruction. Therefore, as long as the instruction length is reasonable, the entire AES operation will not interrupt the CPU very much, which greatly ensures the CPU work efficiency.

[0061] The present invention realizes AES encryption of large-scale data by working in collaboration with the CPU. The accelerator combines the high speed of hardware acceleration with the low cost of software encryption, supports two instruction input modes, CPU and DMA, and improves system efficiency and flexibility. The AES module interacts with other system components through the AHB bus, reduces the CPU burden through automatic interrupts and DMA, optimizes the encryption process, and is suitable for efficient and secure data processing scenarios.

[0062] DMA is used for instruction transfer to reduce the burden on the CPU, allowing it to focus on other control tasks, thereby optimizing system performance and energy efficiency. Supports two instruction input methods, CPU and DMA, providing flexibility and adaptability to meet the needs of different application scenarios.

[0063] The present invention completes the AES encryption process of large-scale data by linking with the CPU. It has the advantages of relatively fast encryption speed of pure hardware AES hardware accelerator and low hardware cost of software encryption. While taking into account speed and area, it frees up the CPU to complete some other control tasks, allowing the overall system to be completed more efficiently.

[0064] The specific technical solutions of the present invention are as follows:

[0065] The position and working principle of the programmable AES module in the overall system are as follows Figure 1 In the whole system, the AES module exchanges data with DMA, CPU, FLASH, SRAM and other modules through the AHB (Advanced High-performance Bus), forming a complete communication architecture.

[0066] When the AES module starts working, the CPU first configures the AES registers and starts the AES workflow.

[0067] After configuration is complete, the system writes the processing instructions into the AES instruction stack. This operation can be done by the CPU or DMA, and the instructions are usually stored in the system's SRAM or FLASH.

[0068] If the CPU is used to write instructions, when there is only one instruction left in the instruction stack, the AES module sends an interrupt signal to the CPU. After receiving the interrupt signal, the CPU quickly writes the new instruction into the instruction stack to ensure that the stack remains fully loaded. This interrupt mechanism ensures the timely transmission and processing of instructions, and avoids affecting the operating efficiency of the AES module due to the empty instruction stack.

[0069] Another way is to use general DMA as the medium for instruction transmission. First, pre-configure the general DMA, and then start the general DMA. When the AES instruction stack is not full, AES sends a request signal (req request) to the general DMA. After receiving the request signal, the general DMA moves the instructions from FLASH or SRAM and writes them into the AES instruction stack. When AES is processing existing instructions, the general DMA continues to load new instructions into the AES instruction stack. In this process, the AES module processes the loaded instructions and the received new instructions in parallel until AES completes all the work in the stack and DMA completes all the instruction transfer work. All operations in this stage are truly completed.

[0070] This programmable AES encryption module has several significant advantages. First, the use of DMA for instruction transmission greatly reduces the workload of the CPU and improves the overall computing efficiency of the system. DMA can quickly and efficiently carry instructions, avoiding instruction loading from becoming a system bottleneck. Secondly, the automated interrupt mechanism ensures that when the CPU is used to write instructions, the instructions can be updated in time, ensuring that the AES instruction stack is always fully loaded, thereby improving the response speed of the system. In addition, the design supports two instruction input methods, CPU and DMA, providing great flexibility, and can be flexibly switched in different application scenarios, with stronger adaptability. By configuring registers, the working status of the AES module can be effectively managed, resources can be used on demand, energy utilization can be improved, and system power consumption can be reduced. Finally, the AES module and other system components (such as CPU, DMA, FLASH, SRAM) exchange data through the AHB bus to form an efficient collaborative working mechanism to ensure the high performance of the system in encryption or decryption tasks. Overall, this design not only improves the working efficiency of the AES encryption module, but also enhances the flexibility and adaptability of the system, and is suitable for various scenarios that require efficient and secure data processing.

[0071] Figure 2 The internal architecture of an Advanced Encryption Standard (AES) encryption and decryption hardware design proposed by the present invention is described. The illustrated architecture includes several main parts, each of which has its own unique functions and roles to ensure the efficient operation of the entire AES system.

[0072] The first is AHB SLV (AHB slave), which is a slave device (Slave) used to communicate with other modules on the Advanced High-Performance Bus (AHB). AHB SLV receives instructions and data from the AHB master device (AHB MST) and transmits instructions to the decoder through the instruction stack. In addition, AHB SLV can also directly transmit data to the calculation module or other data path that needs to be processed.

[0073] The status register is another key component that stores the current state of the AES encryptor. The status register is able to record the progress of the current operation and whether the system is operating normally. This is essential for fault recovery and system stability.

[0074] The decoder is the next very important component, which is responsible for decoding the instructions received from the AHB SLV and distributing these instructions to the corresponding modules. The existence of the decoder enables the AES system to flexibly handle various operation requests from the master device, such as encryption, decryption, data transfer, etc.

[0075] The computing module consists of multiple submodules, each of which implements a specific computing function:

[0076] INV: Inverse operation module, used to perform the inverse transformation step in the AES algorithm. The inverse operation module INV is used to invert data input and output. There are four modes of data inversion, namely byte-level inversion, word-level inversion, doubleword-level inversion and full inversion.

[0077] AES_CORE: AES core module, which performs the core operation steps of AES encryption and decryption, including byte substitution, row shift, column confusion and round key addition. When performing encryption and decryption, it is necessary to configure IV, KEY, PTEXT and other data in advance.

[0078] G2F: Galois field operation module, used for multiplication operations on finite fields, which is part of the AES algorithm. The calculation result will be placed in the dedicated register GF.

[0079] XOR: XOR operation module, used to perform XOR operation, which is an indispensable step in the AES algorithm.

[0080] ADD: Addition operation module. Although it is mainly used for arithmetic operations in the AES algorithm, it may also be expanded for other purposes.

[0081] DMA: The dedicated DMA module is only used to move data in SRAM, mainly used to move SRAM data to dedicated and general registers.

[0082] MOV: Move data between special and general registers.

[0083] The role of the handling module is to transfer data between different computing modules and registers. It ensures that data can flow smoothly and efficiently between different computing steps. This is a key part to ensure the efficient operation of the system.

[0084] Dedicated registers and general registers together form the storage architecture of the AES system. Dedicated registers store specific encryption and decryption data, including initialization vectors (IV), encryption keys (KEY), plaintext data (PTEXT), and ciphertext data (CTEXT). General registers are used to store regular data, such as REG_A (128bit), REG_B (128bit), and REG_C (128bit). These registers are used to store temporary calculation results or other auxiliary data.

[0085] The master device is used to carry the data transmission and reception of the instructions. By building a master device inside the AES system, the transmission and reception of data can be actively controlled, making the AES system more flexible in operation. In addition, the master device focuses on data transmission, and the slave device focuses on the transmission and reception of AES instructions. The separation of instructions and data makes transmission simpler and more efficient. The benefits of this design are mainly reflected in the following aspects:

[0086] 1. Modular design: Each computing module and dedicated module is independent of each other and is responsible for different tasks, making the design easy to test and maintain. If a module fails, only the module needs to be debugged and repaired without affecting the entire system.

[0087] 2. Efficient data handling: The use of the handling module and DMA module greatly improves the data transmission speed and reduces the processing time. This is especially important for application scenarios that require large amounts of data encryption and decryption.

[0088] 3. Flexible instruction processing: Through the decoder, tasks can be flexibly distributed according to different instructions, so that the system can efficiently handle different types of operation requests. This flexibility enables the system to adapt to changing application requirements.

[0089] 4. Parallel processing capability: Multiple computing modules can perform different steps of operations at the same time, which improves the overall processing speed. Parallel processing capability is particularly important when large amounts of data need to be processed quickly.

[0090] In addition, AES_CORE and G2F operations can also be completed using basic operations such as XOR and addition. However, if this method is used, the number of instructions will increase sharply and the encryption time will be significantly increased. Therefore, fully hardwareizing AES_CORE and G2F operations is a compromise between area and speed.

[0091] like Figure 3 As shown in the figure, an operation method is designed for the programmable AES hardware accelerator designed above. The method starts with the process and first checks whether the current AES operation has been completed. If it has not been completed, the system will write a new instruction into the instruction stack and pop the next instruction in the instruction stack. Subsequently, the popped instruction is decoded and assigned to the corresponding hardware resources for processing. After waiting for the current operation to complete, check again whether the instruction stack is empty. If the instruction stack is empty, the operation process ends; if the instruction stack is not empty, continue to loop the above steps until all instructions are executed. This process ensures that the AES encryption module can continuously and efficiently load, decode and execute instructions, while ensuring the order and integrity of instruction execution.

[0092] The present invention also proposes a set of instruction sets, which are applied to the programmable AES hardware accelerator designed above, as shown in Table 1:

[0093] Table 1 Programmable AES hardware accelerator instruction set

[0094]

[0095] Example:

[0096] Since AES now has multiple derivative forms, such as ECB, CBC, CTR, CCM, ECM and GMAC modes, each mode has its own fixed operations, so for a specific mode, separate instructions need to be written.

[0097] like Figure 4 As shown, an example of using the above AES hardware accelerator for CBC encryption is as follows:

[0098] 1. Configure external general DMA to move data to registers such as PTEXT, IV and KEY;

[0099] 2. Use the XOR instruction to XOR PTEXT and IV and store the value in PTEXT; 3. Use the AES_CORE instruction to get the final data and put it in CTEXT;

[0100] 4. Use DMA instruction CTEXT to move data to SRAM for storage;

[0101] 5. Use the MOV instruction to move the CTEXT data to IV;

[0102] 6. Repeat steps 2-5 until all are completed;

[0103] like Figure 5 As shown, an example of using the above AES hardware accelerator for GCM encryption is as follows:

[0104] 1. Configure external general DMA to move data to registers such as PTEXT, IV and KEY;

[0105] 2. Use AES_CORE to calculate the final data and put it into CTEXT;

[0106] 3. Use the MOV instruction to move the CTEXT data to the H special register;

[0107] 4. Use the MOV instruction to move the value of the data register REG_A to the GF special register; 5. Use the G2F instruction to perform the Galois operation and save the result in the GF special register;

[0108] 6. Use the ADD instruction to add the data REG_A and 1 data and put the final result in REG_A; 7. Repeat steps 4-6 to complete the Header Phase operation;

[0109] 8. Use the MOV instruction to move 2 into REG_A;

[0110] 9. Use the ADD instruction to add IV and REG_A and put the result into IV;

[0111] 10. Use the AES_CORE instruction to perform AES operations;

[0112] 11. Use DMA instruction to move the plain text to PTEXT;

[0113] 12. Use the XOR command to perform XOR operation on the data CTEXT and PTEXT and store the result in CTEXT; 13. Use the DMA instruction to move the plaintext CTEXT to SRAM;

[0114] 14. Use the XOR instruction to XOR GF and CTEXT and put the result into the GF register;

[0115] 15. Use the G2F instruction to start the calculation;

[0116] 16. Use the ADD instruction to add IV and 1 and put the result into IV;

[0117] 17. Repeat instructions 10-16 until the Payload Phase related operations are completed;

[0118] 18. Use the XOR instruction to XOR GF and CTEXT and put the result into the GF register;

[0119] 19. Use the G2F instruction to start the calculation;

[0120] 20. Use DMA instruction to move the original IV to the IV special register;

[0121] 21. Use AES_CORE instruction to perform AES operation;

[0122] 22. Use the XOR instruction to XOR GF and CTEXT and put the result into the TAG register;

[0123] 23. Use DMA instructions to move TAG directly to SRAM to complete the Final Phase operation;

[0124] In a specific implementation, the present application provides a computer storage medium and a corresponding data processing unit, wherein the computer storage medium can store a computer program, and when the computer program is executed by the data processing unit, the invention content of a programmable AES encryption module hardware accelerator, instruction set and operation method provided by the present invention and some or all steps in each embodiment can be executed. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0125] Those skilled in the art can clearly understand that the technical solutions in the embodiments of the present invention can be implemented by means of computer programs and their corresponding general hardware platforms. Based on such an understanding, the technical solutions in the embodiments of the present invention can be essentially or partly contributed to the prior art in the form of computer programs, i.e., software products, which can be stored in a storage medium and include several instructions for enabling a device including a data processing unit (which can be a personal computer, a server, a single-chip microcomputer, an MCU or a network device, etc.) to execute the methods described in various embodiments of the present invention or certain parts of the embodiments.

[0126] The present invention provides a programmable AES encryption module hardware accelerator, instruction set and operation method. There are many methods and ways to implement the technical solution. The above is only a preferred implementation of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention. All components not specified in this embodiment can be implemented by existing technologies.

Claims

1. A programmable AES encryption module hardware accelerator, characterized in that: The accelerator is connected to the bus, performs data exchange with the bus, and performs AES encryption and decryption on the data. The accelerator includes: A master device and a slave device connected to the bus, wherein the master device is used to send and receive data transfer instructions; the slave device communicates with other modules on the bus and receives the data transfer instructions and data from the master device.

2. A programmable AES encryption module hardware accelerator according to claim 1, characterized in that: The accelerator also includes: an instruction stack and a decoder, The slave device is connected to the decoder via an instruction stack and transmits its instructions to the decoder.

3. A programmable AES encryption module hardware accelerator according to claim 2, characterized in that: The accelerator further includes: a computing module and a transport module. The decoder decodes the instruction transmitted from the slave device and sends the decoded instruction to the computing module or the transport module connected thereto; The computing module is used to select different computing submodules to perform corresponding operations according to the instructions; The transport module is used to transfer data in the calculation module and the register according to the data transport instruction issued by the main device.

4. A programmable AES encryption module hardware accelerator according to claim 3, characterized in that: The accelerator further includes: a register, The register is used to store data in the accelerator.

5. A programmable AES encryption module hardware accelerator according to claim 4, characterized in that: The register comprises: Special registers and general registers, among which, The dedicated register is used to store specific encryption and decryption data; The general register is used to store conventional data, including intermediate calculation results and auxiliary data; The dedicated registers include a domain operation result register GF, a verification information result register TAG, an initialization vector register IV, a key register H, an encryption key register KEY, a plaintext data register PTEXT, and a ciphertext data register CTEXT.

6. A programmable AES encryption module hardware accelerator according to claim 5, characterized in that: The register further includes: A status register connected to the slave device is used to store the current status of the accelerator.

7. A programmable AES encryption module hardware accelerator according to claim 6, characterized in that: The computing submodule comprises: The inverse operation submodule INV is used to perform the inverse transformation step in the AES encryption and decryption process; the inverse operation submodule INV has four modes of inversion, namely byte-level inversion, word-level inversion, doubleword-level inversion and full inversion; AES core submodule AES_CORE is used to perform the core operation steps of AES encryption and decryption, including byte substitution, row shift, column confusion and round key addition; The Galois field operator G2F is used for multiplication operations on finite fields, and the calculation results are placed in the field operation result register GF; XOR operation submodule XOR, used to perform XOR operation; The addition operation submodule ADD is used to perform addition operation; The dedicated DMA submodule DMA is only used to move data in SRAM to dedicated registers and general registers; The transfer submodule MOV is used to transfer data between special registers and general registers.

8. A programmable AES encryption module hardware accelerator according to claim 7, characterized in that: The bus, master device and slave device are an AHB bus, an AHB master device and an AHB slave device.

9. A programmable AES encryption module hardware accelerator instruction set, characterized in that: Used to control the computing module in the accelerator described in any one of claims 1 to 8 to perform relevant calculations, the instruction set comprising: XOR instruction, performs exclusive OR operation, the input and output are special registers or general registers, the input is 2 registers, and the output is 1 register; AES_CORE instruction, performs AES encryption or decryption operation. Before executing this instruction, confirm that the initialization vector register IV, encryption key register KEY and plaintext data register PTEXT are configured, and the output value is stored in the ciphertext data register CTEXT; specify encryption or decryption mode before running; G2F instruction, performs Galois encryption operation. Before executing this instruction, confirm that the domain operation result register GF and the encryption key register KEY have been configured. The output value is stored in the domain operation result register GF. The INV instruction performs reverse operation and has four modes: byte-level inversion, word-level inversion, double word-level inversion, and full inversion. ADD instruction performs addition operation, using a 32-bit adder to complete 128-bit addition operation. The input and output are special registers or general registers. The input also includes a selection bit constant value. The input is 2 registers and the output is 1 register. DMA instruction, to carry out external data transfer, to complete the bidirectional data transfer operation from SRAM to the general register; The MOV instruction moves data between registers. The data is moved to a register. The input is a constant, a general register, or a special register. The output is a general register or a special register.

10. A method for operating a programmable AES encryption module hardware accelerator, characterized in that: The method is implemented by using the accelerator described in any one of claims 1 to 8, and comprises: Step 1: Determine whether the current round of AES encryption or decryption operation has been completed. If not, execute step 2; otherwise, terminate the current round of operation. Step 2, write the received new instruction into the instruction stack; Step 3, pop the last instruction in the instruction stack; Step 4, decode the popped instruction and assign it to the computing module or the transport module for processing; Step 5, wait for the processing described in step 4 to be completed, check whether the instruction stack is empty, if it is empty, end the operation, otherwise return to execute step 1.

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