Capacitor assembly, power assembly and converter

Abstract

The invention provides a capacitor assembly, a power assembly and a converter, in the capacitor assembly, first ends and positive terminals of a plurality of capacitors of a positive capacitor array are connected to a positive conduction path, and second ends and negative terminals of a plurality of capacitors of a negative capacitor array are connected to a negative conduction path. The second ends of the plurality of capacitors of the positive capacitor array, the first ends of the plurality of capacitors of the negative capacitor array and the transfer end are connected to a second conduction path, and the neutral terminal and the transfer end are connected to a third conduction path, so that for the positive capacitor array, commutation paths of the positive terminal reaching the neutral terminal after passing through each capacitor are equal in length, and commutation paths of the negative terminal reaching the neutral terminal after passing through each capacitor are equal in length. And for a negative capacitor array, commutation paths from a negative terminal to a neutral terminal after passing through each capacitor are equal in length; the second conduction path and the third conduction path are located on different wiring layers respectively, so that current sharing among capacitors of the positive capacitor array and current sharing among capacitors of the negative capacitor array are achieved, and wiring is facilitated.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to a Chinese patent application filed with the State Intellectual Property Office of China on March 28, 2024, with application number 202410363349.5 and application name “A capacitor component, power component and converter with multiple capacitors connected in parallel”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the technical field of integrated circuits, and in particular to a capacitor component, a power component and a converter. Background Art

[0004] In the field of power supply, capacitors are often used to improve circuit stability and reduce noise, especially in inverters and uninterruptible power supplies. Using capacitors as busbar capacitors can not only filter out high-frequency noise from the power supply, but also provide a stable power supply voltage. They are widely used. In order to meet the demand for large capacitance, multiple capacitors are often used in parallel. When multiple capacitors are used in parallel, how to improve the current sharing between the capacitors is an urgent problem to be solved. Summary of the invention

[0005] Embodiments of the present application provide a capacitor component, a power component, and a converter.

[0006] In a first aspect, an embodiment of the present application provides a capacitor assembly, the capacitor assembly comprising a capacitor pool disposed on a printed circuit board and a terminal group and a transfer terminal respectively located on opposite sides of the capacitor pool; the terminal group comprises a positive terminal, a neutral terminal and a negative terminal, the capacitor pool comprises at least one positive capacitor array and at least one negative capacitor array, the positive capacitor array and the negative capacitor array comprise a plurality of capacitors connected in parallel;

[0007] The first ends of the multiple capacitors of the positive capacitor array and the positive terminal are both connected to the positive conduction path, the second ends of the multiple capacitors of the negative capacitor array and the negative terminal are both connected to the negative conduction path, the first conduction path includes the positive conduction path and / or the negative conduction path, the second ends of the multiple capacitors of the positive capacitor array, the first ends of the multiple capacitors of the negative capacitor array and the transfer end are all connected to the second conduction path, and the neutral terminal and the transfer end are both connected to the third conduction path, so that for the positive capacitor array, the commutation paths from the positive terminal to the neutral terminal after passing through each of the capacitors are of equal length, and for the negative capacitor array, the commutation paths from the negative terminal to the neutral terminal after passing through each of the capacitors are of equal length;

[0008] The printed circuit board includes multiple wiring layers, and the second conductive path and the third conductive path are respectively located in different wiring layers.

[0009] In some embodiments, the positive conduction path, the second conduction path and the third conduction path are respectively located in different wiring layers, and the positive conduction path and the negative conduction path are located in the same wiring layer;

[0010] The multi-layer wiring layer includes a first wiring layer, a second wiring layer and a third wiring layer, the first wiring layer includes a first wiring area and a second wiring area, the second wiring layer includes a third wiring area, and the third wiring layer includes a fourth wiring area; the positive terminal is electrically connected to the first wiring area, the negative terminal is electrically connected to the second wiring area, the transfer end is electrically connected to the third wiring area, and the transfer end and the neutral terminal are electrically connected to the fourth wiring area.

[0011] In some embodiments, the current carrying value corresponding to the smallest area among the area of ​​the first wiring region, the area of ​​the second wiring region, the area of ​​the third wiring region, and the area of ​​the fourth wiring region is the smallest current carrying value of the capacitor component.

[0012] In some embodiments, the multi-layer wiring layer further includes a fourth wiring layer and a fifth wiring layer;

[0013] The third conduction path is located in the fourth wiring layer, and the second conduction path is located in the fifth wiring layer; the positive conduction path includes a first sub-path located in the fourth wiring layer and a second sub-path located in the fifth wiring layer, and the first sub-path and the second sub-path are connected in parallel; the negative conduction path includes a third sub-path located in the fourth wiring layer and a fourth sub-path located in the fifth wiring layer, and the third sub-path and the fourth sub-path are connected in parallel.

[0014] In some embodiments, the fourth wiring layer includes a fifth wiring area, a sixth wiring area, and a seventh wiring area, and the fifth wiring layer includes an eighth wiring area, a ninth wiring area, and a tenth wiring area;

[0015] The positive terminal is electrically connected to the fifth wiring area and the eighth wiring area, the negative terminal is electrically connected to the seventh wiring area and the tenth wiring area, the transfer end is electrically connected to the ninth wiring area, and the transfer end and the neutral terminal are electrically connected to the sixth wiring area.

[0016] In some embodiments, in the fourth wiring layer, the fifth wiring area, the sixth wiring area, and the seventh wiring area all extend along the first direction, and the fifth wiring area, the sixth wiring area, and the seventh wiring area are sequentially arranged along the second direction; in the fifth wiring layer, the eighth wiring area, the ninth wiring area, and the tenth wiring area all extend along the first direction, and the eighth wiring area, the ninth wiring area, and the tenth wiring area are sequentially arranged along the second direction;

[0017] The projections of the fifth wiring area and the eighth wiring area along the third direction overlap, the projections of the sixth wiring area and the ninth wiring area along the third direction overlap, and the projections of the seventh wiring area and the tenth wiring area along the third direction overlap;

[0018] The plane where the first direction and the second direction are located is the plane where the printed circuit board is located, and the third direction is perpendicular to the plane where the printed circuit board is located.

[0019] In some embodiments, the current carrying value corresponding to the minimum area among the sum of the areas of the fifth wiring area and the eighth wiring area, the sum of the areas of the seventh wiring area and the tenth wiring area, the area of ​​the sixth wiring area, and the area of ​​the ninth wiring area is the minimum current carrying value of the capacitor component.

[0020] In some embodiments, the positive terminal is the first end of the first capacitor in the positive capacitor array; the negative terminal is the second end of the first capacitor in the negative capacitor array; the intermediate terminal is the second end of the last capacitor in the positive capacitor array, and / or the intermediate terminal is the first end of the last capacitor in the negative capacitor array;

[0021] The first capacitor and the last capacitor are two capacitors with the farthest distance in the positive capacitor array and / or the negative capacitor array.

[0022] In a second aspect, an embodiment of the present application provides a power component, which includes a power conversion circuit and a capacitor component as described in any one of the first aspects, and the power conversion circuit is connected to the capacitor component through the terminal group.

[0023] In a third aspect, an embodiment of the present application provides a converter, wherein the converter includes a capacitor component as described in any one of the first aspect, or includes a power component as described in the second aspect.

[0024] The embodiments of the present application provide a capacitor component, a power component and a converter, wherein the capacitor component includes a capacitor pool arranged on a printed circuit board and a terminal group and a transfer terminal respectively located on opposite sides of the capacitor pool; the terminal group includes a positive terminal, a neutral terminal and a negative terminal, the capacitor pool includes at least one positive capacitor array and at least one negative capacitor array, the positive capacitor array and the negative capacitor array include multiple capacitors connected in parallel; the first ends and the positive terminals of the multiple capacitors in the positive capacitor array are both connected to the positive conduction path, the second ends and the negative terminals of the multiple capacitors in the negative capacitor array are both connected to the negative conduction path, and the first conduction The conduction path includes a positive conduction path and / or a negative conduction path, the second ends of the multiple capacitors of the positive capacitor array, the first ends of the multiple capacitors of the negative capacitor array and the transfer end are all connected to the second conduction path, and the neutral terminal and the transfer end are all connected to the third conduction path, so that for the positive capacitor array, the commutation paths from the positive terminal to the neutral terminal after passing through each capacitor are of equal length, and for the negative capacitor array, the commutation paths from the negative terminal to the neutral terminal after passing through each capacitor are of equal length; wherein the printed circuit board includes multiple wiring layers, and the second conduction path and the third conduction path are respectively located in different wiring layers. In this way, by setting the transfer end on the opposite side of the terminal group, and the positive capacitor array and the negative capacitor array share three connecting terminals in the terminal group, and share the second conduction path and the third conduction path, the positive capacitor array and / or the negative capacitor array have the same length of the commutation path passing through each capacitor, so that the equivalent impedance on the conduction path is equal, and the current equalization between the capacitors of the positive capacitor array and the current equalization between the capacitors of the negative capacitor array are achieved, while reducing the connection paths between the capacitors and reducing the difficulty of wiring; in addition, the second conduction path and the third conduction path are distributed in different wiring layers, and the wiring can be three-dimensionally staggered in a direction perpendicular to the board surface of the printed circuit board, thereby achieving current equalization when the board surface area is constrained, which facilitates wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A connection equivalent diagram of a capacitor assembly provided in an embodiment of the present application Figure 1 ;

[0026] Figure 2 A connection equivalent diagram of a capacitor assembly provided in an embodiment of the present application Figure 2 ;

[0027] Figure 3 A schematic diagram of the structure of a printed circuit board of a capacitor assembly provided in an embodiment of the present application Figure 1 ;

[0028] Figure 4 A schematic diagram of the structure of a printed circuit board of a capacitor assembly provided in an embodiment of the present application Figure 2 ;

[0029] Figure 5A schematic diagram of a power component provided in an embodiment of the present application;

[0030] Figure 6 A schematic diagram of a power component with multiple conversion bridge arms provided in an embodiment of the present application Figure 1 ;

[0031] Figure 7 A schematic diagram of a power component with multiple conversion bridge arms provided in an embodiment of the present application Figure 2 ;

[0032] Figure 8 A schematic diagram of a T-type three-level bridge arm provided in an embodiment of the present application;

[0033] Fig. 9 A schematic diagram of a type I three-level bridge arm provided in an embodiment of the present application;

[0034] Fig.10 The following is a schematic diagram of a rectangular layout of a T-type three-level bridge arm provided in an embodiment of the present application;

[0035] Fig.11 The following is a schematic diagram of a T-type three-level bridge arm diamond layout provided in an embodiment of the present application;

[0036] Fig.12 The following is a schematic diagram of an I-type three-level bridge arm layout provided in an embodiment of the present application. Figure 1 ;

[0037] Fig.13 The following is a schematic diagram of an I-type three-level bridge arm layout provided in an embodiment of the present application. Figure 2 ;

[0038] Fig.14 The following is a schematic diagram of an I-type three-level bridge arm layout provided in an embodiment of the present application. Figure 3 ;

[0039] Fig.15 The following is a schematic diagram of an I-type three-level bridge arm layout provided in an embodiment of the present application. Figure 4 ;

[0040] Fig.16 A schematic diagram of the structure of a converter provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. It is understood that the specific embodiments described herein are only used to explain the relevant application, not to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present application. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application. In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be pointed out that the terms "first\second\third" involved in the embodiments of the present application are only used to distinguish similar objects, and do not represent a specific order for the objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that shown or described.

[0042] IGBT (Insulated Gate Bipolar Transistor): Insulated Gate Bipolar Transistor;

[0043] MOS (Metal-Oxide-Semiconductor Field-Effect Transistor): Metal-Oxide Semiconductor Field-Effect Transistor;

[0044] BJT (Bipolar Junction Transistor): Bipolar junction transistor;

[0045] HBT (Hetero Junction Bipolar Transistor): Heterojunction bipolar transistor.

[0046] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0047] In one embodiment of the present application, a capacitor assembly is provided, including a capacitor pool arranged on a printed circuit board and a terminal group and a transfer end respectively located on opposite sides of the capacitor pool, the terminal group including a first terminal and a second terminal, the capacitor pool including at least one capacitor array, each capacitor array including a plurality of capacitors connected in parallel, the first ends and the first terminals of the plurality of capacitors are both connected to a first conduction path, the second ends and the transfer ends of the plurality of capacitors are both connected to a second conduction path, and the second terminals and the transfer ends are both connected to a third conduction path, so that the commutation path from the first terminal to the second terminal after passing through each capacitor is of equal length.

[0048] In this embodiment, the connection relationship of the capacitor components is equivalent to Figure 1 As shown, the first terminal 11 and the second terminal 12 are used to connect the capacitor assembly to other external components, and multiple capacitors C1 are connected in parallel to form a capacitor array. The first end of each capacitor C1 is connected to the first terminal 11 through the first conductive path 21, and the second end of each capacitor C1 is connected to the transfer end 13 through the second conductive path 22. The transfer end 13 is connected to the second terminal 12 through the third conductive path 23. Figure 1 It can be seen from the diagram that the path length of each capacitor C1 through the first conduction path 21 is the same as the sum of the lengths through the second conduction path 22 and the third conduction path 23, that is, the commutation paths from the first terminal 11 through each capacitor C1 to the second terminal 12 are of equal length, so that the equivalent impedances on the conduction paths of different capacitors are equal, thereby ensuring that the current flowing through each capacitor C1 is evenly distributed.

[0049] In addition, a large capacitor with a preset capacitance is formed by connecting multiple small capacitors in parallel. Since the capacitance inductance is proportional to the pin spacing, the package volume of the small capacitor is small, which makes the single capacitor inductance small. According to experimental data, the inductance of the large capacitor is greater than the inductance of the equivalent large capacitor formed by connecting multiple small capacitors in parallel. It can be seen that the inductance can be further reduced by connecting multiple small capacitors in parallel, and the reverse peak of the device can be reduced. In addition, the distribution position of each small capacitor can be flexibly selected, which also provides greater freedom for the layout of the PCB board.

[0050] In another embodiment of the present application, the capacitor assembly includes a capacitor pool disposed on a printed circuit board and a terminal group and a transfer terminal respectively located on opposite sides of the capacitor pool; the terminal group includes a positive terminal, a neutral terminal and a negative terminal, the capacitor pool includes at least one positive capacitor array and at least one negative capacitor array, and the positive capacitor array and the negative capacitor array include a plurality of capacitors connected in parallel;

[0051] The first ends and positive terminals of the multiple capacitors of the positive capacitor array are connected to the positive conduction path, the second ends and negative terminals of the multiple capacitors of the negative capacitor array are connected to the negative conduction path, the first conduction path includes the positive conduction path and / or the negative conduction path, the second ends of the multiple capacitors of the positive capacitor array, the first ends and the transfer ends of the multiple capacitors of the negative capacitor array are connected to the second conduction path, and the neutral terminal and the transfer end are connected to the third conduction path, so that for the positive capacitor array, the commutation paths from the positive terminal to the neutral terminal after passing through each capacitor are of equal length, and for the negative capacitor array, the commutation paths from the negative terminal to the neutral terminal after passing through each capacitor are of equal length;

[0052] The printed circuit board includes multiple wiring layers, and the second conducting path and the third conducting path are respectively located in different wiring layers.

[0053] In this embodiment, the connection relationship of the capacitor components is equivalent to Figure 2 As shown, it includes at least one positive capacitor array (including multiple capacitors C1, hereinafter referred to as C1) and at least one negative capacitor array (including multiple capacitors C2, hereinafter referred to as C2). For the positive capacitor array C1, the positive terminal BUS+ and the neutral terminal N are respectively equivalent to the previous embodiment ( Figure 1 The first terminal 11 and the second terminal 12 of the capacitor assembly shown in the figure, the positive conduction path 21 is equivalent to the first conduction path 21 of the previous embodiment, the second conduction path 22 is equivalent to the second conduction path 22 of the previous embodiment, the third conduction path 23 is equivalent to the third conduction path 23 in the previous embodiment, and the transfer end (i.e., the N line confluence point in the figure) is equivalent to the transfer end 13 in the previous embodiment; and for the negative capacitor array C2, the negative terminal BUS- and the neutral terminal N in this embodiment are respectively equivalent to the first terminal 11 and the second terminal 12 in the previous embodiment, the negative conduction path 24 is equivalent to the first conduction path 21 in the previous embodiment, the second conduction path 22 is equivalent to the second conduction path 22 in the previous embodiment, the third conduction path 23 is equivalent to the third conduction path 23 in the previous embodiment, and the transfer end (i.e., the N line confluence point in the figure) is equivalent to the transfer end 13 in the previous embodiment. It can be seen that this embodiment is equivalent to the two capacitor arrays in the previous embodiment connected in series, and from the above connection relationship and Figure 2 It can also be seen that in this embodiment, the positive capacitor array C1 and the negative capacitor array C2 are connected in series, and the positive capacitor array and the negative capacitor array share three connection terminals (positive terminal BUS+, neutral terminal N, and negative terminal BUS-), and also share the second conduction path 22 and the third conduction path 23 on the conduction path, so as to achieve current sharing between the capacitors of the positive capacitor array C1 and current sharing between the capacitors of the negative capacitor array C2, while reducing the connection paths between the capacitors and reducing the difficulty of wiring.

[0054] It should be noted that distributing the second conduction path 22 and the third conduction path 23 in different wiring layers can facilitate wiring. Specifically, in order to achieve current sharing, the transfer end will be added during the actual layout, so that the corresponding circuit needs to occupy more board area of ​​the printed circuit board compared to the case where current sharing is not achieved. However, by arranging the second conduction path 22 and the third conduction path 23 in different wiring layers, the wiring can be three-dimensionally staggered in a direction perpendicular to the board surface of the printed circuit board, thereby achieving current sharing when the board area is constrained. Furthermore, according to actual conditions, the positive conduction path and / or the negative conduction path are distributed in the corresponding wiring layer, which can save the board area of ​​the printed circuit board.

[0055] In some embodiments, the positive conduction path 21 , the second conduction path 22 , and the third conduction path 23 are located in different wiring layers, respectively, and the positive conduction path 21 and the negative conduction path 24 are located in the same wiring layer;

[0056] The multilayer wiring layer includes a first wiring layer, a second wiring layer and a third wiring layer, the first wiring layer includes a first wiring area and a second wiring area, the second wiring layer includes a third wiring area, and the third wiring layer includes a fourth wiring area; the positive terminal is electrically connected to the first wiring area, the negative terminal is electrically connected to the second wiring area, the transfer end is electrically connected to the third wiring area, and the transfer end and the neutral terminal are electrically connected to the fourth wiring area.

[0057] The layout of the PCB board of this embodiment is as follows Figure 3 shown. Figure 3 FIG. 1 schematically shows a plurality of capacitors 1 forming a capacitor pool, and terminal groups (including a positive terminal 11, a negative terminal 14, a neutral terminal 12) and a transfer terminal 13 located on both sides of the capacitor pool. Figure 3 As can be seen in the figure, the terminal group is located on the left side of the capacitor pool along the first direction, and the transfer end 13 is located on the right side of the capacitor pool along the first direction, that is, the terminal group and the transfer end are located on opposite sides of the capacitor pool. The multiple capacitors 1 constituting the capacitor pool are divided into a positive capacitor array and a negative capacitor array. Figure 3 (a), (b), and (c) are layout diagrams of different wiring layers of the PCB board, wherein the positive conduction path 21 and the negative conduction path 24 are arranged in the same wiring layer, such as Figure 3 As shown in (a) of FIG. 1 , the second conductive path 22 and the third conductive path 23 are respectively located in the other two wiring layers, as shown in FIG. Figure 3 (b) Figure 3 As shown in (c) in .

[0058] Specifically, by Figure 3 As can be seen from (a) in the figure, the positive terminal 11 (corresponding to Figure 2 BUS+ in the positive capacitor array) and the first end of each capacitor 1 in the positive capacitor array is connected to the positive conduction path 21 (the two pins of capacitor 1, the small white dot in the conduction path indicates that it is connected to the corresponding conduction path, and the black circle point indicates that it is not connected to the conduction path. Figure 3 As shown in (a), the 15 capacitors 1 distributed on the upper side of the PCB board are positive capacitor arrays), and the negative terminal 14 (corresponding to Figure 2 The first end of each capacitor 1 in the negative capacitor array is connected to the negative conduction path 24 (from Figure 3 From (a) in the figure, we can see that the 15 capacitors 1 distributed on the lower side of the PCB board are negative capacitor arrays); Figure 3 As can be seen from (b) in FIG. 1 , the second end of each capacitor 1 in the positive capacitor array and the first end of each capacitor 1 in the negative capacitor array and the transfer end 13 are all connected to the second conducting path 22; Figure 3 As can be seen from (c) in FIG. 1 , the neutral terminal 12 and the transfer terminal 13 are connected via the third conducting path 23 .

[0059] It should be noted that Figure 3 (a) is the first wiring layer, Figure 3 (b) in the figure is the second wiring layer. Figure 3 (c) in the figure is the third wiring layer. In addition, the first wiring layer, the second wiring layer and the third wiring layer may be any three layers among the plurality of wiring layers, and the positional relationship among the first wiring layer, the second wiring layer and the third wiring layer is not limited. For example, the third wiring layer is located above the second wiring layer, and the second wiring layer is located above the first wiring layer.

[0060] It should also be noted that if Figure 3 As shown, area a1 represents the first wiring area, area a2 represents the second wiring area, area a3 represents the third wiring area, and area a4 represents the fourth wiring area. The positive conduction path 21 passes through the first wiring area (a1), the negative conduction path 24 passes through the second wiring area (a2), the second conduction path 22 passes through the third wiring area (a3), and the third conduction path 23 passes through the fourth wiring area (a4). In addition, each wiring area can be composed of copper foil in the PCB board.

[0061] In some embodiments, the current carrying value corresponding to the minimum area among the area of ​​the first wiring area (a1), the area of ​​the second wiring area (a2), the area of ​​the third wiring area (a3), and the area of ​​the fourth wiring area (a4) is the minimum current carrying value of the capacitor component.

[0062] like Figure 3 As shown, the area of ​​the first wiring area (a1) and the area of ​​the second wiring area (a2) are smaller than the area of ​​the third wiring area (a3) ​​and the area of ​​the fourth wiring area (a4). For example, the area of ​​the first wiring area (a1) is equal to the area of ​​the second wiring area (a2), and the area of ​​the third wiring area (a3) ​​is equal to the area of ​​the fourth wiring area (a4). Among them, the current carrying value corresponding to the area of ​​the first wiring area (a1) and / or the area of ​​the second wiring area (a2) can already meet the minimum current carrying value of the capacitor component. Here, the area of ​​the third wiring area (a3) ​​and / or the area of ​​the fourth wiring area (a4) is larger because there is a redundant area, and the board surface utilization rate of the PCB board in this embodiment is low.

[0063] According to the above Figure 3It can be seen that the positive conduction path 21, the second conduction path 22 and the third conduction path 23 are respectively located in different wiring layers of the printed circuit board, and the negative conduction path 24 is located in the same wiring layer as the positive conduction path 21. Different conduction paths are distributed in different wiring layers to facilitate wiring. In addition, since the distribution of the positive capacitor array and the negative capacitor array on the printed circuit board cannot overlap, as long as the positive circuit array and the negative capacitor array are partitioned, the positive conduction path 21 corresponding to the positive capacitor array and the negative conduction path 24 corresponding to the negative capacitor array can be respectively used in the same wiring layer, and the wiring layer can be fully utilized. Moreover, for many circuits, the operating current and operating voltage of the positive half cycle and the negative half cycle are symmetrical, and they are distributed in the same wiring layer. From the wiring perspective, the positive half cycle and the negative half cycle can also be relatively symmetrical, which is conducive to error checking.

[0064] In some embodiments, the positive terminal is the first end of the first capacitor in the positive capacitor array; the negative terminal is the second end of the first capacitor in the negative capacitor array; the intermediate terminal is the second end of the last capacitor in the positive capacitor array, and / or the intermediate terminal is the first end of the last capacitor in the negative capacitor array;

[0065] The first capacitor and the last capacitor are two capacitors with the farthest distance in the positive capacitor array and / or the negative capacitor array.

[0066] from Figure 3 As can be seen, the terminal group including the positive terminal 11, the negative terminal 14, and the neutral terminal 12 is used as the connection terminal between the capacitor assembly and other external components. The connection terminal that needs to be independently set is convenient for other external components to be connected thereto, and the transfer terminal 13 is only used as the summary terminal of the two conduction paths, and there is no need to independently set the connection terminal. For example, in this embodiment, the pin of the capacitor on the far right along the first direction in the capacitor array is used as the transfer terminal 13, specifically the second end of the capacitor on the far right along the first direction in the positive capacitor array and the first end of the capacitor on the far right along the first direction in the negative capacitor array. The capacitor close to the terminal group in the capacitor array is used as the first capacitor, then the capacitor on the far right (i.e., the last capacitor) is the capacitor farthest away from the first capacitor in the capacitor array. In other embodiments, the transfer end 13 can also be independently set with a connection end like a terminal group. Of course, if the terminal group is not used to connect other external components, or other external components can be connected by other means, the pin of a capacitor in the capacitor array can also be used as a terminal group. Of course, the capacitor used as the terminal group should preferably be the first capacitor in the capacitor array that is farthest away from the last capacitor, so as to ensure that the commutation path passing through each capacitor is of equal length.

[0067] In this embodiment, one pin of the first capacitor or the last capacitor in the capacitor array is used as the first terminal (positive terminal 11 and / or negative terminal 14) or the transfer terminal 13 of the terminal group, thereby reducing the number of connection terminals and increasing the layout freedom of the printed circuit board.

[0068] When the capacitor assembly is used as a busbar capacitor, the terminal group may further include a third terminal 15 and a fourth terminal 16, wherein other external devices are connected between the third terminal 15 and the first terminal 11, and other devices are connected between the fourth terminal 16 and the second terminal 12. The other devices here may be inductors, absorption circuits, etc., which are not specifically limited. Thus, the capacitor pool and other devices constitute a complete capacitor assembly, and the external connection terminals of the capacitor assembly include the third terminal 15, the neutral terminal 12, and the fourth terminal 16, which increases the integration of the PCB board and reduces the assembly difficulty of the assembler.

[0069] In the related technology, how to improve the current distribution between capacitors with a smaller board area when the board area of ​​the PCB is limited is also a problem to be solved. In addition, how to improve the current distribution between capacitors with a smaller number of board layers when the board area is the same is also a direction to solve the problem.

[0070] In some embodiments, see Figure 4 , which shows a schematic diagram of the structure of a printed circuit board of a capacitor assembly provided in an embodiment of the present application Figure 2 .like Figure 4 As shown, the multi-layer wiring layer further includes a fourth wiring layer and a fifth wiring layer;

[0071] The third conduction path 23 is located at the fourth wiring layer, and the second conduction path 22 is located at the fifth wiring layer; the positive conduction path 21 includes a first sub-path 211 located at the fourth wiring layer and a second sub-path 212 located at the fifth wiring layer, and the first sub-path 211 and the second sub-path 212 are connected in parallel; the negative conduction path 24 includes a third sub-path 241 located at the fourth wiring layer and a fourth sub-path 242 located at the fifth wiring layer, and the third sub-path 241 and the fourth sub-path 242 are connected in parallel.

[0072] Figure 4 FIG. 1 schematically shows a plurality of capacitors 1 forming a capacitor pool, and terminal groups (including a positive terminal 11, a negative terminal 14, a neutral terminal 12) and a transfer terminal 13 located on both sides of the capacitor pool. Figure 4 As can be seen in the figure, the terminal group is located on the left side of the capacitor pool along the first direction, and the transfer end 13 is located on the right side of the capacitor pool along the first direction, that is, the terminal group and the transfer end are located on opposite sides of the capacitor pool. The multiple capacitors 1 constituting the capacitor pool are divided into a positive capacitor array (the 6 capacitors 1 distributed on the upper side of the PCB board) and a negative capacitor array (the 6 capacitors 1 distributed on the lower side of the PCB board). Figure 4(a) and (b) are wiring diagrams of different wiring layers of the PCB board, wherein the positive conduction path 21 and the negative conduction path 24 each include two sub-paths located in two wiring layers respectively, and the second conduction path 22 and the third conduction path 23 are located in two wiring layers respectively.

[0073] Specifically, by Figure 4 As can be seen in (a), the positive terminal 11 and the first end of each capacitor 1 in the positive capacitor array are connected to the positive conduction path 21 (the small white dot in the conduction path of the two pins of the capacitor 1 indicates that it is connected to the corresponding conduction path, and the black circle dot indicates that it is not connected to the conduction path), the negative terminal 14 and the first end of each capacitor 1 in the negative capacitor array are connected to the negative conduction path 24; and the neutral terminal 12 and the transfer terminal 13 are connected through the third conduction path 23. Figure 4 As can be seen from (b) in FIG. 1 , the second end of each capacitor 1 in the positive capacitor array and the first end of each capacitor 1 in the negative capacitor array and the transfer end 13 are all connected to the second conducting path 22 .

[0074] It should be noted that Figure 4 (a) in FIG. 1 is the fourth wiring layer, Figure 4 (b) in the figure is the fifth wiring layer. In addition, the fourth wiring layer and the fifth wiring layer may be any two layers of the plurality of wiring layers, and the positional relationship between the fourth wiring layer and the fifth wiring layer is not limited. Exemplarily, the fifth wiring layer is located above the fourth wiring layer.

[0075] It should also be noted that the fourth wiring layer serves as a current layer that converges to the terminal group, and the pin of the capacitor 1 connected to the electrical connection network cannot be connected to the fourth wiring layer; the fifth wiring layer serves as a converging layer for all capacitors 1, and the copper foil of the fifth wiring layer cannot be connected to the neutral terminal 12. The current connection points of the fourth wiring layer and the fifth wiring layer are at the capacitor farthest from the terminal group (i.e., the last capacitor), and are connected through vias. The same is true when more wiring layers are needed for connection. This embodiment is only exemplified by the fourth wiring layer and the fifth wiring layer each including one wiring layer, and the fourth wiring layer and / or the fifth wiring layer may also include multiple sub-wiring layers connected in parallel, which is not specifically limited.

[0076] It should also be noted that, in the fourth wiring layer, the first ends and positive terminals 11 of the multiple capacitors of the positive capacitor array are connected to the first sub-path 211; in the fifth wiring layer, the first ends and positive terminals 11 of the multiple capacitors of the positive capacitor array are connected to the second sub-path 212. Similarly, in the fourth wiring layer, the second ends and negative terminals 14 of the multiple capacitors of the negative capacitor array are connected to the third sub-path 241; in the fifth wiring layer, the second ends and negative terminals 14 of the multiple capacitors of the negative capacitor array are connected to the fourth sub-path 242. In other words, for the positive conduction path 21 and the negative conduction path 24, the current passes through the two sub-paths located in the two wiring layers at the same time.

[0077] In some embodiments, Figure 4 As shown, the fourth wiring layer includes a fifth wiring area, a sixth wiring area, and a seventh wiring area, and the fifth wiring layer includes an eighth wiring area, a ninth wiring area, and a tenth wiring area;

[0078] The positive terminal 11 is electrically connected to the fifth wiring area and the eighth wiring area, the negative terminal 14 is electrically connected to the seventh wiring area and the tenth wiring area, the transfer terminal 13 is electrically connected to the ninth wiring area, and the transfer terminal 13 and the neutral terminal 23 are electrically connected to the sixth wiring area.

[0079] Specifically, Figure 4 As shown, area a5 represents the fifth wiring area, area a6 represents the sixth wiring area, area a7 represents the seventh wiring area, area a8 represents the eighth wiring area, area a9 represents the ninth wiring area, and area a10 represents the tenth wiring area. The first sub-path 211 passes through the fifth wiring area (a5), the third conductive path 23 passes through the sixth wiring area (a6), the third sub-path 241 passes through the seventh wiring area (a7), the second sub-path 212 passes through the eighth wiring area (a8), the second conductive path 22 passes through the ninth wiring area (a9), and the fourth sub-path 242 passes through the tenth wiring area (a10). In addition, each wiring area can be composed of copper foil in the PCB board.

[0080] In some embodiments, Figure 4 As shown, in the fourth wiring layer, the fifth wiring area (a5), the sixth wiring area (a6) and the seventh wiring area (a7) all extend along the first direction, and the fifth wiring area (a5), the sixth wiring area (a6) and the seventh wiring area (a7) are arranged in sequence along the second direction; in the fifth wiring layer, the eighth wiring area (a8), the ninth wiring area (a9) and the tenth wiring area (a10) all extend along the first direction, and the eighth wiring area (a8), the ninth wiring area (a9) and the tenth wiring area (a10) are arranged in sequence along the second direction;

[0081] The projections of the fifth wiring area (a5) and the eighth wiring area (a8) along the third direction overlap, the projections of the sixth wiring area (a6) and the ninth wiring area (a9) along the third direction overlap, and the projections of the seventh wiring area (a7) and the tenth wiring area (a10) along the third direction overlap;

[0082] The plane where the first direction and the second direction are located is the plane where the printed circuit board is located, and the third direction is perpendicular to the plane where the printed circuit board is located.

[0083] That is, along the third direction, the fifth wiring area (a5) corresponds to the eighth wiring area (a8), the sixth wiring area (a6) corresponds to the ninth wiring area (a9), and the seventh wiring area (a7) corresponds to the tenth wiring area (a10).

[0084] It should be noted that the third direction is perpendicular to the plane where the printed circuit board is located. On the surface of the printed circuit board, two directions intersecting with each other (for example, perpendicular to each other) are defined, namely, the first direction and the second direction.

[0085] It should also be noted that the projections of the fifth wiring area (a5) and the eighth wiring area (a8) along the third direction can be completely overlapped or partially overlapped. When they are completely overlapped, the fifth wiring area (a5) and the eighth wiring area (a8) have the same shape and equal area; the projections of the seventh wiring area (a7) and the tenth wiring area (a10) along the third direction can be completely overlapped or partially overlapped. When they are completely overlapped, the seventh wiring area (a7) and the tenth wiring area (a10) have the same shape and equal area; because the copper foil of the fifth wiring layer is not connected to the neutral terminal 12, the projections of the sixth wiring area (a6) and the ninth wiring area (a9) along the third direction partially overlap. Exemplarily, the specific implementation of the embodiment of the present application is described in detail by taking the example that the projections of the fifth wiring area (a5) and the eighth wiring area (a8) along the third direction and the projections of the seventh wiring area (a7) and the tenth wiring area (a10) along the third direction are completely overlapped.

[0086] In some embodiments, the current carrying value corresponding to the minimum area among the sum of the areas of the fifth wiring area (a5) and the eighth wiring area (a8), the sum of the areas of the seventh wiring area (a7) and the tenth wiring area (a10), the area of ​​the sixth wiring area (a6), and the area of ​​the ninth wiring area (a9) is the minimum current carrying value of the capacitor component.

[0087] Exemplarily, the sum of the areas of the fifth wiring area (a5) and the eighth wiring area (a8) is equal to the sum of the areas of the seventh wiring area (a7) and the tenth wiring area (a10), and the area value is less than or equal to the area of ​​the sixth wiring area (a6) and the area of ​​the ninth wiring area (a9). The sum of the areas of the fifth wiring area (a5) and the eighth wiring area (a8), and / or the sum of the areas of the seventh wiring area (a7) and the tenth wiring area (a10) corresponds to a current carrying value that can satisfy the minimum current carrying value of the capacitor component; if the minimum current carrying value of the capacitor component is 10A (ampere, ampere), the current carrying values ​​corresponding to the areas of the fifth wiring area (a5), the eighth wiring area (a8), the seventh wiring area (a7) and the tenth wiring area (a10) are 5A respectively.

[0088] In this embodiment, the second conduction path 22 and the third conduction path 23 are staggered, and the positive conduction path 21 and the negative conduction path 24 are divided into two staggered sub-paths, so that not only can the current sharing between the capacitors of the positive capacitor array and the current sharing between the capacitors of the negative capacitor array be achieved, the connection paths between the capacitors are reduced, and the wiring difficulty is reduced, but also less board area of ​​the printed circuit board is occupied and fewer board layers of the printed circuit board are occupied.

[0089] In another embodiment of the present application, a power component is provided, such as Figure 5 As shown, the power component 300 includes the aforementioned capacitor component 100 and a power conversion circuit 3. Since the power component 300 includes the aforementioned capacitor component 100, it has at least the same advantages as the capacitor component.

[0090] exist Figure 5 In the embodiment, the capacitor component 100 and the power conversion circuit 3 are arranged on the same PCB board. In other embodiments, the capacitor component 100 and the power conversion circuit 3 constituting the power component 300 can be respectively arranged on different PCB boards or arranged into multiple PCB boards. Engineers can set it according to needs and there is no specific limitation on this.

[0091] In this embodiment, the power conversion circuit 3 may include multiple conversion bridge arms 31, and the capacitor pool also includes at least one first positive capacitor array 41 and at least one first negative capacitor array 42. The first positive capacitor array 41 and the first negative capacitor array 42 are alternately arranged, and each conversion bridge arm 31 is arranged between the first positive capacitor array 41 and the first negative capacitor array 42.

[0092] In this embodiment, the first positive capacitor array 41 and the first negative capacitor array 42 are alternately arranged, and the power conversion bridge arm (i.e., the conversion bridge arm 31) is arranged between the positive capacitor array and the negative capacitor array, so that the path of each power conversion bridge arm from the capacitor pool is relatively equal in length, and the capacitor arrays are dispersedly arranged on both sides of the power conversion bridge arm, so that each power conversion bridge arm has a positive capacitor array and a negative capacitor array nearby, which is conducive to shortening the commutation path, reducing commutation noise, and reducing reverse peaks.

[0093] For example, see Figure 6 The number of the transformation bridge arms 31 is three. The three transformation bridge arms 31 may constitute three parallel transformation bridge arms, or may correspond to three phases of a three-phase circuit respectively, which is not specifically limited. Figure 6 It can be seen that the three transformation bridge arms 31 are arranged in sequence along the first direction, and the first positive capacitor array 41 and the first negative capacitor array 42 are respectively arranged on both sides of each transformation bridge arm 31. In this embodiment, the first positive capacitor array 41 and the first negative capacitor array 42 are collectively referred to as the first capacitor array, and the number of first capacitors included in each first capacitor array is different. In other embodiments, the number of capacitors included in each bus capacitor array may be the same.

[0094] like Figure 6 The power component 300 shown in the embodiment includes an electrolytic capacitor ( Figure 6 Small circles in the figure) and thin film capacitors ( Figure 6 In the figure, the electrolytic capacitors constitute the aforementioned positive capacitor array and negative capacitor array, and the thin film capacitors constitute the aforementioned first positive capacitor array and first negative capacitor array. In other embodiments, both the electrolytic capacitors and the thin film capacitors can constitute the aforementioned capacitor array, positive capacitor array, negative capacitor array, first positive capacitor array, and first negative capacitor array, and no specific limitation is given to this.

[0095] In this embodiment, the conversion bridge arm 31 is a multi-level bridge arm, and the two multi-level bridge arms distributed on both sides of the first capacitor array are mirror-symmetrical in layout. The first capacitor array includes a first positive capacitor array 41 and a first negative capacitor array 42. More specifically, the multi-level bridge arm can be a T-type three-level bridge arm or an I-type three-level bridge arm.

[0096] Specific as Figure 7 As shown ( Figure 7 The fact that electrolytic capacitors are not shown does not mean that there are no electrolytic capacitors). The area where the multiple switching devices constituting the conversion bridge arm 31 are located is defined as the core device area. The multiple switching devices and decoupling capacitors are all located within the core device area, the capacitor pool is located outside the core device area, and the conversion bridge arms 31 located on both sides of the first capacitor array (the first positive capacitor array 41 or the first negative capacitor array 42) are mirror-symmetrical.

[0097] In this embodiment, a first positive capacitor array 41 and a first negative capacitor array 42 are arranged on both sides of the conversion bridge arm 31, so that a large number of small capacitors are connected in parallel in the positive half-cycle or negative half-cycle commutation circuit of each conversion bridge arm 31, so that the path is short, the inductance is small, and the reverse peak is small.

[0098] In this embodiment, the multi-level bridge arm also includes a decoupling capacitor, which is arranged in a core device area, and the two ends of the decoupling capacitor are respectively connected in parallel with a positive capacitor array or a negative capacitor array, wherein the core device area is a device area formed by multiple switching devices constituting the multi-level bridge arm.

[0099] The following further describes the conversion bridge arm 31 by taking the conversion bridge arm 31 as a T-type three-level bridge arm and an I-type three-level bridge arm as an example.

[0100] The connection relationship of the T-type three-level bridge arm is as follows Figure 8 As shown, the multiple switch devices constituting the T-type three-level bridge arm include a first switch device 311, a second switch device 312, a third switch device 313 and a fourth switch device 314, and the bus capacitor includes a first bus capacitor 315 and a second bus capacitor 316; the first switch device 311 and the fourth switch device 314 are connected in series to form a vertical pipe bridge arm, the second switch device 312 and the third switch device 313 are connected in series to form a horizontal pipe bridge arm, and the first bus capacitor 315 and the second bus capacitor 316 are connected in series to form Capacitor bridge arm, wherein the common point of the first switch device 311 and the fourth switch device 314 is used as the output point (i.e., the AC end), the common point of the first bus capacitor 315 and the second bus capacitor 316 is used as the midpoint O, the two free ends of the vertical tube bridge arm are respectively connected in parallel with the two free ends of the capacitor bridge arm, the first end of the horizontal tube bridge arm is respectively connected to the midpoint, and the second end is connected to the output point, the two free ends of the capacitor bridge arm are also respectively connected to the positive and negative ends of the power supply, and the decoupling capacitor is connected across the free end of the vertical tube bridge arm and the first end of the horizontal tube bridge arm.

[0101] The connection relationship of the I-type three-level bridge arm is as follows Fig. 9As shown, the multiple switch devices constituting the I-type three-level bridge arm include a first switch device 311, a second switch device 312, a third switch device 313, a fourth switch device 314, a first diode 321 and a second diode 322, and the bus capacitor includes a first bus capacitor 315 and a second bus capacitor 316; the first switch device 311, the second switch device 312, the third switch device 313, and the fourth switch device 314 are connected in series in sequence to form an I-type bridge arm, the first bus capacitor 315 and the second bus capacitor 316 are connected in series to form a capacitor bridge arm, and the first diode 321 and the second diode 322 are connected in series to form a diode bridge arm, wherein, The common point of the first switch device 311 and the second switch device 312 serves as the first connection point, the common point of the second switch device 312 and the third switch device 313 serves as the output point, the common point of the third switch device 313 and the fourth switch device 314 serves as the second connection point, the common point of the first bus capacitor 315 and the second bus capacitor 316 serves as the midpoint O, the two free ends of the I-type bridge arm are respectively connected in parallel with the two free ends of the capacitor bridge arm, the two free ends of the diode bridge arm are respectively connected to the first connection point and the second connection point, the common point of the diode bridge arm is connected to the midpoint O, and the decoupling capacitor is connected between the free end of the I-type bridge arm and the common point of the diode bridge arm.

[0102] exist Fig. 9 In (a), the decoupling capacitor includes a first decoupling capacitor 317 and a second decoupling capacitor 318. In a specific embodiment, see Fig. 9 In (a), the first decoupling capacitor 317 is connected between the free end of the first switching device 311 and the anode of the first diode 321, and the second decoupling capacitor 318 is connected between the free end of the fourth switching device 314 and the cathode of the first diode 322; Fig. 9 In (b), the first decoupling capacitor 317 is connected between the free end of the first switch device 311 and the cathode of the second diode 322, and the second decoupling capacitor 318 is connected between the free end of the fourth switch device 314 and the anode of the first diode 321. Fig. 9 The connection scheme of the decoupling capacitor in (a) is as follows: Fig. 9 The commutation path in (b) is shorter.

[0103] From above Figure 8 and Fig. 9 It can be seen that the two ends of the decoupling capacitor are respectively connected in parallel with the first bus capacitor (i.e., the positive capacitor array) or the second bus capacitor (i.e., the negative capacitor array). It should be noted that the conventional T-type three-level bridge arm and the I-type three-level bridge arm do not include a decoupling capacitor. In the present invention, the decoupling capacitor is added to shorten the commutation loop, which can effectively reduce the inductance of the commutation path and reduce the reverse peak.

[0104] It should be noted that Figure 8 and Fig. 9 In the figure, the first switch device 311 to the fourth switch device 314 are all IGBT devices. In other embodiments, the first switch device 311 to the fourth switch device 314 can also be formed by other types of switch devices / switch device combinations, such as MOS, BJT, HBT, diode, etc. At the same time, each switch device can include a single transistor or multiple transistors.

[0105] In the above description, the capacitance of the decoupling capacitor satisfies: the ripple value of the decoupling capacitor for the reverse peak current is greater than the current value of the decoupling capacitor for the power frequency ripple current, and the ripple value of the decoupling capacitor for the reverse peak current is greater than the current value of the decoupling capacitor for the switching frequency ripple.

[0106] It should be noted that there are mainly three types of ripple currents in the conversion bridge arm 31: (1) power frequency ripple current; (2) switching frequency ripple current; (3) reverse peak ripple current (also known as commutation current). The frequencies of these three ripple currents are different, the frequency of the power frequency ripple is less than the frequency of the switching frequency ripple and less than the frequency of the reverse peak ripple (generally, the frequency of the power frequency ripple is 50Hz (hertz) or 60Hz and its multiples, the frequency of the switching frequency ripple is 10kHz (kilohertz) ~ 100kHz, and the frequency of the reverse peak ripple is 1MHz (megahertz) ~ 10MHz). Through experiments, it is found that capacitors of different types and different capacitances have different passing capacity for the three different frequency ripples, and capacitors with small capacitance have a larger passing capacity for high switching frequencies. The capacitance of the decoupling capacitor needs to allow the reverse peak ripple current to pass well, while allowing less passing capacity for the power frequency ripple current and the switching frequency ripple current. Therefore, the capacitance of the decoupling capacitor cannot be too large, otherwise it is easy to be allocated too much switching frequency current, resulting in capacitor overheating.

[0107] In a specific scenario, the decoupling capacitor "used to shorten the commutation path of the switching process from one current loop to another" has a capacitance of 0.47 microfarads, while the bus capacitor corresponding to the absorption of power frequency ripple current can be 470 microfarads, and electrolytic capacitors are selected, which are large in size and are set in a more peripheral area. It can be composed of multiple capacitors in parallel. The bus capacitor corresponding to the absorption of switching frequency ripple current can be 12 microfarads, and film capacitors are generally used. It is also set in a more peripheral area and can be composed of multiple capacitors in parallel. After experimental verification, the 0.47 microfarad decoupling capacitor has almost no current division for power frequency ripple current, the current division for switching frequency ripple current is about 1%, and the current division for reverse peak ripple current is about 99%. The 12 microfarad bus capacitor has a current division of about 95% for switching frequency ripple current, and the division of reverse peak ripple current is about 1%. The 0.47 microfarad decoupling capacitor has almost no current division for reverse peak ripple current, and the current division for power frequency ripple current is about 99%. It can be seen that the reverse peak ripple current (i.e., commutation current) mainly passes through the decoupling capacitor. The above capacitance values ​​and test data are only a set of values ​​in the test process of the inventor, and cannot limit the unique value range of the capacitance of this application, nor can they limit the current division of different capacitors for different ripple currents. It is also as measured in the test, and should be understood based on the inventive concept of the present invention.

[0108] In this embodiment, by setting a decoupling capacitor, and setting the decoupling capacitor and the multiple switching devices constituting the multi-level bridge arm in the core device area, the positive capacitor array and the negative capacitor array are relatively located outside the core device area, and the commutation path through the decoupling capacitor is greatly shortened relative to the commutation path through the positive capacitor array and the negative capacitor array, thereby reducing the path stray inductance during the commutation process, thereby reducing the reverse peak and improving the device life. In other words, the embodiment of the present application can reduce the length of the commutation path during the switching process from the mid-position freewheeling loop to the reverse freewheeling loop by introducing a decoupling capacitor, thereby reducing the reverse peak and extending the device life.

[0109] In yet another embodiment of the present application, a converter is provided. The converter includes the aforementioned capacitor component 100 , or the aforementioned power component 300 .

[0110] The following is a T-type three-level bridge arm (i.e. Figure 8 Taking the structure shown in FIG. 1 as an example, several specific layouts are provided for your reference and understanding.

[0111] In some embodiments, the layout of the T-type three-level bridge arm can be as follows: Figure 7As shown, under this layout, the first switch device 311, the second switch device 312, the third switch device 313, and the fourth switch device 314 present a T-shaped layout; the first switch device 311 and the fourth switch device 314 constitute the short side of the T-shaped layout; the second switch device 312 and the third switch device 313 constitute the long side of the T-shaped layout; the third switch device 313 is close to the short side of the T-shaped layout, and the second switch device 312 is far away from the long side of the T-shaped layout.

[0112] It should be noted that under the T-type layout, even the commutation path through the bus capacitor is relatively short and has a low reverse peak. In addition, when wiring the PCB multilayer board, it is easy to achieve that the two conduction paths of different wiring layers between the switching devices have an overlapping area in the projection direction, and the angle of the current direction in the overlapping area is greater than 90 degrees, that is, the magnetic fields generated by the currents of the two conduction paths are superimposed and offset each other, so that the stray inductances generated by the two conduction paths are also offset, and the generated induced voltage △V is reduced, thereby reducing the reverse peak, avoiding permanent damage to the switching device and improving the circuit life.

[0113] In addition, for the T-type layout, the first decoupling capacitor 317 and the second decoupling capacitor 318 are located between the first switching device 311, the fourth switching device 314 and the third switching device 313; one of the first bus capacitor 315 and the second bus capacitor 316 is located on the side of the first switching device 311 away from the fourth switching device 314, and the other of the first bus capacitor 315 and the second bus capacitor 316 is located on the side of the fourth switching device 314 away from the first switching device 311.

[0114] In this way, a first decoupling capacitor 317 is set between the first switching device 311 and the third switching device 313, and a second decoupling capacitor 318 is set between the fourth switching device 314 and the third switching device 313, so the commutation path through the first decoupling capacitor 317 and the commutation path through the second decoupling capacitor 318 are further shortened, thereby reducing the reverse peak.

[0115] As mentioned above, each switching device may include a single transistor or may include multiple transistors. In the case where each switching device includes multiple transistors, see Figure 7The second switch device 312 includes four second transistors, and the four second transistors are distributed in a trapezoidal shape; the third switch device 313 includes four third transistors, and the four third transistors are distributed in a 2×2 array; the first switch device 311 includes three first transistors, and the three first transistors are distributed in a triangular shape; the fourth switch device 314 includes three fourth transistors, and the three fourth transistors are distributed in a triangular shape (the specific shape of the triangle is not limited, such as a right triangle or an isosceles triangle); the first decoupling capacitor 317 and the second decoupling capacitor 318 are placed in the area surrounded by the first transistor at the top of the triangle, the fourth transistor at the top of the triangle, and the four third transistors.

[0116] In this way, the decoupling capacitor does not occupy additional area and can better reduce the reverse peak.

[0117] See also Fig.10 , providing a second layout of the T-type three-level bridge arm, the first switch device 311, the second switch device 312, the third switch device 313, and the fourth switch device 314 are arranged in a rectangular layout; the first switch device 311 and the fourth switch device 314 are arranged along the first direction, and the second switch device 312 and the third switch device 313 are arranged along the first direction; the first switch device 311 and the third switch device 313 are arranged along the second direction, and the second switch device 312 and the fourth switch device 314 are arranged along the second direction.

[0118] The first decoupling capacitor 317 and the second decoupling capacitor 318 are located between the first switching device 311 , the second switching device 312 , the third switching device 313 and the fourth switching device 314 .

[0119] It should be noted that the commutation path of the rectangular layout is shorter than that of the T-shaped layout, and the first decoupling capacitor 317 and the second decoupling capacitor 318 are also added, so the reverse peak is smaller.

[0120] See also Fig.11 , providing a third layout of the T-type three-level bridge arm, the first switch device 311, the second switch device 312, the third switch device 313, and the fourth switch device 314 are arranged in a diamond shape; the first switch device 311, the third switch device 313 and the fourth switch device 314 are arranged along the first direction, and the first switch device 311, the second switch device 312 and the fourth switch device 314 are arranged along the first direction; the third switch device 313 and the second switch device 312 are arranged along the second direction; the first decoupling capacitor 317 is located between the second switch device 312 and the third switch device 313, and is placed close to the first switch device 311; the second decoupling capacitor 318 is located between the second switch device 312 and the third switch device 313, and is placed close to the fourth switch device 314.

[0121] According to the second and third layouts described above, the core device area can be divided into a first core device area and a second core device area arranged adjacent to each other, and the plurality of switch devices constituting the multi-level circuit can be divided into positive half-cycle devices (corresponding to Fig.10 and Fig.11 The first switching device 311 and the second switching device 312 in the negative half cycle device (corresponding to Fig.10 and Fig.11 The fourth switch device 314 and the third switch device 313 in the circuit are configured to arrange the positive half-cycle device and the first decoupling capacitor in the first core device area, and arrange the negative half-cycle device and the second decoupling capacitor in the second core device area, so that the switch devices and decoupling capacitors that are closely related to each other are more closely arranged, thereby making the connection path between the switch devices and the decoupling capacitors shorter, which can further shorten the commutation path, reduce the inductance, and reduce the reverse peak.

[0122] Similarly, with the I-type three-level bridge arm (i.e. Fig. 9 Taking the structure shown in FIG. 1 as an example, several specific layouts are provided for your reference and understanding.

[0123] Please refer to Fig.12 The core device area is divided into a first core device area and a second core device area, wherein the first switch device 311, the second switch device 312 and the first diode 321 form a triangular layout in the first core device area, and the first decoupling capacitor 317 is arranged on the inner side of the triangular layout (first core device area), the fourth switch device 314, the third switch device 313 and the second diode 322 form a triangular layout in the second core device area, and the second decoupling capacitor 318 is arranged on the inner side of the triangular layout (second core device area), and the first core device area and the second core device area are mirror-symmetrical, wherein the fourth switch device 314 corresponds to the first switch device 311, the third switch device 313 corresponds to the second switch device 312, the second diode 322 corresponds to the first diode 321, and the first decoupling capacitor 317 corresponds to the second decoupling capacitor 318.

[0124] Furthermore, the first pin of the first decoupling capacitor 317 (i.e., the pin connected to the first diode 321) is toward the first diode 321, and the second pin of the first decoupling capacitor 317 (i.e., the pin connected to the first switching device 311) is toward the first switching device 311. Similarly, the second decoupling capacitor 318 and the first decoupling capacitor 317 are mirror-symmetrical. Then, the first pin of the second decoupling capacitor 318 (i.e., the pin connected to the second diode 322) is toward the second diode 322, and the second pin of the second decoupling capacitor 318 (i.e., the pin connected to the fourth switching device 314) is toward the fourth switching device 314.

[0125] In this way, a first decoupling capacitor 317 is provided between the first switch device 311 and the first diode 321, and a second decoupling capacitor 318 is provided between the fourth switch device 314 and the second diode 322, so that the commutation path through the first decoupling capacitor 317 and the commutation path through the second decoupling capacitor 318 are further shortened, thereby reducing the reverse peak. In addition, this layout is conducive to reducing electromagnetic interference and improving electromagnetic compatibility performance.

[0126] In addition to the core device area, a first bus capacitor 315 and a second bus capacitor 316 are provided. The bus capacitor can be formed by connecting multiple small capacitors in parallel, and the distribution position can be flexibly selected. Fig.12 As shown, in this embodiment, the first bus capacitor 315 and the second bus capacitor 316 can both include multiple electrolytic bus capacitors (small circles in the figure) and multiple thin film bus capacitors (small squares in the figure). The electrolytic bus capacitors and the thin film bus capacitors together constitute a capacitor component, which is arranged on one side of the core device area.

[0127] In the second specific layout embodiment, see Fig.13 Similarly, the core device area is divided into a first core device area and a second core device area, wherein the first switch device 311, the second switch device 312 and the second diode 322 form a triangular layout in the first core device area, and the first decoupling capacitor 317 is arranged on the inner side of the triangular layout (first core device area), and the fourth switch device 314, the third switch device 313 and the first diode 321 form a triangular layout in the second core device area, and the second decoupling capacitor 318 is arranged on the inner side of the triangular layout (second core device area), and the first core device area and the second core device area are mirror-symmetrical, wherein the fourth switch device 314 corresponds to the first switch device 311, the third switch device 313 corresponds to the second switch device 312, the second diode 322 corresponds to the first diode 321, and the first decoupling capacitor 317 corresponds to the second decoupling capacitor 318.

[0128] More specifically, the first pin of the first decoupling capacitor 317 (i.e., the pin connected to the second diode 322) is toward the second diode 322, and the second pin of the first decoupling capacitor 317 (i.e., the pin connected to the first switching device 311) is toward the first switching device 311. Similarly, the second decoupling capacitor 318 and the first decoupling capacitor 317 are mirror-symmetrical. Then, the first pin of the second decoupling capacitor 318 (i.e., the pin connected to the first diode 321) is toward the first diode 321, and the second pin of the second decoupling capacitor 318 (i.e., the pin connected to the fourth switching device 314) is toward the fourth switching device 314.

[0129] Under this layout, while inheriting the advantages of the capacitor component, the stress of the commutation loop is small, and it is easy to achieve an overlapping area in the projection direction of the two conduction paths of different wiring layers between the switching devices during PCB multilayer wiring, and the angle between the current directions in the overlapping area is greater than 90 degrees, that is, the magnetic fields generated by the currents of the two conduction paths superimpose and cancel each other, so that the stray inductances generated by the two conduction paths also cancel each other, the generated induced voltage △V is reduced, and thus the reverse peak is reduced, thereby avoiding permanent damage to the switching device and improving the circuit life.

[0130] In the third specific layout embodiment, see Fig.14 The first switch device 311, the second switch device 312 and the second diode 322 form an L-shaped layout in the first core device area, and the second switch device 312 is located at the corner of the L-shaped layout, the first decoupling capacitor 317 is arranged on the inner side of the L-shaped layout (first core device area), the fourth switch device 314, the third switch device 313 and the first diode 321 form an L-shaped layout in the second core device area, the second decoupling capacitor 318 is arranged on the inner side of the L-shaped layout (second core device area), and the first core device area and the second core device area are mirror-symmetrical, wherein the fourth switch device 314 corresponds to the first switch device 311, the third switch device 313 corresponds to the second switch device 312, the second diode 322 corresponds to the first diode 321, and the first decoupling capacitor 317 corresponds to the second decoupling capacitor 318.

[0131] More specifically, the first pin of the first decoupling capacitor 317 (i.e., the pin connected to the second diode 322) is toward the second diode 322, and the second pin of the first decoupling capacitor 317 (i.e., the pin connected to the first switching device 311) is toward the first switching device 311. Similarly, the second decoupling capacitor 318 and the first decoupling capacitor 317 are mirror-symmetrical. Then, the first pin of the second decoupling capacitor 318 (i.e., the pin connected to the first diode 321) is toward the first diode 321, and the second pin of the second decoupling capacitor 318 (i.e., the pin connected to the fourth switching device 314) is toward the fourth switching device 314.

[0132] Under this layout, the stress of the commutation loop is also small.

[0133] In the fourth specific layout embodiment, see Fig.15, the core device area is divided into a first core device area and a second core device area, wherein the first switch device 311, the second switch device 312 and the first diode 321 form an "I" type layout in the first core device area, and the first diode 321 is placed adjacent to the first switch device 311, and the first decoupling capacitor 317 is arranged between the first diode 321 and the first switch device 311, the fourth switch device 314, the third switch device 313 and the second diode 322 form an "I" type layout in the second core device area, and the second diode 322 is placed adjacent to the fourth switch device 314, and the second decoupling capacitor 318 is arranged between the second diode 322 and the fourth switch device 314, and the first core device area and the second core device area are mirror-symmetrical, wherein the fourth switch device 314 corresponds to the first switch device 311, the third switch device 313 corresponds to the second switch device 312, the second diode 322 corresponds to the first diode 321, and the first decoupling capacitor 317 corresponds to the second decoupling capacitor 318.

[0134] Similar to the first layout embodiment, the first pin of the first decoupling capacitor 317 (i.e., the pin connected to the first diode 321) is toward the first diode 321, and the second pin of the first decoupling capacitor 317 (i.e., the pin connected to the first switching device 311) is toward the first switching device 311. Similarly, the second decoupling capacitor 318 and the first decoupling capacitor 317 should be mirror-symmetrical. Then, the first pin of the second decoupling capacitor 318 (i.e., the pin connected to the second diode 322) is toward the second diode 322, and the second pin of the second decoupling capacitor 318 (i.e., the pin connected to the fourth switching device 314) is toward the fourth switching device 314.

[0135] In this layout embodiment, the advantages of shortening the commutation path and reducing the reverse peak are also met.

[0136] It should be noted that the above Figures 13 to 15 Only the layout of the core device area (i.e., the transformation bridge arm 31) is shown schematically, and the layout of the capacitor components can be as follows Fig.12 or Figure 6 The structure shown, Fig.12 and Figure 6 Only three core device areas are taken as an example. In other embodiments, more or fewer core device areas may be set, and there is no specific limitation on this.

[0137] In some embodiments, see Fig.16 , which shows a schematic diagram of the structure of a converter provided by an embodiment of the present application. Fig.16 As shown, the converter 400 includes the aforementioned capacitor component 100 , or the power component 300 .

[0138] Specifically, Fig.16As shown in (a) of FIG. 1 , the converter 400 includes the aforementioned capacitor component 100; Fig.16 As shown in (b) of FIG. 8 , the converter 400 includes the aforementioned power component 300 .

[0139] The converter 400 , because it includes the aforementioned capacitor component 100 or power component 300 , has at least the same advantages as the capacitor component 100 or the power component 300 .

[0140] The above are only preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. It should be noted that in the present application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or device including the element. The above serial numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present application can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided in the present application can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided in the present application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims

1. A capacitor component, characterized in that: The capacitor assembly includes a capacitor pool disposed on a printed circuit board and a terminal group and a transfer terminal respectively located on opposite sides of the capacitor pool; the terminal group includes a positive terminal, a neutral terminal and a negative terminal, the capacitor pool includes at least one positive capacitor array and at least one negative capacitor array, and the positive capacitor array and the negative capacitor array include a plurality of capacitors connected in parallel; The first ends of the multiple capacitors of the positive capacitor array and the positive terminal are both connected to the positive conduction path, the second ends of the multiple capacitors of the negative capacitor array and the negative terminal are both connected to the negative conduction path, the first conduction path includes the positive conduction path and / or the negative conduction path, the second ends of the multiple capacitors of the positive capacitor array, the first ends of the multiple capacitors of the negative capacitor array and the transfer end are all connected to the second conduction path, and the neutral terminal and the transfer end are both connected to the third conduction path, so that for the positive capacitor array, the commutation paths from the positive terminal to the neutral terminal after passing through each of the capacitors are of equal length, and for the negative capacitor array, the commutation paths from the negative terminal to the neutral terminal after passing through each of the capacitors are of equal length; The printed circuit board includes multiple wiring layers, and the second conductive path and the third conductive path are respectively located in different wiring layers.

2. The capacitor assembly according to claim 1, characterized in that: The positive conduction path, the second conduction path and the third conduction path are respectively located in different wiring layers, and the positive conduction path and the negative conduction path are located in the same wiring layer; The multi-layer wiring layer includes a first wiring layer, a second wiring layer and a third wiring layer, the first wiring layer includes a first wiring area and a second wiring area, the second wiring layer includes a third wiring area, and the third wiring layer includes a fourth wiring area; the positive terminal is electrically connected to the first wiring area, the negative terminal is electrically connected to the second wiring area, the transfer end is electrically connected to the third wiring area, and the transfer end and the neutral terminal are electrically connected to the fourth wiring area.

3. The capacitor assembly according to claim 2, characterized in that: A current carrying value corresponding to a minimum area among the areas of the first wiring region, the second wiring region, the third wiring region, and the fourth wiring region is a minimum current carrying value of the capacitor component.

4. The capacitor assembly according to claim 1, characterized in that: The multi-layer wiring layer further includes a fourth wiring layer and a fifth wiring layer; The third conduction path is located in the fourth wiring layer, and the second conduction path is located in the fifth wiring layer; the positive conduction path includes a first sub-path located in the fourth wiring layer and a second sub-path located in the fifth wiring layer, and the first sub-path and the second sub-path are connected in parallel; the negative conduction path includes a third sub-path located in the fourth wiring layer and a fourth sub-path located in the fifth wiring layer, and the third sub-path and the fourth sub-path are connected in parallel.

5. The capacitor assembly according to claim 4, characterized in that: The fourth wiring layer includes a fifth wiring area, a sixth wiring area and a seventh wiring area, and the fifth wiring layer includes an eighth wiring area, a ninth wiring area and a tenth wiring area; The positive terminal is electrically connected to the fifth wiring area and the eighth wiring area, the negative terminal is electrically connected to the seventh wiring area and the tenth wiring area, the transfer end is electrically connected to the ninth wiring area, and the transfer end and the neutral terminal are electrically connected to the sixth wiring area.

6. The capacitor assembly according to claim 5, characterized in that: In the fourth wiring layer, the fifth wiring area, the sixth wiring area and the seventh wiring area all extend along the first direction, and the fifth wiring area, the sixth wiring area and the seventh wiring area are sequentially arranged along the second direction; in the fifth wiring layer, the eighth wiring area, the ninth wiring area and the tenth wiring area all extend along the first direction, and the eighth wiring area, the ninth wiring area and the tenth wiring area are sequentially arranged along the second direction; The projections of the fifth wiring area and the eighth wiring area along the third direction overlap, the projections of the sixth wiring area and the ninth wiring area along the third direction overlap, and the projections of the seventh wiring area and the tenth wiring area along the third direction overlap; The plane where the first direction and the second direction are located is the plane where the printed circuit board is located, and the third direction is perpendicular to the plane where the printed circuit board is located.

7. The capacitor assembly according to claim 6, characterized in that: The current carrying value corresponding to the minimum area among the sum of the areas of the fifth wiring area and the eighth wiring area, the sum of the areas of the seventh wiring area and the tenth wiring area, the area of ​​the sixth wiring area, and the area of ​​the ninth wiring area is the minimum current carrying value of the capacitor component.

8. The capacitor assembly according to any one of claims 1 to 7, characterized in that: The positive terminal is the first end of the first capacitor in the positive capacitor array; the negative terminal is the second end of the first capacitor in the negative capacitor array; the transfer end is the second end of the last capacitor in the positive capacitor array, and / or the transfer end is the first end of the last capacitor in the negative capacitor array; The first capacitor and the last capacitor are two capacitors with the farthest distance in the positive capacitor array and / or the negative capacitor array.

9. A power component, characterized in that: The power component includes a power conversion circuit and a capacitor component according to any one of claims 1 to 8, and the power conversion circuit is connected to the capacitor component through the terminal group.

10. A converter, characterized in that: The converter comprises the capacitor component according to any one of claims 1 to 8, or comprises the power component according to claim 9.

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