High-integration-level carrier plate and manufacturing method thereof

Abstract

The invention discloses a high-integration carrier plate and a manufacturing method thereof, the carrier plate is used for a power module, the carrier plate comprises at least one hollow area, an inductance element is arranged in the hollow area, the inductance element comprises a magnetic core and a winding penetrating through the magnetic core, and the winding penetrates through the magnetic core. A side wall metal piece is arranged on at least one part of the side wall of the hollow area, at least one side wall metal piece is used for being electrically connected with an electrostatic potential end of the power supply module, and the inductance element is fixedly connected with the side wall of the hollow area through an insulated bonding medium layer. The inductance element is embedded in the printed circuit layer substrate, a smaller Vin-GND loop is achieved through wiring of the printed circuit layer substrate frame, and parasitic parameters are reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of high-frequency power supplies, and in particular relates to a highly integrated carrier board and a manufacturing method thereof. Background Art

[0002] With the increasing demand for various types of artificial intelligence and data processing, the global computing power consumption has exploded. Moreover, as the power consumption of these computing units is increasing and the size restrictions are becoming more and more stringent, higher and higher requirements are placed on the floor space, height, efficiency, heat dissipation, and electromagnetic interference of the energy processing units. The power supply that directly powers the computing chip usually uses Figure 1 The buck circuit shown includes magnetic components, capacitors, power chips, etc.

[0003] How to efficiently integrate these parts while meeting the system's numerous requirements for energy processing units, reduce conduction impedance, reduce module size, effectively reduce the loop inductance of the Vin-GND loop, and avoid interference from jump points such as SW to external signals is an urgent problem to be solved. Summary of the invention

[0004] In view of this, one of the purposes of the present invention is to provide a highly integrated carrier and a method for manufacturing the same, embedding the inductor element into the printed circuit layer substrate, utilizing the routing of the printed circuit layer substrate frame to achieve a smaller Vin-GND loop and reduce parasitic parameters.

[0005] To achieve the above-mentioned objectives, the first aspect of the present invention provides a highly integrated carrier board, which is used for a power module and includes at least one hollow area, in which an inductor element is arranged, and the inductor element includes a magnetic core and a winding passing through the magnetic core, and at least a portion of the side walls of the hollow area are provided with side wall metal parts, at least one of the side wall metal parts is used to be electrically connected to an electrostatic potential terminal of the power module, and the inductor element is fixedly connected to the side wall of the hollow area through an insulating adhesive medium layer.

[0006] Preferably, at least a portion of the outer side wall of the carrier is provided with a first outer metal piece corresponding to the position of the side wall metal piece, and the first outer metal piece and the corresponding side wall metal piece are respectively used for electrically connecting to electrically different terminals of the power module.

[0007] Preferably, at least a portion of the outer side wall of the carrier board is provided with a second outer side metal piece corresponding to the position of the side wall metal piece, and the second outer side metal piece is electrically connected to the corresponding side wall metal piece.

[0008] Preferably, the second outer metal member is disposed adjacent to at least one first outer metal member;

[0009] The second outer metal piece is electrically connected to the adjacent first outer metal piece, or the sidewall metal piece at a position corresponding to the second outer metal piece is electrically connected to the sidewall metal piece at a position corresponding to the adjacent first outer metal piece.

[0010] Preferably, the side wall metal pieces are arranged in an array and electrically alternately along the horizontal direction of the carrier board.

[0011] Preferably, a horizontal metal layer is provided in the region between the first outer metal piece and the sidewall metal piece at the corresponding position of the carrier board, and each of the horizontal metal layers is electrically connected to the first outer metal piece or the sidewall metal piece at the corresponding position.

[0012] Preferably, a plurality of the horizontal metal layers are provided, and are alternately electrically connected to the sidewall metal piece / the first outer metal piece.

[0013] Preferably, an insulating dielectric layer is further provided above or below at least one of the horizontal metal layers.

[0014] Preferably, at least a portion of the first outer metal member does not extend to at least one surface of the carrier board along the thickness direction of the carrier board.

[0015] Preferably, at least a portion of the side wall metal member does not extend to at least one surface of the carrier board along the thickness direction of the carrier board.

[0016] Preferably, it further comprises a signal electrical connector, which is arranged in the through hole, and the signal electrical connector and the winding are shielded from electromagnetic interference through the side wall metal piece.

[0017] Preferably, at least one surface of the carrier is provided with a wiring layer.

[0018] Preferably, the wiring layer includes insulating dielectric regions between wirings.

[0019] Preferably, a printed circuit board stack is provided on at least one surface of the carrier, and the printed circuit board stack is fixedly connected to the carrier via an insulating adhesive medium layer and is electrically connected to the carrier via a bonding material piece.

[0020] Preferably, the side walls of the carrier board and printed circuit board stack are provided with integrated outer metal parts.

[0021] Preferably, at least one of the printed circuit board stacks is provided with a stack hollow region, and the stack hollow region is used to arrange a power circuit component, and the power circuit component includes a capacitor.

[0022] Another aspect of the present invention discloses a method for manufacturing the carrier as described above, comprising the following steps:

[0023] S1: hollowing out the printed circuit layer substrate, and then copper plating the entire printed circuit layer substrate;

[0024] S2: Plating a protective layer on the entire printed circuit board substrate;

[0025] S3: Graphic definition, removing the protective layer of the designated area, the designated area includes at least a portion of the edge area, the edge area is the edge of the printed circuit layer substrate and / or the side wall edge formed by hollowing;

[0026] S4: etching to remove the copper in the designated area and make the copper plating on the sidewall of the edge area lower than the upper / lower surface of the printed circuit layer substrate;

[0027] S5: removing the remaining protective layer to form a carrier frame;

[0028] S6: Lamination, fixing the inductor and the carrier frame through an insulating adhesive dielectric layer.

[0029] Preferably, the horizontal segment width of the edge region is less than 200 μm, and the vertical segment width of the edge region is less than 200 μm.

[0030] Preferably, the horizontal segment width of the edge region is less than 100 μm, and the vertical segment width of the edge region is less than 100 μm.

[0031] The beneficial effects of the present invention are:

[0032] (1) The present invention embeds the inductor element into the printed circuit layer substrate and utilizes the inner wall, outer wall and internal wiring structure of the hollow area of ​​the printed circuit layer substrate to form a Vin-GND loop with a smaller loop area, thereby greatly reducing the parasitic inductance of the loop and optimizing the loop parameters;

[0033] (2) The highly integrated carrier board and optimized edge structure of the present invention can reduce the difficulty of external mainboard routing, improve wiring efficiency, reduce wiring impedance, and at the same time reduce the overall height of the power module, improve efficiency and reduce loss;

[0034] (3) The wiring structure of the inner wall of the hollow area of ​​the printed circuit layer substrate of the present invention can not only increase the flow and reduce the connection impedance, but also provide heat diffusion and improve heat dissipation;

[0035] (4) The present invention utilizes the inner wall, outer wall and internal wiring structure of the hollow area of ​​the printed circuit layer substrate to increase the rate of moisture diffusion into the substrate and improve the reliability of the module during use. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 It is a schematic diagram of the Buck circuit of the prior art;

[0038] FIG. 2A to FIG. 3D is a schematic diagram of Embodiment 1 of the present invention;

[0039] FIG. 4A to FIG. 4C Schematic diagram of the second embodiment of the present invention

[0040] FIG. 5A to FIG. 5D This is a schematic diagram of Embodiment 3 of the present invention;

[0041] FIG. 6A to FIG. 6G is a schematic diagram of a fourth embodiment of the present invention;

[0042] 7A to 8B is a schematic diagram of Embodiment 5 of the present invention;

[0043] FIG. 9A to FIG. 11 is a schematic diagram of Embodiment 6 of the present invention;

[0044] FIG. 12A to FIG. 13C is a schematic diagram of Embodiment 7 of the present invention;

[0045] FIG. 14A to FIG. 14D Schematic diagram of Embodiment 8 of the present invention

[0046] 1 printed circuit board substrate; 2 inductor element; 201 magnetic core; 202 winding; 3 side wall metal part; 4 bonding dielectric layer; 51 first outer metal part; 52 second outer metal part; 6 horizontal metal layer; 61 high dielectric constant insulating dielectric layer; 7 external main board; 8 protective layer; 9 through hole; 10 wiring layer; 11 insulating dielectric area; 12 blind hole; 13 printed circuit board stack; 14 bonding material part; 151 power device; 152 capacitor; 16 stack hollow area; 17 power circuit component; 18 metal guide column. DETAILED DESCRIPTION

[0047] One of the cores of the present invention is to provide a highly integrated carrier board and a manufacturing method thereof, embed the inductor element into the printed circuit layer substrate, and use the routing of the printed circuit layer substrate frame to achieve a smaller Vin-GND loop and reduce parasitic parameters.

[0048] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] Embodiment 1

[0050] The highly integrated carrier board disclosed in this embodiment is mainly used in a power module, such as FIG. 2A to FIG. 2C As shown, the carrier includes a printed circuit layer substrate 1 and at least one hollow area, an inductor element 2 is arranged in the hollow area, the inductor element 2 includes a magnetic core 201 and a winding 202 passing through the magnetic core, a first end of the winding 202 fans out from a first surface of the carrier, and a second end of the winding 202 fans out from a second surface of the carrier, at least a portion of the side wall of the hollow area is provided with a side wall metal part 3, at least one side wall metal part 3 is used to be electrically connected to an electrostatic potential terminal of a power module (such as a Vin terminal, a GND terminal, etc.), and the inductor element 2 is fixedly connected to the side wall of the hollow area through an insulating bonding medium layer 4.

[0051] At least a portion of the outer side wall of the printed circuit layer substrate 1 is provided with a first outer metal piece 51 corresponding to the position of the side wall metal piece 3. The first outer metal piece 51 and the corresponding side wall metal piece 3 are respectively used to electrically connect with terminals of the power module with different electrical properties, such as Figure 2A In the embodiment, a part of the side wall metal piece 3 is a GND electrical connection piece, another part is a Vin electrical connection piece, and the first outer metal piece 51 is opposite to the corresponding side wall metal piece 3; Figure 2B and Figure 2C ( Figure 2B In the stereoscopic diagram, the side wall metal parts 3 are all GND electrical connectors, and the first outer metal parts 51 are all Vin electrical connectors. The side frame of the hollowed-out printed circuit layer substrate 1 can be made as thin as possible to reduce the parasitic inductance of the Vin-GND loop (i.e., the input loop).

[0052] Figure 2D for Figure 2B A top view of Figure 2CAs shown, the other outer wall of the printed circuit layer substrate 1 is also provided with a second outer metal piece 52 corresponding to the position of the side wall metal piece 3, and the second outer metal piece 52 is electrically connected to the corresponding side wall metal piece 3. In this embodiment, the two are electrically connected through wiring on the upper surface of the carrier. Further, the second outer metal piece 52 and the first outer metal piece 51 of the outer walls on both sides are arranged adjacent to each other, and the corresponding side wall metal piece 3 is an integrated electrically connected whole, so that an input loop is formed between the inner / outer walls of the frame of the printed circuit board substrate 1, and an input loop is also formed on the outer wall, which can further reduce the parasitic inductance of the loop.

[0053] FIG. 3A to FIG. 3D A manufacturing process of this embodiment is shown, comprising the following steps:

[0054] S1: Hollow out the printed circuit layer substrate 1, then copper plate the entire board, and complete the graphic definition of the copper on the side wall of the hollow area, such as Figure 3A The carrier frame shown;

[0055] S2: The carrier frame and the inductor element 2 are fixedly connected through the insulating bonding medium layer 4, such as Figure 3B As shown;

[0056] S3: Flattening process, removing the excess bonding medium layer 4, such as Figure 3C As shown;

[0057] S4: After the pattern is defined, etching is performed to obtain Figure 3D Carrier board shown.

[0058] Embodiment 2

[0059] The difference between this embodiment and the first embodiment is that a plurality of first outer metal parts 51 or second outer metal parts 52 can be arranged on one side. Figure 4A and Figure 4B As shown, in this embodiment, the side wall metal piece 3 is an integral part on the side of the inductor element 2, and in some other embodiments, the side wall metal piece 3 can be electrically alternately arranged, and the corresponding second outer metal piece 52 is electrically connected to the adjacent first outer metal piece 51. The advantage of doing so is that the parasitic inductance of the loop can be further reduced. In another preferred embodiment, as Figure 4C As shown, the second outer metal piece 52 may not be provided, and the side wall metal piece 3 and the first outer metal piece 51 are electrically alternately provided on the inner / outer side walls to form a plurality of input loops that are in parallel with each other, thereby further reducing the parasitic inductance of the loop.

[0060] Embodiment 3

[0061] The difference between this embodiment and the first embodiment is that a horizontal metal layer 6 is provided in the area between the first outer metal member 51 and the side wall metal member 3 at the corresponding position of the printed circuit layer substrate 1, and each horizontal metal layer 6 is electrically connected to the first outer metal member 51 or the side wall metal member 3 at the corresponding position, such as Figure 5A As shown, since the interlayer spacing of the printed circuit layer substrate 1 is smaller than the width of the hollowed-out frame, the area of ​​the equivalent input loop can be made smaller, thereby further reducing the parasitic inductance of the loop.

[0062] In a preferred embodiment, if Figure 5B As shown, a plurality of horizontal metal layers 6 may be provided, and are alternately electrically connected to the sidewall metal member 3 or the first outer metal member 51 , which is equivalent to forming a plurality of parallel input loops.

[0063] In a preferred embodiment, if Figure 5C and Figure 5D As shown, a high dielectric constant insulating dielectric layer 61, such as a high dielectric constant insulating medium film, is also provided above or below at least one horizontal metal layer 6 to further reduce the loop inductance. Figure 5C All the spacing regions indicated by / D are provided with a high dielectric constant insulating dielectric layer 61 .

[0064] Embodiment 4

[0065] The difference between this embodiment and the first embodiment is that Fig. 6A and Figure 6B ( Fig. 6A As shown in the perspective view, the side wall metal member 3 of the left frame does not extend to the upper / lower surface of the carrier board along the thickness direction of the carrier board ( Fig. 6A The elliptical area on the left and Figure 6B The right elliptical area, that is, the side wall metal part 3 is lower than the bonding medium layer 4), the advantage of this is that the size of the carrier can be further reduced. Similarly, the first outer metal part 51 may not extend to the upper / lower surface of the carrier along the thickness direction of the carrier ( Fig. 6A The right elliptical area in the middle, that is, the first outer metal piece 51 is lower than the edge of the carrier), while further reducing the size of the carrier, can further reduce the difficulty of routing the external mainboard 7 (that is, the pads on the external mainboard 7 at the corresponding position do not need to avoid the position of the side wall metal piece 3 / the first outer metal piece 51 that does not extend to the surface), improve the wiring efficiency, reduce the wiring impedance, etc. Similarly, Figure 4A , 4B, 4C described embodiments, staggered arrangement of Vin / GND, etc., the frame / carrier sidewall metal can be set as needed, whether to extend to the upper / lower surface of the carrier. Optional, Fig. 6A The horizontally arranged staggered Vin / GND wiring layers can also be set up according to actual conditions.

[0066] FIG. 6C to FIG. 6G The method for manufacturing the sidewall structure of this embodiment is shown, comprising the following steps:

[0067] S1.1: hollow out the printed circuit layer substrate 1, and then copper plate the entire printed circuit layer substrate, such as Figure 6C As shown;

[0068] S1.2: Plate a protective layer on the entire printed circuit board 1, such as Fig.6D As shown;

[0069] S1.3: Graphic definition, remove the protective layer of the specified area, the specified area includes at least a portion of the edge area, the edge area is the edge of the printed circuit layer substrate and / or the side wall edge formed by the hollowing, and other areas on the carrier surface or side wall that need to be etched can also be removed in this step (the area to be etched on the carrier surface can also be etched again in subsequent steps), such as Fig. 6E As shown;

[0070] S1.4: Etch to remove copper in the designated area and make the copper plating on the sidewalls of the edge area lower than the upper / lower surface of the printed circuit layer substrate, such as Fig. 6F As shown;

[0071] S1.5: Remove the remaining protective layer to form a carrier frame, such as Figure 6G As shown;

[0072] S2: Lamination, the inductor element 2 and the carrier frame are fixedly connected through the insulating adhesive medium layer 4;

[0073] S3: Optionally, remove the excess bonding medium layer 4 through a planarization process.

[0074] By removing the graphic protection of the sidewall and etching the horizontal graphic simultaneously, the extremely small horizontal line spacing of the sidewall metal part 3 / the first outer metal part 51 / the second outer metal part 52 can be achieved. In a preferred embodiment, during etching, the horizontal segment of the etched edge area (i.e., the horizontal distance a between the copper on the upper / lower surface and the edge of the printed circuit layer substrate after etching) is less than 200μm in width, and the vertical segment (i.e., the vertical distance b between the copper on the sidewall and the edge of the printed circuit layer substrate after etching) is less than 200μm in width. Preferably, the horizontal segment width of the edge area is less than 100μm, and the vertical segment width of the edge area is less than 100μm, which can ensure mutual insulation of the copper plating of the horizontal segment and the vertical segment while making better use of the space.

[0075] Embodiment 5

[0076] The difference between this embodiment and the first embodiment is that 7A to 7C As shown, Figure 7B for Fig. 7AAA cross-section diagram, Figure 7C for Fig. 7A BB cross-sectional view, in this embodiment, the carrier is provided with a through hole 9 for forming an electrical connection channel for connecting the first side wiring and the second side wiring of the carrier. The through holes 9 can be arranged in a single row / multiple rows or on one side / multiple sides of the unit. Those skilled in the art can arrange them according to actual needs. The through holes 9 can be used to set electrical connection structures such as signal electrical connectors.

[0077] In this embodiment, between the through hole 9 and the winding 202, at least a part of the hollow area is provided with a side wall metal part 3, and the side wall metal part 3 is set to a static point, such as Vin, GND, etc., and the electromagnetic interference shielding is achieved between the signal electrical connector and the winding 202 through the side wall metal part 3, which can effectively avoid the interference to the signal caused by the SW point jump on the inductor.

[0078] The principle of signal shielding layer is as follows Figures 7D to 7E As shown, Fig.7D This is a common signal interference transmission path. There is a parasitic capacitor between the interference source 15 (such as a switching waveform) and the sampling circuit 16. The jump signal couples the interference current to the sampling circuit through the capacitor, thereby interfering with the sampling signal. Metallizing the sidewall of the hollow area and connecting the metal to a relatively stable potential, such as Vin, GND, Vout, VDD and other power or ground wires, can cut off the interference coupling path. Fig. 7E As shown, the interference of the internal interference source 15 of the cavity to the external signal is eliminated. The side wall metal part 3 can also shield the high-frequency loop, reduce the loop inductance, and reduce the interference of the carrier system to the outside.

[0079] In a preferred embodiment, if FIG. 8A to FIG. 8B As shown, Figure 8B for Fig. 8A BB cross-section diagram, Fig. 8A The AA cross-section diagram and Figure 7B Similarly, the side wall metal member 3 (such as Fig. 8A The dotted box shows the position and Figure 8B The position marked as the side wall metal part 3 in the figure is lower than the insulating bonding medium layer 4 to further reduce the size of the carrier board.

[0080] Embodiment 6

[0081] The difference between this embodiment and the first embodiment is that Fig.9A As shown, a wiring layer 10 is provided on at least one surface of the carrier. In a preferred embodiment, as Fig. 9B As shown, the wiring layer includes insulating dielectric regions 11 between wirings to further increase solder resistance.

[0082] In a preferred embodiment, as Fig. 10Aand Fig. 10B As shown, more wiring layers 10 can be laminated on the carrier board, and vertical electrical connection can be achieved through blind vias 12.

[0083] In a preferred embodiment, as Fig.11 As shown, the first outer metal member 51 can extend to the wiring layer 10 so as to form a Vin-GND overlap with the corresponding sidewall metal member 3 in the thickness direction ( Fig.11 The part shown in the ellipse area in the middle provides a better coupling effect of the input loop.

[0084] Embodiment 7

[0085] The difference between this embodiment and the first embodiment is that a printed circuit board laminate 13 is provided on at least one surface of the carrier. Fig. 12A and 12B As shown, the printed circuit board stack 13 is fixedly connected to the carrier through the insulating bonding medium layer 4, and is electrically connected to the carrier through the bonding material piece 14. Preferably, a through hole can be opened after the stacking, which is used for fan-out signal connectors. The material of the bonding medium layer 4 includes insulating dielectric materials such as prepreg (Pre-Preg) or ABF (Ajinomoto Build-up Film), and the material of the bonding material piece 14 includes solder, tin-silver alloy, tin-copper alloy, tin-silver-copper alloy, tin-antimony alloy, gold-tin alloy, high-lead solder, silver sintering slurry, copper sintering slurry, transient liquid phase sintering material or conductive slurry. Due to the effective constraint and protection of the insulating medium on the bonding material piece 14, the reliability of the bonding material piece 14 can be effectively improved. The manufacturing method of this embodiment is briefly described as follows:

[0086] S1: preparing a substrate and a printed circuit board stack 13 with a magnetic core embedded therein;

[0087] S2: a bonding medium layer 4 is provided on the surface of the substrate or printed circuit board laminate 13 with the magnetic core embedded therein, and semi-cured;

[0088] S3: opening a window on the bonding medium layer 4;

[0089] S4: placing a bonding material piece 14 at the window opening position and baking to remove the solvent. The bonding material piece 7 may be a silver sintered material, a copper sintered material, a transient liquid phase sintered material or a conductive paste, etc.;

[0090] S5: The substrate with the embedded magnetic core and the printed circuit board stack 13 are pressed together.

[0091] In a preferred embodiment, Fig. 12C As shown, the printed circuit board stack 13 can be fixedly connected to the carrier board by welding.

[0092] In a preferred embodiment, if FIG. 12D to FIG. 12FAs shown, the printed circuit board stack 13 and the side wall of the carrier are provided with an integrated first outer metal part 51 . Fig.12D and Fig.12E The upper surface of the carrier is provided with a printed circuit board stack 13. Fig.12F The upper and lower surfaces of the carrier are both provided with printed circuit board stacks 13, and Fig.12D and Fig.12E The fan-out form of the metal parts on the lower surface of the carrier board is different, and technicians in this field can set it according to needs.

[0093] In a preferred embodiment, if Fig.13A As shown, at least one printed circuit board stack 13 is provided with a stack hollow region 16, and the stack hollow region 16 is used to set a power circuit component 17, and the power circuit component 17 includes a capacitor. In some optimized embodiments, the opening direction of the stack hollow region 16 faces the carrier. In a preferred embodiment, as Fig. 13B and Fig. 13C As shown, the positions of the stacked hollow area 16 and the printed circuit layer substrate 1 can be aligned, and the bonding dielectric layer 4 can be omitted on the corresponding side surface of the inductor element 2. The pins with larger current flow can also be fanned out to the outside through metal guide pillars 18, such as copper pillars, etc. The side walls of the stacked hollow area 16 can be provided with side wall metal parts 3 ( Fig. 13C ), or not set ( Fig. 13B ).

[0094] Embodiment 8

[0095] This embodiment discloses the application scenarios of the carrier board of the above embodiment, such as FIG. 14A to FIG. 14D As shown, components such as power devices 151 and capacitors 152 are arranged on the upper surface of the carrier. Fig.14A Adopted Fig. 10B The carrier board shown, Fig. 14B Adopted Fig. 12A The carrier board shown, Fig. 14C Adopted Fig. 12C The carrier board shown, Fig.14D Adopted Fig. 12C In the case of a carrier board such as Figure 1 After the necessary components in the circuit shown are connected, the corresponding Buck circuit is formed. Since the metal parts on the inner / outer side walls of the frame can electrically connect the input end to the power device on the upper surface, the SW end of the power device 151 provides output current to the lower surface through the winding inside the magnetic core, it can be suitable for scenes such as ultra-thin vertical power supply modules. Optionally, plastic packaging can be used to protect the components mounted on the surface of the carrier.

[0096] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0097] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A highly integrated carrier board, the carrier board is used for a power module, characterized in that: It includes at least one hollow area, in which an inductor element is arranged, and the inductor element includes a magnetic core and a winding passing through the magnetic core. At least a part of the side wall of the hollow area is provided with a side wall metal part, at least one of the side wall metal parts is used to be electrically connected to an electrostatic potential terminal of the power module, and the inductor element is fixedly connected to the side wall of the hollow area through an insulating bonding medium layer.

2. The carrier board according to claim 1, characterized in that: At least a portion of the outer side wall of the carrier is provided with a first outer metal piece corresponding to the position of the side wall metal piece, and the first outer metal piece and the corresponding side wall metal piece are respectively used to electrically connect to terminals of the power module with different electrical properties.

3. The carrier board according to claim 2, characterized in that: At least a portion of the outer side wall of the carrier is provided with a second outer side metal piece corresponding to the position of the side wall metal piece, and the second outer side metal piece is electrically connected to the corresponding side wall metal piece.

4. The carrier board according to claim 3, characterized in that: The second outer metal member is disposed adjacent to at least one first outer metal member; The second outer metal piece is electrically connected to the adjacent first outer metal piece, or the sidewall metal piece at a position corresponding to the second outer metal piece is electrically connected to the sidewall metal piece at a position corresponding to the adjacent first outer metal piece.

5. The carrier board according to claim 2, characterized in that: The side wall metal pieces are arranged in an array along the horizontal direction of the carrier board and are electrically alternately arranged.

6. The carrier board according to claim 2, characterized in that: The carrier board is provided with a horizontal metal layer in the area between the first outer metal piece and the sidewall metal piece at the corresponding position, and each of the horizontal metal layers is electrically connected to the first outer metal piece or the sidewall metal piece at the corresponding position.

7. The carrier board according to claim 6, characterized in that: A plurality of horizontal metal layers are provided, and are alternately electrically connected to the sidewall metal piece / the first outer metal piece.

8. The carrier board according to claim 6, characterized in that: An insulating dielectric layer is also disposed above or below at least one of the horizontal metal layers.

9. The carrier board according to claim 2, characterized in that: At least a portion of the first outer metal member does not extend to at least one surface of the carrier board along the thickness direction of the carrier board.

10. The carrier board according to claim 1, characterized in that: At least a portion of the side wall metal piece does not extend to at least one surface of the carrier board along the thickness direction of the carrier board.

11. The carrier board according to claim 1, characterized in that: It also includes a signal electrical connector, which is arranged in the through hole, and the signal electrical connector and the winding are shielded from electromagnetic interference through the side wall metal part.

12. The carrier board according to claim 1, characterized in that: At least one surface of the carrier is provided with a wiring layer.

13. The carrier board according to claim 12, characterized in that: The wiring layer includes insulating dielectric regions between wirings.

14. The carrier board according to claim 1, characterized in that: A printed circuit board stack is arranged on at least one surface of the carrier board. The printed circuit board stack is fixedly connected to the carrier board through an insulating bonding medium layer and is electrically connected to the carrier board through a bonding material piece.

15. The carrier board according to claim 14, characterized in that: The side walls of the carrier board and the printed circuit board stack are provided with integrated outer metal parts.

16. The carrier board according to claim 14, characterized in that: At least one of the printed circuit board stacks is provided with a stack hollow region, and the stack hollow region is used to set a power circuit component, and the power circuit component includes a capacitor.

17. A method for manufacturing a carrier board according to claim 9 or 10, characterized in that: The steps include: S1: hollowing out the printed circuit layer substrate, and then copper plating the entire printed circuit layer substrate; S2: Plating a protective layer on the entire printed circuit board substrate; S3: Graphic definition, removing the protective layer of the designated area, the designated area includes at least a portion of the edge area, the edge area is the edge of the printed circuit layer substrate and / or the side wall edge formed by hollowing; S4: etching to remove the copper in the designated area and make the copper plating on the sidewall of the edge area lower than the upper / lower surface of the printed circuit layer substrate; S5: removing the remaining protective layer to form a carrier frame; S6: Lamination, fixing the inductor and the carrier frame through an insulating adhesive dielectric layer.

18. The manufacturing method according to claim 17, characterized in that: The horizontal segment width of the edge region is less than 200 μm, and the vertical segment width of the edge region is less than 200 μm.

19. The manufacturing method according to claim 18, characterized in that: The horizontal segment width of the edge region is less than 100 μm, and the vertical segment width of the edge region is less than 100 μm.

Images