Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device based on a BJT structure and a manufacturing method of the semiconductor device, and the semiconductor device can reduce the beta gain of a parasitic transistor in the device, improves the breakdown voltage between a collector electrode C and an emitter electrode E, maintains the breakdown voltage between the emitter electrode E and a base electrode B as much as possible, and improves the reliability of the device. And the breakdown voltage between the collector C and the base B is not changed, so that the circuit performance is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a semiconductor device with a BJT structure and a method for manufacturing the semiconductor device. Background Art

[0002] In the existing BJT structure semiconductor devices, there is a high Gummel lateral parasitic NPN structure, refer to Figure 1 As shown, Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor device with an existing BJT structure. Figure 1 The NPN transistor 100 in the figure is a lateral parasitic NPN structure in the device. The β gain of the lateral parasitic NPN transistor 100 is particularly large, which affects the performance of the device.

[0003] In the prior art, the current of the base can be increased by surrounding a highly doped wide P-type ring, thereby reducing the parasitic gain. However, this method requires occupying additional device area, so when it is desired to save device area, this method is not desirable.

[0004] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide a semiconductor device based on a BJT structure and a method for manufacturing the semiconductor device, which can reduce the β gain of the parasitic transistor in the device, increase the breakdown voltage between the collector C and the emitter E, and keep the breakdown voltage between the emitter E and the base B, and the breakdown voltage between the collector C and the base B unchanged as much as possible, thereby improving circuit performance.

[0006] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:

[0007] A semiconductor device, comprising:

[0008] A semiconductor body including a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having a first doping type disposed on the buried layer;

[0009] a first trench extending from the top surface of the epitaxial layer into the buried layer, wherein a first conductive material having a second doping type is disposed in the first trench, and the first conductive material electrically connects the buried layer to the top surface of the epitaxial layer;

[0010] A first drift region, disposed in the epitaxial layer and located within a range surrounded by the first trench, wherein the first drift region has a second doping type;

[0011] A first well region, disposed in the epitaxial layer and between the first trench and the first drift region, the first well region having a first doping type, a second doping type or a non-doping type;

[0012] A second well region, disposed in the epitaxial layer and below the first well region, the second well region having a second doping type;

[0013] a third well region, disposed in the epitaxial layer, the third well region comprising a first third sub-well region inserted between the first well region and the first trench, and a second third sub-well region inserted between the first well region and the first drift region, the third well region having a first doping type;

[0014] in,

[0015] When the first well region has a second doping type, the doping concentration of the second well region is greater than the doping concentration of the first well region;

[0016] When the first well region has a first doping type, the doping concentration of the third well region is greater than the doping concentration of the first well region.

[0017] In one or more embodiments of the present invention, the sum of the depths of the first well region and the second well region is greater than the depth of the third well region; and / or,

[0018] The depth of the first well region is equal to the depth of the third well region; and / or,

[0019] The depth of the second well region is smaller than the depth of the third well region.

[0020] In one or more embodiments of the present invention, the first third sub-well region and the second third sub-well region are respectively disposed adjacent to the first well region, and the second well region is disposed adjacent to the first well region.

[0021] In one or more embodiments of the present invention, the first well region has a first area where the second well region has a second area where the third well region has a third area where the third well region has a third area where the first well region has a second area where the second ... second area where the third well region has a third area where

[0022] By performing ion implantation of a first doping type in the first region and the third region, a third well region is formed in the third region, and the first region has the first doping type; by performing ion implantation of a second doping type in the first region and the second region, the first region having the first doping type is counter-doped, and a first well region is formed in the first region, and at the same time, a second well region is formed in the second region; or,

[0023] By performing ion implantation of the second doping type in the first region and the second region, a second well region is formed in the second region, and the first region has the second doping type. By performing ion implantation of the first doping type in the first region and the third region, the first region having the second doping type is counter-doped to form a first well region in the first region. At the same time, a third well region is formed in the third region.

[0024] In one or more embodiments of the present invention, the semiconductor device further includes a first isolation structure, which is disposed between the first trench and the third well region, and the first isolation structure extends from a top surface of the epitaxial layer into the buried layer.

[0025] In one or more embodiments of the present invention, the semiconductor device also includes a second isolation structure, which is arranged between the third well region and the first drift region, and the second isolation structure extends from the top surface of the epitaxial layer into the epitaxial layer and has a preset distance from the buried layer.

[0026] In one or more embodiments of the present invention, the first well region includes a plurality of first well region units disposed at intervals, the second well region includes a plurality of second well region units disposed at intervals, and the plurality of first well region units and the plurality of second well region units are disposed in one-to-one correspondence.

[0027] In one or more embodiments of the present invention, the third well region includes a third third sub-well region unit inserted between adjacent first well region units and adjacent second well region units, and the third third sub-well region unit is adjacent to the first third sub-well region and the second third sub-well region respectively.

[0028] In one or more embodiments of the present invention, the second and third sub-well regions include a plurality of second and third sub-well region units that are spaced apart from each other, and adjacent second and third sub-well region units are separated by the epitaxial layer.

[0029] The first trench and the third well region, and the third well region and the first drift region are separated by the epitaxial layer.

[0030] A method for manufacturing a semiconductor device, comprising:

[0031] Providing a semiconductor body, the semiconductor body comprising a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having a first doping type disposed on the buried layer;

[0032] forming a first trench in the semiconductor body, the first trench extending from the top surface of the epitaxial layer into the buried layer, a first conductive material having a second doping type disposed in the first trench, the first conductive material electrically connecting the buried layer to the top surface of the epitaxial layer;

[0033] forming a first drift region having a second doping type and a first doping region having a first doping type in the semiconductor body, wherein the first drift region is disposed in the epitaxial layer and is located within a range surrounded by the first trench, and the first doping region is disposed in the epitaxial layer and is located between the first trench and the first drift region;

[0034] A portion of the first doped region is counter-doped with a second doping type to form a second well region below the first doped region, a first well region is formed in the first doped region, and a portion of the first doped region that is not counter-doped forms a third well region.

[0035] A semiconductor device, comprising:

[0036] A semiconductor body including a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having a first doping type disposed on the buried layer;

[0037] a first trench extending from the top surface of the epitaxial layer into the buried layer, wherein a first conductive material having a second doping type is disposed in the first trench, and the first conductive material electrically connects the buried layer to the top surface of the epitaxial layer;

[0038] A first drift region, disposed in the epitaxial layer and located within a range surrounded by the first trench, wherein the first drift region has a second doping type;

[0039] a fourth well region, disposed in the epitaxial layer and between the first trench and the first drift region, the fourth well region having a second doping type, and comprising a plurality of fourth well region units disposed at intervals;

[0040] A third well region is arranged in the epitaxial layer, and the third well region includes a first third sub-well region inserted between the fourth well region and the first trench, a second third sub-well region inserted between the fourth well region and the first drift region, and a third third sub-well region unit inserted between adjacent fourth well region units, the third third sub-well region unit is respectively adjacent to the first third sub-well region and the second third sub-well region, and the third well region has a first doping type.

[0041] In one or more embodiments of the present invention, the depth of the fourth well region is greater than the depth of the third well region.

[0042] In one or more embodiments of the present invention, the semiconductor device further includes a first isolation structure, which is disposed between the first trench and the third well region, and the first isolation structure extends from a top surface of the epitaxial layer into the buried layer.

[0043] In one or more embodiments of the present invention, the semiconductor device also includes a second isolation structure, which is arranged between the third well region and the first drift region, and the second isolation structure extends from the top surface of the epitaxial layer into the epitaxial layer and has a preset distance from the buried layer.

[0044] In one or more embodiments of the present invention, the second and third sub-well regions include a plurality of second and third sub-well region units that are spaced apart from each other, and adjacent second and third sub-well region units are separated by the epitaxial layer.

[0045] A semiconductor device, comprising:

[0046] A semiconductor body including a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having a first doping type disposed on the buried layer;

[0047] a first trench extending from the top surface of the epitaxial layer into the buried layer, wherein a first conductive material having a second doping type is disposed in the first trench, and the first conductive material electrically connects the buried layer to the top surface of the epitaxial layer;

[0048] A first drift region, disposed in the epitaxial layer and located within a range surrounded by the first trench, wherein the first drift region has a second doping type;

[0049] a fourth well region, disposed in the epitaxial layer and between the first trench and the first drift region, the fourth well region having a second doping type;

[0050] a third well region, disposed in the epitaxial layer, the third well region comprising a first third sub-well region inserted between the fourth well region and the first trench, and a second third sub-well region inserted between the fourth well region and the first drift region, the third well region having a first doping type;

[0051] A first isolation structure is disposed between the first trench and the third well region, and the first isolation structure extends from a top surface of the epitaxial layer into the buried layer.

[0052] In one or more embodiments of the present invention, the semiconductor device also includes a second isolation structure, which is arranged between the third well region and the first drift region, and the second isolation structure extends from the top surface of the epitaxial layer into the epitaxial layer and has a preset distance from the buried layer.

[0053] In one or more embodiments of the present invention, the second and third sub-well regions include a plurality of second and third sub-well region units that are spaced apart from each other, and adjacent second and third sub-well region units are separated by the epitaxial layer.

[0054] Compared with the prior art, the semiconductor device and the method for manufacturing the semiconductor device of the present invention can reduce the β gain of the parasitic transistor in the device, increase the breakdown voltage between the collector C and the emitter E, and keep the breakdown voltage between the emitter E and the base B, and the breakdown voltage between the collector C and the base B unchanged as much as possible, thereby improving circuit performance.

[0055] The semiconductor device and the method for manufacturing the semiconductor device of the present invention are compatible with the existing MTI / DTI basic process, do not increase the additional mask cost, reduce the parasitic NPN transistor gain of the semiconductor device with a BJT structure, and improve the circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0057] Figure 1 It is a cross-sectional schematic diagram of a semiconductor device based on a BJT structure according to an embodiment of the prior art;

[0058] Figure 2 is a cross-sectional schematic diagram of a semiconductor device based on a BJT structure according to an embodiment;

[0059] Figure 3is a cross-sectional schematic diagram of a semiconductor device based on a BJT structure in Example 1;

[0060] Figure 4 is a top view of a semiconductor device based on a BJT structure in Example 1;

[0061] Figure 5 is a cross-sectional schematic diagram of a semiconductor device based on a BJT structure in Example 2;

[0062] Figure 6 is a top view of a semiconductor device based on a BJT structure in Example 2;

[0063] Figure 7 is a top view of a semiconductor device based on a BJT structure in Example 3;

[0064] Figure 8 is a top view of a semiconductor device based on a BJT structure in Example 4;

[0065] Fig. 9 is a top view of a semiconductor device based on a BJT structure in Example 5;

[0066] Fig.10 is a top view of a semiconductor device based on a BJT structure in Example 6;

[0067] Fig.11 is a top view of a semiconductor device based on a BJT structure in Example 7;

[0068] Fig.12 is a cross-sectional schematic diagram of a semiconductor device based on a BJT structure in Example 7;

[0069] Fig.13 is a top view of a semiconductor device based on a BJT structure in Example 8;

[0070] Fig.14 is a cross-sectional schematic diagram of a semiconductor device based on a BJT structure in Example 8;

[0071] Fig.15 is a top view of a semiconductor device based on a BJT structure in Example 9;

[0072] Fig.16 is a top view of a semiconductor device based on a BJT structure in Example 10;

[0073] Fig.17 It is a top view of the semiconductor device based on the BJT structure in Example 11. DETAILED DESCRIPTION

[0074] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0075] As mentioned in the background art, in order to solve the problem of high Gummel lateral parasitic NPN transistor 100 in BJT structure semiconductor devices, a highly doped wide P-type ring is provided to increase the base current, but this method requires occupying additional device area.

[0076] Therefore, how to solve the high Gummel problem of the lateral parasitic NPN structure in the semiconductor device with BJT structure while keeping the device area unchanged is a question worth considering.

[0077] The study found that by adding an embedded N-type doped region in the P-type well and shorting both to the base metal connection, a new lateral parasitic NPN transistor 200 can be formed between the device emitter E and the base B, thereby increasing the total current of the base B of the original lateral parasitic NPN transistor 100 and reducing Gummel. Figure 2 As shown, Figure 2 is a schematic cross-sectional structure diagram of a semiconductor device with a BJT structure in one embodiment, Figure 2 The NPN transistor 200 is another lateral parasitic NPN structure newly added in the device.

[0078] Therefore, by adding an embedded N-type doped region in the P-type well, a new lateral parasitic NPN structure is constructed between the emitter E and the base B, which can greatly improve the breakdown voltage between the collector C and the emitter E.

[0079] However, this method brings benefits as well as great drawbacks. This method will reduce the breakdown voltage between the emitter E and the base B, roughly from a maximum of 80V to 30V; at the same time, it will also reduce the breakdown voltage between the collector C and the base B, roughly from a maximum of 100V to 50V, resulting in an imbalance in the overall performance of the device.

[0080] Therefore, in order to solve the high Gummel problem of the lateral parasitic NPN structure in the semiconductor device with BJT structure while keeping the device area unchanged and the overall performance of the device balanced and stable, the present invention provides a semiconductor device based on BJT structure and a method for manufacturing the semiconductor device, which can reduce the β gain of the parasitic transistor in the device, increase the breakdown voltage between the collector C and the emitter E, and keep the breakdown voltage between the emitter E and the base B, and the breakdown voltage between the collector C and the base B unchanged as much as possible, thereby improving the circuit performance.

[0081] The semiconductor device of the present invention comprises a semiconductor body, a first trench, a first drift region, a first well region, a second well region and a third well region.

[0082] The semiconductor body includes a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having the first doping type disposed on the buried layer. The first doping type may be P-type, and the second doping type may be N-type. Alternatively, the first doping type is N-type, and the second doping type is P-type.

[0083] The first trench extends from the top surface of the epitaxial layer to the buried layer. A first conductive material having a second doping type is disposed in the first trench. The first conductive material electrically connects the buried layer to the top surface of the epitaxial layer. Since the first conductive material is connected to the buried layer, the first conductive material can be used as a collector C of the semiconductor device. The first trench is arranged in an annular shape, and the first trench is the device region.

[0084] The first drift region is arranged in the epitaxial layer and is located within the range surrounded by the first trench. A separation space is formed between the first drift region and the first trench. The first drift region has a second doping type. The first drift region can be used as an emitter E of the semiconductor device.

[0085] The first well region is arranged in the epitaxial layer and is located in the interval space between the first trench and the first drift region. The first well region has a first doping type, a second doping type or a non-doping type, and the first well region is also arranged in a ring shape.

[0086] The second well region is arranged in the epitaxial layer and is located below the first well region. The second well region is arranged adjacent to the first well region and has a second doping type. The second well region is also arranged in an annular shape. The depth of the second well region is less than the depth of the first well region.

[0087] The third well region is arranged in the epitaxial layer, and the third well region includes a first third sub-well region inserted between the first well region and the first trench, and a second third sub-well region inserted between the first well region and the first drift region, and the first third sub-well region and the second third sub-well region are respectively arranged adjacent to the first well region. The third well region is also arranged in a ring shape. The third well region has a first doping type. The third well region can be used as a base B of the semiconductor device. The depth of the third well region is less than the sum of the depths of the first well region and the second well region, and the depth of the third well region is equal to the depth of the first well region.

[0088] When the first well region has the second doping type, the doping concentration of the second well region is greater than the doping concentration of the first well region; when the first well region has the first doping type, the doping concentration of the third well region is greater than the doping concentration of the first well region.

[0089] In the above technical solution, the first well region, the second well region and the third well region can be formed in the following manner. Specifically, the first well region has a first region, the second well region has a second region, the third well region has a third region, and the sum of the third region and the first region is the first doping region. First, by performing ion implantation of the first doping type in the first region and the third region (the first doping region), the third well region is formed in the third region, and the first region has the first doping type; then, by performing ion implantation of the second doping type in the first region and the second region, the first region with the first doping type is counter-doped, and the first well region is formed in the first region, and at the same time, the second well region is formed in the second region. Alternatively, by performing ion implantation of the second doping type in the first region and the second region, the second well region is formed in the second region, and the first region has the second doping type; then, by performing ion implantation of the first doping type in the first region and the third region (the first doping region), the first region with the second doping type is counter-doped, and the first well region is formed in the first region, and at the same time, the third well region is formed in the third region.

[0090] It can be understood that the above technical solution is based on the existing MTI / DTI (mid trench isolation / deep trench isolation) basic process, first forming a first doping region of the first doping type, and then doping the second doping type in the region, the doping of the second doping type partially overlaps with the original first doping type region in the lateral direction, and the doping depth of the second doping type in the prior art is deeper than that of the first doping type, so there is still a partial region with the second doping type at the bottom of the base - the second well region 42, but the upper part of the base will be counter-doped by the first doping type, thereby forming the first well region 41.

[0091] The doping type of the first region is balanced by controlling the ion implantation dose of the first doping type and the ion implantation dose of the second doping type, so that the first well region presents a weakly doped second doping type or a weakly doped first doping type or a non-doped type.

[0092] It is understandable that the methods of forming the first trench in the semiconductor body and performing ion implantation on the semiconductor body are both existing processes, and the present invention will not describe them in detail.

[0093] In the above technical solution, there is no specific requirement for the doping type of the first well region. It is only required that the second well region presents a doping type different from that of the third well region, and the second well region slightly protrudes from the lower surface of the third well region (the side surface away from the top surface of the epitaxial layer).

[0094] The second well region is set to form a new lateral parasitic NPN (based on the first doping type being P type and the second doping type being N type) or PNP (based on the first doping type being N type and the second doping type being P type) in the semiconductor device. The effect of the newly generated lateral parasitic NPN or PNP is similar to Figure 2 Like the LNPN transistor 200 shown in the figure, current is provided to the base region of the original lateral parasitic transistor, thereby reducing the β gain of the original lateral parasitic transistor in the device and increasing the breakdown voltage between the collector C and the emitter E. At the same time, since the second well region is not formed by completely penetrating the third well region, the current provided to the base region of the original lateral parasitic transistor is relatively small, and while reducing the β gain, it will not have a significant adverse effect on the breakdown voltage between the emitter E and the base B, and the breakdown voltage between the collector C and the base B of the semiconductor device.

[0095] In a preferred embodiment, the semiconductor device may further include a first isolation structure. The first isolation structure is disposed between the first trench and the third well region. The first isolation structure extends from the top surface of the epitaxial layer into the buried layer. The width of the first isolation structure ranges from 0.5 μm to 0.7 μm, and the depth ranges from 13 μm to 18 μm. The first isolation structure is formed by sidewall thermal oxidation and / or oxide deposition.

[0096] The semiconductor device also includes a second isolation structure. The second isolation structure is arranged between the third well region and the first drift region. The second isolation structure extends from the top surface of the epitaxial layer into the epitaxial layer and has a preset distance from the buried layer. The width of the second isolation structure ranges from 0.35 μm to 0.5 μm, and the depth ranges from 0.4 μm to 13 μm. The second isolation structure is formed by sidewall thermal oxidation and / or oxide deposition.

[0097] In the above technical solution, the provision of the first isolation structure can improve the breakdown voltage between the collector C and the base B. The provision of the second isolation structure can improve the breakdown voltage between the emitter E and the base B.

[0098] In another preferred embodiment, the first well region includes a plurality of first well region units arranged at intervals, and the plurality of first well region units are arranged in a ring. The second well region includes a plurality of second well region units arranged at intervals, and the plurality of second well region units are arranged in a ring. The plurality of first well region units are arranged one-to-one with the plurality of second well region units. The third well region also includes a third third sub-well region unit inserted between adjacent first well region units and between adjacent second well region units, and the third third sub-well region unit is adjacent to the first third sub-well region and the second third sub-well region, respectively. The third third sub-well region unit is adjacent to the adjacent first well region unit and the second well region unit, respectively.

[0099] By changing the area occupied by the second well region in the device region, the influence on the breakdown voltage between the emitter E and the base B and the breakdown voltage between the collector C and the base B can be further reduced.

[0100] In the above-mentioned embodiment, the semiconductor device may also include a first isolation structure and / or a second isolation structure. The first isolation structure is arranged between the first trench and the third well region. The second isolation structure is arranged between the third well region and the first drift region.

[0101] In another preferred embodiment, the second and third sub-well regions include a plurality of second and third sub-well region units disposed at intervals, the plurality of second and third sub-well region units are arranged in a ring shape, and adjacent second and third sub-well region units are separated by an epitaxial layer.

[0102] In addition, the present invention further provides a semiconductor device, including a semiconductor body, a first trench, a first drift region, a fourth well region and a third well region.

[0103] The semiconductor body includes a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having the first doping type disposed on the buried layer. The first doping type may be P-type, and the second doping type may be N-type. Alternatively, the first doping type is N-type, and the second doping type is P-type.

[0104] The first trench extends from the top surface of the epitaxial layer to the buried layer. A first conductive material having a second doping type is disposed in the first trench. The first conductive material electrically connects the buried layer to the top surface of the epitaxial layer. Since the first conductive material is connected to the buried layer, the first conductive material can be used as a collector C of the semiconductor device. The first trench is arranged in an annular shape, and the first trench is the device region.

[0105] The first drift region is arranged in the epitaxial layer and is located within the range surrounded by the first trench. A separation space is formed between the first drift region and the first trench. The first drift region has a second doping type; the first drift region can be used as an emitter E of the semiconductor device.

[0106] The fourth well region is arranged in the epitaxial layer and between the first trench and the first drift region. The fourth well region has the second doping type and includes a plurality of fourth well region units arranged at intervals. The plurality of fourth well region units are arranged in a ring shape.

[0107] The third well region is arranged in the epitaxial layer, and the third well region includes a first third sub-well region inserted between the fourth well region and the first trench, a second third sub-well region inserted between the fourth well region and the first drift region, and a third third sub-well region unit inserted between adjacent fourth well region units, and the third third sub-well region unit is adjacent to the first third sub-well region and the second third sub-well region respectively. The depth of the third well region is less than the depth of the fourth well region. The third well region has a first doping type.

[0108] In the above technical solution, the breakdown voltage between the emitter E and the base B of the semiconductor device and the breakdown voltage between the collector C and the base B are kept unchanged by setting the intervals of the fourth well region units.

[0109] In a preferred embodiment, the semiconductor device may further include a first isolation structure, which is disposed between the first trench and the third well region. The first isolation structure extends from the top surface of the epitaxial layer into the buried layer. The width of the first isolation structure ranges from 0.5 μm to 0.7 μm, and the depth ranges from 13 μm to 18 μm. The first isolation structure is formed by sidewall thermal oxidation and / or oxide deposition.

[0110] The semiconductor device may further include a second isolation structure, the second isolation structure being disposed between the third well region and the first drift region, the second isolation structure extending from the top surface of the epitaxial layer into the epitaxial layer and having a preset distance from the buried layer. The second isolation structure has a width ranging from 0.35 μm to 0.5 μm and a depth ranging from 0.4 μm to 13 μm. The second isolation structure is formed by sidewall thermal oxidation and / or oxide deposition.

[0111] In another preferred embodiment, the second and third sub-well regions include a plurality of second and third sub-well region units disposed at intervals, the plurality of second and third sub-well region units are arranged in a ring shape, and adjacent second and third sub-well region units are separated by an epitaxial layer.

[0112] In the above technical scheme, the punch-through breakdown path of the emitter E and the base B can be narrowed by setting the spacing between the second and third sub-well area units, and the width of the spacing area between adjacent second and third sub-well area units can be adjusted, thereby reducing the β gain without causing a significant adverse effect on the breakdown voltage between the emitter E and the base B, and the breakdown voltage between the collector C and the base B of the semiconductor device.

[0113] Furthermore, the present invention provides a semiconductor device, including a semiconductor body, a first trench, a first drift region, a fourth well region, a third well region and a first isolation structure.

[0114] The semiconductor body includes a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having the first doping type disposed on the buried layer. The first doping type may be P-type, and the second doping type may be N-type. Alternatively, the first doping type is N-type, and the second doping type is P-type.

[0115] The first trench extends from the top surface of the epitaxial layer to the buried layer. A first conductive material having a second doping type is disposed in the first trench. The first conductive material electrically connects the buried layer to the top surface of the epitaxial layer. Since the first conductive material is connected to the buried layer, the first conductive material can be used as a collector C of the semiconductor device. The first trench is arranged in an annular shape, and the first trench is the device region.

[0116] The first drift region is arranged in the epitaxial layer and is located within the range surrounded by the first trench. A separation space is formed between the first drift region and the first trench. The first drift region has a second doping type; the first drift region can be used as an emitter E of the semiconductor device.

[0117] The fourth well region is disposed in the epitaxial layer and between the first trench and the first drift region, and the fourth well region has the second doping type.

[0118] The third well region is disposed in the epitaxial layer, the third well region includes a first third sub-well region inserted between the fourth well region and the first trench, and a second third sub-well region inserted between the fourth well region and the first drift region, the second third sub-well region and the first third sub-well region are adjacent to the fourth well region respectively. The third well region has a first doping type.

[0119] The first isolation structure is disposed between the first trench and the third well region, and the first isolation structure extends from the top surface of the epitaxial layer into the buried layer. The width of the first isolation structure ranges from 0.5 μm to 0.7 μm, and the depth ranges from 13 μm to 18 μm. The first isolation structure is formed by sidewall thermal oxidation and / or oxide deposition.

[0120] In a preferred embodiment, the semiconductor device further comprises a second isolation structure, the second isolation structure is arranged between the third well region and the first drift region, the second isolation structure extends from the top surface of the epitaxial layer into the epitaxial layer and has a preset distance from the buried layer. The width of the second isolation structure ranges from 0.35 μm to 0.5 μm, and the depth ranges from 0.4 μm to 13 μm. The second isolation structure is formed by sidewall thermal oxidation and / or oxide deposition.

[0121] In another preferred embodiment, the second and third sub-well regions include a plurality of second and third sub-well region units disposed at intervals, the plurality of second and third sub-well region units are arranged in a ring shape, and adjacent second and third sub-well region units are separated by an epitaxial layer.

[0122] The semiconductor device of the present invention can reduce the β gain of the parasitic transistor in the device, increase the breakdown voltage between the collector C and the emitter E, and keep the breakdown voltage between the emitter E and the base B, and the breakdown voltage between the collector C and the base B unchanged as much as possible, thereby improving circuit performance.

[0123] The semiconductor device of the present invention is described in detail below through several specific embodiments in combination with the accompanying drawings to facilitate understanding of the technical solution of the present invention.

[0124] Embodiment 1:

[0125] like Figure 3 and Figure 4 As shown, the semiconductor device in Embodiment 1 of the present invention includes a semiconductor body 10 , a first trench 20 , a first drift region 30 , a first well region 41 , a second well region 42 and a third well region 50 .

[0126] The semiconductor body 10 includes a P-type doped substrate 11, an N-type doped buried layer 12 disposed on the substrate 11, and a P-type doped epitaxial layer 13 disposed on the buried layer 12. The epitaxial layer has a depth of 13 μm, and the buried layer 12 has a depth of 8 μm.

[0127] The first trench 20 extends from the top surface of the epitaxial layer 13 to the buried layer 12. The first trench 20 is arranged in a ring shape to divide the device area in the device. A barrier layer 22 is arranged on the sidewall of the first trench 20. The first trench 20 is filled with a P-type doped first conductive material 21-polysilicon. The first conductive material 21 is connected to the buried layer 12, and is used to electrically connect the buried layer 12 to the top surface of the epitaxial layer 13.

[0128] Since the first conductive material 21 is connected to the buried layer 12 , the first conductive material 21 can be used as a collector C of the semiconductor device.

[0129] The first drift region 30 is disposed in the epitaxial layer 13 and is located within the range surrounded by the first trench 20. A separation space is formed between the first drift region 30 and the first trench 20. The first drift region 30 is an N-type drift region and can serve as an emitter E of a semiconductor device.

[0130] The first well region 41 is disposed in the epitaxial layer 13 and is located in the spacing space between the first trench 20 and the first drift region 30. The first well region 41 is a weak P-type well region. The first well region 41 is also disposed in a ring shape.

[0131] The second well region 42 is disposed in the epitaxial layer 13 and is located below the first well region 41. The second well region 42 is disposed adjacent to the first well region 41. The second well region 42 is an N-type well region. The second well region 42 is also disposed in an annular shape. The depth of the second well region 42 is less than the depth of the first well region 41.

[0132] The third well region 50 is disposed in the epitaxial layer 13, and includes a first third sub-well region 51 inserted between the first well region 41 and the first trench 20, and a second third sub-well region 52 inserted between the first well region 41 and the first drift region 30, and the first third sub-well region 51 and the second third sub-well region 52 are respectively disposed adjacent to the first well region 41. The third well region 50 is also disposed in an annular shape, and its depth is equal to the depth of the first well region 41.

[0133] The third well region 50 is a P-type well region, and the doping concentration of the third well region 50 is greater than the doping concentration of the first well region 41 .

[0134] The third well region 50 may serve as a base B of the semiconductor device.

[0135] In the above technical solution, the first well region 41 , the second well region 42 and the third well region 50 may be formed in the following manner.

[0136] Specifically, the first well region 41 has a first region, the second well region 42 has a second region, and the third well region 50 has a third region.

[0137] First, P-doping is performed in the first region and the third region (first doping region) to form a third well region 50 in the third region, and the first region has a P-type doping type; then, N-type doping is performed in the first region and the second region to counter-dope the P-doped first region to form a first well region 41 in the first region, and at the same time, a second well region 42 is formed in the second region.

[0138] The semiconductor device in the first embodiment of the present invention may further include a second trench 70 and a third trench 80 .

[0139] The second trench 70 is located at the periphery of the first trench 20 . The second trench 70 extends from the top surface of the epitaxial layer 13 into the substrate 11 . A second trench structure 71 is disposed in the second trench 70 . The second trench structure 71 electrically connects the substrate 11 to the top surface of the epitaxial layer 13 .

[0140] The third trench 80 is located between the first trench 20 and the second trench 70. The third trench 80 extends from the top surface of the epitaxial layer 13 into the substrate 11, and its depth is less than that of the second trench 70. A third trench isolation structure 81 is disposed in the third trench 80, and the third trench structure 81 is used to isolate the first trench 20 from the second trench 70 to increase the breakdown voltage therebetween.

[0141] It should be noted that Figure 4 Not shown Figure 3 The second groove 70 and the third groove 80 in the embodiment of the present invention.

[0142] Embodiment 2:

[0143] refer to Figure 5 and Figure 6 As shown, the difference between the present embodiment 2 and the present embodiment 1 is that in the present embodiment 2, a first isolation structure 61 is further provided between the first trench 20 and the third well region 50 , and a second isolation structure 62 is further provided between the third well region 50 and the first drift region 30 .

[0144] The first isolation structure 61 extends from the top surface of the epitaxial layer 13 into the buried layer 12. The second isolation structure 62 extends from the top surface of the epitaxial layer 13 into the epitaxial layer 13 and has a preset distance from the buried layer 12. Both the first isolation structure 61 and the second isolation structure 62 are formed by sidewall thermal oxidation and / or oxide deposition.

[0145] It should be noted that Figure 6 Not shown Figure 5 The second groove 70 and the third groove 80 in the embodiment of the present invention.

[0146] Embodiment 3:

[0147] refer to Figure 7 As shown, the difference between this embodiment 3 and embodiment 1 is that in this embodiment 3, the second and third sub-well regions 52 include a plurality of second and third sub-well region units 521 that are spaced apart, the plurality of second and third sub-well region units 521 are arranged in a ring shape, and adjacent second and third sub-well region units 521 are separated by an epitaxial layer.

[0148] Embodiment 4:

[0149] refer to Figure 8As shown, the difference between the present embodiment 4 and the embodiment 1 is that in the present embodiment 4, the first well region 41 includes a plurality of first well region units 411 disposed at intervals, and the plurality of first well region units 411 are arranged in a ring shape.

[0150] The second well region 42 includes a plurality of second well region units 421 arranged at intervals, and the plurality of second well region units 421 are arranged in a ring shape. The plurality of first well region units 411 and the plurality of second well region units 421 are arranged in a one-to-one correspondence.

[0151] The third well region 50 also includes a third sub-well region unit 531 inserted between adjacent first well region units 411 and adjacent second well region units 421, and the third sub-well region unit 531 is adjacent to the first third sub-well region 51 and the second third sub-well region 52 respectively, and the third sub-well region unit 531 is adjacent to the adjacent first well region unit 411 and the second well region unit 421 respectively.

[0152] Embodiment 5:

[0153] refer to Fig. 9 As shown, the difference between the present embodiment 5 and the embodiment 4 is that in the present embodiment 5, a first isolation structure 61 is further provided between the first trench 20 and the third well region 50 , and a second isolation structure 62 is further provided between the third well region 50 and the first drift region 30 .

[0154] The first isolation structure 61 extends from the top surface of the epitaxial layer 13 into the buried layer 12. The second isolation structure 62 extends from the top surface of the epitaxial layer 13 into the epitaxial layer 13 and has a preset distance from the buried layer 12. Both the first isolation structure 61 and the second isolation structure 62 are formed by sidewall thermal oxidation and / or oxide deposition.

[0155] Embodiment 6:

[0156] refer to Fig.10 As shown, the difference between the present embodiment 6 and the embodiment 4 is that in the present embodiment 6, the second and third sub-well regions 52 include a plurality of second and third sub-well region units 521 arranged at intervals, the plurality of second and third sub-well region units 521 are arranged in a ring shape, and each second and third sub-well region unit 521 corresponds to and is adjacent to a third and third sub-well region unit 531. Adjacent second and third sub-well region units 521 are separated by an epitaxial layer.

[0157] Embodiment 7:

[0158] refer to Fig.11 and Fig.12 As shown, the semiconductor device in Embodiment 7 of the present invention includes a semiconductor body 10 , a first trench 20 , a first drift region 30 , a fourth well region 43 and a third well region 50 .

[0159] The semiconductor body 10 includes a P-type doped substrate 11, an N-type doped buried layer 12 disposed on the substrate 11, and a P-type doped epitaxial layer 13 disposed on the buried layer 12. The epitaxial layer has a depth of 13 μm, and the buried layer 12 has a depth of 8 μm.

[0160] The first trench 20 extends from the top surface of the epitaxial layer 13 to the buried layer 12. The first trench 20 is arranged in a ring shape to divide the device area in the device. A barrier layer 22 is arranged on the sidewall of the first trench 20. The first trench 20 is filled with a P-type doped first conductive material 21-polysilicon. The first conductive material 21 is connected to the buried layer 12, and is used to electrically connect the buried layer 12 to the top surface of the epitaxial layer 13.

[0161] Since the first conductive material 21 is connected to the buried layer 12 , the first conductive material 21 can be used as a collector C of the semiconductor device.

[0162] The first drift region 30 is disposed in the epitaxial layer 13 and is located within the range surrounded by the first trench 20. A separation space is formed between the first drift region 30 and the first trench 20. The first drift region 30 is an N-type drift region and can serve as an emitter E of a semiconductor device.

[0163] The fourth well region 43 is disposed in the epitaxial layer 13 and between the first trench 20 and the first drift region 30. The fourth well region 43 is an N-type well region. The fourth well region 43 includes a plurality of fourth well region units 431 disposed at intervals. The plurality of fourth well region units 431 are arranged in a ring shape.

[0164] refer to Fig.11 As shown, the third well region 50 is arranged in the epitaxial layer 13, and the third well region 50 includes a first third sub-well region 51 inserted between the fourth well region 43 and the first trench 20, and a second third sub-well region 52 inserted between the fourth well region 43 and the first drift region 30, and a third third sub-well region unit 531 inserted between adjacent fourth well region units 431. The first third sub-well region 51 and the second third sub-well region 52 are respectively arranged adjacent to the fourth well region 43. The third third sub-well region unit 531 is adjacent to the adjacent fourth well region unit 431. The third third sub-well region unit 531 is respectively arranged adjacent to the first third sub-well region 51 and the second third sub-well region 52.

[0165] The third well region 50 is also arranged in an annular shape, and its depth is less than that of the fourth well region 43. The third well region 50 is a P-type well region and can be used as a base B of the semiconductor device.

[0166] The semiconductor device in the seventh embodiment of the present invention may further include a second trench 70 and a third trench 80 .

[0167] The second trench 70 is located at the periphery of the first trench 20 . The second trench 70 extends from the top surface of the epitaxial layer 13 into the substrate 11 . A second trench structure 71 is disposed in the second trench 70 . The second trench structure 71 electrically connects the substrate 11 to the top surface of the epitaxial layer 13 .

[0168] The third trench 80 is located between the first trench 20 and the second trench 70. The third trench 80 extends from the top surface of the epitaxial layer 13 into the substrate 11, and its depth is less than the second trench 70. A third trench isolation structure 81 is disposed in the third trench 80, and the third trench structure 81 is used to isolate the first trench 20 from the second trench 70 to increase the breakdown voltage therebetween.

[0169] Embodiment 8:

[0170] refer to Fig.13 and Fig.14 As shown, the difference between the present embodiment 8 and the embodiment 7 is that in the present embodiment 8, a first isolation structure 61 is further provided between the first trench 20 and the third well region 50 , and a second isolation structure 62 is further provided between the third well region 50 and the first drift region 30 .

[0171] The first isolation structure 61 extends from the top surface of the epitaxial layer 13 into the buried layer 12. The second isolation structure 62 extends from the top surface of the epitaxial layer 13 into the epitaxial layer 13 and has a preset distance from the buried layer 12. Both the first isolation structure 61 and the second isolation structure 62 are formed by sidewall thermal oxidation and / or oxide deposition.

[0172] Embodiment 9:

[0173] refer to Fig.15 As shown, the difference between this embodiment 9 and embodiment 7 is that in this embodiment 9, the second third sub-well region 52 includes a plurality of second third sub-well region units 521 arranged at intervals, and each second third sub-well region unit 521 corresponds to and is adjacent to a third third sub-well region unit 531. The plurality of second third sub-well region units 521 are arranged in a ring shape, and adjacent second third sub-well region units 521 are separated by an epitaxial layer.

[0174] Embodiment 10:

[0175] refer to Fig.16 As shown, the semiconductor device in embodiment 10 of the present invention includes a semiconductor body 10 , a first trench 20 , a first drift region 30 , a fourth well region 43 , a third well region 50 , a first isolation structure 61 and a second isolation structure 62 .

[0176] The semiconductor body 10 includes a P-type doped substrate 11, an N-type doped buried layer 12 disposed on the substrate 11, and a P-type doped epitaxial layer 13 disposed on the buried layer 12. The epitaxial layer has a depth of 13 μm, and the buried layer 12 has a depth of 8 μm.

[0177] The first trench 20 extends from the top surface of the epitaxial layer 13 to the buried layer 12. The first trench 20 is arranged in a ring shape to divide the device area in the device. A barrier layer 22 is arranged on the sidewall of the first trench 20. The first trench 20 is filled with a P-type doped first conductive material 21-polysilicon. The first conductive material 21 is connected to the buried layer 12, and is used to electrically connect the buried layer 12 to the top surface of the epitaxial layer 13.

[0178] Since the first conductive material 21 is connected to the buried layer 12 , the first conductive material 21 can be used as a collector C of the semiconductor device.

[0179] The first drift region 30 is disposed in the epitaxial layer 13 and is located within the range surrounded by the first trench 20. A separation space is formed between the first drift region 30 and the first trench 20. The first drift region 30 is an N-type drift region and can serve as an emitter E of a semiconductor device.

[0180] The fourth well region 43 is disposed in the epitaxial layer 13 and is located between the first trench 20 and the first drift region 30. The fourth well region 43 is an N-type well region. The fourth well region 43 is disposed in a ring shape.

[0181] The third well region 50 is disposed in the epitaxial layer 13, and includes a first third sub-well region 51 inserted between the fourth well region 43 and the first trench 20, and a second third sub-well region 52 inserted between the fourth well region 43 and the first drift region 30. The first third sub-well region 51 and the second third sub-well region 52 are disposed adjacent to the fourth well region 43, respectively.

[0182] The third well region 50 is also arranged in an annular shape, and its depth is less than that of the fourth well region 43. The third well region 50 is a P-type well region and can be used as a base B of the semiconductor device.

[0183] The first isolation structure 61 is disposed between the first trench 20 and the third well region 50. The first isolation structure 61 extends from the top surface of the epitaxial layer 13 into the buried layer 12.

[0184] The second isolation structure 62 is disposed between the third well region 50 and the first drift region 30. The second isolation structure 62 extends from the top surface of the epitaxial layer 13 into the epitaxial layer 13 and has a predetermined distance from the buried layer 12.

[0185] The first isolation structure 61 and the second isolation structure 62 are both formed by sidewall thermal oxidation and / or oxide deposition.

[0186] The semiconductor device in the tenth embodiment of the present invention may further include a second trench 70 and a third trench 80 .

[0187] The second trench 70 is located at the periphery of the first trench 20 . The second trench 70 extends from the top surface of the epitaxial layer 13 into the substrate 11 . A second trench structure 71 is disposed in the second trench 70 . The second trench structure 71 electrically connects the substrate 11 to the top surface of the epitaxial layer 13 .

[0188] The third trench 80 is located between the first trench 20 and the second trench 70. The third trench 80 extends from the top surface of the epitaxial layer 13 into the substrate 11, and its depth is less than that of the second trench 70. A third trench isolation structure 81 is disposed in the third trench 80, and the third trench structure 81 is used to isolate the first trench 20 from the second trench 70 to increase the breakdown voltage therebetween.

[0189] Embodiment 11:

[0190] refer to Fig.17 As shown, the semiconductor device in Embodiment 11 of the present invention includes a semiconductor body 10 , a first trench 20 , a first drift region 30 , a fourth well region 43 and a third well region 50 .

[0191] The semiconductor body 10 includes a P-type doped substrate 11, an N-type doped buried layer 12 disposed on the substrate 11, and a P-type doped epitaxial layer 13 disposed on the buried layer 12. The epitaxial layer has a depth of 13 μm, and the buried layer 12 has a depth of 8 μm.

[0192] The first trench 20 extends from the top surface of the epitaxial layer 13 to the buried layer 12. The first trench 20 is arranged in a ring shape to divide the device area in the device. A barrier layer 22 is arranged on the sidewall of the first trench 20. The first trench 20 is filled with a P-type doped first conductive material 21-polysilicon. The first conductive material 21 is connected to the buried layer 12, and is used to electrically connect the buried layer 12 to the top surface of the epitaxial layer 13.

[0193] Since the first conductive material 21 is connected to the buried layer 12 , the first conductive material 21 can be used as a collector C of the semiconductor device.

[0194] The first drift region 30 is disposed in the epitaxial layer 13 and is located within the range surrounded by the first trench 20. A separation space is formed between the first drift region 30 and the first trench 20. The first drift region 30 is an N-type drift region and can serve as an emitter E of a semiconductor device.

[0195] The fourth well region 43 is disposed in the epitaxial layer 13 and is located between the first trench 20 and the first drift region 30. The fourth well region 43 is an N-type well region. The fourth well region 43 is disposed in a ring shape.

[0196] The third well region 50 is disposed in the epitaxial layer 13, and the third well region 50 includes a first third sub-well region 51 inserted between the fourth well region 43 and the first trench 20, and a second third sub-well region 52 inserted between the fourth well region 43 and the first drift region 30. The first third sub-well region 51 and the second third sub-well region 52 are respectively disposed adjacent to the fourth well region 43. The second third sub-well region 52 includes a plurality of second third sub-well region units 521 disposed at intervals, and the plurality of second third sub-well region units 521 are arranged in a ring shape, and adjacent second third sub-well region units 521 are separated by an epitaxial layer.

[0197] The third well region 50 is also arranged in an annular shape, and its depth is less than that of the fourth well region 43. The third well region 50 is a P-type well region and can be used as a base B of the semiconductor device.

[0198] The semiconductor device in the eleventh embodiment of the present invention may further include a second trench 70 and a third trench 80 .

[0199] The second trench 70 is located at the periphery of the first trench 20 . The second trench 70 extends from the top surface of the epitaxial layer 13 into the substrate 11 . A second trench structure 71 is disposed in the second trench 70 . The second trench structure 71 electrically connects the substrate 11 to the top surface of the epitaxial layer 13 .

[0200] The third trench 80 is located between the first trench 20 and the second trench 70. The third trench 80 extends from the top surface of the epitaxial layer 13 into the substrate 11, and its depth is less than that of the second trench 70. A third trench isolation structure 81 is disposed in the third trench 80, and the third trench structure 81 is used to isolate the first trench 20 from the second trench 70 to increase the breakdown voltage therebetween.

[0201] Compared with the prior art, the semiconductor device of the present invention can reduce the β gain of the parasitic transistor in the device, increase the breakdown voltage between the collector C and the emitter E, and keep the breakdown voltage between the emitter E and the base B, and the breakdown voltage between the collector C and the base B unchanged as much as possible, thereby improving circuit performance.

[0202] The semiconductor device of the present invention is compatible with the existing MTI / DTI basic process, does not increase the additional mask cost, reduces the parasitic NPN transistor gain of the semiconductor device with a BJT structure, and improves the circuit performance.

[0203] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0204] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a substrate (11) having a first doping type, a buried layer (12) having a second doping type disposed on the substrate, and an epitaxial layer (13) having a first doping type disposed on the buried layer; A first trench (20) extending from the top surface of the epitaxial layer into the buried layer, wherein a first conductive material (21) of a second doping type is disposed in the first trench, and the first conductive material electrically connects the buried layer to the top surface of the epitaxial layer; A first drift region (30) is arranged in the epitaxial layer and located within a range surrounded by the first trench, the first drift region having a second doping type; A first well region (41) is arranged in the epitaxial layer and located between the first trench and the first drift region, the first well region having a first doping type, a second doping type or a non-doping type; A second well region (42) is disposed in the epitaxial layer and below the first well region, the second well region having a second doping type; A third well region (50) is disposed in the epitaxial layer, the third well region comprising a first third sub-well region (51) inserted between the first well region and the first trench, and a second third sub-well region (52) inserted between the first well region and the first drift region, the third well region having a first doping type; in, When the first well region has a second doping type, the doping concentration of the second well region is greater than the doping concentration of the first well region; When the first well region has a first doping type, the doping concentration of the third well region is greater than the doping concentration of the first well region.

2. The semiconductor device according to claim 1, wherein: The sum of the depths of the first well region and the second well region is greater than the depth of the third well region; and / or, The depth of the first well region is equal to the depth of the third well region; and / or, The depth of the second well region is smaller than the depth of the third well region.

3. The semiconductor device according to claim 1, wherein: The first third sub-well region and the second third sub-well region are respectively disposed adjacent to the first well region, and the second well region is disposed adjacent to the first well region.

4. The semiconductor device according to claim 3, characterized in that The first well region has a first area, the second well region has a second area, and the third well region has a third area; By performing ion implantation of a first doping type in the first region and the third region, a third well region is formed in the third region, and the first region has the first doping type; by performing ion implantation of a second doping type in the first region and the second region, the first region having the first doping type is counter-doped, and a first well region is formed in the first region, and at the same time, a second well region is formed in the second region; or, By performing ion implantation of the second doping type in the first region and the second region, a second well region is formed in the second region, and the first region has the second doping type. By performing ion implantation of the first doping type in the first region and the third region, the first region having the second doping type is counter-doped to form a first well region in the first region. At the same time, a third well region is formed in the third region.

5. The semiconductor device according to claim 1, wherein: It also includes a first isolation structure (61), which is arranged between the first trench and the third well region, and extends from the top surface of the epitaxial layer into the buried layer.

6. The semiconductor device according to claim 1, wherein: It also includes a second isolation structure (62), which is arranged between the third well region and the first drift region, and the second isolation structure extends from the top surface of the epitaxial layer into the epitaxial layer and has a preset distance from the buried layer.

7. The semiconductor device according to claim 1, wherein: The first well region includes a plurality of first well region units (411) arranged at intervals, and the second well region includes a plurality of second well region units (421) arranged at intervals, and the plurality of first well region units and the plurality of second well region units are arranged in a one-to-one correspondence.

8. The semiconductor device according to claim 7, characterized in that The third well region includes a third third sub-well region unit (531) inserted between adjacent first well region units and between adjacent second well region units, and the third third sub-well region unit is adjacent to the first third sub-well region and the second third sub-well region respectively.

9. The semiconductor device according to claim 1, wherein: The second and third sub-well regions include a plurality of second and third sub-well region units (521) arranged at intervals, and adjacent second and third sub-well region units are separated by the epitaxial layer.

10. The semiconductor device according to claim 1, wherein: The first trench and the third well region, and the third well region and the first drift region are separated by the epitaxial layer.

11. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a substrate (11) having a first doping type, a buried layer (12) having a second doping type disposed on the substrate, and an epitaxial layer (13) having a first doping type disposed on the buried layer; forming a first trench (20) in the semiconductor body, the first trench extending from the top surface of the epitaxial layer into the buried layer, a first conductive material (21) having a second doping type being disposed in the first trench, the first conductive material electrically connecting the buried layer to the top surface of the epitaxial layer; A first drift region (30) having a second doping type and a first doping region having a first doping type are formed in the semiconductor body, wherein the first drift region is arranged in the epitaxial layer and is located within a range surrounded by the first trench, and the first doping region is arranged in the epitaxial layer and is located between the first trench and the first drift region; A second doping type is counter-doped on a portion of the first doping region to form a second well region (42) below the first doping region, a first well region (41) is formed within the first doping region, and a portion of the first doping region that is not counter-doped forms a third well region (50).

12. A semiconductor device, characterized in that: include: A semiconductor body, comprising a substrate (11) having a first doping type, a buried layer (12) having a second doping type disposed on the substrate, and an epitaxial layer (13) having a first doping type disposed on the buried layer; A first trench (20) extending from the top surface of the epitaxial layer into the buried layer, wherein a first conductive material (21) of a second doping type is disposed in the first trench, and the first conductive material electrically connects the buried layer to the top surface of the epitaxial layer; A first drift region (30) is arranged in the epitaxial layer and located within a range surrounded by the first trench, the first drift region having a second doping type; A fourth well region (43) is arranged in the epitaxial layer and between the first trench and the first drift region, the fourth well region has a second doping type, and the fourth well region includes a plurality of fourth well region units (431) arranged at intervals; A third well region (50) is arranged in the epitaxial layer, the third well region includes a first third sub-well region (51) inserted between the fourth well region and the first trench, a second third sub-well region (52) inserted between the fourth well region and the first drift region, and a third third sub-well region unit (531) inserted between adjacent fourth well region units, the third third sub-well region unit is respectively adjacent to the first third sub-well region and the second third sub-well region, and the third well region has a first doping type.

13. The semiconductor device according to claim 12, characterized in that The depth of the fourth well region is greater than the depth of the third well region.

14. The semiconductor device according to claim 12, wherein: It also includes a first isolation structure (61), which is arranged between the first trench and the third well region, and extends from the top surface of the epitaxial layer into the buried layer.

15. The semiconductor device according to claim 12, wherein: It also includes a second isolation structure (62), which is arranged between the third well region and the first drift region, and the second isolation structure extends from the top surface of the epitaxial layer into the epitaxial layer and has a preset distance from the buried layer.

16. The semiconductor device according to claim 12, wherein: The second and third sub-well regions include a plurality of second and third sub-well region units (521) arranged at intervals, and adjacent second and third sub-well region units are separated by the epitaxial layer.

17. A semiconductor device, characterized in that: include: A semiconductor body, comprising a substrate (11) having a first doping type, a buried layer (12) having a second doping type disposed on the substrate, and an epitaxial layer (13) having a first doping type disposed on the buried layer; A first trench (20) extending from the top surface of the epitaxial layer into the buried layer, wherein a first conductive material (21) of a second doping type is disposed in the first trench, and the first conductive material electrically connects the buried layer to the top surface of the epitaxial layer; A first drift region (30) is arranged in the epitaxial layer and located within a range surrounded by the first trench, the first drift region having a second doping type; a fourth well region (43), arranged in the epitaxial layer and located between the first trench and the first drift region, the fourth well region having a second doping type; A third well region (50) is disposed in the epitaxial layer, the third well region comprising a first third sub-well region (51) inserted between the fourth well region and the first trench, and a second third sub-well region (52) inserted between the fourth well region and the first drift region, the third well region having a first doping type; A first isolation structure (61) is disposed between the first trench and the third well region, and the first isolation structure extends from the top surface of the epitaxial layer into the buried layer.

18. The semiconductor device according to claim 17, wherein: It also includes a second isolation structure (62), which is arranged between the third well region and the first drift region, and the second isolation structure extends from the top surface of the epitaxial layer into the epitaxial layer and has a preset distance from the buried layer.

19. The semiconductor device according to claim 17, wherein: The second and third sub-well regions include a plurality of second and third sub-well region units (521) arranged at intervals, and adjacent second and third sub-well region units are separated by the epitaxial layer.

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