Trench gate type IGBT and manufacturing method thereof
By setting the emitter region and gate region in the trench of the IGBT device and reducing its contact area, the problem of slow switching speed and large losses caused by large Miller capacitance in traditional IGBT devices is solved, and more efficient switching is achieved performance.
Patent Information
- Application Number
- CN202411590994.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-08
- Publication Date
- 2025-02-18
AI Technical Summary
The Miller capacitor of traditional trench gate IGBTs is relatively large, resulting in slow switching speed and large loss.
By dividing the trench unit of the conventional IGBT device into three, and an emitter region and a gate region are provided in the trench, the main part of the emitter region is arranged at the bottom of the gate region, the emitter region and the gate region. Insulating medium is arranged between the two sides for isolation, reducing the contact area between the collector region and the gate region.
The Miller capacitor of the IGBT is reduced, the switching speed of the IGBT is increased, and the switching loss of the IGBT is reduced.
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Figure CN119486165A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a trench gate IGBT and a manufacturing method thereof. Background Art
[0002] As an important power switching device, the insulated gate bipolar transistor (IGBT) combines the advantages of MOSFET and bipolar transistor to become a power transistor with the advantages of both devices. It has high input impedance, can be driven with low power, and can amplify current to large current. It has been widely used in various application fields. IGBT has two types: planar and trench. Compared with planar IGBT, trench gate IGBT can significantly reduce the on-state voltage drop without increasing the turn-off loss. However, the Miller capacitance of traditional trench gate IGBT is large, and it has the disadvantages of slow switching speed and high loss. With the continuous development of power electronics technology, the market has higher and higher performance requirements for IGBT devices, and an IGBT device with lower switching loss is urgently needed.
[0003] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention
[0004] The object of the present invention is to provide a trench gate IGBT and a method for manufacturing the same, so as to solve the problem of large Miller capacitance of the trench gate IGBT.
[0005] In order to solve the above technical problems, the present invention provides a method for manufacturing a trench gate IGBT, comprising:
[0006] providing a substrate;
[0007] Etching the substrate to form a groove;
[0008] Depositing polysilicon at the bottom of the trench to form an emitter region;
[0009] Continue to deposit an insulating medium with a first preset height on the top of the emitter region;
[0010] Etching two sides of the insulating medium to form two accommodating cavities with a second preset height, wherein the second preset height is smaller than the first preset height;
[0011] Depositing polysilicon in the accommodating cavity to form a gate region;
[0012] Continue to etch the insulating medium between the two accommodating cavities to form an opening extending to the emitter region between the accommodating cavities, wherein the critical dimension of the opening is smaller than the critical dimension of the remaining insulating medium, and fill the opening with polysilicon to connect the emitter region.
[0013] Preferably, after forming the trench and before forming the emitter region, a gate oxide layer is provided on the inner wall of the trench.
[0014] Preferably, after the emitter region is connected through the opening, ion implantation is performed on the top of the substrate to form a first conductive type region; and ion implantation is performed on a side of the first conductive type region close to the trench to form a second conductive type region.
[0015] Preferably, after forming the second conductive type region, an interlayer dielectric is disposed on the surface of the substrate, the interlayer dielectric and part of the substrate are etched to form a plurality of contact holes to expose each conductive region, and a metal layer is formed on the interlayer dielectric.
[0016] Preferably, after the metal layer is formed, ion implantation is performed on the bottom of the substrate to form a collector region.
[0017] A trench gate IGBT, comprising:
[0018] A substrate having a groove thereon;
[0019] An emitter region, arranged at the bottom of the trench, wherein a portion of the top of the emitter region extends longitudinally to the surface of the substrate;
[0020] The gate region is arranged on both sides of the partial region, wherein the emitter region and the gate region are isolated by an insulating medium.
[0021] Preferably, the inner wall of the trench also has a gate oxide layer.
[0022] Preferably, a first conductive type region is arranged at the intervals between the trenches and at a side of the trench facing away from the intervals, and a second conductive type region is arranged at a side of the first conductive type region close to the trenches.
[0023] Preferably, the surface of the substrate further has an interlayer dielectric and a metal layer, the interlayer dielectric is further provided with a plurality of contact holes to expose each conductive region, and the metal layer is arranged on the top of the interlayer dielectric.
[0024] Preferably, a collector region is further provided on a side of the substrate facing away from the metal layer.
[0025] In the manufacturing method of the trench gate IGBT provided by the present invention, a conventional IGBT device trench unit is divided into three, an emitter region and a gate region are arranged in the trench, a main part of the emitter region is arranged at the bottom of the gate region, and an insulating medium is arranged between the emitter region and the gate region for isolation, thereby reducing the contact area between the collector region and the gate region, thereby reducing the Miller capacitance of the IGBT, increasing the switching speed of the IGBT, and reducing the switching loss of the IGBT.
[0026] The trench gate IGBT provided by the present invention and the method for manufacturing the trench gate IGBT provided by the present invention belong to the same inventive concept. Therefore, the trench gate IGBT provided by the present invention has at least all the advantages of the method for manufacturing the trench gate IGBT provided by the present invention, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.
[0028] Figure 1 is a schematic diagram of a groove structure according to an embodiment of the present invention;
[0029] Figure 2 is a schematic diagram of the emitter region structure of an embodiment of the present invention;
[0030] Figure 3 is a schematic diagram of the structure of a second insulating medium according to an embodiment of the present invention;
[0031] Figure 4 is a schematic diagram of the gate region structure of an embodiment of the present invention;
[0032] Figure 5 It is a schematic diagram of a structure of an emitter region provided in an embodiment of the present invention;
[0033] Figure 6 is a schematic diagram of an ion implantation structure according to an embodiment of the present invention;
[0034] Figure 7 It is a schematic diagram of the structure of a trench gate IGBT provided by an embodiment of the present invention;
[0035] Figure 8 is an execution flow chart of an embodiment of the present invention;
[0036] Fig. 9 1 is a graph showing capacitance and voltage curves of an embodiment of the present invention and a prior art structure.
[0037] In the attached figure:
[0038] 1. Substrate; 2. Trench; 3. Hard mask layer; 4. Gate oxide layer; 5. Emitter region; 6. Insulating medium; 7. Gate region; 8. First conductivity type region; 9. Second conductivity type region; 10. Interlayer dielectric; 11. Metal layer; 12. Collector region. DETAILED DESCRIPTION
[0039] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0040] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features. The term "proximal end" is usually the end close to the operator, and the term "distal end" is usually the end close to the patient. "One end" and "the other end" as well as "proximal end" and "distal end" usually refer to two corresponding parts, which include not only the endpoints. The terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of the two elements or the interaction relationship between the two elements. In addition, as used in the present invention, an element is arranged on another element, which usually only means that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and it cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, one element can be in any position such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0041] Although the term "groove" is traditionally used to define an elongated trench, the term "groove" used in the present disclosure is not limited to elongated trenches, but should be interpreted broadly to include rectangular holes that are not elongated, square holes, circular or round holes, and even holes with serpentine or polygonal geometries, any and all of which are considered "grooves" in the present disclosure.
[0042] The inventors have found that the Miller capacitance of the traditional trench IGBT is relatively large, and has the disadvantages of slow switching speed and large loss.
[0043] Based on this, the core idea of the present invention is to divide the traditional IGBT device trench unit into three, set the emitter region and the gate region in the trench, set the main part of the emitter region at the bottom of the gate region, and arrange an insulating medium between the emitter region and the gate region for isolation, thereby reducing the contact area between the collector region and the gate region, thereby reducing the Miller capacitance Cres of the IGBT, increasing the switching speed of the IGBT, and reducing the switching loss of the IGBT.
[0044] For details, please refer to Figure 1-Figure 9 , which is a schematic diagram of an embodiment of the present invention. A method for manufacturing a trench gate IGBT, comprising:
[0045] S1, provide a substrate 1. The material of the substrate 1 may include a semiconductor material, an insulating material, a conductive material or any combination thereof; and the substrate 1 may be a single-layer structure or a multi-layer structure. For example, the substrate 1 may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors. And, the substrate 1 may be, for example, a layered substrate of Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator.
[0046] S2, forming a groove 2 on the substrate 1. Exemplarily, a hard mask layer 3 and a photoresist (not shown) are formed on the surface of the substrate 1, the hard mask layer 3 is etched by the photoresist, and then the substrate 1 is etched by the hard mask layer 3 to form two deeper grooves 2, such as Figure 1 shown.
[0047] S3 , depositing polysilicon at the bottom of the trench 2 to form an emitter region 5 . At this time, the top surface of the emitter region 5 is lower than the surface of the substrate 1 .
[0048] After forming the trench 2 and before forming the emitter region 5, a gate oxide layer 4 is also provided on the inner wall of the trench 2. After removing the hard mask layer 3 used to form the trench 2, for example, silicon oxide is deposited on the surface of the substrate 1 and in the trench 2 to form the gate oxide layer 4. The gate oxide layer 4 can be formed by processes such as chemical vapor deposition or atomic layer deposition (ALD).
[0049] In one embodiment, the emitter region 5 is formed by depositing polysilicon, such as Figure 2 As shown, the emitter region 5 is located at the bottom of the trench 2 .
[0050] S4, continue to deposit the insulating medium 6 of a first preset height on the top of the emitter region 5. The insulating medium 6 is also silicon oxide. It can be understood that the silicon oxide is continuously deposited on the top of the emitter region 5 until the silicon oxide in the trench 2 is higher than or flush with the surface of the gate oxide layer 4 on the substrate 1, and then the silicon oxide outside the trench 2 is removed by CMP. Figure 3 It can be understood that the longitudinal direction here is the depth direction of the groove 2.
[0051] S5, etching the two sides of the insulating medium 6 to form two accommodating cavities with a second preset height, wherein the second preset height is smaller than the first preset height, such as Figure 3 As shown in the cross-sectional view, etching starts from the top of the insulating medium 6 on both sides, where the two sides of the insulating medium 6 are the two sides adjacent to the side walls of the groove 2 in the lateral direction, wherein the second preset height is less than the first preset height, thereby ensuring that there is a certain height of the insulating medium 6 between the bottom of the accommodating cavity and the emitter region 5.
[0052] S6, depositing polysilicon in the accommodating cavity to form a gate region 7, setting the gate region 7 in the insulating medium 6 at the top of the emitter region 5, and the gate region 7 is longitudinally arranged along the side wall of the trench 2.
[0053] Specifically, a photoresist is formed on the substrate 1 and the insulating medium 6. After photolithography, etching is performed on the side of the insulating medium 6 adjacent to the gate oxide layer 4, so that the cross section of the insulating medium 6 forms a "convex" structure, and a space for accommodating the gate region 7 is formed through the gate oxide layer 4 in the trench 2, and the gate region 7 is formed by depositing polysilicon at this location, such as Figure 4 As shown, the deposition method includes but is not limited to chemical vapor deposition and atomic layer deposition (ALD).
[0054] S7, continue to etch the insulating medium 6 between the two accommodating cavities, form an opening extending to the emitter region 5 between the accommodating cavities, the critical dimension of the opening is smaller than the critical dimension of the remaining insulating medium 6, fill polysilicon in the opening to connect the emitter region 5, continue to form photoresist on the surface of the substrate 1 and form the required pattern by photolithography, etch the insulating medium 6 between the accommodating cavities, form an opening extending to the emitter region 5 to connect the emitter region 5, the critical dimension of the opening is smaller than the critical dimension of the remaining insulating medium, so that the finally formed gate region 7 and the emitter region 5 have a portion of the insulating medium 6.
[0055] In one embodiment, if Figure 5 As shown, after forming an opening extending to the emitter region 5, a dielectric is deposited in the opening to connect the emitter region 5. Polysilicon is continuously deposited in the opening until it is flush with the substrate 1 to form a complete emitter region 5. It should be noted that a portion of the insulating dielectric 6 is retained between the emitter region 5 and the gate region 7, and the insulating dielectric 6 is, for example, silicon oxide.
[0056] S8, after the emitter region 5 is connected through the opening, ion implantation is performed on the top of the substrate 1 to form a first conductive type region 8; ion implantation is performed on the side of the first conductive type region 8 close to the groove 2 to form a second conductive type region 9. Ion implantation is performed on the top of the substrate 1: ion implantation is performed in the intervals between the grooves 2 and on the side of the groove 2 away from the intervals to form a first conductive type region 8; ion implantation is performed on the side of the first conductive type region 8 close to the groove 2 to form a second conductive type region 9.
[0057] For example, the first conductivity type is P type and the second conductivity type is N type. Therefore, the first conductivity type region 8 may be doped with P type dopants, such as boron. However, in other embodiments of the present invention, the carriers may be holes, in which case the first conductivity type is N type, and correspondingly, the second conductivity type is P type.
[0058] Before ion implantation, the gate oxide layer 4 on the surface of the substrate 1 can be removed, and a patterned photoresist can be formed on the substrate 1. Then, P-type ions are implanted in the region exposed by the photoresist, i.e., the region between the grooves 2 and the side of the groove 2 away from the gap, to form a first conductive type region 8, and the photoresist is removed. Photoresist is formed again to expose the regions on both sides of the groove 2, and N-type ions used as source terminals are implanted to form a second conductive type region 9 adjacent to the gate oxide layer 4 on both sides of the groove 2, as shown in FIG. Figure 6 shown.
[0059] S9, after forming the second conductive type region 9, an interlayer dielectric 10 is disposed on the surface of the substrate 1, the interlayer dielectric 10 and a portion of the substrate 1 are etched to form a plurality of contact holes to expose each conductive region, and a metal layer 11 is formed on the interlayer dielectric 10, such as Figure 7 shown.
[0060] After ion implantation, an interlayer dielectric 10 is formed on the surface 1 of the substrate 1, a photoresist is further provided, and the interlayer dielectric 10 is etched to form a contact hole, through which the top of the emitter region 5 is exposed, and the interlayer dielectric 10 is covered with photoresist again, and the area on one side of the second conductive type region 9 is exposed by photolithography and etched to form a contact hole connected to the second conductive type region 9, the photoresist is removed, and then a metal layer 11 is deposited in the contact hole and on the interlayer dielectric 10.
[0061] In one embodiment, after forming the metal layer 11, the back collector region 12 is formed, for example, by back P-type ion implantation. Figure 7 shown.
[0062] Among them, the interlayer dielectric 10 (ILD layer) includes one or more dielectric materials to provide isolation functions to various device components (such as gates) and various conductive components (such as metal lines, contacts and vias). The interlayer dielectric 10 includes dielectric materials such as silicon oxide, low-k dielectric materials, other suitable dielectric materials or combinations thereof. In some examples, the low-k dielectric material includes fluorinated silicon glass (FSG), carbon-doped silicon oxide, dry gel, aerogel, amorphous fluorinated carbon, polyparaxylene, BCB (bisbenzocyclobutene), polyimide and / or other suitable dielectric materials with a dielectric constant substantially less than that of thermal silicon oxide. For example, the formation of the interlayer dielectric 10 includes deposition and CMP. Deposition may include spin coating, CVD, other suitable deposition techniques or combinations thereof. The metal layer 11 includes materials such as TiN, a composite mask containing TiN, copper, aluminum, tungsten, etc.
[0063] refer to Fig. 9 As can be seen from the simulation chart shown in Table 1 below, by setting the relative positions of the gate region 7 and the emitter region 5, the contact area between the collector and the gate region 7 is reduced, thereby reducing the Cres of the IGBT, increasing the switching speed of the IGBT, and reducing the switching loss of the IGBT.
[0064] Table 1 Simulation data of conventional structure and improved structure of this application
[0065] Simulation parameters General structure Improved structure Rate of change Vth(V) 5.54 5.6 1.08％ Cres(pf) 7.21 5.69 -21.08％ Eon(mJ) 0.115 0.104 -9.57％ Eoff(mJ) 0.538 0.502 -6.69％ Etot(mJ) 0.653 0.606 -16.26％
[0066] Based on the same technical concept, the present disclosure also provides a trench gate IGBT, such as Figure 7 As shown, including:
[0067] A substrate 1, wherein a groove 2 is provided on the substrate 1;
[0068] An emitter region 5 is arranged at the bottom of the trench 2, and a portion of the top of the emitter region 5 extends longitudinally to the surface of the substrate 1;
[0069] The gate region 7 is arranged on both sides of the partial region, wherein the emitter region 5 and the gate region 7 are isolated from each other by an insulating medium.
[0070] It can be considered that the emitter region 5 has a first part and a second part opposite to each other, the first part is arranged at the bottom of the trench 2, the bottom of the second part is connected to the top of the first part, and the top of the second part extends to the surface of the substrate 1 to connect the emitter region 5 out of the trench 2. The gate region 7 is arranged on the top of the first part, and the gate region 7 is arranged longitudinally along the side wall of the trench 2.
[0071] In one embodiment, the material of the substrate 1 may include semiconductor materials, insulating materials, conductive materials or any combination thereof; and the substrate 1 may be a single-layer structure or a multi-layer structure. For example, the substrate 1 may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors. And, the substrate 1 is, for example, a layered substrate of Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. The emitter region 5 and the gate region 7 are both polysilicon, and the insulating medium 6 and the gate oxide layer 4 are both silicon oxide.
[0072] Specifically, the inner wall of the trench 2 also has a gate oxide layer 4. The first conductive type region 8 is arranged in the intervals between the trenches 2 and on the side of the trench 2 away from the intervals, and the second conductive type region 9 is arranged on the side of the first conductive type region 8 close to the trench 2.
[0073] Before ion implantation, the gate oxide layer 4 on the surface of the substrate 1 can be removed, and a patterned photoresist can be formed on the substrate 1. Then, P-type ions are implanted in the region exposed by the photoresist, i.e., the region between the grooves 2 and the side of the groove 2 away from the gap, to form a first conductive type region 8, and the photoresist is removed. Photoresist is formed again to expose the regions on both sides of the groove 2, and N-type ions used as source terminals are implanted to form a second conductive type region 9 adjacent to the gate oxide layer 4 on both sides of the groove 2, as shown in FIG. Figure 6 shown.
[0074] like Figure 7 As shown, the surface of the substrate 1 also has an interlayer dielectric 10, and the interlayer dielectric 10 is also provided with a plurality of contact holes to expose each conductive area. A metal layer 11 is arranged on the top of the interlayer dielectric 10. A collector region 12 is also arranged on the side of the substrate 1 away from the metal layer 11.
[0075] Among them, the interlayer dielectric 10 (ILD layer) includes one or more dielectric materials to provide isolation functions to various device components (such as gates) and various conductive components (such as metal lines, contacts and vias). The interlayer dielectric 10 includes dielectric materials such as silicon oxide, low-k dielectric materials, other suitable dielectric materials or combinations thereof. In some examples, the low-k dielectric material includes fluorinated silicon glass (FSG), carbon-doped silicon oxide, dry gel, aerogel, amorphous fluorinated carbon, polyparaxylene, BCB (bisbenzocyclobutene), polyimide and / or other suitable dielectric materials with a dielectric constant substantially less than that of thermal silicon oxide. For example, the formation of the interlayer dielectric 10 includes deposition and CMP. Deposition may include spin coating, CVD, other suitable deposition techniques or combinations thereof. The metal layer 11 includes materials such as TiN, a composite mask containing TiN, copper, aluminum, tungsten, etc.
[0076] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.
Claims
1. A method for manufacturing a trench gate IGBT, characterized in that: include: providing a substrate; Etching the substrate to form a groove; Depositing polysilicon at the bottom of the trench to form an emitter region; Continue to deposit an insulating medium with a first preset height on the top of the emitter region; Etching two sides of the insulating medium to form two accommodating cavities with a second preset height, wherein the second preset height is smaller than the first preset height; Depositing polysilicon in the accommodating cavity to form a gate region; Continue to etch the insulating medium between the two accommodating cavities to form an opening extending to the emitter region between the accommodating cavities, wherein the critical dimension of the opening is smaller than the critical dimension of the remaining insulating medium, and fill the opening with polysilicon to connect the emitter region.
2. The method for manufacturing a trench gate IGBT according to claim 1, characterized in that: After forming the trench and before forming the emitter region, a gate oxide layer is provided on the inner wall of the trench.
3. The method for manufacturing a trench gate IGBT according to claim 1, wherein: After the emitter region is connected through the opening, ions are implanted into the top of the substrate to form a first conductive type region; and ions are implanted into a side of the first conductive type region close to the groove to form a second conductive type region.
4. The method for manufacturing a trench gate IGBT according to claim 3, characterized in that: After forming the second conductive type region, an interlayer dielectric is disposed on the surface of the substrate, the interlayer dielectric and a portion of the substrate are etched to form a plurality of contact holes to expose each conductive region, and a metal layer is formed on the interlayer dielectric.
5. The method for manufacturing a trench gate IGBT according to claim 4, characterized in that: After the metal layer is formed, ions are implanted into the bottom of the substrate to form a collector region.
6. A trench gate IGBT, characterized in that: include: A substrate having a groove thereon; An emitter region, arranged at the bottom of the trench, wherein a portion of the top of the emitter region extends longitudinally to the surface of the substrate; The gate region is arranged on both sides of the partial region, wherein the emitter region and the gate region are isolated by an insulating medium.
7. The trench gate IGBT according to claim 6, characterized in that: The inner wall of the trench also has a gate oxide layer.
8. The trench gate IGBT according to claim 6, characterized in that: A first conductive type region is arranged at the intervals between the trenches and at a side of the trench facing away from the intervals, and a second conductive type region is arranged at a side of the first conductive type region close to the trenches.
9. The trench gate IGBT according to claim 6, characterized in that: The surface of the substrate is also provided with an interlayer dielectric and a metal layer. The interlayer dielectric is also provided with a plurality of contact holes to expose each conductive region. The metal layer is arranged on the top of the interlayer dielectric.
10. The trench gate IGBT according to claim 9, characterized in that: A collector region is also disposed on a side of the substrate facing away from the metal layer.