Power MOSFET and preparation method thereof

Abstract

The invention discloses a power MOSFET and a preparation method thereof, and belongs to the technical field of microelectronics. The power MOSFET comprises a substrate layer, an AlN buffer layer, a Ga2O3 buffer layer and a Ga2O3 epitaxial layer which are arranged from bottom to top, wherein the top surface of the Ga2O3 epitaxial layer is provided with a groove, and an oxide isolation layer is arranged in the groove; the drain electrode is arranged on one side of the Ga2O3 epitaxial layer and is adjacent to the oxide isolation layer; the source electrode is arranged in the middle area of the other side of the Ga2O3 epitaxial layer; second grooves are formed in the two sides of the source electrode; a NiO layer and an insulated gate dielectric layer are arranged on the second groove from bottom to top; a gate electrode with a non-planar gate structure is arranged on the insulated gate dielectric layer; and a gap part around the second groove and the gate electrode is filled with a first oxide isolation layer. Through structural design and material selection, the problems of serious heat dissipation and gate electrode electric leakage of existing similar devices are solved, and the voltage withstanding performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic technology, and in particular to a power MOSFET and a preparation method thereof. Background Art

[0002] As a new type of ultra-wide bandgap semiconductor material, Ga2O3 has the advantages of excellent physical properties, low cost, and high quality, and has received widespread attention in the semiconductor field. Compared with the currently common wide bandgap semiconductors SiC and GaN, β-Ga2O3 has a larger BaliGa quality factor and a lower expected growth cost, and has greater potential in high-voltage, high-power, high-efficiency, and small-volume electronic devices. However, due to its low thermal conductivity, the prepared β-Ga2O3 device will cause serious degradation of device performance due to the self-heating effect. Regarding the problem of poor thermal conductivity of β-Ga2O3, the thermal conductivity of the device is generally improved by using methods such as substrate thinning, external heat dissipation system, and heterogeneous integration.

[0003] The substrate thinning solution has not been widely used because it can easily cause β-Ga2O3 to break during the thinning process; Wang et al. from Virginia Tech in the United States used silver plates with good thermal conductivity to encapsulate devices, which improved the thermal diffusivity of β-Ga2O3. However, due to the extremely low thermal conductivity of β-Ga2O3, the improvement in thermal conductivity is limited and this problem cannot be fundamentally solved. The best solution to solve the low thermal conductivity of β-Ga2O3 is to use heterogeneous integration technology on high thermal conductivity substrate materials to realize the preparation of heterogeneous β-Ga2O3 devices. To achieve this heterogeneous integration, 4H-SiC with high thermal conductivity is the first choice, but there are many physical mismatch problems between 4H-SiC and β-Ga2O3, such as lattice mismatch, crystal mismatch, mutual diffusion and reverse domain.

[0004] So far, the existing β-Ga2O3 power MOSFETs all have dense electric field distribution in the epitaxial layer below the gate corner, which is very easy to be broken down and has serious electrode leakage, resulting in a pair of contradictory device performance parameters of high breakdown voltage and low on-resistance. In addition, it is difficult to achieve P-type doping because the valence band of Ga2O3 material is too flat and affected by the excessive main ionization energy. Therefore, it is impossible to use a pn junction to effectively block the leakage between the source and drain electrodes like the traditional structure. Summary of the invention

[0005] The object of the present invention is to provide a power MOSFET and a method for preparing the same, so as to solve the problems existing in the above-mentioned prior art.

[0006] To achieve the above object, the present invention provides the following solutions:

[0007] One of the technical solutions of the present invention: a power MOSFET, comprising a substrate layer, an AlN buffer layer, a Ga2O3 buffer layer and a Ga2O3 epitaxial layer arranged from bottom to top;

[0008] Wherein, a groove is provided on the top surface of the Ga2O3 epitaxial layer, and an oxidation isolation layer is provided in the groove;

[0009] The drain electrode is arranged on one side of the Ga2O3 epitaxial layer and is adjacent to the oxidized isolation layer;

[0010] The source electrode is arranged in the middle area of ​​the other side of the Ga2O3 epitaxial layer;

[0011] Symmetrical second grooves are arranged on both sides of the source electrode; the second grooves include inclined surface segments;

[0012] A NiO layer and an insulating gate dielectric layer are disposed on the second trench from bottom to top;

[0013] A gate electrode with a non-planar gate structure is disposed on the insulating gate dielectric layer;

[0014] The second trench and a gap portion around the gate electrode are filled with a first oxide isolation layer.

[0015] Further, the material of the substrate layer includes 4H-SiC;

[0016] 4H-SiC can improve the poor heat dissipation problem of Ga2O3 materials, and its thermal stability is significantly improved compared with MOSFET devices based on the same substrate.

[0017] There are many physical mismatch problems between SiC substrate and Ga2O3, such as lattice mismatch, crystal form mismatch, mutual diffusion and reverse domain, which are not conducive to the growth of Ga2O3 crystals. AlN and Ga2O3, which have the same wide band gap, have low lattice mismatch and thermal mismatch, so they can be used as a buffer layer between SiC and Ga2O3, greatly reducing the defect problems in the device and improving the performance of the device.

[0018] The Ga2O3 buffer layer set in the power MOSFET can reduce the defect density caused by lattice mismatch and improve device performance.

[0019] The insulating gate dielectric layer disposed on the NiO layer can increase the width of the depletion region at the corner of the gate electrode, making the electric field distribution at the corner of the device smoother.

[0020] And / or, the materials of the oxidation isolation layer and the first oxidation isolation layer are both insulating materials such as Al2O3, SiO2 or HfO2;

[0021] The insulating material can isolate the source and drain electrodes to prevent source and drain breakdown.

[0022] And / or, the angle of the bottom corner of the gate electrode is greater than 90° (increasing the angle of the gate corner and the width of the depletion region under the gate), further smoothing the electric field distribution at the corner of the device, making it less susceptible to breakdown, and improving device performance.

[0023] The present invention implants a first oxide isolation layer above the gate electrode, which can effectively block the source and drain electrodes to prevent source and drain breakdown.

[0024] Furthermore, the thickness ratio of the substrate layer, the AlN buffer layer, the Ga2O3 buffer layer and the Ga2O3 epitaxial layer (referring to the maximum thickness of the Ga2O3 epitaxial layer) is 5-10 μm: 50-200 nm: 3-5 μm: 7-10 μm;

[0025] And / or, the substrate layer has a doping concentration of 1×10 18 ~5×10 18 cm -3 n-type highly doped 4H-SiC material;

[0026] And / or, the Ga2O3 buffer layer has a doping concentration of 1.5×10 16 ~4×10 16 cm -3 β-Ga2O3 materials;

[0027] And / or, the Ga2O3 epitaxial layer has a doping concentration of 1×10 16 ~2×10 16 cm -3 n-type highly doped β-Ga2O3 material.

[0028] Furthermore, the thickness ratio of the Ga2O3 epitaxial layer, the NiO layer and the insulating gate dielectric layer is 7-10 μm: 100-300 nm: 20-50 nm;

[0029] And / or, the ratio of the thickness of the second trench (referring to the total thickness of the NiO layer, the insulating gate dielectric layer and the lower part of the gate electrode) to the depth of the trench is (0.6-1): (0.675-8), and the thickness of the second trench is less than the depth of the trench;

[0030] And / or, the NiO layer has a doping concentration of 1×10 17 ~2×10 17 cm -3 P-type heavily doped nickel oxide material (P-NiO material).

[0031] The P-NiO material and the n-type highly doped β-Ga2O3 material used in the present invention can form a pn heterojunction, making the electric field distribution at the corner under the gate more gentle, further improving the voltage resistance of the device, and the P-type doping can effectively block gate leakage, reduce the forward on-resistance of the device, and increase the forward current of the device, thereby obtaining a better power quality factor.

[0032] Furthermore, the depth of the groove is at least 10% of the thickness of the Ga2O3 epitaxial layer, and the depth of the groove is not greater than the thickness of the Ga2O3 epitaxial layer.

[0033] Technical solution 2 of the present invention: A method for preparing the above-mentioned power MOSFET comprises the following steps:

[0034] After cleaning the substrate layer, an AlN buffer layer is grown, followed by a Ga2O3 buffer layer, and then a Ga2O3 epitaxial layer;

[0035] Etching the Ga2O3 epitaxial layer to form a groove;

[0036] depositing an oxide isolation layer in the trench;

[0037] Etching is performed on one side of the trench to form a symmetrical step-like structure, and then etching is continued to form a trapezoidal structure, followed by self-aligned F plasma treatment to form a second trench;

[0038] Depositing a NiO layer material on the Ga2O3 epitaxial layer to form a NiO layer, then etching to form regional openings for source and drain electrodes, then depositing an insulating gate dielectric layer material to form an insulating gate dielectric layer, and etching to form regional openings for source and drain electrodes after deposition;

[0039] Depositing a metal electrode material on the insulating gate dielectric layer of each second trench to form a gate region;

[0040] Depositing an oxide isolation material on the device having the gate region to form a plane, and then etching to form regional openings for the source electrode and the drain electrode and to open the gate region;

[0041] injecting a metal electrode material into the gate region, then depositing a layer of the metal electrode material on the device surface, and forming an alloy layer by stripping;

[0042] The alloy layer is etched to form a source electrode, a drain electrode and a gate electrode to obtain the power MOSFET.

[0043] Furthermore, the method for growing the AlN buffer layer includes a molecular beam epitaxy (PA-MBE) method; the process conditions of the molecular beam epitaxy (PA-MBE) method include:

[0044] Reaction chamber pressure: 10~50uTorr;

[0045] Reaction chamber gases: Al and N2;

[0046] Reaction chamber temperature: 800~1200℃;

[0047] And / or, the method for growing the Ga2O3 buffer layer includes LPCVD; the process conditions of the LPCVD method include:

[0048] Reaction chamber gas: Ar;

[0049] Deposition power: 200~400W.

[0050] And / or, the method for growing the Ga2O3 epitaxial layer includes a pulsed laser deposition method; the process conditions of the pulsed laser deposition method include:

[0051] The target material is (AlGa)2O3;

[0052] The oxygen partial pressure in the chamber is 0.01 to 0.03 mbAr;

[0053] The distance between the sample to be grown and the target material is 4 to 5 cm;

[0054] The growth temperature is 500-800°C;

[0055] The energy density of the laser is 2 to 4 J / cm 2 , the pulse frequency of the laser is 3~5HZ;

[0056] The total number of pulses for film growth is 6000 to 9000.

[0057] Furthermore, the etching method includes ICP etching or RIE etching;

[0058] The process conditions of the ICP etching method include:

[0059] Reaction chamber pressure: 10-30mTorr;

[0060] Reaction chamber gases: BCl3 and Ar;

[0061] Reaction chamber gas flow rate ratio: BCl3:Ar=20sccm:10~15sccm;

[0062] Etching power: 200~400W;

[0063] And / or, the process conditions of the RIE etching method include:

[0064] Reaction chamber pressure: 20-40 mTorr;

[0065] Reaction chamber gases: BCl3 and Ar;

[0066] Reaction chamber gas flow rate ratio: BCl3:Ar=35sccm:5sccm;

[0067] Etching power: 200~400W;

[0068] And / or, the process conditions of the self-aligned F plasma treatment include:

[0069] Reaction chamber pressure: 30mTorr;

[0070] Reaction chamber gas: CF4;

[0071] RF power: 200W;

[0072] Furthermore, the method for depositing the material of the NiO layer is a magnetron sputtering method; the process conditions of the magnetron sputtering method are as follows:

[0073] Nickel-oxygen ratio: 1:1;

[0074] Sputtering gas: Ar;

[0075] Cavity pressure: 2~10Pa;

[0076] Cavity temperature: 80~200℃;

[0077] Sputtering power: 10~100W;

[0078] And / or, the method for depositing the material of the insulating gate dielectric layer and the material of the oxidation isolation is an ALD method; the process conditions of the ALD method are as follows:

[0079] Reaction chamber temperature: 200-300°C;

[0080] Reaction chamber pressure: 800~900Pa;

[0081] Reaction chamber gas: high purity nitrogen;

[0082] Reaction chamber gas flow rate: 300 sccm.

[0083] Technical solution three of the present invention: an application of the above-mentioned power MOSFET in a high-voltage circuit or transformer circuit chip.

[0084] The present invention adopts AlN as a buffer layer to heterogeneously integrate a β-Ga2O3 buffer layer on a SiC substrate, thereby improving the thermal conductivity of Ga2O3; a Ga2O3 buffer layer is grown on the AlN buffer layer to effectively reduce the defect density inside the lattice, and further improve the forward conduction current of the device; through the design of a trapezoidal Fin with an angle greater than 90° at the corner of the gate, the electric field distribution at the corner of the device is smoothed, and the structural problems of the existing β-Ga2O3 MOSFET, such as the dense electric field distribution of the epitaxial layer below the corner of the gate and the easy breakdown, are solved, thereby improving the voltage resistance of the device; a NiO layer is added below the insulating gate dielectric (such as Al2O3) under the gate to block the leakage of the gate electrode, improve the forward conduction current and breakdown voltage of the device, and thus obtain a better power quality factor.

[0085] The present invention discloses the following technical effects:

[0086] (1) The present invention solves the serious problems of heat dissipation and gate electrode leakage in existing similar devices by designing the power MOSFET structure and selecting materials, thereby improving the voltage resistance performance of the device.

[0087] (2) The present invention uses AlN as a buffer layer to heterogeneously integrate a Ga2O3 buffer layer and an epitaxial layer (heterogeneously integrates a β-Ga2O3 field effect transistor) on a high thermal conductivity 4H-SiC substrate, which fundamentally solves the problem of severe self-heating effect of β-Ga2O3 devices, greatly improves the voltage resistance of the device, and solves the problem of poor heat dissipation performance of β-Ga2O3 field effect transistors. The present invention can be used to manufacture high-voltage circuits and transformer circuit chips.

[0088] (3) The present invention uses AlN, which has low lattice mismatch and thermal mismatch with Ga2O3, as a buffer layer to better grow β-Ga2O3 crystals, thereby solving the problem of the difficulty in directly growing β-Ga2O3 crystals on a 4H-SiC substrate and better improving the thermal conductivity of the device.

[0089] (4) The present invention adopts a non-planar gate structure, which increases the width of the depletion region at the corner of the trench gate oxide layer, making the electric field distribution at the corner of the device smoother, further improving the reliability and voltage resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0090] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0091] Figure 11 is a schematic diagram of the structure of a power MOSFET, wherein 100 is a substrate layer, 101 is an AlN buffer layer, 102 is a Ga2O3 buffer layer, 103 is a Ga2O3 epitaxial layer, 104 is an oxide isolation layer, 105 is a NiO layer, 106 is an insulating gate dielectric layer, 107 is a gate electrode, 108 is a source electrode, and 109 is a drain electrode;

[0092] Figure 2 1 is a schematic diagram of the preparation process of a power MOSFET, wherein 100 is a substrate layer, 101 is an AlN buffer layer, 102 is a Ga2O3 buffer layer, 103 is a Ga2O3 epitaxial layer, 104 is an oxide isolation layer, 105 is a NiO layer, and 106 is an insulating gate dielectric layer;

[0093] Figure 3 1 is a schematic diagram of the preparation process of a power MOSFET, wherein 100 is a substrate layer, 101 is an AlN buffer layer, 102 is a Ga2O3 buffer layer, 103 is a Ga2O3 epitaxial layer, 104 is an oxide isolation layer, 105 is a NiO layer, 106 is an insulating gate dielectric layer, 107 is a gate electrode, 108 is a source electrode, 109 is a drain electrode, and 104-1 is a first oxide isolation layer;

[0094] Figure 4 The on-resistance variation curves of the power MOSFET device (with 4H-SiC substrate) and the device without substrate prepared in Example 1 with temperature;

[0095] Figure 5 The transfer characteristic curves of the power MOSFET device prepared in Example 2 and the device without the NiO layer;

[0096] Figure 6 The breakdown characteristic curve of the power MOSFET device prepared in Example 3;

[0097] Figure 7 This is the breakdown characteristic curve of a MOSFET device without a Ga2O3 buffer layer. DETAILED DESCRIPTION

[0098] Various exemplary embodiments of the present invention will now be described in detail. This detailed description should not be considered as limiting the present invention, but should be understood as a more detailed description of certain aspects, features, and embodiments of the present invention.

[0099] It should be understood that the terms described in the present invention are only for describing special embodiments and are not intended to limit the present invention. In addition, for the numerical range in the present invention, it should be understood that each intermediate value between the upper and lower limits of the scope is also specifically disclosed. Each smaller range between the intermediate value in any stated value or stated range and any other stated value or intermediate value in the described range is also included in the present invention. The upper and lower limits of these smaller ranges can be independently included or excluded in the scope.

[0100] Unless otherwise indicated, all technical and scientific terms used herein have the same meanings as those generally understood by those skilled in the art. Although the present invention describes only preferred methods and materials, any methods and materials similar or equivalent to those described herein may also be used in the implementation or testing of the present invention. All documents mentioned in this specification are incorporated by reference to disclose and describe the methods and / or materials associated with the documents. In the event of a conflict with any incorporated document, the content of this specification shall prevail.

[0101] It will be apparent to those skilled in the art that various modifications and variations may be made to the specific embodiments of the present invention description without departing from the scope or spirit of the present invention. Other embodiments derived from the present invention description will be apparent to the skilled artisan. The present invention description and examples are exemplary only.

[0102] The words “include,” “including,” “have,” “contain,” etc. used in this document are open-ended terms, meaning including but not limited to.

[0103] The “parts” described in the following examples are all “parts by weight”.

[0104] In a first aspect of the present invention, a power MOSFET is provided, comprising a substrate layer 100, an AlN buffer layer 101, a Ga2O3 buffer layer 102 and a Ga2O3 epitaxial layer 103 arranged from bottom to top;

[0105] Wherein, a groove is provided on the top surface of the Ga2O3 epitaxial layer 103, and an oxidized isolation layer 104 is provided in the groove;

[0106] The drain electrode 109 is disposed on one side of the Ga2O3 epitaxial layer 103 and is adjacent to the oxidized isolation layer 104;

[0107] The source electrode 108 is disposed in the middle region of the other side of the Ga2O3 epitaxial layer 103;

[0108] The source electrode 108 is provided with second grooves on both sides; the second grooves include inclined surface segments;

[0109] A NiO layer 105 and an insulating gate dielectric layer 106 are disposed on the second trench from bottom to top;

[0110] A gate electrode 107 with a non-planar gate structure is arranged on the insulating gate dielectric layer (106);

[0111] The second trench and the gap around the gate electrode (107) are partially filled with a first oxide isolation layer.

[0112] The schematic diagram of the power MOSFET is shown in Figure 1 .

[0113] A second aspect of the present invention provides a method for preparing a power MOSFET, comprising the following steps:

[0114] (1) Cleaning the 4H-SiC substrate and growing the AlN buffer layer:

[0115] For a doping concentration of 1×10 18 ~5×10 18 cm -3 The n-type highly doped 4H-SiC material is in-situ cleaned, and then immersed in a mixed solution of HCl:H2O2:H2O with a volume ratio of 5:3:3 at 60°C to completely oxidize its surface; then the substrate is immersed in a mixed solution of NiO:HF with a volume ratio of 10:1 to remove the generated oxide layer, and a substrate layer 100 ( Figure 2 (a)). Subsequently, a 50-200 nm AlN buffer layer 101 is grown by molecular beam epitaxy (PA-MBE) at a substrate temperature of 750°C. Figure 2 (b) Figure ).

[0116] Molecular beam epitaxy PA-MBE method, process conditions include:

[0117] Reaction chamber pressure: 10~50uTorr;

[0118] Reaction chamber gases: Al and N2;

[0119] Reaction chamber temperature: 800~1200℃.

[0120] (2) Growing a Ga2O3 buffer layer 102 on the AlN buffer layer 101:

[0121] The quartz boat was placed in deionized water, acetone solution, deionized water, anhydrous ethanol solution and deionized water for ultrasonic cleaning for 15 min, then placed in a beaker, filled with deionized water and stored for later use; the LPCVD method was used with a doping concentration of 1.5×10 16 ~4×10 16 cm -3A Ga2O3 buffer layer 102 with a thickness of 3 to 5 μm is grown on the AlN buffer layer 101 using the β-Ga2O3 material. The grown sample is dried with nitrogen and stored for later use ( Figure 2 (c) Figure ).

[0122] The process conditions of LPCVD method include:

[0123] Reaction chamber gas: Ar;

[0124] Deposition power: 200~400W.

[0125] (3) Growing a Ga2O3 epitaxial layer 103 on the Ga2O3 buffer layer 102:

[0126] The sample grown in step (2) was placed in the reaction chamber of the device and a pulsed laser deposition method was used with a doping concentration of 1×10 16 ~2×10 16 cm -3 A Ga2O3 epitaxial layer 103 with a thickness of 7 to 10 μm is grown on the Ga2O3 buffer layer 102 ( Figure 2 (d) Figure ).

[0127] The pulsed laser deposition method, the process conditions include:

[0128] The target material is (AlGa)2O3;

[0129] The oxygen partial pressure in the chamber is 0.01 to 0.03 mbAr;

[0130] The distance between the sample to be grown and the target material is 4 to 5 cm;

[0131] The growth temperature is 500-800°C;

[0132] The energy density of the laser is 2 to 4 J / cm 2 , the pulse frequency of the laser is 3~5HZ;

[0133] The total number of pulses for film growth is 6000 to 9000.

[0134] (4) Etching grooves:

[0135] A photoresist is applied on the Ga2O3 epitaxial layer 103, and a region to be etched is obtained by photolithography along the middle of the Ga2O3 epitaxial layer 103. The Ga2O3 epitaxial layer 103 after photolithography is then placed in the cavity of an inductively coupled plasma ICP system, and a groove with a depth of 1.0 to 5.8 μm and a length of 440 to 500 nm is etched in the region to be etched ( Figure 2 (e) Figure ).

[0136] (5) Oxidation isolation layer 104 injection:

[0137] The device is placed in an atomic layer deposition (ALD) system, and an insulating material is deposited in the groove in the middle of the epitaxial layer formed by etching in the above step (4) to fill the groove with the insulating material. The epitaxial layer after the oxide isolation layer is implanted is photolithographically processed, and the device after photolithography is placed in the cavity of an inductively coupled plasma (ICP) system to etch the oxide isolation material deposited outside the groove to obtain an oxide isolation layer 104 ( Figure 2 (f) Figure ).

[0138] In a specific embodiment of the present invention, the insulating material includes Al2O3, SiO2 or HfO2.

[0139] (6) Etching the fin groove area:

[0140] A photoresist is applied on the Ga2O3 epitaxial layer 103 on one side of the groove, and a region to be etched is obtained by photolithography along the Ga2O3 epitaxial layer 103. Then, the device after photolithography is placed in the chamber of the inductively coupled plasma ICP system, and a fin groove is etched in the region to be etched ( Figure 2 (g) Figure ).

[0141] (7) Etching the groove area:

[0142] Photoresist is applied to the left and right sides of the fin groove formed in the above step (6), and the area to be etched is obtained by photolithography. Then, the device after photolithography is placed in the chamber of the inductively coupled plasma ICP system, and the grooves on both sides of the fin structure are etched in the area to be etched to form a symmetrical stepped structure (see Figure 2 (h) Figure ).

[0143] (8) Engraving inclined table:

[0144] The device structure is placed in a plasma etcher RIE, and BCl3 gas is used to perform bevel etching with the anode metal as a mask (bevel depth is 0.6-1 μm, bevel angle is 80-85°), and then self-aligned F plasma treatment is performed to obtain the second groove ( Figure 2 (i) Figure ).

[0145] The process conditions of RIE include:

[0146] Reaction chamber pressure: 20-40 mTorr;

[0147] Reaction chamber gases: BCl3 and Ar;

[0148] Reaction chamber gas flow rate ratio: BCl3:Ar=35sccm:5sccm;

[0149] Etching power: 200~400W.

[0150] Self-aligned F plasma treatment, process conditions include:

[0151] Reaction chamber pressure: 30mTorr;

[0152] Reaction chamber gas: CF4;

[0153] RF power: 200W.

[0154] (9) Deposition of NiO layer 105:

[0155] The etched device is placed in the chamber of the magnetron sputtering system, and a layer of P-type NiO material with a thickness of 100 to 300 nm (doping concentration of 1×10 17 ~2×10 17 cm -3 P-type heavily doped nickel oxide material) to form a NiO layer 105 ( Figure 2 (j) Figure ).

[0156] (10) Open holes in the source and drain electrode regions:

[0157] The sputtered epitaxial layer is photolithographically processed to form opening patterns in the source and drain electrode regions; the photolithographically processed device is then placed in the chamber of the inductively coupled plasma (ICP) system to etch and form openings in the source and drain electrode regions ( Figure 2 (k) Figure ).

[0158] (11) Depositing the insulating gate dielectric layer 106:

[0159] The device after opening is placed in an atomic layer deposition ALD system, and a layer of insulating gate dielectric material (such as Al2O3) with a thickness of 20 to 50 nm is deposited to form an insulating gate dielectric layer 106 ( Figure 2 (l) Figure); Repeat the above step (10) for the deposited device to finally form openings in the source and drain electrode regions ( Figure 3 (m) Figure).

[0160] (12) Growth gate:

[0161] The insulating gate dielectric layer 106 of each second groove is photolithographically processed to form a gate region pattern, and then placed in the chamber of the magnetron sputtering system. A layer of metal Ti with a thickness of 10 nm is deposited on the insulating gate dielectric layer 106, and then a layer of Au with a thickness of 20 nm is deposited. The gate region ( Figure 3 (m) Figure).

[0162] (13) Oxidation isolation layer injection:

[0163] The device obtained in step (12) is placed in an atomic layer deposition ALD system to deposit an insulating material (the insulating material includes Al2O3, SiO2 or HfO2) so that the insulating material fills the second trench and covers the epitaxial layer to form a first oxide isolation layer 104-1 ( Figure 3 (n) Figure).

[0164] (14) Open holes in the source and drain electrode regions and open the gate region:

[0165] The epitaxial layer after the oxide isolation layer is implanted is photolithographically processed to form the source, drain, and gate electrode region opening patterns; the photolithographic device is then placed inside the inductively coupled plasma ICP system cavity, and the source and drain electrode region openings are etched, and the connection ports between the gates on both sides and the outside are etched (see Figure 3 (o) Figure).

[0166] (15) Gate metal alloy injection:

[0167] The etched device is placed in an atomic layer deposition (ALD) system, and metal Ti and metal Au with a thickness ratio of (60-80): (120-140) are deposited at the connection points between the gates on both sides and the outside world. Metal Ti is deposited first, and then metal Au is deposited (filling the entire gate area). The deposited epitaxial layer is photolithographically processed, and the photolithographic device is placed in the cavity of an inductively coupled plasma (ICP) system to etch away the Ti / Au alloy deposited outside the gate area. Figure 3 (p) Figure).

[0168] (16) Deposition of alloy layer:

[0169] The etched device is placed in an electron beam evaporation E-Beam system, and a layer of metal Ti with a thickness of 60 to 80 nm is first deposited, and then a layer of metal Au with a thickness of 120 to 140 nm is deposited. The device after electron beam evaporation is then placed in a stripping solution to form an alloy layer ( Figure 3 (q) graph).

[0170] (17) Etching the alloy layer to form source, drain and gate electrodes:

[0171] The device surface after the alloy layer is deposited is photolithographically processed to form opening patterns in other regions except the source, drain and gate regions. The photolithographically processed device is then placed in the chamber of the inductively coupled plasma (ICP) system and etched to finally form a source electrode 108, a drain electrode 109 and a gate electrode 107. The device is then fabricated to obtain a power MOSFET ( Figure 3 (r) Figure).

[0172] The angle at the bottom corner of the gate electrode is greater than 90°.

[0173] The process conditions of the inductively coupled plasma ICP in steps (4), (5), (6), (7), (10), (11), (14), (15), and (17) include:

[0174] Reaction chamber pressure: 10-30mTorr;

[0175] Reaction chamber gases: BCl3 and Ar;

[0176] Reaction chamber gas flow rate ratio: BCl3:Ar=20sccm:10~15sccm;

[0177] Etching power: 200~400W;

[0178] The process conditions of magnetron sputtering in step (9) include:

[0179] Nickel-oxygen ratio: 1:1;

[0180] Sputtering gas: Ar;

[0181] Cavity pressure: 2~10Pa;

[0182] Cavity temperature: 80~200℃;

[0183] Sputtering power: 10~100W;

[0184] The process conditions of the ALD method in steps (5), (11), (13) and (15) include:

[0185] Reaction chamber temperature: 200-300°C;

[0186] Reaction chamber pressure: 800~900Pa;

[0187] Reaction chamber gas: high purity nitrogen;

[0188] Reaction chamber gas flow rate: 300 sccm.

[0189] A third aspect of the present invention provides an application of the above-mentioned power MOSFET in a high voltage circuit or a transformer circuit chip.

[0190] Example 1

[0191] A method for preparing a power MOSFET:

[0192] (1) Cleaning the 4H-SiC substrate and growing the AlN buffer layer 101:

[0193] The doping concentration is 2.5×10 18 cm -3The n-doped 4H-SiC substrate was in-situ cleaned, and then immersed in a mixed solution of HCl:H2O2:H2O with a volume ratio of 5:3:3 at 60°C to completely oxidize its surface; then the substrate was immersed in a mixed solution of NiO:HF with a volume ratio of 10:1 to remove the generated oxide layer, and obtain a substrate layer 100 with a thickness of 9μm. Subsequently, a 100nm AlN buffer layer 101 was grown by molecular beam epitaxy PA-MBE method at a substrate temperature of 750°C. After the growth, it was placed in a beaker, poured with deionized water to cover it, and sealed for later use ( Figure 2 (a) and (b) of Figure 3).

[0194] Molecular beam epitaxy PA-MBE method, the process conditions are as follows:

[0195] Reaction chamber pressure: 10uTorr;

[0196] Reaction chamber gases: Al and N2;

[0197] Reaction chamber temperature: 850°C;

[0198] (2) Growing a Ga2O3 buffer layer 102 on the AlN buffer layer 101:

[0199] The quartz boat was placed in deionized water, acetone solution, deionized water, anhydrous ethanol solution and deionized water for ultrasonic cleaning for 15 min each, then placed in a beaker, filled with deionized water and kept for later use; the LPCVD method was used to dope the quartz boat with a concentration of 3×10 16 cm -3 The Ga2O3 buffer layer 102 with a thickness of 3.3 μm is grown from the β-Ga2O3 material, and the grown sample is dried with nitrogen and stored for later use ( Figure 2 (c) Figure ).

[0200] The process conditions of the LPCVD method are as follows:

[0201] Reaction chamber gas: Ar;

[0202] Deposition power: 400W.

[0203] (3) Growing a Ga2O3 epitaxial layer 103 on the Ga2O3 buffer layer 102:

[0204] The sample grown in step (2) was placed in the reaction chamber of the device and a doping concentration of 2×10 16 cm -3 The n-type highly doped β-Ga2O3 material is grown on the substrate to form a Ga2O3 epitaxial layer 103 with a thickness of 8.8 μm ( Figure 2 (d) Figure ).

[0205] The pulse laser deposition method has the following process conditions:

[0206] The target material is (AlGa)2O3;

[0207] The oxygen partial pressure in the chamber is 0.01 mbAr;

[0208] The distance between the sample to be grown and the target material is 4 cm;

[0209] The growth temperature is 500°C;

[0210] The energy density of the laser is 2J / cm 2 , the pulse frequency of the laser is 5HZ;

[0211] The total number of pulses for film growth was 9000.

[0212] (4) Etching grooves:

[0213] A photoresist is applied on the Ga2O3 epitaxial layer 103, and the region to be etched is obtained by photolithography along the middle of the epitaxial layer. The epitaxial layer after photolithography is then placed in the cavity of the inductively coupled plasma ICP system, and a groove with a depth of 5.8 μm and a length of 500 nm is etched in the region to be etched ( Figure 2 (e) Figure ).

[0214] Inductively coupled plasma ICP, the process conditions are as follows:

[0215] Reaction chamber pressure: 10mTorr;

[0216] Reaction chamber gases: BCl3 and Ar;

[0217] Reaction chamber gas flow rate ratio: BCl3:Ar=20sccm:10sccm;

[0218] Etching power: 300W.

[0219] (5) Oxidation isolation layer 104 injection:

[0220] The device is placed in an atomic layer deposition (ALD) system, and a layer of Al2O3 with a thickness of 5.8 μm is deposited in the groove formed by etching in the above step (4). The epitaxial layer after the oxide isolation layer is implanted is photolithographically processed, and the device after photolithography is placed in the chamber of an inductively coupled plasma (ICP) system, and the oxide isolation material deposited outside the groove is etched away to form an oxide isolation layer 104 ( Figure 2 (f) Figure ).

[0221] Atomic layer deposition ALD, the process conditions are as follows:

[0222] Reaction chamber temperature: 300°C;

[0223] Reaction chamber pressure: 900Pa;

[0224] Reaction chamber gas: high purity nitrogen;

[0225] Reaction chamber gas flow rate: 300 sccm.

[0226] Inductively coupled plasma ICP, the process conditions are as follows:

[0227] Reaction chamber pressure: 30mTorr

[0228] Reaction chamber gases: BCl3 and Ar;

[0229] Reaction chamber gas flow rate ratio: BCl3:Ar=20sccm:15sccm;

[0230] Etching power: 300W.

[0231] (6) Etching the fin groove area:

[0232] A photoresist is applied on the Ga2O3 epitaxial layer 103, and the area to be etched is obtained by photolithography along the left side of the epitaxial layer. Then, the epitaxial layer after photolithography is placed in the cavity of the inductively coupled plasma ICP system, and the fin groove is etched with a depth of 100 nm in the area to be etched ( Figure 2 (g) Figure ).

[0233] Inductively coupled plasma ICP, the process conditions are as follows:

[0234] Reaction chamber pressure: 20mTorr;

[0235] Reaction chamber gases: BCl3 and Ar;

[0236] Reaction chamber gas flow rate ratio: BCl3:Ar=20sccm:15sccm;

[0237] Etching power: 300W.

[0238] (7) Etching the groove area:

[0239] Photoresist is applied to the left and right sides of the fin groove formed in the above step (6), and the area to be etched is obtained by photolithography. Then, the device after photolithography is placed in the chamber of the inductively coupled plasma ICP system, and the grooves on both sides of the fin structure are etched in the area to be etched to form a symmetrical stepped structure ( Figure 2 (h) Figure ).

[0240] Inductively coupled plasma ICP, the process conditions are as follows:

[0241] Reaction chamber pressure: 20mTorr;

[0242] Reaction chamber gases: BCl3 and Ar;

[0243] Reaction chamber gas flow rate ratio: BCl3:Ar=20sccm:15sccm;

[0244] Etching power: 250W.

[0245] (8) Engraving inclined table:

[0246] The device structure is placed in a plasma etcher RIE, and BCl3 gas is used to perform bevel etching with the anode metal as a mask (bevel depth is 800nm, bevel angle is 85°), and then self-aligned F plasma treatment is performed to obtain the second groove ( Figure 2 (i) Figure ).

[0247] The process conditions of RIE are as follows:

[0248] Reaction chamber pressure: 30mTorr;

[0249] Reaction chamber gases: BCl3 and Ar;

[0250] Reaction chamber gas flow rate ratio: BCl3:Ar=35sccm:5sccm;

[0251] Etching power: 200W.

[0252] Self-aligned F plasma treatment, the process conditions are as follows:

[0253] Reaction chamber pressure: 30mTorr;

[0254] Reaction chamber gas: CF4;

[0255] RF power: 200W.

[0256] (9) Deposition of NiO layer 105:

[0257] The etched device was placed in the chamber of the magnetron sputtering system, and a layer of P-type NiO material with a thickness of 200 nm (doping concentration of 1.5×10 17 cm -3 P-type heavily doped nickel oxide material) to form a NiO layer 105 ( Figure 2 (j) Figure ).

[0258] Magnetron sputtering, process conditions are as follows:

[0259] Nickel-oxygen ratio: 1:1;

[0260] Sputtering gas: Ar;

[0261] Cavity pressure: 7Pa;

[0262] Cavity temperature: 90℃;

[0263] Sputtering power: 80W.

[0264] (10) Open holes in the source and drain electrode regions:

[0265] The sputtered epitaxial layer is photolithographically processed to form opening patterns in the source and drain electrode regions; the photolithographically processed device is then placed in the chamber of the inductively coupled plasma (ICP) system to etch and form openings in the source and drain electrode regions ( Figure 2 (k) Figure ).

[0266] Inductively coupled plasma ICP, the process conditions are as follows:

[0267] Reaction chamber pressure: 30mTorr;

[0268] Reaction chamber gases: BCl3 and Ar;

[0269] Reaction chamber gas flow rate ratio: BCl3:Ar=20sccm:15sccm;

[0270] Etching power: 300W.

[0271] (11) Deposition of insulating gate dielectric layer 106

[0272] The device with the hole opened is placed in an atomic layer deposition ALD system to deposit a layer of Al2O3 dielectric with a thickness of 30nm to form an insulating gate dielectric layer 106 ( Figure 2 (l) Figure); Repeat the above step 10 for the deposited epitaxial layer, and finally form the source and drain electrode regions ( Figure 3 (m) Figure).

[0273] Atomic layer deposition ALD, the process conditions are as follows:

[0274] Reaction chamber temperature: 300°C;

[0275] Reaction chamber pressure: 900Pa;

[0276] Reaction chamber gas: high purity nitrogen;

[0277] Reaction chamber gas flow rate: 300 sccm.

[0278] Inductively coupled plasma ICP, the process conditions are as follows:

[0279] Reaction chamber pressure: 30mTorr;

[0280] Reaction chamber gases: BCl3 and Ar;

[0281] Reaction chamber gas flow rate ratio: BCl3:Ar=20sccm:15sccm;

[0282] Etching power: 300W.

[0283] (12) Growth gate:

[0284] The insulating gate dielectric layer 106 of each second trench is photolithographically processed to form a gate region pattern, and then placed in the chamber of the magnetron sputtering system, and a layer of metal Ti with a thickness of 10 nm is first deposited on the Al2O3 dielectric layer, and then a layer of metal Au with a thickness of 20 nm is deposited, and the metal Ti and Au outside the gate region are removed by etching to form a gate region ( Figure 3 (m) Figure).

[0285] The process conditions of magnetron sputtering include:

[0286] Sputtering gas: Ar;

[0287] Cavity pressure: 7Pa;

[0288] Cavity temperature: 150℃;

[0289] Sputtering power: 80W.

[0290] (13) Oxide isolation layer injection

[0291] The device obtained in step (12) is placed in an atomic layer deposition ALD system, and insulating material (the insulating material includes Al2O3) is deposited again, so that the insulating material fills the second trench and covers the epitaxial layer to form a first oxide isolation layer 104-1 ( Figure 3 (n) Figure)

[0292] Atomic layer deposition ALD, the process conditions are as follows:

[0293] Reaction chamber temperature: 200°C;

[0294] Reaction chamber pressure: 800Pa;

[0295] Reaction chamber gas: high purity nitrogen;

[0296] Reaction chamber gas flow rate: 300 sccm.

[0297] (14) Open holes in the source and drain electrode regions and open the gate region:

[0298] The epitaxial layer after the oxide isolation layer is implanted is photolithographically processed to form the source, drain, and gate electrode region opening patterns; the photolithographic device is then placed in the chamber of the inductively coupled plasma ICP system, and the source and drain electrode regions are etched to form openings, and the gate region is etched (see Figure 3 (o) Figure).

[0299] Inductively coupled plasma ICP, the process conditions are as follows:

[0300] Reaction chamber pressure: 30mTorr;

[0301] Reaction chamber gases: BCl3 and Ar;

[0302] Reaction chamber gas flow rate ratio: BCl3:Ar=20sccm:15sccm;

[0303] Etching power: 200W.

[0304] (15) Gate metal alloy injection:

[0305] The etched device is placed in an atomic layer deposition (ALD) system, and metal Ti and metal Au with a thickness ratio of 1:2 are deposited at the connection points between the gates on both sides and the outside world. Metal Ti is deposited first, and then metal Au is deposited (filling the entire gate area). The deposited epitaxial layer is photolithographically processed, and the photolithographic device is placed in the cavity of an inductively coupled plasma (ICP) system to etch away the Ti / Au alloy deposited outside the gate area. ( Figure 3 (p) Figure).

[0306] Atomic layer deposition ALD, the process conditions are as follows:

[0307] Reaction chamber temperature: 300°C;

[0308] Reaction chamber pressure: 900Pa;

[0309] Reaction chamber gas: high purity nitrogen;

[0310] Reaction chamber gas flow rate: 300 sccm.

[0311] Inductively coupled plasma ICP, the process conditions are as follows:

[0312] Reaction chamber pressure: 20mTorr;

[0313] Reaction chamber gases: BCl3 and Ar;

[0314] Reaction chamber gas flow rate ratio: BCl3:Ar=20sccm:10sccm;

[0315] Etching power: 300W.

[0316] (16) Deposition of alloy layer:

[0317] The etched device is placed in an electron beam evaporation E-Beam system to deposit a layer of metal Ti with a thickness of 10nm, and then a layer of metal Au with a thickness of 20nm. The device after electron beam evaporation is then placed in a stripping solution to form an alloy layer ( Figure 3 (q) graph).

[0318] Electron beam evaporation E-Beam, the process conditions are as follows:

[0319] Reaction chamber pressure: 5uTorr.

[0320] (17) Etching the alloy layer to form source, drain and gate electrodes:

[0321] The device surface after the alloy layer is deposited is photolithographically processed to form opening patterns in other regions except the source, drain and gate regions. The photolithographically processed device is then placed in the chamber of the inductively coupled plasma (ICP) system and etched to finally form a source electrode 108, a drain electrode 109 and a gate electrode 107. The device is then fabricated to obtain a power MOSFET ( Figure 3 (r) Figure).

[0322] Inductively coupled plasma ICP, the process conditions are as follows:

[0323] Reaction chamber pressure: 30mTorr;

[0324] Reaction chamber gases: BCl3 and Ar;

[0325] Reaction chamber gas flow rate ratio: BCl3:Ar=20sccm:15sccm;

[0326] Etching power: 300W.

[0327] Example 2

[0328] A method for preparing a power MOSFET:

[0329] (1) Cleaning the 4H-SiC substrate and growing the AlN buffer layer 101:

[0330] For a thickness of 10 μm and a doping concentration of 2.5×10 18 cm -3 The n-doped 4H-SiC substrate was in-situ cleaned, and then immersed in a mixed solution of HCl:H2O2:H2O with a volume ratio of 5:3:3 at 60°C to completely oxidize its surface; then the substrate was immersed in a mixed solution of NiO:HF with a volume ratio of 10:1 to remove the generated oxide layer, and obtain a substrate layer 100 with a thickness of 9μm. Subsequently, a 200nm AlN buffer layer 101 was grown by molecular beam epitaxy PA-MBE method at a substrate temperature of 750°C. After the growth, it was placed in a beaker, poured with deionized water to cover it, and sealed for storage.

[0331] The remaining steps are the same as in Example 1.

[0332] Example 3

[0333] A method for preparing a power MOSFET:

[0334] (1) Cleaning the 4H-SiC substrate and growing the AlN buffer layer 101: Same as in Example 1.

[0335] (2) Growing a Ga2O3 buffer layer 102 on the AlN buffer layer 101:

[0336] The quartz boat was placed in deionized water, acetone solution, deionized water, anhydrous ethanol solution and deionized water for ultrasonic cleaning for 15 min each, then placed in a beaker, filled with deionized water and kept for later use; the LPCVD method was used to dope the quartz boat with a concentration of 3×10 16 cm -3 The Ga2O3 buffer layer 102 with a thickness of 4.3 μm is grown from the β-Ga2O3 material, and the grown sample is dried with nitrogen and stored for later use.

[0337] The process conditions of the LPCVD method are as follows:

[0338] Reaction chamber gas: Ar;

[0339] Deposition power: 300W.

[0340] (3) Growing a Ga2O3 epitaxial layer 103 on the Ga2O3 buffer layer 102: Same as Example 1.

[0341] (4) Etching grooves: same as in Example 1.

[0342] (5) Injection of oxidation isolation layer 104: Same as in Example 1.

[0343] (6) Etching the fin groove area: same as in Example 1.

[0344] (7) Etching the groove area: same as in Example 1.

[0345] (8) Carving an inclined table top: same as in Example 1.

[0346] (9) Deposition of NiO layer 105:

[0347] The etched device was placed in the chamber of the magnetron sputtering system, and a layer of P-type NiO material with a thickness of 300 nm (doping concentration of 1.5×10 17 cm -3 P-type heavily doped nickel oxide material) to form a NiO layer 105 ( Figure 2 (j) Figure ).

[0348] Magnetron sputtering, process conditions are as follows:

[0349] Nickel-oxygen ratio: 1:1;

[0350] Sputtering gas: Ar;

[0351] Cavity pressure: 8Pa;

[0352] Cavity temperature: 90℃;

[0353] Sputtering power: 80W.

[0354] (10) Opening holes in the source and drain electrode regions: same as in Example 1.

[0355] (11) Depositing an insulating gate dielectric layer 106: Same as in Example 1.

[0356] (12) Gate growth: same as in Example 1.

[0357] (13) Oxidation isolation layer injection: same as in Example 1.

[0358] (14) Open holes in the source and drain electrode regions and open the gate region:

[0359] The epitaxial layer after the oxide isolation layer is implanted is photolithographically processed to form the source, drain, and gate electrode region opening patterns; the photolithographic device is then placed in the chamber of the inductively coupled plasma ICP system, and the source and drain electrode regions are etched to form openings, and the gate region is etched (see Figure 3 (o) Figure).

[0360] Inductively coupled plasma ICP, the process conditions are as follows:

[0361] Reaction chamber pressure: 30mTorr;

[0362] Reaction chamber gases: BCl3 and Ar;

[0363] Reaction chamber gas flow rate ratio: BCl3:Ar=20sccm:15sccm;

[0364] Etching power: 300W.

[0365] (15) Gate metal alloy injection:

[0366] The etched device is placed in an atomic layer deposition (ALD) system, and metal Ti and metal Au with a thickness ratio of 1:2 are deposited at the connection points between the gates on both sides and the outside world. Metal Ti is deposited first, and then metal Au is deposited (filling the entire gate area). The deposited epitaxial layer is photolithographically processed, and the photolithographic device is placed in the cavity of an inductively coupled plasma (ICP) system to etch away the Ti / Au alloy deposited outside the gate area.

[0367] Atomic layer deposition ALD, the process conditions are as follows:

[0368] Reaction chamber temperature: 250°C;

[0369] Reaction chamber pressure: 850Pa;

[0370] Reaction chamber gas: high purity nitrogen;

[0371] Reaction chamber gas flow rate: 300 sccm.

[0372] Inductively coupled plasma ICP, the process conditions are as follows:

[0373] Reaction chamber pressure: 25mTorr;

[0374] Reaction chamber gases: BCl3 and Ar;

[0375] Reaction chamber gas flow rate ratio: BCl3:Ar=20sccm:10~15sccm;

[0376] Etching power: 300W.

[0377] The remaining steps are the same as in Example 1.

[0378] Effect Example 1

[0379] The power MOSFET device (with 4H-SiC substrate) and the device without substrate prepared in Example 1 were simulated by sentaurus TCAD software, and the on-resistance was extracted at different temperatures. The results are shown in Figure 4 .

[0380] Preparation method of a device without substrate: The same as Example 1, except that there is no 4H-SiC substrate, and a Ga2O3 buffer layer is grown on a cleaned AlN substrate; wherein the cleaning method of the AlN substrate is: in-situ cleaning of the AlN substrate, and then immersing it in a mixed solution of HCl:H2O2:H2O with a volume ratio of 5:3:3 at 60°C to completely oxidize its surface; then immersing the substrate in a mixed solution of NiO:HF with a volume ratio of 10:1 to remove the generated oxide layer, thereby obtaining an AlN substrate with a thickness of 100 nm.

[0381] from Figure 4 It can be seen that with the increase of T, the Ron(T) / Ron(1100K) of all devices show a strict upward trend, but in the temperature range from 1100K to 2000K, compared with the device without substrate, the Ron(T) / Ron(1100K) of the device with 4H-SiC substrate prepared in Example 1 increases slowly. Therefore, the performance of the heterogeneously integrated gallium oxide MOSFET using 4H-SiC substrate is more stable and has good heat dissipation capability.

[0382] Effect Example 2

[0383] The power MOSFET device (with NiO layer) and the device without NiO layer prepared in Example 2 were simulated by using sentaurus TCAD software to obtain the transfer characteristic curves of the two groups of devices. Figure 5 .

[0384] Preparation method of a device without a NiO layer: The same as Example 2, except that the NiO layer is not deposited, and an insulating gate dielectric layer is directly deposited on the surface of the epitaxial layer (ie, steps (9) and (10) are not performed).

[0385] from Figure 5 It can be seen that the threshold voltage of the MOSFET with a NiO layer is -0.613V, which is a normally-on device; while the threshold voltage of the MOSFET without a NiO layer is 1.236V, which is a normally-off device. Compared with the MOSFET with a NiO layer, the carrier concentration in the source and drain channels is lower when the gate voltage is 0V. Therefore, the addition of the NiO layer can increase the carrier concentration in the device channel when the gate voltage is 0V, thereby increasing the forward conduction current and reducing the forward conduction resistance.

[0386] Effect Example 3

[0387] The power MOSFET devices prepared in Example 3 (with a gallium oxide buffer layer) and without a gallium oxide buffer layer were simulated using sentaurus TCAD software to obtain breakdown characteristic curves of the two groups of devices. Figure 6 and Figure 7 .

[0388] Preparation method of a device without a gallium oxide buffer layer: Same as Example 3, except that a Ga2O3 buffer layer is not grown on the AlN buffer layer, but a Ga2O3 epitaxial layer is grown directly on the AlN buffer layer (ie, step (2) is not performed).

[0389] from Figure 6 It can be seen that the breakdown voltage of the MOSFET with a gallium oxide buffer layer prepared in Example 3 is 3855V; Figure 7 It can be seen that the breakdown voltage of the MOSFET without a gallium oxide buffer layer is 2921 V. Therefore, the gallium oxide buffer layer can effectively improve the voltage resistance of the device.

[0390] The above effect examples are all based on the situation that the oxidized isolation layer 104 and the first oxidized isolation layer 104 - 1 are not implanted in the simulated device.

[0391] The embodiments described above are only descriptions of the preferred modes of the present invention, and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A power MOSFET, characterized in that: It includes a substrate layer, an AlN buffer layer, a Ga2O3 buffer layer and a Ga2O3 epitaxial layer arranged from bottom to top; Wherein, a groove is provided on the top surface of the Ga2O3 epitaxial layer, and an oxidation isolation layer is provided in the groove; The drain electrode is arranged on one side of the Ga2O3 epitaxial layer and is adjacent to the oxidized isolation layer; The source electrode is arranged in the middle area of ​​the other side of the Ga2O3 epitaxial layer; The source electrode is symmetrically provided with second grooves on both sides; the second grooves include inclined surface segments; A NiO layer and an insulating gate dielectric layer are disposed on the second trench from bottom to top; A gate electrode with a non-planar gate structure is disposed on the insulating gate dielectric layer; The second trench and a gap portion around the gate electrode are filled with a first oxide isolation layer.

2. The power MOSFET according to claim 1, characterized in that: The material of the substrate layer includes 4H-SiC; And / or, the materials of the oxidation isolation layer and the first oxidation isolation layer are both insulating materials; And / or, the angle of the bottom corner of the gate electrode is greater than 90°.

3. The power MOSFET according to claim 1, characterized in that: The thickness ratio of the substrate layer, the AlN buffer layer, the Ga2O3 buffer layer and the Ga2O3 epitaxial layer is 5-10 μm: 50-200 nm: 3-5 μm: 7-10 μm; And / or, the substrate layer has a doping concentration of 1×10 18 ~5×10 18 cm -3 n-type highly doped 4H-SiC material; And / or, the Ga2O3 buffer layer has a doping concentration of 1.5×10 16 ~4×10 16 cm -3 β-Ga2O3 materials; And / or, the Ga2O3 epitaxial layer has a doping concentration of 1×10 16 ~2×10 16 cm -3 n-type highly doped β-Ga2O3 material.

4. The power MOSFET according to claim 1, characterized in that: The thickness ratio of the Ga2O3 epitaxial layer, the NiO layer and the insulating gate dielectric layer is 7-10 μm: 100-300 nm: 20-50 nm; And / or, the ratio of the thickness of the second groove to the depth of the groove is (0.6-1):(0.675-8), and the thickness of the second groove is smaller than the depth of the groove; And / or, the NiO layer has a doping concentration of 1×10 17 ~2×10 17 cm -3 P-type heavily doped nickel oxide material.

5. The power MOSFET according to claim 1, characterized in that: The depth of the groove is at least 10% of the thickness of the Ga2O3 epitaxial layer, and the depth of the groove is not greater than the thickness of the Ga2O3 epitaxial layer.

6. A method for preparing a power MOSFET according to any one of claims 1 to 5, characterized in that: The following steps are involved: After cleaning the substrate layer, an AlN buffer layer is grown, followed by a Ga2O3 buffer layer, and then a Ga2O3 epitaxial layer; Etching the Ga2O3 epitaxial layer to form a groove; depositing an oxide isolation layer in the trench; Etching is performed on one side of the trench to form a symmetrical step-like structure, and then etching is continued to form a trapezoidal structure, followed by self-aligned F plasma treatment to form a second trench; Depositing a NiO layer material on the Ga2O3 epitaxial layer to form a NiO layer, then etching to form regional openings for source and drain electrodes, then depositing an insulating gate dielectric layer material to form an insulating gate dielectric layer, and etching to form regional openings for source and drain electrodes after deposition; Depositing a metal electrode material on the insulating gate dielectric layer in the second trench to form a gate region; Depositing an oxide isolation material on the device having the gate region to form a plane, and then etching to form regional openings for the source electrode and the drain electrode and to open the gate region; injecting a metal electrode material into the gate region, then depositing a layer of the metal electrode material on the device surface, and forming an alloy layer by stripping; The alloy layer is etched to form a source electrode, a drain electrode and a gate electrode to obtain the power MOSFET.

7. The preparation method according to claim 6, characterized in that: The method used to grow the Ga2O3 buffer layer includes LPCVD method; The process conditions of the LPCVD method include: Reaction chamber gas: Ar; Deposition power: 200~400W; And / or, the method for growing the Ga2O3 epitaxial layer includes a pulsed laser deposition method; the process conditions of the pulsed laser deposition method include: The target material is (AlGa)2O3; The oxygen partial pressure in the chamber is 0.01 to 0.03 mbAr; The distance between the sample to be grown and the target material is 4 to 5 cm; The growth temperature is 500-800°C; The energy density of the laser is 2 to 4 J / cm 2 , the pulse frequency of the laser is 3~5HZ; The total number of pulses for film growth is 6000 to 9000.

8. The preparation method according to claim 6, characterized in that: The etching method includes ICP etching or RIE etching; The process conditions of the ICP etching method include: Reaction chamber pressure: 10-30mTorr; Reaction chamber gases: BCl3 and Ar; Reaction chamber gas flow rate ratio: BCl3:Ar=20sccm:10~15sccm; Etching power: 200~400W; And / or, the process conditions of the RIE etching method include: Reaction chamber pressure: 20-40 mTorr; Reaction chamber gases: BCl3 and Ar; Reaction chamber gas flow rate ratio: BCl3:Ar=35sccm:5sccm; Etching power: 200~400W; And / or, the process conditions of the self-aligned F plasma treatment include: Reaction chamber pressure: 30mTorr; Reaction chamber gas: CF4; RF power: 200W.

9. The preparation method according to claim 6, characterized in that: The method for depositing the material of the NiO layer is magnetron sputtering; the process conditions of the magnetron sputtering method are as follows: Nickel-oxygen ratio: 1:1; Sputtering gas: Ar; Cavity pressure: 2~10Pa; Cavity temperature: 80~200℃; Sputtering power: 10~100W; And / or, the method for depositing the material of the insulating gate dielectric layer and the material of the oxidation isolation is an ALD method; the process conditions of the ALD method are as follows: Reaction chamber temperature: 200-300°C; Reaction chamber pressure: 800~900Pa; Reaction chamber gas: high purity nitrogen; Reaction chamber gas flow rate: 300 sccm.

10. Use of the power MOSFET according to any one of claims 1 to 5 in a high voltage circuit or transformer circuit chip.

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