Systems and methods for configuring bits using distributed memory in artificial neural networks

Abstract

A system and method for configuring bits using distributed memory in an artificial neural network is provided. Systems and techniques include identifying a network layer for performing memory operations; identifying a subset of a plurality of configuration bit clusters of the volatile distributed memory, the configuration bit clusters of the subset being mapped to the identified network layer using a cluster mapping; in response to identifying the subset of the plurality of configuration bit clusters, initiating the subset of the plurality of configuration bit clusters; loading network component data from the subset of the plurality of configuration bit clusters into a local buffer; and applying the network component data to the network layer for performing the memory operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 520,879, filed on August 21, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate particularly to using clusters of configuration bits in volatile distributed memory.More particularly, certain embodiments of the present disclosure relate to loading network component data from or into local buffers using clusters of configuration bits in volatile distributed memory. Background Art

[0004] A network (e.g., an artificial neural network) may include layers with hardware neurons. For some such layers and / or hardware neurons, the associated weight values ​​and bias values ​​may require memory operations, such as storage operations, extraction operations, modification operations, read operations, and / or write operations. For example, in an inference application, the weight values ​​and bias values ​​of each hardware neuron may be stored in an off-chip memory. During the use of the hardware neurons, the weight values ​​and bias values ​​may be loaded from the off-chip memory into an on-chip random access memory (RAM) and / or registers (wherein the network may be implemented). Off-chip memory access to weight values ​​and bias values ​​may significantly increase the power consumption of the chip and / or increase delays in the operation of the hardware neurons. Such memory access may also require the implementation of an undesirable amount of standby voltage. Summary of the invention

[0005] Various aspects discussed herein may include a method comprising: identifying a network layer for performing a memory operation; identifying a subset of a plurality of configuration bit clusters of a volatile distributed memory, the configuration bit clusters of the subset being mapped to the identified network layer using a cluster map; in response to identifying the subset of the plurality of configuration bit clusters, enabling the subset of the plurality of configuration bit clusters; loading network component data from the subset of the plurality of configuration bit clusters into a local buffer; and applying the network component data to the network layer for performing the memory operation.

[0006] Various aspects discussed herein may include a method comprising: identifying a network layer performing a memory operation; identifying a subset of a plurality of configuration bit clusters of a volatile distributed memory, the configuration bit clusters of the subset being mapped to the identified network layer using a cluster map; in response to identifying the subset of the plurality of configuration bit clusters, initiating the subset of the plurality of configuration bit clusters; loading network component data from a local buffer into the subset of the plurality of configuration bit clusters; and storing the network component data at the subset of the plurality of configuration bit clusters.

[0007] Various aspects discussed herein may include a system comprising: a network comprising multiple network layers, the multiple network layers including a first layer identified for performing a memory operation; a local buffer, the local buffer communicating with a cluster map; and a volatile distributed memory comprising multiple configuration bit clusters, wherein the local buffer: initiates a subset of the multiple configuration bit clusters based on the cluster map; receives network component data from the subset of the multiple configuration bit clusters; and provides the network component data to the first layer identified for performing the memory operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the following detailed description, reference will be made to the accompanying drawings. The accompanying drawings show different aspects of the present disclosure, and where appropriate, reference numerals illustrating similar structures, components, materials and / or components in different drawings are labeled in a similar manner. It should be understood that various combinations of structures, components and / or components (other than those specifically shown) are contemplated and within the scope of the present disclosure.

[0009] In addition, there are many embodiments of the present disclosure described and illustrated herein. The present disclosure is not limited to any single aspect or its embodiment, nor is it limited to any combination and / or arrangement of such aspects and / or embodiments. In addition, each of the aspects of the present disclosure and / or its embodiments can be used alone or in combination with one or more of the other aspects of the present disclosure and / or its embodiments. For the sake of brevity, certain arrangements and combinations are not discussed and / or illustrated separately herein; however, all arrangements and combinations are considered to be within the scope of the present invention.

[0010] Figure 1 A functional diagram depicting an exemplary artificial neural network according to an exemplary embodiment of the present disclosure.

[0011] Figure 2 Describes an exemplary embodiment according to the present disclosure Figure 1 An example of a hardware neuron for an artificial neural network.

[0012] Figure 3Describes an exemplary embodiment according to the present disclosure Figure 1 Another functional diagram of an exemplary artificial neural network.

[0013] Figure 4 An exemplary embodiment of a volatile distributed memory and a local cache memory is depicted according to an exemplary embodiment of the present disclosure.

[0014] Figure 5A Depicted is an exemplary embodiment of configuration bits according to an exemplary embodiment of the present disclosure.

[0015] Figure 5B Describes an exemplary embodiment of the present disclosure for Figure 5A An exemplary implementation of configuration bits to perform read operations and write operations.

[0016] Figure 5C An exemplary embodiment of a configuration bit cluster is depicted according to an exemplary embodiment of the present disclosure.

[0017] Fig. 6A An exemplary embodiment of a configuration bit implemented as a magnetic tunnel junction (MTJ) bridge is depicted according to an exemplary embodiment of the present disclosure.

[0018] Figure 6B An exemplary embodiment of a configuration bit implemented as an MTJ branch is depicted according to an exemplary embodiment of the present disclosure.

[0019] Figure 6C Depicted is an exemplary embodiment of configuration bits implemented using multiple MTJ bridges according to an exemplary embodiment of the present disclosure.

[0020] Figure 7 Another exemplary embodiment of volatile distributed memory and local cache memory according to aspects of the present disclosure is depicted.

[0021] Fig. 8A A flow chart depicting an exemplary method for performing a read operation using volatile distributed memory and a local cache memory according to aspects of the present disclosure.

[0022] Figure 8B A flow chart depicting an exemplary method for performing write operations using volatile distributed memory and local cache memory according to aspects of the present disclosure.

[0023] Fig. 9 Depicts a flow chart for training a machine learning model according to an exemplary embodiment of the present disclosure.

[0024] Many embodiments are described and illustrated herein. The disclosure is neither limited to any single aspect or its embodiment, nor to any combination and / or arrangement of such aspects and / or embodiments. Each of the aspects of the disclosure and / or its embodiments can be used alone or in combination with one or more of the other aspects of the disclosure and / or its embodiments. For the sake of brevity, many of those combinations and arrangements are not discussed separately in this article.

[0025] As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that includes a list of elements does not include only those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term "exemplary" is used in the sense of an "example" rather than an "ideal." DETAILED DESCRIPTION

[0026] Detailed description aspects are disclosed herein. However, for the purpose of describing the exemplary embodiments of the present disclosure, the specific structural details and functional details disclosed herein are only representative. The present disclosure can be embodied in many alternative forms and should not be construed as being limited to the embodiments set forth herein. In addition, the terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the exemplary embodiments described herein.

[0027] When the specification refers to "one embodiment" or "an embodiment", it is intended to mean that a particular feature, structure, characteristic, or function described in connection with the embodiment in question is included in at least one contemplated embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places in the specification do not constitute multiple references to a single embodiment of the present disclosure.

[0028] Unless the context clearly indicates otherwise, as used herein, the singular forms "a / an" and "said" are also intended to include the plural forms. It should also be noted that in some alternative implementations, the features and / or steps described may not occur in the order depicted in the figures or discussed herein. For example, two steps or figures shown in succession may instead be performed substantially simultaneously or may sometimes be performed in reverse order, depending on the functions / actions involved. In some aspects, depending on the functions / actions involved, one or more of the described features or steps may be omitted entirely or may be performed using intermediate steps therebetween without departing from the scope of the embodiments described herein.

[0029] In addition, the terms "first", "second" and similar terms do not represent any order, quantity or importance in this article, but are used to distinguish one element from another element. Similarly, relative directional terms such as "top", "bottom" and the like are used with reference to the orientation of the structure shown in the described figure. It should also be noted that all numerical values ​​disclosed herein may have a variation of ±10% (unless a different variation is specified) from the disclosed numerical values. In addition, all relative terms such as "about", "substantially", "approximately" and the like are used to indicate a possible variation of ±10% (unless otherwise stated or another variation is specified).

[0030] In one aspect, the present disclosure relates to techniques and implementations for programming memory devices, including, for example, volatile or "persistent" memory (e.g., magnetoresistive random access memory (MRAM) or ReRAM) that is capable of maintaining data when power is disabled. Although the following description refers to MRAM, register memory, or ReRAM memory device cells, the embodiments disclosed herein may be implemented in other memory devices including, but not limited to, electrically erasable programmable read-only memory (EEPROM) and / or ferroelectric random access memory (FRAM).

[0031] Conventional techniques for network memory operations include storing network component data (e.g., weights, biases, etc.) associated with a network layer, neuron, or arc in an off-chip volatile memory such as a NOR or NAND memory. Such conventional techniques may include on-chip volatile memory implemented using static random access memory (SRAM) or flip-flops or register files, which requires high standby current to operate. According to such conventional techniques, network component data (e.g., weights, biases, etc.) associated with a network layer is loaded from an off-chip volatile memory such as an external NOR (e.g., flash memory) to an on-chip volatile memory. Such a loading operation increases the inefficiency in both the amount of time to perform the loading operation and the power required to perform the loading operation.

[0032] For example, an artificial neural network may include an input layer, a plurality of intermediate layers (e.g., hidden layers), and an output layer. The input layer may receive one or more inputs of the artificial neural network. The input provided via the input layer may be applied to one or more hidden intermediate layers including hardware neurons. One or more hidden layers may be trained based on supervised, semi-supervised, or unsupervised machine learning. Each neuron may have a plurality of corresponding network component data (e.g., weights, biases, layers, etc.) stored in a memory. During the training process (e.g., learning operation) of training the artificial neural network, such network component data associated with one or more hardware neurons or layers may be accessed (e.g., read), modified, deleted, written, rewritten, added, and / or similarly processed. Therefore, a large amount of memory access may be required during the artificial neural network training process. In addition, during the production use (e.g., reasoning operation) of the trained artificial neural network, the network component data neurons may be accessed and / or applied via separate memory accesses. In addition, the artificial neural network may continue to be trained (e.g., based on feedback) during the reasoning operation. Therefore, components of hardware neurons or layers may be modified, deleted, written, rewritten, and / or added during the production process. During inference operations of an artificial neural network, multiple network components (e.g., weights or biases) for each neuron or layer may have to be loaded into volatile memory. Conventionally, such loading is implemented by storing the weights or biases in off-chip NOR and / or NAND flash memory, as discussed above. Data from such flash memory is loaded into a distributed on-chip memory that communicates with the artificial neural network processor before performing inference operations, and is provided by the distributed on-chip memory to locally available volatile storage components, such as SRAM, scan chains, or registers. In such conventional methods, the additional power consumption and elapsed time during such data movement and use of such storage components may be undesirable.

[0033] The present disclosure relates to systems and methods for using configuration bit clusters of volatile distributed memory. According to certain embodiments, artificial neural network component data (e.g., related to weight values, bias values, processing layers, etc.) can be stored using distributed MRAM configuration bits of volatile distributed memory. The network component data can be associated with multiple network layers. For example, a first subset of network component data can be stored in a first subset of configuration bit clusters and a second subset of network component data can be stored in a second subset of configuration bit clusters. Such subsets of configuration bit clusters can each be mapped to one or more network layers (e.g., neural network layers). For example, the configuration bit clusters of the first subset can be mapped to the first network layer associated with the first subset of network component data. Similarly, the configuration bit clusters of the second subset can be mapped to the second network layer associated with the second subset of network component data. Such network component data can be stored at one or more configuration bit clusters, so that a single configuration bit cluster or multiple configuration bit clusters can be accessed to extract (e.g., read) and / or update (e.g., write) such network component data.

[0034] A given network layer (e.g., a neural network layer) may be identified for performing a memory operation (e.g., an inference-based operation, a learning-based operation, etc.). The identification may be based on activation of the network layer (e.g., based on a network layer component being powered, based on a network layer configuration bit being powered, based on one or more signals being generated or received corresponding to the network layer, and / or the like). For example, a network layer may be identified for an inference memory operation or a learning memory operation. As used herein, an "inference memory operation" may correspond to an operation for using a trained neural network to, for example, generate an output or perform additional or iterative training. Thus an output may be generated based on one or more inputs and network component data (e.g., weight values, bias values, etc.) associated with one or more layers of the network.

[0035] An inference memory operation may require, for example, approximately 1000 read operations or write operations associated with the network component data discussed herein. According to an example, during an inference memory operation, a given network layer (e.g., of a neural network) may be identified for producing an output or for producing a component of an output (e.g., where such a component may be used by one or more other network layers to produce the overall output). As further discussed herein, a given network layer may have corresponding network component data that may be produced during a learning memory operation. It will be understood that the corresponding network component data may be updated during an inference memory operation (e.g., during a continued or updated learning operation). Such corresponding network component data may be retrieved (e.g., a read operation) or updated (e.g., a write operation) based on a given network layer being initiated or otherwise triggered to perform an inference memory operation.

[0036] Similarly, for example, a given network layer (e.g., a neural network layer) may be identified for a learning memory operation. As used herein, a "learning memory operation" may correspond to an operation for training a neural network to, for example, generate an output based on the training. Such an output may be generated based on one or more inputs and network component data (e.g., weight values, bias values, etc.). The network component data may be generated and / or updated during the learning operation. According to an example, the learning memory operation may require approximately 100,000 or more read operations or write operations associated with the network component data discussed herein. According to an example, during the learning memory operation, a given network layer (e.g., of a neural network) may be identified for training the given network layer based on one or more of supervised learning, unsupervised learning, and semi-supervised learning. A given network layer may have corresponding network component data that may be generated and / or updated based on the learning operation. Such corresponding network component data may be extracted (e.g., a read operation) or updated (e.g., a write operation) based on the given network layer being initiated or otherwise triggered to perform the learning memory operation.

[0037] As discussed herein, network component data corresponding to a given network layer may be stored in one or more configuration bit clusters of a volatile distributed memory. The distributed volatile memory may store multiple configuration bit clusters such that each of the subsets of such configuration bit clusters corresponds to a corresponding network layer (e.g., a neural network layer). Thus, the volatile distributed memory may include multiple subsets of configuration bit clusters, wherein each subset includes one or more configuration bit clusters. Based on a cluster mapping, each subset of the configuration bit clusters may be mapped to a corresponding network layer (e.g., a corresponding neural network layer). The cluster mapping may identify which subset of configuration bit clusters is associated with which corresponding network layer. The cluster mapping may be implemented using any applicable mapping technology, such as, but not limited to, a mapping table, a pointer-based system, a mapping database, and / or the like.

[0038] As discussed above, a network layer may be identified for performing memory operations. A network layer may be implemented in or communicate with a local buffer (e.g., data may be received from and / or provided to a local buffer). A local buffer may be implemented as an on-chip local memory connected to a digital or analog component. For example, a local buffer may be connected to a given network layer and / or may be connected to each network layer of a network (e.g., a neural network). A local buffer may be implemented as an on-chip memory, a volatile memory, an SRAM, and / or the like. According to some embodiments, a local buffer may be located on the same chip or processing device as a network, a network layer, and / or a volatile distributed memory. According to other embodiments, a local buffer may be located on the same chip or processing device as a network, and a network layer and a volatile distributed memory may also be located on the same chip or processing device. A local buffer may be in active electrical communication with, for example, a given network layer at a given time. It will be understood that one or more layers of a network may be implemented using digital or analog components that are in electrical communication with a local buffer. According to this example, memory operations for a first given network layer are performed in communication with the local buffer at a first time, and memory operations for a second given network layer are performed in communication with the local buffer at a second time. The first time and the second time may be different times, or may be the same time. As further discussed herein, network component data from a subset of the configuration bit clusters associated with a given network layer may be accessed by the local buffer to perform a read or write operation.

[0039] The local memory may access the cluster map when identifying a network layer for performing a memory operation. The cluster map may be used to identify a subset of configuration bit clusters of a volatile distributed memory, the configuration bit clusters of the subset being mapped to the identified network layer. In response to identifying the subset of configuration bit clusters based on the cluster map, a local buffer or another component may enable the subset of configuration bit clusters. This enabling may include providing a minimum threshold voltage to the subset of configuration bit clusters, may include providing a minimum threshold voltage to a read latch block associated with the subset of configuration bit clusters, may include providing a minimum threshold voltage to a read select device associated with the subset of configuration bit clusters, and / or the like.

[0040] Activating the subset of configuration bit clusters may result in reading network component data from the subset of configuration bit clusters of the volatile distributed memory into the local buffer. Alternatively or in addition, such activation may result in writing new or updated network component data from the local buffer to the subset of configuration bit clusters of the volatile distributed memory. It will be appreciated that the volatile distributed memory may be designed to store a larger volume of network component data than the local buffer. For example, the volatile distributed memory may store network component data corresponding to multiple network layers, while the local buffer may store network component data associated with any single network layer at a given time.

[0041] The volatile distributed memory can remain in a powered-off state except when a given subset of the configuration bit clusters is started according to the techniques disclosed herein. The subset of the configuration bit clusters can be powered on immediately (e.g., in less than about 10ns) to perform read and / or write operations. Such power-on from a powered-off state can be real-time because such a subset of the configuration bit clusters does not require standby power or associated bias circuitry to start. In addition, starting only a subset of the configuration bit clusters rather than starting the entire volatile distributed memory as performed according to conventional techniques can reduce the amount of minimum threshold voltage applied to power on the configuration bit clusters of the subset.

[0042] In response to enabling the subset of configuration bit clusters, network component data from the subset of configuration bit clusters may be loaded onto a local buffer in accordance with a read operation. Such network component data may be applied to (e.g., provided to) a corresponding network layer for performing a memory operation. For example, such network component data may be provided to a digital or analog component in electrical communication with the local buffer, wherein the digital or analog component is configured to implement an operation associated with a given network layer. Alternatively, in response to enabling the subset of configuration bit clusters, network component data may be loaded from a local buffer to the subset of configuration bit clusters in accordance with a write operation. Such network component data may be provided by a corresponding network layer in accordance with, for example, a training or retraining memory operation.

[0043] Thus, when power is applied to the applicable subset of the configuration bit clusters, network component data stored at the configuration bit clusters of the volatile distributed memory can be immediately accessed. When the corresponding memory operation is completed (e.g., when the applicable network component data is loaded from a given subset of the configuration bit clusters), the enabled configuration bit clusters of the subset can be powered off (e.g., the voltage applied to enable the subset of the configuration bit clusters can be removed). Thus, by using a volatile distributed memory and by enabling only the applicable subset of the configuration bit clusters, power consumption can be reduced compared to conventional techniques. In addition, since only the applicable subset of the configuration bit clusters corresponding to the network layer is enabled in the volatile distributed memory, a standby voltage may not be required to perform the memory operations disclosed herein. Thus, the techniques disclosed herein can be used without consuming a standby voltage and consuming limited resources by enabling only the applicable subset of the configuration bit clusters.

[0044] Therefore, one or more problems exhibited by conventional methods can be solved by certain embodiments described herein. For example, power consumption, computing resources and / or time can be reduced by using volatile distributed memory (e.g., MRAM, register-based memory, etc.) and local buffer architecture disclosed herein. Certain embodiments disclosed herein can reduce power consumption, computing resources and / or delays by providing on-chip access (e.g., replacing off-chip access) to network component data (e.g., weight values, bias values, processing layer information, etc.). In addition, by having on-chip access, certain embodiments can reduce the amount of routing required to provide values ​​from volatile distributed memory to the network processing circuit system, which can save chip space, reduce or eliminate circuits of artificial neural networks, etc.

[0045] Reference now Figure 1 , depicts a functional diagram of an exemplary artificial neural network 100 according to an exemplary embodiment of the present disclosure. As shown, the artificial neural network 100 may include an input layer 102, one or more hidden layers (hidden layer 104), and an output layer 106. The input layer 102 may provide input values ​​108a and 108b to the hidden layer 104, and the hidden layer may process the input values ​​108a (a1) and 108b (a2). The hidden layer 104 may include one or more hardware neurons 110 (also referred to herein as neuron devices) for performing processing by using network component data. As depicted by "Output 1" and "Output 2", the hidden layer 104 may provide the processing results to the output layer 106 (e.g., to the hardware neurons 112a and 112b of the output layer 106) to output to a device or user for further processing, and / or similar operations.

[0046] As described in more detail herein, network component data (e.g., weight values, bias values, etc.) may be stored in volatile distributed memory and may be used during operation of artificial neural network 100. For example, a weight value may be associated with each arc (or synapse) between input layer 102 and hidden layer 104 and between hidden layer 104 and output layer 106. Figure 1 , as arrows between those layers. Additionally or alternatively, bias values ​​may be associated with each hardware neuron 110a, 110b, 110c, 112a, and 112b in the artificial neural network 100. As discussed herein, a subset of the configuration bit clusters at the volatile distributed memory may store such network component data for each respective arc, neuron, and / or layer.

[0047] Although certain embodiments may be described herein in the context of an artificial neural network 100, certain embodiments may be applicable to feedforward neural networks, radial basis function neural networks, Kohonen self-organizing neural networks, recurrent neural networks (RNNs), convolutional neural networks (CNNs), modular neural networks (MNNs), and / or the like.

[0048] Figure 2 Describes an exemplary embodiment according to the present disclosure Figure 1 An example diagram 200 of the hardware neurons 110 of the artificial neural network 100 is shown. As shown, Figure 2 The hardware neuron 110 may include weight operation circuit systems 114a, 114b, bias operation circuit systems 116, and activation function circuit systems 120 that may implement a rectified linear unit (ReLU) activation function or a sigmoid activation function. The hardware neuron 110 may be part of a given neural network layer of the artificial neural network 100. The hardware neuron may be implemented via a digital or analog computing module 404b, as described herein with reference to Figure 4 Further disclosed. The hardware neuron 110 can communicate with the local buffer 404a (eg, the hardware neuron 110 can receive network component data from the local buffer 404a or provide network component data to the local buffer 404a). Figure 4The local buffer 404a is further described. For example, the hardware neuron 110 can receive network component data, such as weight values ​​122a, weight values ​​122b, and / or bias values ​​124, from the local buffer 404a. The hardware neuron 110 can apply the input values ​​108a and / or 108b to the operation circuit system 114a, 114b, and / or the bias operation circuit system 116 (e.g., of the digital or analog computing module 404b) to perform an operation by applying the received network component data (e.g., weight values ​​122a, weight values ​​122b, and / or bias values ​​124). As a specific example, the weight operation circuit system 114 can multiply the input value 108a by the weight value 122a (e.g., a1*W1). In some embodiments, the weight values ​​122a, 122b, and / or bias values ​​124 can be updated during the training of the artificial neural network 100 based on, for example, a feedback loop.

[0049] The local buffer 404a may be in electrical communication with multiple layers of the artificial neural network 100 (e.g., multiple arcs, neurons, etc. of each layer of the artificial neural network 100), which may be implemented using digital or analog computations 404b (e.g., as a given layer at a given time). As discussed herein, the local buffer 404a may be in active electrical communication with a single layer of the artificial neural network 100 at a given time, such that network component data for a given layer may be loaded at the local buffer 404a, and such that memory operations for the given layer may be performed in communication with the local buffer 404a.

[0050] Figure 3 Depiction Figure 1 The extended functional diagram 300 of the artificial neural network 100 is shown in FIG. Figure 3 As shown, the plurality of hidden layers 104 of the artificial neural network 100 are shown as hidden layers 104a, 104b, 104c, and 104d. The input layer 102 and the output layer 106 of the artificial neural network 100 are also depicted in FIG. Figure 3 In addition, Figure 3 include Figure 2 and Figure 4 As shown, the local buffer 404a is designed to functionally communicate with each of the plurality of hidden layers 104 (e.g., the hidden layers may be implemented using digital or analog computing modules 404b). As described herein, the local buffer 404a may be designed to load network component data for a given layer that performs memory operations. Figure 3As shown, the hidden layer 104b can be identified for performing a memory operation (e.g., an inference operation or a learning operation). Therefore, based on the cluster mapping, the local buffer 404a can receive the network component data associated with the hidden layer 104b from the volatile distributed memory. The local buffer 404a can provide the received network component data mapped to the hidden layer 104b and can transmit the received network component data to the hidden layer 104b for performing the memory operation.

[0051] Figure 4 A functional diagram 400 is depicted including a volatile distributed memory 402 and a core 418. The core 418 may include a local buffer 404a and a digital or analog computing module 404b, also as described with respect to Figure 2 and Figure 3 As mentioned. The volatile distributed memory 402 can be located on the same chip as the core 418 or can be located off-chip from the core 418. The power supply to the volatile distributed memory 402 can be turned off during a closed (e.g., standby) state so that no power is consumed in such a closed state. As discussed herein, the volatile distributed memory 402 can be immediately started (e.g., in less than about 10ns) to an open state. When the volatile distributed memory 402 is in the closed state, the volatile nature of the volatile distributed memory 402 can maintain the data stored therein.

[0052] The volatile distributed memory 402 may include a plurality of configuration bit clusters. Each configuration bit cluster may include one or more volatile configuration bits (eg, implemented using MRAM, register memory, etc.). Figure 5A Diagram 500 depicts a single configuration bit 502 that may be implemented as volatile memory (e.g., as part of a configuration bit cluster of volatile distributed memory 402). Configuration bit 502 may be designed to receive a digital input (e.g., read, write 0, write 1), perform a corresponding read or write operation, and may provide an output (e.g., a data output of a read operation). Figure 5A As shown, the configuration bit 502 can receive a digital read signal or a write signal (e.g., write 0 or write 1). The VDD supply logic level voltage can be supplied to the configuration bit 502, and the configuration bit 502 can be dynamically scaled to perform certain operations (e.g., write operations). The configuration bit 502 can transition from a power-off state to a power-on state in less than about 10ns (e.g., less than about 5ns). Figure 5B Describe the corresponding Figure 5A5. The configuration bit 502 of FIG. 5 is a write operation 510 and a read operation 520. As shown, the write operation 510 can be performed in response to the write operation input, and the configuration bit 502 can be configured to have a true (e.g., 1) bit value in response to the write 1 input or a false (e.g., 0) bit value in response to the write 0 input. The read operation 520 can be performed in response to the read operation input and can produce a data output that provides the current configuration (e.g., true or false configuration) of the configuration bit 502. The read operation can be performed in less than about 10ns (e.g., less than about 5ns). The write operation can be performed in approximately the time period required to write the state (e.g., true or false) into the volatile storage component.

[0053] Figure 5C A cluster 540 of eight configuration bits is depicted. Figure 5C As shown, multiple configuration bits (e.g., multiple instances of configuration bit 502) can be grouped to create a cluster of configuration bits (e.g., cluster 540). Each of the eight configuration bits in cluster 540 can be similar to Figure 5A Configuration bit 502. Therefore, each of the eight configuration bits in cluster 540 can be designed to perform a read operation and / or a write operation in the manner described with reference to configuration bit 502. For example, each of the eight configuration bits in cluster 540 can be designed to store a bit value (e.g., via a write operation) and / or output a stored bit value (e.g., via a read operation). A given cluster of configuration bits (e.g., cluster 540) can be designed to perform a real-time open operation (e.g., ready for a read or write operation) via a supply voltage ramp that satisfies a minimum supply threshold value. It will be understood that although cluster 540 includes eight configuration bits, any number of applicable configuration bits may be included in a given cluster. In addition, volatile distributed memory 402 may include clusters with different numbers of configuration bits. For example, a first cluster may include eight configuration bits, while a different second cluster may include sixteen configuration bits (or any number of configuration bits different from the first cluster).

[0054] return Figure 4 , the volatile distributed memory 402 may include multiple configuration bit clusters. Figure 4As shown, the volatile distributed memory 402 may include configuration bit clusters 402a to 402h. It will be understood that the configuration bit clusters 402a to 402h are shown only as examples, and the volatile distributed memory 402 may include any suitable number of clusters. In addition, although the configuration bit clusters 402a to 402h are depicted as being similar in size, it will be understood that the clusters in the volatile distributed memory 402 may have any suitable number of configuration bits (e.g., two or more configuration bits). As discussed herein, the volatile distributed memory 402 (including the clusters included therein and the configuration bits included within the clusters) may be implemented as a volatile memory.

[0055] Configuration bit clusters 402a to 402h may store network component data (e.g., weights, biases, etc.) associated with portions of a neural network. Although such portions of a neural network are generally referred to herein as network layers, it will be understood that a subset of a network may be a layer, arc, grouping, or the like associated with a neural network. As discussed herein, a subset of configuration bit clusters may store network component data for a given subset (e.g., a given layer) of a neural network. Such network component data may be stored at a subset of configuration bit clusters such that the subset is formed by a single configuration bit cluster or a plurality of configuration bit clusters. Thus, a subset of configuration bit clusters mapped to a given network layer may include one cluster or a plurality of clusters within the volatile distributed memory 402. A given subset of configuration bit clusters (e.g., one given cluster or a plurality of given clusters) may be accessed to extract (e.g., read) and / or update (e.g., write) network component data associated with a corresponding network layer.

[0056] like Figure 4 As also depicted in, the core 418 may include a local buffer 404a and a digital or analog computing module 404b. As discussed herein, the local buffer 404a may be a memory implemented as a volatile memory. The digital or analog computing module 404b may include a digital and / or analog system component designed to implement one or more network components such as network layers, neurons, and / or the like. The local buffer 404a and / or the digital or analog computing module 404b may access a cluster map (e.g., based on a network layer identified for performing memory operations). The digital or analog computing module 404b may also receive network component data loaded (e.g., stored) at the local buffer memory 404a to implement an identified network layer (e.g., to perform a read operation) or may provide network component data to a corresponding subset of a configuration bit cluster (e.g., to implement a write operation). The digital or analog computing module 404b may include a network component, such as a circuit system that may allow the digital or analog computing module 404b to act as or implement a network component (e.g., layer, neuron, etc.). The digital or analog computing module 404b may, for example, act as or implement a currently active network layer (e.g., Figure 3 active hidden layer 104b).

[0057] refer to Figure 3 and Figure 4 , the hidden network layer 104b can be identified for performing a memory operation (e.g., an inference operation, a learning operation, etc.). The hidden network layer 104b can be identified based on a triggering action corresponding to the hidden network layer 104b. The triggering action can be, for example, an input received at the hidden network layer 104b (e.g., from one or more other layers), an output requested from the hidden network layer 104b (e.g., from one or more other layers) upon completion of a sequential or dynamic network process, and / or the like. The core 418 can receive an indication (e.g., a signal) corresponding to the identification of the hidden network layer 104b. The indication can be received from the hidden network layer 104b, one or more other hidden layers 104, or other components associated with the artificial neural network 100.

[0058] In response to receiving an indication corresponding to the identification of the hidden network layer 104b, the core 418 (e.g., via the local buffer 404a and / or the digital or analog computing module 404b) can access a cluster map (e.g., an image table, a pointer-based system, a mapping database, etc.). The core 418 can access the cluster map to identify a subset of the configuration bit clusters of the volatile distributed memory 402 that correspond to the identified hidden network layer 104b. For example, Figure 4 As shown, the cluster map may identify a subset of the configuration bit clusters represented by cluster 402d. As discussed, the subset of configuration bit clusters may be a single cluster or a group of clusters associated with network component data associated with a given layer (eg, hidden network layer 104b).

[0059] In response to identifying a subset of configuration bit clusters, the identified subset of configuration bit clusters can be enabled. The identified subset of configuration bit clusters can be enabled in response to applying a minimum threshold voltage (e.g., VDD average voltage) to the subset of multiple configuration bit clusters. The minimum threshold voltage can be provided by core 418 or can be caused to be provided by core 418.

[0060] According to one embodiment, Figure 4The volatile distributed memory 402 can be implemented using a read latch block associated with each configuration bit and / or each configuration bit cluster. The read latch block can be designed to read and store the configuration bit state (e.g., for a single configuration bit or a configuration bit cluster). According to this embodiment, a minimum threshold voltage can be applied to the write component and / or the read latch block associated with the cluster. Each configuration bit or each configuration bit cluster can be associated with a corresponding read latch block. The read latch block can be designed to read one or more states of a given configuration bit and / or configuration bit cluster, and can be further configured to communicate with the core 418 to receive and / or provide the one or more states. For example, as referenced herein Figure 5A and Figure 5B As discussed, a read or write operation can be triggered by applying a minimum threshold voltage to the configuration bit 502. The configuration bit 502 can be immediately (e.g., in less than about 10 ns) enabled to perform the read or write operation. Figure 5B As shown, the read operation 520 can be implemented by a read latch block associated with a configuration bit or a configuration bit cluster. The read latch block can provide a "dout" output corresponding to each configuration bit in the configuration bit or configuration bit cluster.

[0061] The minimum threshold voltage may be applied in response to an indication (e.g., a signal) generated at the core 418, which may be triggered by the local buffer 404a and / or the digital or analog computing module 404b. As discussed herein, prior to startup, an identified subset of the configuration bit cluster may be in a closed state (e.g., without standby power). An identified subset of the configuration bit cluster may be started from a closed state to an open state in less than about 10ns (e.g., in less than about 5ns). Since the configuration bit clusters discussed herein are implemented as volatile (e.g., MRAM, registers, etc.) memory, such clusters may not require standby current to store network component data. Since such clusters may be started from a closed state to an open state in less than about 10ns, standby current may not be required to meet the minimum time associated with storing network component data and read or write operations of network component data.

[0062] When the identified subset of the configuration bit clusters is enabled, network component data may be loaded (e.g., read) from the identified subset of the configuration bit clusters into the local buffer 404a of the core 418. The network component data so loaded may be provided to the corresponding network layer for network operation. Alternatively, the network component data (e.g., updates to existing network component data) may be received from the corresponding network layer during network operation. When the identified subset of the configuration bit clusters is enabled, the network component data may be written from the local buffer 404a of the core 418 to the identified subset of the configuration bit clusters. When the network component data is loaded and / or written, the identified subset of the configuration bit clusters may be disabled. The identified subset of the configuration bit clusters may be disabled so that power (e.g., a minimum threshold voltage) provided to the identified subset of the configuration bit clusters may be removed. Thus, the identified subset of the configuration bit clusters, and by extension, the volatile distributed memory 402 may be returned to a closed state so that no power consumption is exhibited before a subsequent load or write operation is performed.

[0063] Therefore, the technology disclosed herein can be used to read data from or write data to an identified subset of a configuration bit cluster. Such read operations and write operations can facilitate memory operations (e.g., reasoning operations, learning operations, etc.) associated with the corresponding network layer. As discussed herein, volatile distributed memory and local buffers can allow such read operations and write operations to be triggered immediately (e.g., within about 10ns). Such real-time triggering can be facilitated by a configuration bit cluster of a volatile distributed memory, which can be powered on immediately (e.g., in less than about 10ns).

[0064] In addition, the power consumption associated with the operations discussed herein can be substantially lower than that required by conventional techniques. For example, identifying and enabling only a subset of the configuration bit clusters rather than the entire distributed memory (e.g., the entire volatile distributed memory 402) results in reduced power consumption. Furthermore, since a standby voltage is not required to provide standby power to the distributed memory, such a standby voltage is not required to perform the operations disclosed herein.

[0065] It will be appreciated that the operations discussed above may be repeated to perform subsequent memory operations. For example, at some time after performing a memory operation associated with hidden layer 104 b, hidden layer 104 c may be identified for use in performing a subsequent memory operation. As discussed herein, after performing a memory operation associated with hidden layer 104 b, a subset of the configuration bit clusters associated with hidden layer 104 b may be deactivated. According to the techniques disclosed herein, a subsequent set of multiple configuration bit clusters (e.g., Figure 4The cluster 402b of can be identified as being mapped to the hidden layer 104c. A subsequent set of multiple configuration bit clusters can be initiated (e.g., Figure 4 402b), and the corresponding network component data may be loaded to or from the local buffer 404a of the core 418. As disclosed herein, the corresponding memory operations may be performed in association with the hidden layer 104c.

[0066] Fig. 6A Depicted as reference Figure 5A The configuration 600 of the exemplary configuration bits 502 is discussed. For example, Fig. 6A Circuitry configured to write and read a multi-time programmable configuration bit 502 of a first value or a second value is depicted in accordance with an exemplary embodiment of the present disclosure. For example, the configuration bit 502 may be an MRAM (e.g., a switching MRAM or a spin transfer torque (STT) MRAM) or a ReRAM bit that may be reprogrammed multiple times to represent different values. Fig. 6A The circuitry of configuration bits 502 illustrated in may allow a first value (eg, a 0 value in a binary 0 and 1 system) or a second value (eg, a 1 value in a binary 0 and 1 system) to be written or read.

[0067] As shown, the configuration bit 502 can be implemented using a magnetic tunnel junction (MTJ) bridge 502a. The MTJ bridge 502a can be connected to or can include a voltage amplifier 604 and / or an inverter ( Fig. 6A MTJ bridge 502a may include one or more resistive components 608 (eg, resistive components 608a, 608b, 608c, and 608d). Fig. 6A The MTJ bridge 502a is illustrated as including four resistive components 608, but some embodiments may include any number of multiple resistive components 608, such as a number of resistive components greater than four (e.g., 5, 6, 7, 8, etc. resistive components). The resistive components 608 may include an MTJ or another type of electrical component capable of providing resistance to the flow of current. For example, the resistive components 608 may have multiple resistance states (e.g., a low resistance state (parallel) or Rp, and a high resistance state (anti-parallel) or Rap).

[0068] The MTJ bridge 502a may also include one or more electrodes 612 (e.g., electrodes 612a, 612b, 612c, and 612d) to electrically connect different resistive components 608 in series or in parallel. For example, the MTJ bridge 502a may include four resistive components, wherein two first resistive components are electrically connected in series and two second resistive components are electrically connected in series, and wherein the first resistive components are electrically connected to the second resistive components in parallel. As a specific example, the resistive components 608a, 608b (forming a first group of resistive components 608) may be electrically connected in series via the electrode 612a, the resistive components 608c, 608d (forming a second group of resistive components 608) may be electrically connected in series via the electrode 612b, and the first group and the second group of resistive components may be electrically connected in parallel via the electrodes 612c, 612d.

[0069] Configuration bit 502 may include one or more electrical connections 610 (eg, electrical connections 610a, 610b, 610c, 610d, and 610e). Electrical connection 610a may electrically connect electrode 612a to a voltage supply ( Fig. 6A 604) and electrical connection 610b may electrically connect electrode 612b to the voltage supply. Electrical connection 610c may electrically connect electrode 612c to the input of voltage amplifier 604 and electrical connection 610d may electrically connect electrode 612d to the input of voltage amplifier 604. Electrical connection 610e may electrically connect the output of the voltage amplifier to an inverter ( Fig. 6A The inverter may be in different states depending on whether the gate of the inverter is opened or closed. Based on the voltage applied to the MTJ bridge 502a, the inverter may be in a first state (eg, 1 state) indicating a first value (eg, 1 value).

[0070] As described above, the resistance component 608 can have two resistance states (e.g., a high resistance state Rap and a low resistance state Rp). For the first state of the inverter, the resistance components 608a, 608d can be in the high resistance state and the resistance components 608b, 608c can be in the low resistance state. For the second state of the inverter, the resistance components 608a, 608d can be in the low resistance state and the resistance components 608b, 608c can be in the high resistance state.

[0071] In some embodiments, Fig. 6A The MTJ bridge 502a of the configuration bit 502 shown in FIG. 1 can store one bit, and for multiple bits, the configuration bit 502 can utilize Fig. 6A The MTJ bridge 502a shown is configured with multiple examples. The MTJ bridge 502a can be read, multi-time programmed (MTP) and / or one-time programmed (OTP).

[0072] Figure 6B Depicted as reference Figure 5A Another configuration 620 of the exemplary configuration bits 502 discussed above. As shown, Figure 6B , a dedicated read latch circuit 622 can be connected to the configuration bit 502. The read latch circuit 622 can be connected to both the first branch 626a of the plurality of MTJs (e.g., four MTJs) configured in series and the second branch 626b of the plurality of MTJs configured in series. The read latch circuit 622 can be designed to read (e.g., sense) the resistance difference between the first branch 626a and the second branch 626b of the plurality of MTJs configured in series. The resistance difference can provide a read output corresponding to the state of the configuration bit 502 (e.g., true 1 or false 0).

[0073] Figure 6C Depicted as reference Figure 5A Another configuration 630 of the exemplary configuration bits 502 discussed. As shown, Figure 6C , a dedicated read latch circuit 632 may be connected to the configuration bit 502. The read latch circuit 632 may be connected to a first MTJ bridge 636a of a plurality of MTJs (e.g., eight MTJs) configured in series and in parallel and a second bridge 636b of a plurality of MTJs configured in series and in parallel (e.g., as shown in reference Fig. 6A ). The read latch circuit 632 can be designed to read (eg, sense) a resistance difference between the first bridge 636a and the second bridge 636b. The resistance difference can provide a read output corresponding to the state of the configuration bit 502 (eg, true 1 or false 0).

[0074] although Figure 6B Configuration 620 and Figure 6C Configuration 630 is generally discussed with reference to read operations, but it will be understood that write operations can be implemented using the resistor circuits discussed with reference to these configurations. For example, Figure 6B The state of the configuration bit 502 in the configuration 620 of can be updated by modifying the resistance state associated with the first branch 626a and / or the second branch 626b and / or the state associated with the resistor (e.g., MTJ) included in the branch. Similarly, for example, Figure 6C The state of the configuration bit 502 in the configuration 630 may be updated by modifying the resistance state associated with the first bridge 636a and / or the second bridge 636b and / or the state associated with the resistors (eg, MTJs) included in the bridges.

[0075] Figure 7 Depicts a functional diagram 700 including a volatile distributed memory 702. Diagram 700 also includes a core 418, which includes a local buffer 404a and a digital or analog computing module 404b, as shown in reference Figure 2 , Figure 3 and Figure 4 The core 418 can be electrically connected to each configuration bit cluster of the configuration bits of the volatile distributed memory 702 . Figure 7 The core 418 is shown electrically connected to the configuration bit cluster 706h. However, it will be understood that the core 418 can be electrically connected to all configuration bit clusters (e.g., configuration bit clusters 706a to 706h) of the volatile distributed memory 702. It will also be understood that the configuration bit clusters 706a to 706h are shown only as examples, and the volatile distributed memory 702 can include any suitable number of clusters. In addition, although the configuration bit clusters 706a to 706h are depicted as being similar in size, it will be understood that the clusters in the volatile distributed memory 702 can have any suitable number of configuration bits (e.g., two or more configuration bits). As discussed herein, the volatile distributed memory 702 (including the clusters included therein and the configuration bits included within the clusters) can be implemented as volatile memory.

[0076] As disclosed herein, the core 418 may be designed to enable a subset of the configuration bit clusters of the volatile distributed memory 702 based on the cluster mapping. For example, the core 418 may enable a subset of the configuration bit clusters that are mapped to the network layer identified for performing memory operations. Figure 7 As shown, for example, the core 418 may enable the configuration bit cluster 706h. As discussed herein, enabling may include causing a minimum threshold voltage to be applied to a read select device 708h associated with a given subset of the configuration bit clusters. Each cluster of the volatile distributed memory 702 may be associated with a read select device component and an MTJ network (e.g., as described in reference to FIG. 6A to FIG. 6C For example, Figure 7 As shown, the core 418 may provide a signal to a read select device 708h corresponding to the configuration bit cluster 706h. In response, the read select device 708h may enable the MTJ network 710h associated with the configuration bit cluster 706h.

[0077] The activation of a given MTJ network associated with a given configuration bit cluster may cause an operation (e.g., a read operation or a write operation) associated with the configuration bits of the given configuration bit cluster to be performed. As discussed herein, a subset of configuration bit clusters may store network component data stored via individual configuration bit states. Thus, activating an MTJ network associated with one or more configuration bit clusters may cause an operation to be performed by those one or more configuration bit clusters. For example, activating MTJ network 710h may cause states associated with the configuration bits of cluster 706h to be loaded into read latch block 704. These states may represent network component data stored at cluster 706h. In addition, these states may be provided from read latch block 704 to core 418.

[0078] The read latch block 704 may be designed to receive (eg, load) network component data (eg, configuration bit states for a given subset of the cluster). Figure 4 Compared to the volatile distributed memory 402 of FIG. 4 , the volatile distributed memory 702 can be designed to have a single read latch block 704 component. Such a read latch block 704 component can be designed to load network component data from a subset of configuration bit clusters addressed (e.g., enabled) via the core 418. Therefore, the volatile distributed memory 702 can be designed to have fewer electrical components than the volatile distributed memory 402 that can be designed to have multiple read latch blocks (e.g., a read latch block associated with each cluster).

[0079] Each volatile distributed memory 702 cluster may have a corresponding read selection device (e.g., a read selection device 708h associated with cluster 706h). The read selection device may effectively operate as a switch that changes the connected MTJ network from a power-off state to a power-on state and / or performs an operation. Although the read selection device is generally disclosed herein as corresponding to a given cluster of volatile distributed memory 702, it will be understood that each configuration bit or a subset of configuration bits associated with the cluster may be associated with a respective read selection block. As discussed herein, the core 418 may address a given subset of the cluster. The core 418 may address a given subset of the cluster to perform a read or write operation. Such addressing may include receiving a start signal at one or more clusters from the core 418. Such addressing may enable the corresponding read selection block to enable the corresponding MTJ network of the given subset of the cluster. During a write operation, enabling the corresponding MTJ network may cause the network component data to be loaded into the configuration bits of the cluster subset. During a read operation, the corresponding MTJ network is enabled to connect to one or more columns (e.g., electrical paths) connected to the read select device. The connection can cause the network component data stored via these MTJ networks to be loaded into the read latch block 704 for transmission to the core 418. Therefore, the read latch block 704 can be designed to load the network component data associated with a single cluster at a given time.

[0080] According to an embodiment of the disclosed subject matter, the local buffer 118 can be replaced by a multiplexer (Mux) circuit that outputs network component data (e.g., multiple sets of bit values) from a subset of multiple configuration bit clusters of a volatile distributed memory (e.g., volatile distributed memory 402 or volatile distributed memory 702 as discussed herein). For such an embodiment, the identified subset of multiple configuration bit clusters of the volatile distributed memory can remain in a powered-on state during a read operation. In addition, for such an embodiment, the identified subset of multiple configuration bit clusters of the volatile distributed memory can be enabled to be in a powered-on state to perform a write operation, and can be disabled (e.g., powered off) after the write operation is completed. It will be understood that although the embodiments disclosed herein generally relate to networks (e.g., neural networks), these embodiments are also applicable to any distributed core or distributed computing implementation.

[0081] Fig. 8A Flowchart 800 depicts an exemplary method for performing a read operation using a volatile distributed memory and a local buffer as disclosed herein. At step 802 of flowchart 800, a network layer for performing a memory operation may be identified. The identified network layer may be identified based on a memory operation performed or to be performed associated with the identified network layer.

[0082] At step 804, a subset of a plurality of configuration bit clusters of a volatile distributed memory (e.g., volatile distributed memory 402 or volatile distributed memory 702 as discussed herein) may be identified. The identified subset of the plurality of configuration bit clusters of the volatile distributed memory may be identified as mapping to the network layer identified at step 802. As discussed herein, the identified subset of the plurality of configuration bit clusters of the volatile distributed memory may be a cluster storing network component data associated with the network layer identified at 802.

[0083] At step 806, the subset of the plurality of configuration bit clusters of the volatile distributed memory identified at step 804 may be activated. These clusters may be activated from a power-off state rather than a power-on state or a standby power state. Activation of these clusters may be real-time (e.g., less than about 10 ns).

[0084] At step 808, network component data stored at the subset of the plurality of configuration bit clusters of the volatile distributed memory initiated at step 806 may be loaded into a local buffer. The loading may include transferring the network component data stored in the subset of clusters to the local buffer. At step 810, the network component data loaded at step 808 may be applied to the network layer identified at step 802. Such applying may include providing the network component data loaded into the local buffer to the identified network layer via an electrical connection.

[0085] Figure 8B Flowchart 820 depicts an exemplary method for performing write operations using volatile distributed memory and local buffers as disclosed herein. At step 822 of flowchart 820, a network layer for performing memory operations may be identified in a manner similar to that described with reference to step 802 of flowchart 800. At step 824, a subset of a plurality of configuration bit clusters of a volatile distributed memory (e.g., volatile distributed memory 402 or volatile distributed memory 702 as discussed herein) may be identified in a manner similar to that described with reference to step 804 of flowchart 800.

[0086] At step 826, the subset of the plurality of configuration bit clusters of the volatile distributed memory identified at step 824 may be enabled in a manner similar to that described with reference to step 806 of flowchart 800. At step 828, network component data may be loaded from a local buffer into the subset of the plurality of configuration bit clusters of the volatile distributed memory identified at step 824. The network component data may be loaded by transferring network component data received at the local buffer (e.g., from the network layer identified at step 822) to the subset of the plurality of configuration bit clusters of the volatile distributed memory. At step 830, the network component data loaded at step 828 may be stored at the subset of the plurality of configuration bit clusters of the volatile distributed memory. The subset of the plurality of configuration bit clusters of the volatile distributed memory may be powered off (e.g., deactivated) such that the network component data stored at step 830 may remain stored at such clusters for subsequent reading or modification (e.g., writing).

[0087] Thus, flow charts 800 and 820 provide techniques for using a local buffer and a volatile distributed memory. Such use can be implemented without consuming any standby current because the plurality of configuration bit clusters of the volatile distributed memory can be directly started up from a shutdown state (e.g., in less than about 10 ns) to perform an operation (e.g., a read or write operation).

[0088] One or more implementations disclosed herein may be applied using a machine learning model, a neural network, or a non-AI rule-based system. For example, a trained neural network may be used to perform one or more inference operations. A neural network may be trained by updating one or more layers of a neural network and / or based on generating, updating, and / or modifying network component data associated with one or more such layers. Such training may be based on, for example, training data. For example, Fig. 9 As shown in flowchart 910 of FIG. 1 , training data 912 may include one or more of level inputs 919 and known results 918 associated with a neural network to be trained (e.g., during a learning operation). Level inputs 919 may come from any applicable source, including an input or system. For a neural network generated based on supervised or semi-supervised training, known results 918 may be included. Known results 918 may not be used to train an unsupervised neural network. Known results 918 may include known or expected outputs for future inputs that are similar or belong to the same category as level inputs 919 that do not have corresponding known outputs.

[0089] The training data 912 and the training algorithm 920 may be provided to a training component 930, which may apply the training data 912 to the training algorithm 920 to generate, update, or modify network component data associated with one or more layers of the neural network. Depending on the implementation, the training component 930 may provide a comparison result 916 that compares a previous output of the corresponding neural network to apply the previous results to retrain the neural network. The comparison result 916 may be used by the training component 930 to update the network component data corresponding to the layer of the neural network. The training algorithm 920 may utilize a machine learning network and / or model, including but not limited to a deep learning network, such as a deep neural network (DNN), a convolutional neural network (CNN), a fully convolutional network (FCN), and a recurrent neural network (RCN), a probabilistic model such as a Bayesian Network and a graphical model, and / or a discriminative model such as a decision forest and a maximum margin method, or the like.

[0090] In general, any process or operation discussed in this disclosure is understood to be computer-implemented, such as described herein (e.g., in Figures 1 to 9The processes and / or procedures discussed in the present invention may be performed by one or more processors of a computer system, any system or device for implementing the technology disclosed herein. The process or process steps performed by one or more processors may also be referred to as operations. The one or more processors may be configured to perform such a process by accessing instructions (e.g., software or computer readable code) that, when executed by the one or more processors, cause the one or more processors to perform the process. The instructions may be stored in a memory of a computer system. The processor may be a central processing unit (CPU), a graphics processing unit (GPU), or any suitable type of processing unit.

[0091] Although the principles of the present disclosure are described herein with reference to illustrative examples of specific applications, it should be understood that the present disclosure is not limited thereto. For example, instead of a bit cell (e.g., configuration bit) based on MTJ, another memory bit such as a resistive RAM or ferroelectric RAM bit technology can be used to design an anti-fuse circuit system using the present disclosure. Another memory bit can have a programmed state and at least one unprogrammed state. The at least one unprogrammed state can also include a plurality of unprogrammed states, for example, a low unprogrammed state, a high unprogrammed state, and one or more intermediate unprogrammed states. The general skilled person and the skilled person who obtains the teachings provided herein will recognize that additional modifications, applications, embodiments, and replacements of equivalents all fall within the scope of the features described herein. Therefore, the required features should not be considered to be limited by the previous description.

[0092] In one embodiment, the present disclosure is interested in a method comprising: identifying a network layer for performing a memory operation; identifying a subset of a plurality of configuration bit clusters of a volatile distributed memory, the configuration bit clusters of the subset being mapped to the identified network layer using a cluster map; in response to identifying the subset of the plurality of configuration bit clusters, initiating the subset of the plurality of configuration bit clusters; loading network component data from the subset of the plurality of configuration bit clusters into a local buffer; and applying the network component data to the network layer for performing the memory operation.

[0093] Various aspects of the present disclosure may include one or more of the following features: the network layer is identified based on the memory operation; the cluster map is at least one of a mapping table, a pointer-based system, or a mapping database; the subset of the plurality of configuration bit clusters is activated by applying a minimum threshold voltage to the subset of the plurality of configuration bit clusters; the subset of the plurality of configuration bit clusters is activated in less than about 10ns from the application of the minimum threshold voltage; the volatile distributed memory is one of a magnetoresistive random access memory (MRAM) or a register memory; when loading the network component data, the subset of the plurality of configuration bit clusters is deactivated; after deactivating the subset of the plurality of configuration bit clusters, a second subset of the plurality of configuration bit clusters is activated; and a cluster update operation for the second subset of the plurality of configuration bit clusters is triggered, wherein the cluster update operation includes writing updated network component data to the second subset of the plurality of configuration bit clusters, wherein the updated network component data is received from the local buffer; the plurality of The subset of configuration bit clusters stores one or more of weights or biases associated with the network layer; the network layer is a neural network layer, wherein the memory operation is one of an inference operation or a training operation associated with the neural network layer; starting the subset of the plurality of configuration bit clusters includes: receiving a start signal at the subset of the plurality of configuration bit clusters from the local buffer; in response to receiving the start signal, starting a read selection device associated with the subset of the plurality of configuration bit clusters; and in response to starting the read selection device, connecting an MTJ network associated with a cluster in the subset of the plurality of configuration bit clusters to a column connected at a read latch block of the volatile distributed memory, wherein loading network component data from the subset of the plurality of configuration bit clusters into the local buffer includes: in response to the MTJ network being connected to the column connected at the read latch block, loading a configuration bit state associated with the MTJ network into the read latch block; and providing the configuration bit state to the local buffer.

[0094] In another embodiment, the present disclosure is interested in a method comprising: identifying a network layer that performs memory operations; identifying a subset of multiple configuration bit clusters of a volatile distributed memory, wherein the configuration bit clusters of the subset are mapped to the identified network layer using a cluster mapping; in response to identifying the subset of the multiple configuration bit clusters, starting the subset of the multiple configuration bit clusters; loading network component data from a local buffer into the subset of the multiple configuration bit clusters; and storing the network component data at the subset of the multiple configuration bit clusters.

[0095] Various aspects of the present disclosure may include one or more of the following features: the subset of the multiple configuration bit clusters is activated by applying a minimum threshold voltage to the subset of the multiple configuration bit clusters; the subset of the multiple configuration bit clusters is activated in less than about 10ns from applying the minimum threshold voltage.

[0096] In yet another embodiment, the present disclosure is of interest in a system comprising: a network comprising a plurality of network layers, the plurality of network layers comprising a first layer identified for performing a memory operation; a local buffer communicating with a cluster map; and a volatile distributed memory comprising a plurality of configuration bit clusters, wherein the local buffer: initiates a subset of the plurality of configuration bit clusters based on the cluster map, receives network component data from the subset of the plurality of configuration bit clusters, and provides the network component data to the first layer identified for performing the memory operation.

[0097] Various aspects of the present disclosure may include one or more of the following features: the local buffer is on the same chip as the volatile distributed memory; the subset of the plurality of configuration bit clusters is enabled in less than about 10 ns from application of a minimum threshold voltage.

[0098] The foregoing description of the present invention has been described for the purpose of clarity and understanding. It is not intended to limit the present invention to the precise form disclosed. Various modifications may be possible within the scope and equivalents of this application.

Claims

1. A method, comprising: identifying a network layer used to perform the memory operation; identifying a subset of a plurality of configuration bit clusters of a volatile distributed memory, the configuration bit clusters of the subset being mapped to the identified network layer using a cluster map; responsive to identifying the subset of the plurality of configuration bit clusters, enabling the subset of the plurality of configuration bit clusters; loading network component data from said subset of said plurality of configuration bit clusters into a local buffer; as well as The network component data is applied to the network layer for performing the memory operation.

2. The method of claim 1, wherein the network layer is identified based on the memory operation.

3. The method of claim 1, wherein the cluster map is at least one of a mapping table, a pointer-based system, or a mapping database.

4. The method of claim 1, wherein the subset of the plurality of configuration bit clusters is enabled by applying a minimum threshold voltage to the subset of the plurality of configuration bit clusters.

5. The method of claim 4, wherein said subset of said plurality of configuration bit clusters is enabled in less than about 10 ns from said applying of said minimum threshold voltage.

6. The method of claim 1, wherein the volatile distributed memory is one of a magnetoresistive random access memory (MRAM) or a register memory.

7. The method of claim 1, further comprising, when loading the network component data, deactivating the subset of the plurality of configuration bit clusters.

8. The method of claim 7, further comprising: After deactivating the subset of the plurality of configuration bit clusters, activating a second subset of the plurality of configuration bit clusters; as well as A cluster update operation is triggered for the second subset of the plurality of configuration bit clusters, wherein the cluster update operation comprises writing updated network component data to the second subset of the plurality of configuration bit clusters.

9. The method of claim 8, wherein the updated network component data is received from the local buffer.

10. The method of claim 1, wherein the subset of the plurality of configuration bit clusters stores one or more of weights or biases associated with the network layer.

11. The method of claim 1, wherein the network layer is a neural network layer.

12. The method of claim 11, wherein the memory operation is one of an inference operation or a training operation associated with the neural network layer.

13. The method of claim 1 , wherein enabling the subset of the plurality of configuration bit clusters comprises: receiving an enable signal at the subset of the plurality of configuration bit clusters from the local buffer; activating a read selection device associated with the subset of the plurality of configuration bit clusters in response to receiving the activation signal; as well as In response to activating the read selection device, MTJ networks associated with clusters in the subset of the plurality of configuration bit clusters are connected to columns connected at a read latch block of the volatile distributed memory.

14. The method of claim 13, wherein loading network element data from the subset of the plurality of configuration bit clusters into the local buffer comprises: in response to the MTJ network being connected to the column connected at the read latch block, loading a configuration bit state associated with the MTJ network into the read latch block; as well as The configuration bit state is provided to the local buffer.

15. A method comprising: Identify the network layer that performs the memory operation; identifying a subset of a plurality of configuration bit clusters of a volatile distributed memory, the configuration bit clusters of the subset being mapped to the identified network layer using a cluster map; responsive to identifying the subset of the plurality of configuration bit clusters, enabling the subset of the plurality of configuration bit clusters; loading network component data from a local buffer into said subset of said plurality of configuration bit clusters; as well as The network element data is stored at the subset of the plurality of configuration bit clusters.

16. The method of claim 15, wherein the subset of the plurality of configuration bit clusters is enabled by applying a minimum threshold voltage to the subset of the plurality of configuration bit clusters.

17. The method of claim 16, wherein said subset of said plurality of configuration bit clusters is enabled in less than about 10 ns from said applying of said minimum threshold voltage.

18. A system, comprising: a network comprising a plurality of network layers, the plurality of network layers including a first layer identified for performing a memory operation; a local buffer in communication with the cluster map; as well as A volatile distributed memory comprising a plurality of configuration bit clusters, wherein the local buffer: enabling a subset of the plurality of configuration bit clusters based on the cluster map; receiving network component data from said subset of said plurality of configuration bit clusters; and The network component data is provided to the first layer identified for performing the memory operation.

19. The system of claim 18, wherein the local buffer and the volatile distributed memory are on the same chip.

20. The system of claim 18, wherein said plurality of said configuration bit clusters of said subset are enabled in less than about 10 ns from application of a minimum threshold voltage.

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