A multifunctional protection device and its manufacturing process

Abstract

The invention discloses a multifunctional protection device and a manufacturing process thereof, belonging to the technical field of protection devices. A silicon dioxide layer is grown on a P-type single-crystal silicon wafer, a boron ion implantation window is photoetched on the front side of the P-type single-crystal silicon wafer, a light boron layer is doped on the front side of the P-type single-crystal silicon wafer by ion implantation, and the light boron layer is redistributed by high-temperature diffusion, a light phosphorus implantation window is photoetched on the front and back sides of the P-type single-crystal silicon wafer, a phosphorus layer is ion implanted on the front and back sides of the P-type single-crystal silicon wafer, and the phosphorus layer is redistributed by high-temperature diffusion, a concentrated boron diffusion zone window is photoetched on the front side of the P-type single-crystal silicon wafer, concentrated boron diffusion is performed on the front side, concentrated phosphorus layer diffusion windows are photoetched on the front and back sides of the P-type single-crystal silicon wafer, concentrated phosphorus layer diffusion is performed on both sides, a groove etching window is photoetched on the front side of the P-type single-crystal silicon wafer, silicon etching is performed to form an inner groove mesa structure, and metallization treatment is performed on the front and back sides of the P-type single-crystal silicon wafer to construct a metal layer.

Description

Technical Field

[0001] The present invention relates to a protection device, in particular to a multifunctional protection device and a manufacturing process thereof, belonging to the technical field of protection devices. Background Art

[0002] A Zener diode is a surface-contact crystal diode made of silicon material, also known as a Zener diode. This diode is a semiconductor device with very high resistance until the critical reverse breakdown voltage. When the Zener diode breaks down in reverse, the terminal voltage remains almost unchanged within a certain current range, exhibiting a voltage-stabilizing characteristic. Therefore, it is widely used in voltage-stabilized power supplies and limiting circuits.

[0003] A trigger diode is a special diode, also known as a trigger tube. Based on its special four-layer PNPN structure, it can conduct in both forward and reverse directions. The unidirectional trigger tube is improved on the basis of the bidirectional trigger tube. When working, it only uses one direction to trigger the voltage, and the chip manufacturing process is simpler than that of the bidirectional trigger tube. This device has a wide range of applications, such as power switches, AC dimming, motor control, negative ion generators, pulse igniters and other fields.

[0004] As common discrete devices, the two diodes are independently manufactured in chip manufacturing and finished product packaging. However, in actual use, they are often used together in some circuits. With the trend of miniaturization of integrated circuit packaging and the requirement of cost reduction, various circuit board manufacturers are trying to reduce the package volume and reduce the area of ​​​​circuit boards. However, the two devices as independent devices cannot be reduced any further and have reached the design limit. Therefore, a multifunctional protection device and its manufacturing process are designed to solve the above problems. Summary of the Invention

[0005] The main purpose of the present invention is to provide a multifunctional protection device and a manufacturing process thereof.

[0006] The purpose of the present invention can be achieved by adopting the following technical solutions:

[0007] A multifunctional protective device manufacturing process comprises the following steps:

[0008] Step 1: growing a silicon dioxide layer on the front and back of a P-type single crystal silicon wafer by thermal oxidation;

[0009] Step 2: Photolithography a boron ion implantation window on the front side of the P-type single crystal silicon wafer;

[0010] Step 3: A light boron layer is doped on the front side of the P-type single crystal silicon wafer by ion implantation. The light boron layer is then redistributed by high-temperature diffusion. At the same time, a silicon dioxide layer is grown on the surface to serve as a mask for subsequent diffusion.

[0011] Step 4: Photolithography of light phosphorus injection windows on the front and back of the P-type single crystal silicon wafer;

[0012] Step 5: Ion implantation of a phosphorus layer is performed on the front and back sides of the P-type single crystal silicon wafer. The phosphorus layer is then distributed through high-temperature diffusion. At the same time, a silicon dioxide layer is grown on the surface as a mask for subsequent diffusion.

[0013] Step 6: Photolithography of the boron-rich diffusion window on the front side of the P-type single crystal silicon wafer;

[0014] Step 7: Diffuse a concentrated boron layer on the front side of the P-type single crystal silicon wafer, and simultaneously grow a layer of silicon dioxide on the surface as a masking layer for subsequent diffusion;

[0015] Step 8: Photolithography to create phosphorus-rich windows on the front and back of the P-type single crystal silicon wafer;

[0016] Step 9: Diffusion of concentrated phosphorus layer is performed on the front and back of the P-type single crystal silicon wafer, and a layer of silicon dioxide is grown on the surface as a subsequent masking layer;

[0017] Step 10: Photolithography a trench etching window on the front side of the P-type single crystal silicon wafer;

[0018] Step 11: Perform silicon etching at the trench etching window on the front side of the P-type single crystal silicon wafer to form an inner trench mesa structure;

[0019] Step 12: Fill a layer of glass into the inner trench mesa formed on the front side of the P-type single crystal silicon wafer as a PN junction protection passivation layer;

[0020] Step 13: Deposit a silicon dioxide layer on the front of the P-type single crystal silicon wafer by LPCVD;

[0021] Step 14: Photoetch the lead windows of the trigger tube and the voltage regulator tube on the front and back of the P-type single crystal silicon wafer, and at the same time, open the scribe grooves on the edge;

[0022] Step 15: Metallization treatment is performed on the front and back sides of the P-type single crystal silicon wafer to construct a metal layer;

[0023] Step 16: Photoetching the electrode lead welding area on the front side of the P-type single crystal silicon wafer;

[0024] Step 17: Alloying is performed under vacuum to form an ohmic contact between the metal layer and the silicon, thereby completing the device protection.

[0025] Preferably, in step 1, the resistivity of the P-type single crystal silicon wafer is 20-100 Ω.cm.

[0026] Preferably, the ion implantation energy of the light boron layer doped by ion implantation in step 3 is E=60~110KeV, and the dose DOSE=1E13 / cm 2 ~8E14 / cm 2 ;

[0027] The temperature of the light boron layer diffusion is: 1260℃~1280℃, time: 80~120h, and the final x j =60~100µm.

[0028] Preferably, in step 5, the ion implantation energy E=60~110KeV and the dose DOSE=5E14 / cm 2 ~2E15 / cm 2 ;

[0029] The temperature of phosphorus layer re-diffusion is: 1230℃~1260℃, time: 20~50h, and the final x j =15~35µm.

[0030] Preferably, the temperature of the pre-diffusion of the concentrated boron layer in step seven is: 1000°C~1100°C, time: 60min~300min, and surface concentration R=2~15Ω / □;

[0031] The temperature of the concentrated boron layer is 1150℃~1250℃, the time is 5~10h, and the final x j =10~30µm.

[0032] Preferably, the pre-diffusion temperature of the concentrated phosphorus layer in step nine is: 960° C. to 1100° C., the time is: 60 min to 120 min, and R=0.8 to 5Ω / □;

[0033] The temperature of the concentrated phosphorus layer is: 1000℃~1150℃, time: 4~8h, and the final x j =8~20µm.

[0034] Preferably, the depth of the inner groove terrace in step 11 is 40-80 μm.

[0035] Preferably, the glass passivation temperature in step 12 is 460° C. to 750° C.

[0036] Preferably, in step fifteen, the metal layer on the front and back sides of the P-type single crystal silicon wafer is an aluminum layer on the front side with a thickness of 4 to 6 μm, and the metal layer on the back side is a titanium nickel silver layer with a thickness of 1 to 3 μm.

[0037] A multifunctional protection device includes a P-type single crystal silicon wafer, wherein a phosphorus layer is provided on the back side of the P-type single crystal silicon wafer and near the middle of the front side of the P-type single crystal silicon wafer;

[0038] A concentrated phosphorus layer is provided in the phosphorus layer on the front side of the P-type single crystal silicon wafer, and a concentrated phosphorus layer is provided in the phosphorus layer on the back side of the P-type single crystal silicon wafer;

[0039] A light boron layer is provided on the front side of the P-type single crystal silicon wafer and below the phosphorus layer on the front side of the P-type single crystal silicon wafer;

[0040] A concentrated boron layer is also provided in the phosphorus layer on the front side of the P-type single crystal silicon wafer.

[0041] Beneficial technical effects of the present invention:

[0042] The present invention provides a multifunctional protection device and its manufacturing process. The product of this patent can achieve the purpose of replacing two different types of chips with one chip. One chip realizes two functions. The chip manufacturing is applicable to the same process platform, which greatly saves the chip production cost and cycle.

[0043] The trigger voltage of the trigger tube can be adjusted arbitrarily between 70-300V. Based on the same chip, only fine-tuning of the process is required to meet the voltage requirements of different application fields. There is no need to design and develop chips separately, and the two chips are not affected by each other.

[0044] A three-terminal package shape can replace the original two two-terminal package shapes, saving the package cost and reducing the space occupied by the circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A chip cross-sectional view of a preferred embodiment of a multifunctional protection device and its manufacturing process according to the present invention;

[0046] Figure 2 A front plan view of a preferred embodiment of a multifunctional protection device and a manufacturing process thereof according to the present invention;

[0047] Figure 3 A circuit diagram of a preferred embodiment of a multifunctional protection device and a manufacturing process thereof according to the present invention;

[0048] Figure 4-Figure 18 A schematic diagram is made for each step of a preferred embodiment of a multifunctional protection device and a manufacturing process thereof according to the present invention.

[0049] In the figure: 1. P-type single crystal silicon wafer, 2. Silicon dioxide layer, 3. Boron ion implantation window, 4. Light boron layer, 5. Light phosphorus implantation window, 6. First phosphorus layer, 7. Titanium nickel silver layer, 8. Concentrated boron diffusion region window, 9. Concentrated boron layer, 10. Concentrated phosphorus region window; 11. Concentrated phosphorus layer, 12. Groove corrosion window, 13. Inner groove mesa, 14. PN junction protection passivation layer, 15. Lead window, 16. Aluminum layer, 17. Electrode lead welding area. DETAILED DESCRIPTION

[0050] In order to make the technical solution of the present invention more clear and specific to those skilled in the art, the present invention is further described in detail below with reference to embodiments and drawings, but the embodiments of the present invention are not limited thereto.

[0051] like Figure 1-2 The manufacturing process of a multifunctional protection device chip shown includes the following steps:

[0052] Step 1) A silicon dioxide layer 2 is grown on a P-type single crystal silicon wafer 1 having a resistivity of 20-100 Ω.cm by thermal oxidation. Figure 4 ;

[0053] Step 2) Photolithography of the boron ion implantation window 3 on the front side, see Figure 5 ;

[0054] Step 3) The front side is doped with a light boron layer 4 by ion implantation, and the light boron layer 4 is redistributed by high temperature diffusion. At the same time, a layer of silicon dioxide 2 is grown on the surface as a mask for subsequent diffusion. The ion implantation energy E = 60~110KeV and the dose DOSE = 1E13 / cm 2 ~8E14 / cm 2 Boron re-diffusion temperature: 1260℃~1280℃, time: 80~120h, final x j =60~100µm, see Figure 6 ;

[0055] Step 4) Double-sided photolithography to create a light phosphorus injection window 5, see Figure 7 ;

[0056] Step 5) Phosphorus layer 6 is ion-implanted on both sides of the chip and distributed by high-temperature diffusion. At the same time, a silicon dioxide layer 2 is grown on the surface as a mask for subsequent diffusion. The ion implantation method is to dope a layer of light phosphorus with an ion implantation energy of E=60~110KeV and a dose of DOSE=5E14 / cm 2 ~2E15 / cm 2 ; Phosphorus re-diffusion temperature: 1230℃~1260℃, time: 20~50h, final x j =15~35µm, see Figure 8 ;

[0057] Step 6) Photolithography of the concentrated boron diffusion area window 8 on the front side, see Figure 9 ;

[0058] Step 7) Diffuse the concentrated boron layer 9 on the front surface and grow a silicon dioxide layer 2 on the surface as a mask for subsequent diffusion. The pre-diffusion temperature of the concentrated boron layer 9 is 1000°C to 1100°C and the time is 60min to 300min.

[0059] R=2~15Ω / □; the temperature of the concentrated boron layer 9 is: 1150℃~1250℃, time: 5~10h, and the final x j =10~30µm, see Figure 10 ;

[0060] Step 8) Double-sided photolithography to create a phosphorus-rich window 10, see Figure 11 ;

[0061] Step 9) Diffuse the concentrated phosphorus layer 11 on both sides, and simultaneously grow a silicon dioxide layer 2 on the surface as a subsequent masking layer. The pre-diffusion temperature of the concentrated phosphorus layer 11 is: 960℃~1100℃, and the time is: 60min~120min.

[0062] R = 0.8 ~ 5Ω / □; the temperature of the concentrated phosphorus layer 11 is: 1000 ℃ ~ 1150 ℃, time: 4 ~ 8h, the final xj = 8 ~ 20µm, see Figure 12 ;

[0063] Step 10) Photoetch a groove etch window 12 on the front side, see Figure 13 ;

[0064] Step 11) Silicon etching is performed at the front trench etching window 12 to form an inner trench mesa 13 structure. The depth of the trench is 40~80µm. Figure 14 ;

[0065] Step 12) Fill the inner groove of the front side with a glass layer as the final PN junction protection passivation layer 14. The glass passivation temperature is: 460℃~750℃, see Figure 15 ;

[0066] Step 13) depositing a silicon dioxide layer 2 on the surface by LPCVD, wherein the thickness of the silicon dioxide layer 2 is 0.1-0.5 μm;

[0067] Step 14) Photoetch the lead windows 15 of the trigger tube and the voltage regulator tube on the front and back sides, and at the same time, make scribe grooves on the edges. Figure 16 ;

[0068] Step 15) Metallize the front and back surfaces. The front surface of the metal layer is an aluminum layer 16 with a thickness of 4 to 6 μm, and the back surface is a titanium nickel silver layer 7 with a thickness of 1 to 3 μm. Figure 17 ;

[0069] Step 16) Photolithography the welding area of ​​the electrode lead and remove the metal in the unnecessary area. Figure 18 ;

[0070] Step 17) Alloying is performed in a vacuum at a temperature of 300-500°C to form a good ohmic contact between the metal and silicon, thus completing the chip production. Figure 18 . Example

[0071] The P-type resistivity in step 1 is 20~30Ω.cm; in step 3, the ion implantation energy of the light boron layer 4 is E=70KeV, and the dose DOSE=2.9E14 / cm 2 The temperature of the light boron layer 4 is 1270℃ and the time is 100h. The ion implantation energy of the phosphorus layer 6 in step 5 is E=70KeV and the dose DOSE=9E14 / cm 2 The temperature of phosphorus layer 6 re-diffusion is 1240℃, and the time is 38h; the temperature of concentrated boron layer 9 pre-diffusion in step 7 is 1050℃, and the time is 120min; the temperature of concentrated boron layer 9 re-diffusion is 1180℃, and the time is 5h. The final chip parameters are: trigger tube V DRM :105~110V、I H :10~50mA; V of the voltage regulator tube BR :400~420V. Example

[0072] The P-type resistivity in step 1 is 40~60Ω.cm; in step 3, the ion implantation energy of the light boron layer 4 is E=70KeV, and the dose DOSE=1.35E14 / cm 2 The temperature of the light boron layer 4 is 1270℃ and the time is 102h. The ion implantation energy of the phosphorus layer 6 in step 5 is E=70KeV and the dose DOSE=8.5E14 / cm 2 The temperature of phosphorus layer 6 re-diffusion is 1240℃, and the time is 40h; the temperature of concentrated boron layer 9 pre-diffusion in step 7 is 1060℃, and the time is 150min; the temperature of concentrated boron layer 9 re-diffusion is 1200℃, and the time is 5h. The final chip parameters are: trigger tube V DRM : 145~155V, IH: 10~50mA; VBR of Zener diode: 600~700V.

[0073] The above is only a further embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes based on the technical solutions and concepts of the present invention within the scope disclosed by the present invention, which fall within the scope of protection of the present invention.

Claims

1. A process for manufacturing a multifunctional protection device, characterized in that: The steps include: Step 1: growing a silicon dioxide layer (2) on the front and back sides of the P-type single crystal silicon wafer (1) by thermal oxidation; Step 2: Photolithography a boron ion implantation window (3) on the front surface of the P-type single crystal silicon wafer (1); Step 3: doping a light boron layer (4) on the front side of the P-type single crystal silicon wafer (1) by ion implantation, and redistributing the light boron layer (4) by high temperature diffusion, while growing a silicon dioxide layer (2) on the surface as a masking layer for subsequent diffusion; Step 4: Photolithography of light phosphorus injection windows (5) on the front and back of the P-type single crystal silicon wafer (1); Step 5: Ion implantation of a phosphorus layer (6) is performed on the front and back surfaces of the P-type single crystal silicon wafer (1), and the phosphorus layer (6) is distributed by high-temperature diffusion. At the same time, a silicon dioxide layer (2) is grown on the surface as a masking layer for subsequent diffusion. Step 6: Photolithography of a concentrated boron diffusion region window (8) on the front side of the P-type single crystal silicon wafer (1); Step 7: Diffuse a concentrated boron layer (9) on the front surface of the P-type single crystal silicon wafer (1), and simultaneously grow a silicon dioxide layer (2) on the surface as a masking layer for subsequent diffusion; Step 8: Photolithography of concentrated phosphorus area windows (10) on the front and back of the P-type single crystal silicon wafer (1); Step nine: Diffusion of a concentrated phosphorus layer (11) is performed on the front and back surfaces of the P-type single crystal silicon wafer (1), and a silicon dioxide layer (2) is grown on the surface as a subsequent masking layer; Step 10: Photolithography a trench etching window (12) on the front side of the P-type single crystal silicon wafer (1); Step 11: performing silicon etching at the front trench etching window of the P-type single crystal silicon wafer (1) to form an inner trench mesa (13) structure; Step 12: Filling a glass layer into the inner groove mesa (13) formed on the front side of the P-type single crystal silicon wafer (1) as a PN junction protection passivation layer (14); Step 13: depositing a silicon dioxide layer (2) on the front surface of the P-type single crystal silicon wafer (1) by LPCVD; Step 14: Photoetching the lead windows (15) of the trigger tube and the voltage regulator tube on the front and back of the P-type single crystal silicon wafer (1), and simultaneously opening a scribe groove on the edge; Step 15: Perform metallization treatment on the front and back of the P-type single crystal silicon wafer (1) to construct a metal layer; Step 16: Photoetching an electrode lead welding area (17) on the front side of the P-type single crystal silicon wafer (1); Step 17: Alloying is performed under vacuum to form an ohmic contact between the metal layer and the silicon, thereby completing the device protection.

2. The process for manufacturing a multifunctional protective device according to claim 1, characterized in that: In step 1, the resistivity of the P-type single crystal silicon wafer (1) is 20-100 Ω.cm.

3. The process for manufacturing a multifunctional protective device according to claim 2, characterized in that: In step 3, the ion implantation energy of the light boron layer (4) doped by ion implantation is E=60~110KeV, and the dose DOSE=1E13 / cm2~8E14 / cm2; The diffusion temperature of the light boron layer (4) is: 1260℃~1280℃, the time is: 80~120h, and the final xj=60~100µm.

4. The process for manufacturing a multifunctional protective device according to claim 3, characterized in that: In step 5, the phosphorus layer (6) is doped by ion implantation with an ion implantation energy of E=60~110KeV and a dose of DOSE=5E14 / cm2~2E15 / cm2; The temperature of the phosphorus layer (6) is 1230℃~1260℃, the time is 20~50h, and the final xj=15~35μm.

5. The process for manufacturing a multifunctional protective device according to claim 4, characterized in that: The pre-diffusion temperature of the concentrated boron layer (9) in step 7 is: 1000℃~1100℃, time: 60min~300min, surface concentration R=2~15Ω / □; The temperature of the re-diffusion of the concentrated boron layer (9) is: 1150℃~1250℃, time: 5~10h, and the final xj=10~30μm.

6. The process for manufacturing a multifunctional protective device according to claim 5, characterized in that: In step nine, the pre-diffusion temperature of the concentrated phosphorus layer (11) is: 960°C~1100°C, the time is: 60min~120min, R=0.8~5Ω / □; The re-diffusion temperature of the concentrated phosphorus layer (11) is: 1000℃~1150℃, time: 4~8h, and the final xj=8~20μm.

7. The process for manufacturing a multifunctional protective device according to claim 6, characterized in that: The depth of the inner groove terrace (13) in step 11 is 40~80μm.

8. The process for manufacturing a multifunctional protective device according to claim 7, characterized in that: The glass passivation temperature in step 12 is: 460℃~750℃.

9. The process for manufacturing a multifunctional protection device according to claim 8, characterized in that: In step 15, the metal layers on the front and back of the P-type single crystal silicon wafer (1) are aluminum layers (16) on the front with a thickness of 4 to 6 μm, and titanium nickel silver layers (7) on the back with a thickness of 1 to 3 μm.

10. A multifunctional protection device, manufactured based on the multifunctional protection device manufacturing process according to claim 9, characterized in that: It comprises a P-type single crystal silicon wafer (1), wherein a phosphorus layer (6) is provided on the back side of the P-type single crystal silicon wafer (1) and near the middle of the front side of the P-type single crystal silicon wafer (1); A concentrated phosphorus layer (11) is provided in the phosphorus layer (6) on the front side of the P-type single crystal silicon wafer (1), and a concentrated phosphorus layer (11) is laid on the phosphorus layer (6) on the back side of the P-type single crystal silicon wafer (1); A light boron layer (4) is provided on the front surface of the P-type single crystal silicon wafer (1) and below the phosphorus layer (6) on the front surface of the P-type single crystal silicon wafer (1); A concentrated boron layer (9) is also provided in the phosphorus layer (6) on the front surface of the P-type single crystal silicon wafer (1).

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