Bus measurement for calculating and displaying timing characteristics of bus protocol in test and measurement instrument

Abstract

The invention discloses a bus measurement for calculating and displaying timing characteristics of a bus protocol in a test and measurement instrument. Systems and methods enable measurement in a test and measurement instrument of an operating signal timing parameter of an electrical signal transmitted by a device under test over an electrical bus. The bus timing characteristic analyzer identifies nominal signal timing parameters for the acquired electrical signals. The nominal signal timing parameter is defined by a bus protocol and defines a timing criterion for the electrical signal. The analyzer measures an operating signal timing parameter for each of the acquired electrical signals, and for each of the electrical signals, compares the operating signal timing parameter to a nominal signal timing parameter to determine whether the operating signal timing parameter satisfies a timing criterion. The analyzer then displays a visual indication of each of the electrical signals on the test and measurement instrument, which indicates whether the operating signal timing parameter of the electrical signals satisfies the timing criteria.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present disclosure claims priority under 35 U.S.C. §119 to Indian Provisional Patent Application No. 202321057202, filed on August 25, 2023, entitled “BUS MEASUREMENT TO CALCULATE AND DISPLAY THE REPORT FOR TIMING CHARACTERISTICS OF ANY BUS PROTOCOL IN OSCILLOSCOPE,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure generally relates to acquiring and decoding electrical signals being transmitted on an electrical bus using a test and measurement instrument, and more particularly to a test and measurement instrument that determines whether the acquired electrical signals to be decoded meet required timing characteristics defined by a bus protocol of the electrical bus. Background Art

[0003] In test and measurement instruments such as oscilloscopes, protocol decoding is the process of converting or decoding electrical signals transmitted by a device under test (DUT) on a serial electrical bus. Protocol decoding converts these electrical signals into corresponding bit sequences as defined by the bus protocol of the electrical bus. This functionality of the test and measurement instrument enables designers to verify the design and operation of the DUT using decoded messages or frames transmitted on the electrical bus. Many different types of serial buses are used today, each with an associated bus protocol defined by a corresponding standard. Each bus protocol includes a protocol layer that describes the encoding techniques for the electrical signals transmitted on the electrical bus, the definitions of different frames and packets, specific bit patterns, and error handling.

[0004] In protocol decoding, the DUT under test is coupled to an electrical bus, and the test and measurement instrument acquires electrical signals transmitted to and from the DUT on the electrical bus. As part of the process, the user configures the protocol decoder in the instrument, including selecting the type of electrical bus under test and the configuration of thresholds and other related settings defined for the selected bus through the bus configuration menu of the protocol decoder. The protocol decoder in the instrument then converts or decodes the acquired electrical signals to generate corresponding frames formed by these electrical signals according to the bus protocol. Decoding includes identifying frame information such as the start of a frame and the end of a frame according to the bus protocol for the electrical bus, and checking the values ​​of different packets transmitted as part of the frame. The protocol decoder identifies errors in the decoded packets and displays the decoded packets together with an indication of the errors detected for review by the user. Errors can include, for example, packets with incorrect values ​​(i.e., bit sequences) and error checking including a cyclic redundancy check (CRC) or a parity check for the decoded packets.

[0005] The configuration of the protocol decoder includes threshold settings used during the decoding of electrical signals to decode the "1" and "0" bits in a bit sequence or bit stream transmitted on the electrical bus. The protocol decoder uses these thresholds along with information from the bus protocol of the electrical bus on which the electrical signal is transmitted to decode the signal. For example, the protocol decoder uses information about the frame format defined for the bus protocol to detect the beginning and end of a frame and to detect different types of frames such as address frames and data frames.

[0006] The signal timing characteristics of the electrical signals transmitted on the electrical bus are also defined by the bus protocol. More specifically, the signal timing characteristics are defined by the nominal signal timing parameters defined for the bus protocol. For example, the nominal signal timing parameters may include rise time and fall time parameters for the rising edge and falling edge of the electrical signal, establish and maintain start condition time parameters, data establish and maintain time parameters, stop condition establish time parameters, define the buffer time parameters of the minimum time between stop and start conditions on the electrical bus, etc., depending on the protocol of the specific electrical bus utilized. The electrical signals transmitted on the electrical bus must meet or comply with the timing characteristics defined by the associated nominal signal timing parameters to ensure the proper operation of the electrical bus. Failure of the electrical signals to comply with these nominal signal timing parameters may result in erroneous information being transmitted on the electrical bus. Test and measurement instruments require improved techniques to ensure that the acquired electrical signals decoded by the protocol decoder meet the required timing characteristics defined by the corresponding bus protocol as part of the electrical signals acquired by decoding. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1is a block diagram of a test and measurement system including a test and measurement instrument according to an embodiment of the present disclosure, the test and measurement instrument including a bus timing characteristics analyzer for analyzing timing characteristics of electrical signals transmitted on an electrical bus.

[0008] Figure 2 is a signal timing diagram illustrating a number of nominal signal timing parameters associated with data and clock signals of an Inter-Integrated Circuit (I2C) electrical bus.

[0009] Figure 3 is a signal timing diagram illustrating data and clock signals of an I2C bus and showing address frames and data frames transmitted on the bus according to the I2C bus protocol.

[0010] Figure 4 is a signal timing diagram showing data and clock signals acquired by the instrument and decoded data and address frames as generated by a protocol decoder of the test and measurement instrument.

[0011] Figure 5 According to the embodiment of the present disclosure, Figure 1 Flowchart of a process performed by a bus timing characteristics analyzer to analyze the timing characteristics of data and clock signals transmitted on an I2C bus.

[0012] Figure 6 The embodiment according to the present disclosure is illustrated. Figure 1 The Bus Timing Characteristics Analyzer presents a sample configuration display on the user interface for configuration by a user of the Bus Timing Characteristics Analyzer.

[0013] Figure 7 According to the embodiment of the present disclosure, Figure 1 The Bus Timing Characteristics Analyzer displays the bus configuration on the test and measurement instrument user interface.

[0014] Figure 8 A bus timing results configuration display presented by a bus timing characteristics analyzer on a user interface of a test and measurement instrument according to an embodiment of the present disclosure is illustrated.

[0015] Fig. 9 A display of bus timing results presented by a bus timing characteristics analyzer on a user interface of a test and measurement instrument according to an embodiment of the present disclosure is illustrated.

[0016] Fig.10 Another example of a bus timing result display according to an embodiment of the present disclosure is illustrated, which further includes a time domain representation of the acquired electrical signal. DETAILED DESCRIPTION

[0017] Embodiments of the present disclosure relate to methods of analyzing timing characteristics of electrical signals transmitted by a device under test (DUT) on an electrical bus and in a test and measurement instrument for testing the DUT, and systems for implementing these methods according to embodiments of the present disclosure.

[0018] According to an embodiment of the present disclosure, a bus timing characteristic analyzer of a test and measurement instrument determines whether the timing characteristics of electrical signals transmitted on an electrical bus meet the timing standards or characteristics required by these electrical signals as defined by the bus protocol of the electrical bus. In response to user input, the bus timing characteristic analyzer is configured for the desired type of electrical bus being used, and in response to the user input, loads or retrieves the nominal signal timing parameters for the electrical signals of the desired bus. The nominal signal timing parameters are defined by the bus protocol and define the timing standards for the electrical signals. The test and measurement instrument captures or acquires the electrical signals transmitted to and from the DUT on the bus, and the bus timing characteristic analyzer measures the operational signal timing parameters of the acquired electrical signals. The bus timing characteristic analyzer then compares the operational signal timing parameters with the nominal signal timing parameters to determine whether the operational signal timing parameters meet the defined timing standards. Then, a visual indication is displayed on the test and measurement instrument by the bus timing characteristic analyzer, the visual indication indicating the result of the comparison. The visual indication displays to the user whether the operational signal timing parameters for the electrical signal meet the timing standards. The bus timing characteristics analyzer also presents a display on the user interface of the test and measurement instrument that enables the user to browse the comparison results for each signal timing parameter. As part of testing the DUT, this browsing enables the user to more closely examine the specific events of the errors detected in the timing characteristics of the electrical signals.

[0019] Figure 1 A test and measurement system 100 is illustrated that includes a test and measurement instrument 102, which includes a bus timing characteristics analyzer 104, which determines whether the timing characteristics of electrical signals ES transmitted on an electrical bus EB meet the timing standards or characteristics required by these electrical signals as defined by the bus protocol of the electrical bus. The electrical signals ES are transmitted on the electrical bus EB by one or more devices 106 coupled to the electrical bus, one of which is a device under test (DUT). The test and measurement instrument 102 captures or acquires the electrical signals ES transmitted by the DUT on the electrical bus over a period of time to generate an “acquisition” or “acquired waveform” of the electrical signals. The bus timing characteristics analyzer 104 analyzes the acquired waveform to determine whether the electrical signals ES transmitted on the electrical bus EB meet the timing characteristics required by these electrical signals as defined by the bus protocol of the electrical bus. Figure 1In an example embodiment of , the electrical bus EB is an Inter-Integrated Circuit (I2C) bus having three devices 106 coupled to the I2C bus in the form of a bus controller 108 and two bus target devices or targets 110, 112. For example, the bus controller 108 may be a microcontroller, and the bus targets 110 and 112 are an Electrically Erasable Programmable Read Only Memory (EEPROM) and a real-time clock module, respectively.

[0020] The instrument 102 includes one or more processors 114, which can be configured to execute instructions from the memory 116, and can execute any method and / or associated steps corresponding to such instructions. The user interface 118 is coupled to the one or more processors 114, and can include, for example, a keyboard, a mouse, a touch screen, an output display, a file storage device, and / or any other control that a user can use to interact with the instrument 102. In some embodiments, the user interface 118 can be connected to a remote interface (not shown) or controlled by a remote interface (not shown) so that the user can control the operation of the instrument 102 in a remote location physically away from the instrument. The display portion of the user interface 118 can be a digital screen such as an LCD, LED, or any other monitor to display waveforms, measurements, and other data to the user. In some embodiments, the main output display of the user interface 118 can also be positioned away from the instrument 102.

[0021] The instrument 102 further includes one or more measurement units 120 that perform the function of measuring parameters and other qualities of signals from the DUT being measured or tested by the instrument 102. Typical measurements include measuring voltage, current, and power of a signal in the time domain, and measuring characteristics of a signal in the frequency domain. The measurement unit 120 represents any measurement typically performed on a test and measurement instrument, and the bus timing characteristics analyzer 104 may be integrated within or coupled to such a measurement unit 120. The test and measurement instrument 102 is coupled via cables 122a, 122b and probes 124a, 124b to sense or detect an electrical signal ES transmitted on the I2C bus. This coupling to the electrical signal ES is represented by the dashed lines of each probe 124a, 124b.

[0022] When the electrical bus EB is Figure 1In the example embodiment of the I2C bus, the electrical signal ES corresponds to the serial data signal SDA and the serial clock signal SCL. As an example, embodiments of the present disclosure relate to an I2C bus, and embodiments of the present disclosure are not limited to test equipment coupled to the I2C bus. The electrical bus EB can be any one of a variety of different types of electrical buses. The electrical bus EB can be any electrical bus in which the characteristics of the electrical signals according to the bus protocol are clearly defined in the bus specification. In some embodiments of the present disclosure, the electrical bus EB is one of an I2C bus, an I3C or "SenseWire" bus, an RS-232 bus, a universal serial bus (USB) bus, an embedded USB (eUSB) bus, a serial peripheral interface (SPI) bus, an embedded SPI (eSPI) bus, and a SENT (i.e., SAE J2716) bus.

[0023] In operation of the bus timing characteristics analyzer 104, a user initially provides input through the user interface 118 of the instrument 102 to configure the bus timing characteristics analyzer for testing of a DUT. The DUT corresponds to one of the devices 106 being tested and is therefore Figure 1 The user inputs include an identification of the type of electrical bus EB that the DUT is utilizing. In response to the user inputs, the bus timing characteristics analyzer 104 is configured to analyze specific timing characteristics of the electrical signal ES transmitted on the identified electrical bus EB. Figure 1 In the example embodiment of , the electrical bus EB is an I2C bus. Thus, in this example, the user input identifies the I2C bus, and the bus timing characteristics analyzer 104 retrieves the corresponding nominal signal timing parameters of the I2C bus from the memory 116, the corresponding nominal signal timing parameters defining the signal timing characteristics of the bus. Alternatively, these nominal signal timing parameters may be stored in another memory (not shown), such as the memory of the bus timing characteristics analyzer 104 or a memory external to the instrument 102.

[0024] In some embodiments, the nominal signal timing parameters of the I2C bus include a rise time parameter tRise for the rising edge of the SDA and SCL signals, a fall time parameter tFall for the falling edge of the SDA and SCL signals, and a clock frequency f that defines the SCL signal. SCLThe clock period tFreq of the I2C bus is tFreq. Each nominal signal timing parameter tRise, tFall, tFreq has a range of acceptable values, where the range is defined by the corresponding minimum and maximum values ​​of the signal timing parameters so that the SDA and SCL signals comply with the bus protocol specification of the I2C bus. Therefore, in some embodiments, the nominal signal timing parameters of the I2C bus include the maximum rise time tRisemax and the minimum rise time tRisemin for the rising edge of the SDA and SCL signals, the maximum fall time tFallmax and the minimum fall time tFallmin for the falling edge of the SDA and SCL signals, and the maximum clock period tFreqmax and the minimum clock period tFreqmin for the SCL signal.

[0025] In addition to these nominal signal timing parameters, in some embodiments of the present disclosure, the bus timing characteristics analyzer 104 may utilize additional or alternative nominal signal timing parameters. For example, additional nominal signal timing parameters that the bus timing characteristics analyzer 104 may utilize include setup and hold times for the SDA signal as defined in the bus protocol specification for the I2C bus, along with setup and hold times for start and stop conditions. Figure 2 is a signal timing diagram illustrating a number of nominal signal timing parameters associated with the SDA and SCL signals. Figure 2 In the example signal timing diagram of , the I2C nominal signal timing parameters tRise and tFall are specified as t r and t f , and the clock period tFreq is not explicitly illustrated. Figure 2 Additional nominal signal timing parameters are also illustrated, which can be used by the bus timing characteristics analyzer 104 in further embodiments of the present disclosure. These additional signal timing parameters include hold start condition time tHD; STA, minimum low clock period tLOW, minimum high clock period tHIGH, data hold time tHD; DAT, establish start condition time tSU; DAT, establish start condition time tSU; STA, hold start condition time tHD; STA, establish stop condition time tSU; STO and bus idle time tBUF. Each of these additional signal timing parameters is defined in the bus protocol of the I2C bus and will be understood by those skilled in the art and therefore will not be described in more detail herein.

[0026] Before describing the operation of the bus timing characteristics analyzer 104 in more detail, the operation of the protocol decoder PD of the instrument 102 will first be briefly described. Typically, the user will use the bus timing characteristics analyzer 104 in conjunction with the protocol decoder PD of the instrument 102. The protocol decoder PD is shown ( Figure 1) is coupled to the measurement unit 120 to receive the acquisition of the SDA, SCL signals from the measurement unit 120. The protocol decoder PD then converts or decodes the bit sequence in the acquisition of the SDA, SCL signals transmitted on the I2C bus into a frame as defined by the bus protocol of the I2C bus. The designer uses the protocol decoder to verify the design and operation of the DUT under test by checking the decoded frames transmitted to and from the DUT on the I2C bus.

[0027] Figure 3 1 is a signal timing diagram illustrating SDA and SCL signals and showing address frames and data frames transmitted on the I2C bus according to the bus protocol. The protocol decoder PD decodes the bit sequence transmitted by the SDA signal using the SCL signal to generate corresponding decoded data. Figure 4 is a signal timing diagram generated by the protocol decoder PD, showing the SCL and SDA signals acquired by the instrument 102 at the top of the diagram and the decoded data of the bit sequence of the SDA signal as generated by the protocol decoder at the bottom of the diagram. The correct values ​​of the address frame A and data frame D being transmitted are known during the DUT test, allowing the protocol decoder PD to detect errors in the decoded values ​​of the address and data frames. The protocol decoder can mark or indicate errors detected in the decoded data as displayed for user review.

[0028] The protocol decoder PD does not perform a timing characteristics analysis of the SDA, SCL signals transmitted on the I2C bus. Therefore, in the case where errors in the decoded data are caused by the timing characteristics of the SDA, SCL signals not meeting the specifications given by the nominal signal timing parameters of the I2C bus, the protocol decoder PD cannot identify such errors. The bus timing characteristics analyzer 104 according to an embodiment of the present disclosure enables the identification of these types of errors caused by errors in the timing characteristics of the SDA, SCL signals. Reference will now be made to Figure 5 The flowchart of FIG. 1 describes the overall operation of the bus timing characteristics analyzer 104 in more detail.

[0029] Figure 5 1 is a flowchart of a process 500 for analyzing the timing characteristics of SDA and SDL signals executed by the bus timing characteristics analyzer 104 according to an embodiment of the present disclosure. Before the bus timing characteristics analyzer 104 starts to execute the process 500, the user uses the user interface 118 ( Figure 1 ) supplies input to select a "protocol utility" option in a configuration menu presented by the user interface. Upon selecting the protocol utility, the user supplies input to identify the type of electrical bus EB being used, and the bus timing characteristics analyzer 104 thereafter performs an analysis of the timing characteristics of the electrical signal ES transmitted on the electrical bus EB. Figure 6-8The configuration of the bus timing characteristics analyzer 104 is described in more detail.

[0030] Once the user provides input to select the I2C bus, the bus timing characteristics analyzer 104 begins execution of the process 500 at operation 502 and loads or retrieves the nominal signal timing parameters of the I2C bus (i.e., the selected bus). As discussed above, in some embodiments, the nominal signal timing parameters include the rise time tRise for the rising edge of the SDA and SCL signals, the fall time tFall for the falling edge of the SDA and SCL signals, and the clock frequency f for the SCL signal. CL Or clock period tFreq. Nominal signal timing parameters may be specified in terms of maximum and minimum values ​​around the nominal values, and thus in some embodiments may include a maximum rise time tRisemax, a minimum rise time tRisemin, a maximum fall time tFallmax, a minimum fall time tFallmin, a maximum clock period tFreqmax, and a minimum clock period tFreqmin for the SCL signal.

[0031] After retrieving the tRisemax, tRisemin, tFallmax, tFallmin, tFreqmax, and tFreqmin parameters at operation 502, process 500 proceeds to operation 504 and detects rising and falling edges in the current acquisition or acquired waveform of the SDA, SCL signals acquired by the instrument 102. The bus timing characteristics analyzer 104 may detect these edges, or the edge detection may be performed by other components in the instrument 102, such as the measurement unit 120. Whether performed by the bus timing characteristics analyzer 104 or by other components in the instrument 102, once the rising and falling edges in the current acquisition or acquired waveform are detected at operation 504, process 500 proceeds to operation 506 and initializes a plurality of operational variables used in calculating the current acquisition operational signal timing parameters of the SDA, SCL signals. The operation variables include the current edge index EDGE, the total edge count EDGECNT, the rise time tRise, the fall time tFall, and the frequency tFreq associated with the rising and falling edges detected in the current acquisition and the frequency of the SCL signal for each unit interval (UI) of the SCL signal. In operation 506, each of EDGE, tRise, tFall, and tFreq is initialized to zero, and the total edge count EDGECNT is set to the total number of edges detected in the acquisition.

[0032] From operation 506, process 500 proceeds to operation 508 and determines whether the current detected edge in the acquisition as defined by the value of edge index EDGE is less than the total edge count EDGECNT. When the determination at operation 508 is true, process 500 proceeds to operation 510 and measures or calculates a rise time tRise of a detected rising edge corresponding to the current value of edge index EDGE. In operation 510, process 500 also measures or calculates a fall time tFall of a detected falling edge corresponding to the current value of edge index EDGE. From operation 510, process 500 proceeds to operation 512 and calculates or measures a clock period tFreq or clock frequency f of a current unit interval UI of the SCL signal. CL Process 500 then proceeds from operation 512 to operation 514 and calculates and saves the values ​​of rise time tRise, fall time tFall, and frequency tFreq associated with the current value of edge index EDGE in the currently acquired measurement vector MV.

[0033] The process 500 then proceeds from operation 514 to operation 516 and determines whether each of the rise time tRise, the fall time tFall, and the frequency tFreq associated with the current value of the edge index EDGE satisfies the timing characteristics or timing criteria defined by the corresponding nominal signal timing parameters retrieved in operation 502. Therefore, in operation 516, the process 500 determines whether the current measured or calculated rise time tRise is greater than the minimum rise time tRisemin and less than the maximum rise time tRisemax, as required by the I2C bus protocol for the rising edge of the SDA, SCL signals. Similarly, in operation 516, the process 500 determines whether the current measured or calculated fall time tFall is greater than the minimum fall time tFallmin and less than the maximum fall time tFallmax, as required by the I2C bus protocol for the falling edge of the SDA, SCL signals. Finally, in operation 516, process 500 also determines whether the currently measured or calculated clock period tFR is greater than the minimum clock frequency tFreqmin and less than the maximum clock frequency tFreqmax, as required by the I2C bus protocol for the SCL signal.

[0034] When one or more of the determinations in operation 516 are negative, process 500 proceeds to operation 518 and generates a separate failure vector FV for each detected failure in operation 516. Thus, process 500 generates a rising-edge failure vector FV-R in operation 518, which indicates whether the rise time tRise of the current rising edge corresponding to the current value of the edge index EDGE meets the timing criteria defined by the corresponding nominal timing parameter (i.e., whether tRisemin < tRise < tRisemax). In operation 518, a pass or fail value is stored in the rising-edge failure vector FV-R to indicate whether the rise time tRise of the current rising edge has passed or failed the timing criteria. In operation 518, process 500 also generates a falling-edge failure vector FV-F and a clock-frequency failure vector FV-CF in operation 518. In operation 518, a pass or fail value is stored in each of the falling-edge failure vector FV-F and the clock-frequency failure vector FV-CF to indicate whether the fall time tFall of the falling edge and the clock frequency fsCL of the clock period tFreq corresponding to the value of the current edge index EDGE have passed or failed the corresponding timing criteria.

[0035] Process 500 proceeds from operation 518 to operation 520, and the value of the current edge index EDGE is incremented, then the process returns to operation 508 and determines whether the current value of the edge index EDGE is less than the total edge count EDGECNT. Additionally, when all of the determinations in operation 516 are positive, process 500 also proceeds directly to operation 520, which means that no failures have been detected for any of the signal timing parameters tRise, tFall, tFreq being analyzed. Each of the rising-edge failure vector FV-R, the falling-edge failure vector FV-F, and the clock-frequency failure vector FV-CF initially stores a pass value for tRise, tFall, and tFreq corresponding to the current edge index EDGE. Thus, when all of the determinations in operation 516 are positive, process 500 immediately proceeds to operation 520 and the current edge index EDGE is incremented, with all initial values of tRise, tFall, and tFreq corresponding to the current edge index EDGE remaining at the initially set pass values in each of the FV-R, FV-F, FV-CF vectors.

[0036] Process 500 continues to execute operations 508 - 520 until the determination in operation 508 is negative, which indicates that the timing characteristics of all detected edges in the current acquisition have been measured and determined to have passed or failed the corresponding timing criteria. When the determination in operation 508 is negative, process 500 proceeds to operation 522 and through the user interface 118 ( Figure 1 ) displays whether each of the measured operational signal timing parameters tRise, tFall, tFreq has passed or failed the timing standard of the I2C bus as defined by the corresponding nominal signal timing parameters tRisemin, tRisemax, tFallmin, tFallmax, tFreqmin and tFreqmax.

[0037] When at least one rising edge or falling edge or the clock frequency for at least one unit interval UI does not meet the timing criteria as defined by the corresponding nominal signal timing parameters, the measured operating signal timing parameters tRise, tFall, tFreq are determined to have failed the associated timing criteria. At operation 522, when all edges or frequencies or all unit intervals UI of the SDA, SCL signals meet the associated timing criteria, the process 500 displays a "pass" indication of the measured signal timing parameters tRise, tFall, tFreq. Conversely, when a failure is detected, the process 500 displays a "fail" indication of the measured signal timing parameters tRise, tFall, tFreq at operation 522. In addition, when a failure is detected for the measured signal timing parameters tRise, tFall, tFreq, the process 500 utilizes the associated failure vectors FV-R, FV-F, FV-CF at operation 522 to enable the user to browse the failure vectors and check each failure instance of the corresponding signals SDA, SCL. The following will refer to Figure 6-8 The operation of the bus timing characteristics analyzer 104 in performing operation 522 is described in greater detail to present pass and fail indications and allow a user to review and more closely examine the failures. After operation 522, process 500 proceeds to operation 524 and ends.

[0038] Figure 6A sample configuration display 600 presented by the bus timing characteristics analyzer 104 on the user interface 118 to enable a user to configure the bus timing characteristics analyzer 104 in accordance with an embodiment of the present disclosure is illustrated. In the configuration display 600, a "protocol utility" option is added to the existing configuration menu, and the user selects the option to configure the bus timing characteristics analyzer 104 to perform an analysis of the timing characteristics of the electrical signals generated by the DUT. The existing configuration menu presented in the configuration display 600 provides several signal analysis options that the instrument 102 can perform on the acquired waveform. These analysis options are selected by additional tabs at the top of the configuration display 600, and include a WBG-DPT tab for selecting a wide bandgap double pulse test of the DUT, a DPM tab for selecting a digital power management test of the DUT, an IMDA tab for selecting an inverter motor drive analysis test of the DUT, a power tab for selecting a power test of the DUT, and a jitter tab for selecting a jitter analysis of the DUT.

[0039] The user selects the protocol utility via the Standard tab presented in the upper left corner of the configuration display 600. The user selects the Standard tab, and thereafter the user selects the protocol utility option, which is presented in the lower left portion of the configuration display 600 as one of a number of different types of bus measurements that the instrument 102 can perform on the electrical signals of the DUT. Figure 6 , the Standard label is shown with a thicker line and the Protocol label is shown with a dashed line to indicate that both labels have been selected by the user. The user then selects the bus source via the Source field displayed in the middle left portion of the configuration display 600 to define the type of bus being analyzed, such as an I2C bus. The Source field is Figure 6 Shown in the figure is bus 1.

[0040] Once the Source field is selected, the user can configure the parameters for the selected type of bus as the source of the electrical signal being analyzed. Figure 7 , which is displayed by the user interface 118 of the instrument 102. The configuration display 700 includes display fields to allow the user to display or not display the output of the bus timing characteristics analyzer 104 on the user interface 118. The label field allows the user to assign a desired label to the bus being analyzed. The type of bus being analyzed is set in the bus type field and Figure 7 In the example shown in FIG. 1 , an I2C bus is shown. As discussed above, different types of buses can be analyzed, and the user selects the appropriate bus through the bus type field.

[0041] The user then selects the appropriate channel CH on the instrument for the electrical signal corresponding to the selected bus type. As discussed above, the I2C bus includes SDA and SCL signals. Figure 6In the example of FIG. 7 , one of the SDA, SCL signals is coupled to the first channel CH1 of the instrument 104, and the other of the SDA, SCL signals is coupled to the second channel CH2 of the instrument. The Threshold field in the display 700 is used to set the corresponding threshold voltages for the SDA, SCL signals coupled to the first and second channels CH1, CH2 of the instrument 102. The R / W bit field in the display 700 provides the user with the option of including the read / write bit R / W in the decoded address on the I2C bus. The Display Format field allows the user to select the desired format for displaying the SDA, SCL signals, i.e., whether the signals are displayed as a bus (i.e., as Figure 7 When the bus format is selected, each value of each decoded frame is displayed, as in Figure 4 The bottom is shown for an I2C bus. The Display Format field allows the user to select the desired format for the decoded frame values ​​to be displayed, such as Hexadecimal (Hex), Binary, Decimal, and other format options may also be provided.

[0042] Figure 8 A bus timing results configuration display 800 is illustrated that allows a user to configure the desired results of the bus timing characteristics analyzer 104 analysis to be displayed for user review. More specifically, the configuration display 800 includes a navigation source field in the lower left portion of the display that allows the user to select the desired timing characteristics or standards to be displayed for user review. Figure 8 In the example of , the source field is bus 1, where bus 1 corresponds to the I2C bus. Navigating the source field accordingly provides the user with an option to select a desired one of the timing parameters analyzed by the bus timing characteristics analyzer 104.

[0043] As discussed above, in an embodiment, these timing parameters include the frequency of the clock signal SCL, the rise time for the rising edge of the SCL signal, the fall time for the falling edge of the SCL signal, and the rise time and fall time for the rising and falling edges of the data signal SDA. These different timing parameters are Figure 8 The Navigation Source field in the configuration display 800 of FIG. 8 is shown in the drop-down subfield available. For this subfield, the rising edge of the SCL signal is selected to be shown by the thicker line. The Measurement Navigation Type field is also part of the configuration display 800 and allows the user to determine whether to review all events for the selected timing parameter or only events that failed. This selection is made through the All Events subfield and the Failed subfield of the Measurement Navigation Type field. For example, in the Figure 8 In the example, the rising time of the rising edge of the SCL signal is selected, as in Figure 8Selecting the All Events subfield in the example of will allow the user to browse and review the rise time parameters calculated for all rising edges of the SCL signal in the current acquisition being analyzed by the bus timing characteristics analyzer 104 .

[0044] Fig. 9 The bus timing characteristics analyzer 104 is shown displaying bus timing results 900 through the user interface 118 of the instrument 104 to allow a user to review the results of the timing characteristics analysis of the timing parameters being analyzed. Fig. 9 In the example of FIG. 8 , for an I2C bus, the bus timing result configuration display 800 shows the previously discussed measurement or operational timing parameters, namely, the rise and fall time parameters for the rising and falling edges of the SDA and SCL signals, together with the frequency of the SCL signal. These operational signal timing parameters are specified in the configuration display 900 as follows: the rise time for the rising edge of the SCL signal is specified as the clock rise time trCL; the fall time for the falling edge of the SCL signal is specified as the clock fall time tfCL; the rise time for the rising edge of the SDA signal is specified as the data rise time trDA; the fall time for the falling edge of the SDA signal is specified as the data fall time tfDA; and the frequency of the SCL signal is specified as the clock frequency fsCL.

[0045] The bus timing results display 900 also includes a value field for each of the trCL, tfCL, trDA, tfDA, and fsCL timing parameters, which shows the value of the timing parameter. The status field for each timing parameter shows whether the timing parameter has passed or failed the analysis of the bus timing characteristics analyzer 104. The user can then use the navigation buttons 902, 904 to browse through the selected signal timing parameters to review an instance of a desired one of the parameters. The user navigates through the navigation buttons 904 to view the value of the desired one of the parameters. Fig. 9 The thicker line through the button in is shown as selected. In some embodiments, in the absence of a violation for a given signal timing parameter, navigation is disabled for that parameter. For example, in Fig. 9 In the example of , no navigation through the instances of the trDA, tfCL, and fsCL parameters is provided because these parameters passed the analysis as indicated by the corresponding status fields. Each of the trCL and trDA parameters can then be browsed using buttons 902, 904 because these parameters did not pass the analysis as indicated by the corresponding status fields. The minimum and maximum buttons Min', Max' in the bus timing results display 900 enable the user to identify the minimum and maximum values ​​of the selected timing parameters.

[0046] In an embodiment, the bus timing characteristics analyzer 104 performs additional analysis on each signal timing parameter being analyzed. For example, in an embodiment, the bus timing characteristics analyzer 104 calculates the mean, minimum, maximum, and standard deviation for each of the signal timing parameters tfCL, trCL, tfCL, trDA, and tfDA. In addition, in an embodiment, navigating through the selected signal timing parameters using buttons 902, 904 can also be illustrated by the user interface 118 in the time domain representation of the corresponding signals SDA, SCL, so that the user can see an example of the signal timing parameters being analyzed in the time domain representation of the corresponding SDA, SCL signals. Fig.10 Another example bus timing results display 1000 is illustrated, which includes a Fig. 9 900, along with the SDA, SCL signals and a time domain representation of the decoded frame shown in the left portion of the frame. In this embodiment, specific instances of failure of the timing parameters shown in the bus timing results display 900 are also identified or marked by a dashed box 1000 in the time domain representation of the SDA, SCL signals.

[0047] In some embodiments, the nominal signal timing parameters for the I2C bus include parameters for the standard operating mode and the fast operating mode. For the standard mode, the nominal signal timing parameters may include a rise time parameter tRise of 1000 nanoseconds (ns) for the rising edge of the SDA and SCL signals, a fall time parameter tFall of 300ns for the falling edge of the SDA and SCL signals, a clock frequency tFreq of less than or equal to 100KHz, and a minimum low clock period tLOW of 4.7 microseconds (μs) and a minimum high clock period tHIGH of 4.0μs. For the fast mode, the nominal signal timing parameters may include a rise time parameter tRise of 20ns to 300ns for the rising edge of the SDA and SCL signals, a fall time parameter tFall of 20ns to 300ns for the falling edge of the SDA and SCL signals, a clock frequency tFreq of less than or equal to 400KHz, and a minimum low clock period tLOW of 1.3μs and a minimum high clock period tHIGH of 0.6μs.

[0048] Aspects of the present disclosure may be operated on specially created hardware, on firmware, digital signal processors, or on a specially programmed general-purpose computer including a processor operating according to programming instructions. The term controller or processor as used herein is intended to include microprocessors, microcomputers, application-specific integrated circuits (ASICs), and dedicated hardware controllers. One or more aspects of the present disclosure may be embodied in computer-usable data and computer-executable instructions, such as in one or more program modules, which are executed by one or more computers (including monitoring modules) or other devices. Typically, program modules include routines, programs, objects, components, data structures, etc., which perform specific tasks or implement specific abstract data types when executed by a processor in a computer or other device. Computer executable instructions may be stored on non-temporary computer-readable media such as hard disks, optical disks, removable storage media, solid-state memory, random access memory (RAM), etc. As will be appreciated by those skilled in the art, the functionality of program modules may be combined or distributed in various aspects as desired. In addition, the functionality may be embodied in firmware or hardware equivalents such as integrated circuits, FPGAs, etc., in whole or in part. Certain data structures may be used to more efficiently implement one or more aspects of the present disclosure, and such data structures are contemplated to be within the scope of the computer-executable instructions and computer-usable data described herein.

[0049] In some cases, the disclosed aspects can be implemented with hardware, firmware, software or any combination thereof. The disclosed aspects can also be implemented as instructions carried or stored thereon by one or more or non-transitory computer-readable media, which can be read and executed by one or more processors. Such instructions can be referred to as computer program products. Computer-readable media as discussed herein means any medium that can be accessed by a computing device. As an example and not limitation, computer-readable media can include computer storage media and communication media.

[0050] Computer storage media means any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital video disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, and any other volatile or non-volatile, removable or non-removable media implemented in any technology. Computer storage media excludes the signals themselves and transient forms of signal transmission.

[0051] Communication media refers to any medium that can be used for the transmission of computer-readable information. By way of example and not limitation, communication media may include coaxial cables, fiber optic cables, air, or any other medium suitable for the transmission of electrical, optical, radio frequency (RF), infrared, acoustic or other types of signals. Example

[0052] Illustrative examples of the technology disclosed herein are provided below. Configurations of the technology may include any one or more of the following examples and any combination thereof.

[0053] Example 1 is a test and measurement instrument, comprising: one or more processors configured to control the acquisition of multiple electrical signals transmitted by a device under test on an electrical bus according to a bus protocol; and a bus timing characteristics analyzer, configured to: identify nominal signal timing parameters of the acquired multiple electrical signals, the nominal signal timing parameters being defined by the bus protocol and defining timing standards for the multiple electrical signals; measure operating signal timing parameters of each of the acquired multiple electrical signals; for each of the acquired multiple electrical signals, compare the operating signal timing parameters with the nominal signal timing parameters to determine whether the operating signal timing parameters meet the timing standards; and display a visual indication of each of the multiple electrical signals on the test and measurement instrument, indicating whether the operating signal timing parameters of the electrical signal meet the timing standards.

[0054] Example 2 is the test and measurement instrument of Example 1, wherein the bus timing characteristics analyzer is further configured to detect edges in each of the multiple electrical signals acquired in order to measure the operating signal timing parameters of each of the multiple electrical signals acquired; determine whether each edge is a rising edge or a falling edge; and use the rising edge and falling edge of the electrical signal to measure the operating signal timing parameters of each of the multiple electrical signals acquired.

[0055] Example 3 is the test and measurement instrument of Example 1 or Example 2, wherein the multiple electrical signals acquired include at least one data signal, and wherein the operating signal timing parameters for the at least one data signal include a rise time measured for each rising edge of the at least one data signal and a fall time measured for each falling edge of the at least one data signal.

[0056] Example 4 is a test and measurement instrument of any one of Examples 1-3, wherein the nominal signal timing parameters include a nominal rise time signal timing parameter and a nominal fall time signal timing parameter, and wherein the bus timing characteristics analyzer is further configured to compare, for the at least one data signal, the measured rise time of each rising edge with the nominal rise time signal timing parameter; and to compare, for the at least one data signal, the measured fall time of each falling edge with the nominal fall time signal timing parameter.

[0057] Example 5 is a test and measurement instrument of any one of Examples 1-4, wherein the nominal rise time signal timing parameter includes a range around the nominal value, the range being defined by the minimum and maximum permissible values ​​of the nominal rise time signal timing parameter, and wherein the nominal fall time signal timing parameter includes a range around the nominal value, the range being defined by the minimum and maximum permissible values ​​of the nominal fall time signal timing parameter, and wherein the bus timing characteristics analyzer is further configured to determine whether a measured rise time of each rising edge of the at least one data signal has a value within the range of the nominal rise time signal timing parameter; and determine whether a measured fall time of each falling edge of the at least one data signal has a value within the range of the nominal fall time signal timing parameter.

[0058] Example 6 is the test and measurement instrument of any of Examples 1-5, wherein the nominal signal timing parameters further include a setup time tSU and a hold time tHD for the at least one data signal.

[0059] Example 7 is a test and measurement instrument of any one of Examples 1-6, wherein the multiple electrical signals acquired further include a clock signal, and wherein the nominal signal timing parameters for the clock signal include a nominal clock frequency, a nominal rise time signal timing parameter, and a nominal fall time signal timing parameter.

[0060] Example 8 is a test and measurement instrument of any one of Examples 1-7, wherein a visual indication of each of the plurality of electrical signals indicates a pass condition when all operating signal timing parameters meet the timing criteria of the electrical signals, and indicates a fail condition when one or more of the operating signal timing parameters do not meet the timing criteria.

[0061] Example 9 is a test and measurement instrument of any of Examples 1-8, wherein the electrical bus is one of an Inter-Integrated Circuit (I2C) bus, an I3C or SenseWire bus, an RS-232 bus, a Universal Serial Bus (USB) bus, an embedded USB (eUSB) bus, a Serial Peripheral Interface (SPI) bus, an embedded SPI (eSPI), and a SENT bus.

[0062] Example 10 is the test and measurement instrument of any of Examples 1-9, wherein the test and measurement instrument may include an oscilloscope.

[0063] Example 11 is a test and measurement system comprising: a plurality of electronic devices, an electrical bus interconnecting the electronic devices, one of the electronic devices being a device under test (DUT), and the electrical bus transmitting electrical signals by having nominal signal timing parameters defined by a bus protocol of the electrical bus, the nominal signal timing parameters defining timing standards for the electrical signals; and a test and measurement instrument comprising one or more processors configured to control the acquisition of electrical signals; and a bus timing characteristics analyzer configured to: identify nominal signal timing parameters of the acquired electrical signals, the nominal signal timing parameters being defined by the bus protocol and defining timing standards for the electrical signals; measure operational signal timing parameters of each of the acquired electrical signals; for each of the acquired electrical signals, compare the operational signal timing parameters with the nominal signal timing parameters to determine whether the operational signal timing parameters meet the timing standards; and display a visual indication of each of the electrical signals on the test and measurement instrument, indicating whether the operational signal timing parameters of the electrical signal meet the timing standards.

[0064] Example 12 is the test and measurement system of Example 11, wherein the electrical bus is one of an Inter-Integrated Circuit (I2C) bus, an I3C or SenseWire bus, an RS-232 bus, a Universal Serial Bus (USB) bus, an embedded USB (eUSB) bus, a Serial Peripheral Interface (SPI) bus, an embedded SPI (eSPI), and a SENT bus.

[0065] Example 13 is the test and measurement system of Example 11 or Example 12, wherein the test and measurement instrument further may include a memory, and wherein the nominal signal timing parameters are stored in the memory.

[0066] Example 14 is the test and measurement system of any of Examples 11-13, wherein the test and measurement instrument may include an oscilloscope.

[0067] Example 15 is a test and measurement system of any one of Examples 11-14, wherein the acquired electrical signals include a clock signal and a data signal, wherein the nominal signal timing parameters include rise time and fall time signal timing parameters for the rising and falling edges of the clock and data signals, and further include frequency signal timing parameters for the clock signal.

[0068] Example 16 is the test and measurement system of any of Examples 11-15, wherein the test and measurement instrument may further include a protocol decoder configured to convert a bit sequence in the electrical signal acquisition into a frame according to a bus protocol of the electrical bus.

[0069] Example 17 is a method for measuring operating signal timing parameters of an electrical signal transmitted on an electrical bus, the method comprising retrieving, by a test and measurement instrument, nominal signal timing parameters for the electrical signal, the nominal signal timing parameters being defined by a bus protocol of the electrical bus and defining a timing standard for the electrical signal; acquiring the electrical signal in the test and measurement instrument; detecting edges in the acquired electrical signal in the test and measurement instrument; measuring, in the test and measurement instrument, operating signal timing parameters associated with the detected edges of the acquired electrical signal; comparing, in the test and measurement instrument, the operating signal timing parameters with the nominal signal timing parameters to determine whether the operating signal timing parameters meet the timing standard; storing the results of the comparison in the test and measurement instrument; and displaying a pass or fail indication of each of the electrical signals on the test and measurement instrument based on the stored comparison results.

[0070] Example 18 is the method of Example 17, wherein the electrical bus is an I2C bus, and the electrical signal includes a clock signal and a data signal.

[0071] Example 19 is the method of Example 17 or Example 18, wherein the nominal signal timing parameters include a rise time tRise for each rising edge of the clock and data signals, a fall time tFall for each falling edge of the clock and data signals, a clock frequency tFreq of the clock signal, a start condition hold time tHD; STA, a minimum low clock period tLOW, a minimum high clock period tHIGH, a data hold time tHD; DAT, a start condition establishment time tSU; DAT, a start condition establishment time tSU; STA, a start condition hold time tHD; STA, a stop condition establishment time tSU; STO and a bus idle time tBUF.

[0072] Example 20 is the method of any of Examples 17-19, wherein the nominal signal timing parameters include a maximum value and a minimum value for each nominal signal timing parameter.

[0073] The previously described versions of the disclosed subject matter have many advantages that have been described or will be apparent to those of ordinary skill. Nevertheless, these advantages or features are not required in all versions of the disclosed apparatus, system or method.

[0074] Additionally, this written description refers to specific features. It will be understood that the disclosure in this specification includes all possible combinations of those specific features. Where a specific feature is disclosed in the context of a particular aspect or example, the feature may also be used in the context of other aspects and examples to the extent possible.

[0075] Furthermore, when reference is made in this application to a method having two or more defined steps or operations, the defined steps or operations may be performed in any order or simultaneously, unless the context excludes those possibilities.

[0076] Although specific examples of the present invention have been shown and described for purposes of illustration, it will be appreciated that various modifications may be made without departing from the spirit and scope of the present invention. Accordingly, the present invention should not be limited except by the appended claims.

Claims

1. A test and measurement instrument comprising: one or more processors configured to control acquisition of a plurality of electrical signals transmitted by the device under test on the electrical bus in accordance with the bus protocol; and Bus Timing Characteristic Analyzer, configured as: identifying nominal signal timing parameters of the acquired plurality of electrical signals, the nominal signal timing parameters being defined by a bus protocol and defining a timing standard for the plurality of electrical signals; measuring an operational signal timing parameter of each of the acquired plurality of electrical signals; For each of the acquired plurality of electrical signals, comparing the operating signal timing parameter with the nominal signal timing parameter to determine whether the operating signal timing parameter meets the timing criteria; and A visual indication of each of the plurality of electrical signals is displayed on the test and measurement instrument indicating whether an operational signal timing parameter of the electrical signal meets a timing criterion.

2. The test and measurement instrument of claim 1, wherein: The bus timing characteristics analyzer is further configured to measure the operation signal timing parameters of each of the acquired plurality of electrical signals: detecting an edge in each of the acquired plurality of electrical signals; Determine whether each edge is a rising or falling edge; and An operational signal timing parameter of each of the acquired plurality of electrical signals is measured using rising and falling edges of the electrical signals.

3. The test and measurement instrument of claim 2, wherein: The acquired multiple electrical signals include at least one data signal, and wherein the operational signal timing parameters for the at least one data signal include a rise time measured for each rising edge of the at least one data signal and a fall time measured for each falling edge of the at least one data signal.

4. The test and measurement instrument of claim 3, wherein: The nominal signal timing parameters include a nominal rise time signal timing parameter and a nominal fall time signal timing parameter, and wherein the bus timing characteristics analyzer is further configured to: for the at least one data signal, comparing a measured rise time of each rising edge to a nominal rise time signal timing parameter; and For the at least one data signal, a measured fall time of each falling edge is compared to a nominal fall time signal timing parameter.

5. The test and measurement instrument of claim 4, wherein: The nominal rise time signal timing parameter includes a range around the nominal value, the range being defined by minimum and maximum permissible values ​​of the nominal rise time signal timing parameter, and wherein the nominal fall time signal timing parameter includes a range around the nominal value, the range being defined by minimum and maximum permissible values ​​of the nominal fall time signal timing parameter, and wherein the bus timing characteristics analyzer is further configured to: determining whether a measured rise time of each rising edge of the at least one data signal has a value within a nominal rise time signal timing parameter range; and A determination is made as to whether a measured fall time of each falling edge of the at least one data signal has a value within a nominal fall time signal timing parameter range.

6. The test and measurement instrument of claim 5, wherein: The nominal signal timing parameters further include a setup time tSU and a hold time tHD for the at least one data signal.

7. The test and measurement instrument of claim 1, wherein: The acquired plurality of electrical signals further comprises a clock signal, and wherein the nominal signal timing parameters for the clock signal comprise a nominal clock frequency, a nominal rise time signal timing parameter, and a nominal fall time signal timing parameter.

8. The test and measurement instrument of claim 1, wherein: The visual indication of each of the plurality of electrical signals indicates a pass condition when all of the operational signal timing parameters meet the timing criteria for the electrical signals and indicates a fail condition when one or more of the operational signal timing parameters do not meet the timing criteria.

9. The test and measurement instrument of claim 1, wherein: The electrical bus is one of an Inter-Integrated Circuit (I2C) bus, an I3C or "SenseWire" bus, an RS-232 bus, a Universal Serial Bus (USB) bus, an embedded USB (eUSB) bus, a Serial Peripheral Interface (SPI) bus, an embedded SPI (eSPI), and a SENT bus.

10. The test and measurement instrument of claim 1, wherein: The test and measurement instrument includes an oscilloscope.

11. A test and measurement system comprising: Multiple electronic devices; an electrical bus interconnecting the electronic devices, one of the electronic devices being a device under test (DUT), and the electrical bus communicating electrical signals with nominal signal timing parameters defined by a bus protocol of the electrical bus, the nominal signal timing parameters defining a timing standard for the electrical signals; and Test and measurement instruments, including: one or more processors configured to control acquisition of the electrical signal; and Bus Timing Characteristic Analyzer, configured as: identifying nominal signal timing parameters of the acquired electrical signal, the nominal signal timing parameters being defined by the bus protocol and defining a timing standard for the electrical signal; measuring an operational signal timing parameter of each of the acquired electrical signals; For each of the acquired electrical signals, comparing the operational signal timing parameters to the nominal signal timing parameters to determine whether the operational signal timing parameters meet the timing criteria; and A visual indication of each of the electrical signals is displayed on the test and measurement instrument indicating whether an operational signal timing parameter of the electrical signal meets timing criteria.

12. The test and measurement system of claim 11, wherein: The electrical bus is one of an Inter-Integrated Circuit (I2C) bus, an I3C or "SenseWire" bus, an RS-232 bus, a Universal Serial Bus (USB) bus, an embedded USB (eUSB) bus, a Serial Peripheral Interface (SPI) bus, an embedded SPI (eSPI), and a SENT bus.

13. The test and measurement system of claim 11, wherein: The test and measurement instrument further comprises a memory, and wherein the nominal signal timing parameters are stored in the memory.

14. The test and measurement system of claim 11, wherein: The test and measurement instrument includes an oscilloscope.

15. The test and measurement system of claim 11, wherein: The acquired electrical signals include a clock signal and a data signal, wherein the nominal signal timing parameters include rise time and fall time signal timing parameters for rising and falling edges of the clock and data signals, and further include frequency signal timing parameters for the clock signal.

16. The test and measurement system of claim 11, wherein: The test and measurement instrument further includes a protocol decoder configured to convert a bit sequence in the electrical signal acquisition into a frame according to a bus protocol of the electrical bus.

17. A method for measuring an operational signal timing parameter of an electrical signal transmitted on an electrical bus, the method comprising: retrieving, by the test and measurement instrument, nominal signal timing parameters for the electrical signal, the nominal signal timing parameters being defined by a bus protocol of the electrical bus and defining a timing standard for the electrical signal; Acquiring electrical signals in test and measurement instruments; Detecting edges in acquired electrical signals in test and measurement instruments; measuring, in a test and measurement instrument, operating signal timing parameters associated with detected edges of the acquired electrical signal; In a test and measurement instrument, comparing an operating signal timing parameter with a nominal signal timing parameter to determine whether the operating signal timing parameter meets a timing standard; storing the results of the comparison in the test and measurement instrument; and Based on the stored comparison results, a pass or fail indication for each of the electrical signals is displayed on the test and measurement instrument.

18. The method according to claim 17, wherein: The electrical bus is an I2C bus, and the electrical signal includes a clock signal and a data signal.

19. The method according to claim 18, wherein: The nominal signal timing parameters include the rise time tRise for each rising edge clock and data signal, the fall time tFall for each falling edge of the clock and data signal, the clock frequency tFreq of the clock signal, the hold start condition time tHD; STA, the minimum low clock period tLOW, the minimum high clock period tHIGH, and the data hold time tHD; DAT, establish start condition time tSU; DAT, establish start condition time tSU; STA, maintain start condition time tHD; STA, establish stop condition time tSU; STO and bus idle time tBUF.

20. The method according to claim 17, wherein: The nominal signal timing parameters include a maximum value and a minimum value for each nominal signal timing parameter.

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