Communication interface circuit supporting communication link change and method of operation thereof

Abstract

A communication interface circuit supporting a communication link change and a method of operating the same, the communication interface circuit including: a protocol layer circuit generating packet data based on input data; and a physical layer circuit that encodes the packet data to output a transmission state, and drives a data channel including a plurality of three-phase line links based on the transmission state, where the physical layer circuit may include an encoder that encodes the packet data to output the transmission state. The encoder calculates a transmission state based on a preorder state output from the encoder within a previous unit interval, a symbol mapped to the packet data, and a control code, and wherein the control code indicates a coding change based on a coupling relationship of the plurality of three-phase line links. A communication interface circuit stably transmits data.

Description

Technical Field

[0001] Example embodiments described herein relate to communication interface circuits and methods of operating the same. Background Art

[0002] Components inside the electronic device exchange data with each other through a communication link. The components are connected to the communication link through a communication interface circuit. The transmission data is converted into a format suitable for transmission by the communication interface and sent through the communication link.

[0003] There are communication standards for data exchanged between components. For example, an image sensing device may exchange data with other components by using a camera serial interface (CSI) and C-PHY defined by the Mobile Industry Processor Interface (MIPI) Alliance. Summary of the invention

[0004] Example embodiments provide a communication interface circuit supporting stable data transmission.

[0005] According to an example embodiment, a communication interface circuit includes: a protocol layer circuit, which generates packet data based on input data; and a physical layer circuit, which encodes the packet data to output a transmission state, and drives a data channel including multiple three-phase line links based on the transmission state, wherein the physical layer circuit includes an encoder, which calculates the transmission state based on a preamble state output from the encoder in a previous unit interval, a symbol mapped to the packet data, and a control code, and wherein the control code indicates a coding change based on a coupling relationship of the multiple three-phase line links.

[0006] According to an example embodiment, a communication interface circuit includes: a physical layer circuit, which generates multiple differential signals based on a driving voltage of each of multiple three-phase line links of a data channel, and outputs symbols based on the multiple differential signals; and a protocol layer circuit, which demaps the symbols and outputs data, wherein the physical layer circuit includes a decoder, which is configured to calculate the symbols based on a received differential signal based on the multiple differential signals, a preamble differential signal based on the multiple differential signals in a previous unit interval, and a control code, and wherein the control code indicates a decoding change based on a coupling relationship of the multiple three-phase line links.

[0007] According to an example embodiment, a method of operating a communication interface circuit includes: generating packet data based on input data; encoding the packet data to output a transmission state; and driving a data channel based on the transmission state, the data channel including a plurality of three-phase line links, wherein encoding the packet data includes calculating the transmission state based on a preamble state output in a previous unit interval, a symbol mapped to the packet data, and a control code, and the control code indicates a coding change based on a coupling relationship of the plurality of three-phase line links.

[0008] The communication interface circuit according to the exemplary embodiment of the present disclosure may stably transmit data. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects and features will become apparent by describing example embodiments in detail with reference to the accompanying drawings.

[0010] Figure 1 is a block diagram illustrating a communication interface circuit according to an example embodiment;

[0011] Figure 2 is a block diagram illustrating a transmission-side communication interface circuit according to an example embodiment;

[0012] Figure 3 is a block diagram illustrating a communication interface circuit based on an analog multiplexer to support communication link changes;

[0013] Figure 4 is a circuit diagram of a communication interface circuit according to an example embodiment;

[0014] Figure 5 and Figure 6 is a diagram illustrating a state diagram for encoding a communication interface circuit according to an example embodiment;

[0015] Figures 7 to 11 is a diagram illustrating an example of a communication link change of a communication interface circuit according to an example embodiment;

[0016] Fig.12 is a block diagram illustrating a receiving-side communication interface circuit according to an example embodiment;

[0017] Fig.13 is a block diagram illustrating a communication interface circuit according to an example embodiment;

[0018] Fig.14 is a circuit diagram illustrating a communication interface circuit according to an example embodiment;

[0019] Fig.15 is a block diagram illustrating a decoder according to an example embodiment;

[0020] Fig.16 is a diagram illustrating a symbol interpreter of a decoder according to an example embodiment; and

[0021] Fig.17 is a flow chart illustrating a method of operating a transmission-side communication interface circuit according to an example embodiment. DETAILED DESCRIPTION

[0022] Hereinafter, example embodiments will be described clearly and in detail so that those skilled in the art can easily practice the example embodiments.

[0023] Figure 1 is a block diagram illustrating a transmitting side communication interface circuit according to an example embodiment. For convenience, the transmitting side communication interface circuit will be referred to as a transmitting interface circuit, and the receiving side communication interface circuit will be referred to as a receiving interface circuit. The communication interface circuit can operate as one or both of the transmitting interface circuit or the receiving interface circuit.

[0024] refer to Figure 1 , the transmitting interface circuit 100 includes a protocol layer circuit 110 and a physical layer circuit 120 .

[0025] The transmission interface circuit 100 may be a communication circuit for transmitting data between electronic devices as internal components of a mobile device, a vehicle, etc. The internal component may be an image sensing device or a display device. For example, the transmission interface circuit 100 may be used to couple mobile computing devices such as smart phones, tablet computers, laptop computers, etc., household electrical appliances such as refrigerators, camcorders, etc., wearable computing devices, and components in vehicles and similar devices. For example, the transmission interface circuit 100 may be arranged to connect an application processor and an image sensing device of a mobile device.

[0026] The transmission interface circuit 100 may be implemented as part of an integrated circuit included in a component. For example, the transmission interface circuit 100 may be implemented as a circuit block of an image sensor of an image sensing device. Alternatively, the transmission interface circuit 100 may be implemented as a circuit block of a display driver IC (DDI) of a display device.

[0027] Alternatively, the transmit interface circuit 100 may be implemented as a separate communication chip connected to the components. For example, the transmit interface circuit 100 may be implemented as a communication semiconductor chip such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA) to support data exchange between components.

[0028] The protocol layer circuit 110 may receive data and generate transmission data Tx_Data in the form of packet data.

[0029] The protocol layer circuit 110 may generate a payload based on the input data, and insert a header and a footer suitable for transmission before and after the payload, respectively, to generate transmission data Tx_Data in the form of packet data.

[0030] According to example embodiments, the protocol layer circuit 110 may generate the transmission data Tx_Data according to a camera serial interface (CSI)-2, a display serial interface (DSI), and DSI-2 defined by a mobile industry processor interface (MIPI) alliance.

[0031] The transmission data Tx_Data may be provided to the physical layer circuit 120, and the physical layer circuit 120 may encode the transmission data Tx_Data to generate a driving signal. Each communication link is driven at a different signal level based on the driving signal. The data signal may be transmitted by changing the signal level of the communication link.

[0032] The physical layer circuit 120 may send a data signal to the receiving interface circuit 200 of the receiving side through the data channel LANE. The physical layer circuit 120 may send a data signal through at least one data channel LANE. For example, the physical layer circuit 120 may send a data signal through multiple data channels.

[0033] The physical layer circuit 120 can send data signals through data channels LANE provided on multiple communication links. For example, multiple data channels can be provided on multiple three-phase communication links. The communication link can be referred to as a line link. Each line link, also referred to as a three-phase line link in this article, can send a signal at one of three different levels within a unit interval. For example, each line link can send one of a high level signal HIGH, a medium level signal MID, and a low level signal LOW within a unit interval.

[0034] The physical layer circuit 120 may drive multiple line links according to C-PHY defined by the MIPI Alliance. For example, the physical layer circuit 120 may include multiple line drivers configured to couple components to three three-phase line links. The physical layer circuit 120 encodes the transmission data Tx_Data to generate a drive signal. The drive signal may define the signal level of each line link.

[0035] In one unit interval, the signal level state of each of the plurality of wire links providing one data channel LANE is defined as a wire state. Therefore, one wire state can be transmitted to the receiving interface circuit 200 through one data channel LANE per unit interval.

[0036] In this specification, a line state transmitted in a current unit interval on the same data lane LANE may be referred to as a transmission state. A line state transmitted in a previous unit interval continuous with a unit interval in which the transmission state is transmitted may be referred to as a preceding state. Therefore, the preceding state is transmitted through the data lane LANE, and the transmission state is transmitted through the data lane LANE in the next consecutive unit interval.

[0037] The physical layer circuit 120 encodes the transmission data Tx_Data to prevent the same line state from being continuously transmitted in continuous unit intervals. The physical layer circuit 120 generates a driving signal so that the signal levels of the constituent line states of the three line links are different from each other. For example, within a specific unit interval, the signal levels of the three line links that transmit the line state defined as +x may be a high level signal HIGH, a low level signal LOW, and a medium level signal MID in sequence. Therefore, the physical layer circuit 120 may calculate the transmission state with reference to the preceding state. As a result, the physical layer circuit 120 does not continuously output the same line state. That is, the preceding state and the transmission state transmitted through the same data channel LANE are different from each other.

[0038] The physical layer circuit 120 according to an example embodiment includes an encoder 125. The encoder 125 calculates a transmission state based on a preamble state, a symbol, and a control code.

[0039] The encoder of the physical layer circuit of the conventional communication interface circuit calculates the transmission state based only on the preamble state and the symbol. In contrast, the encoder 125 of the physical layer circuit 120 according to the exemplary embodiment also calculates the transmission state based on the control code CONTROL_CODE.

[0040] The control code CONTROL_CODE is a code indicating a coding change based on a coupling relationship of a plurality of three-phase line links.

[0041] refer to Figure 1 , the multiple transmission pins TXPIN_A, TXPIN_B and TXPIN_C of the transmission interface circuit 100 are electrically coupled to the multiple reception pins RXPIN_A, RXPIN_B and RXPIN_C of the reception interface circuit 200 respectively. For example, Figure 1The diagram shows a transmission pin ATXPIN_A coupled to a reception pin ARXPIN_A, a transmission pin B TXPIN_B coupled to a reception pin BRXPIN_B, and a transmission pin C TXPIN_C coupled to a reception pin C RXPIN_C. In this case, based on the reception pins, the line link between the transmission pin ATXPIN_A and the reception pin ARXPIN_A may be referred to as a line link A, the line link between the transmission pin B TXPIN_B and the reception pin B RXPIN_B may be referred to as a line link B, and the line link between the transmission pin C TXPIN_C and the reception pin C RXPIN_C may be referred to as a line link C.

[0042] Depending on the coupling settings between components, the coupling relationship between the transmission pins TXPIN_A, TXPIN_B, and TXPIN_C and the reception pins RXPIN_A, RXPIN_B, and RXPIN_C may vary. Figure 1 It is exemplarily illustrated that the transmission pins TXPIN_A, TXPIN_B, and TXPIN_C are sequentially coupled to the reception pins RXPIN_A, RXPIN_B, and RXPIN_C, respectively, but the coupling relationship may be changed. For example, the transmission pin ATXPIN_A may be coupled to the reception pin C RXPIN_C, the transmission pin B TXPIN_B may be coupled to the reception pin B RXPIN_B, and the transmission pin C TXPIN_C may be coupled to the reception pin A RXPIN_A. In this case, it can be seen that the line link A and the line link C are exchanged with each other based on the transmission interface circuit 100, and in this specification, it may be referred to as A / C line exchange.

[0043] The transmission interface circuit 100 provides a driving signal to each line link of the data channel LANE based on the coupling relationship of the exchanged line links. For example, in order to send a line state defined as +x, the transmission interface circuit 100 drives the line link A coupled to the transmission pin A, the line link B coupled to the transmission pin B, and the line link C coupled to the transmission pin C with a high level signal HIGH, a low level signal LOW, and a middle level signal MID, respectively. When the line link A and the line link C are interchanged, in order to send a line state defined as +x, the transmission interface circuit 100 can drive the line link C coupled to the transmission pin A, the line link B coupled to the transmission pin B, and the line link A coupled to the transmission pin C with a middle level signal MID, a low level signal LOW, and a high level signal HIGH, respectively.

[0044] The encoder 125 of the physical layer circuit 120 according to the example embodiment may perform encoding differently according to the exchange between two of the three 3-phase line links according to C-PHY of MIPI. For example, based on the received control code, the encoder 125 may encode the same symbol into mutually different line states when line link A and line link C are exchanged, when line link A and line link B are exchanged, and when line link B and line link C are exchanged.

[0045] In addition, the encoder 125 of the physical layer circuit 120 according to the example embodiment can perform encoding differently according to the change of three of the three three-phase line links according to the C-PHY of MIPI. For example, based on the control code provided, the encoder 125 can appropriately perform encoding for the coupling relationship that changes from line link A, line link B, and line link C to line link B, line link C, and line link A in order. Or, based on the control code provided, the encoder 125 can appropriately perform encoding for the coupling relationship that changes from line link A, line link B, and line link C to line link C, line link A, and line link B in order.

[0046] In the operation of establishing the coupling of components, there are cases where degradation of signal characteristics according to the communication link and degradation of signal characteristics according to the coupling pad characteristics can be solved by changing the communication link. In addition, the communication link may need to be changed due to the arrangement of coupling terminals between components.

[0047] Therefore, the physical layer circuit 120 according to the example embodiment can appropriately perform encoding for the changed coupling relationship of the communication link based on the control code indicating the change of the coupling relationship of the communication link. As a result, the degradation of the communication channel can be reduced, and the data signal can be stably transmitted. In addition, the physical layer circuit 120 can stably transmit the data signal by supporting various interconnections between components due to the arrangement of the coupling terminals.

[0048] Figure 2 is a block diagram illustrating the physical layer circuit 120 in detail according to an example embodiment.

[0049] refer to Figure 2 The physical layer circuit 120 may include a mapping circuit 121 , a parallel-to-serial converter 123 , an encoder 125 , a pre-driver control circuit 127 , and a driver 129 .

[0050] Figure 2 The illustration shows that the transmit pins TXPIN_A, TXPIN_B, and TXPIN_C are sequentially coupled to the line link A, the line link B, and the line link C, but the coupling relationship may be changed. For example, Figure 2The physical layer circuit according to example embodiments in may support A / C line switching in which transmit pin A TXPIN_A is coupled to line link C and transmit pin C TXPIN_C is coupled to line link A. Other types of line switching of multiple line links may also be supported.

[0051] The mapping circuit 121 maps the provided transmission data Tx_Data into symbols. The mapping circuit 121 can receive 16 binary bit data and map it to 7 symbols. The mapping circuit 121 can map the 16-bit data to 7 symbols according to the mapping standard defined by C-PHY of MIPI. The seven symbols can be provided to the encoder 125 one by one through the parallel-to-serial converter 123.

[0052] The parallel-to-serial converter 123 can provide 3 binary bits corresponding to each of the seven symbols to the encoder 125. Each symbol can have one of five forms and is expressed with 3 binary bits. The 3 binary bits of each symbol can indicate the type of transition from the preamble state to the transmit state based on the previous symbol. For example, the 3 binary bits may include a flip bit Tx_Flip, a rotation bit Tx_Rotation, and a polarity change bit Tx_Polarity. Each of the flip bit Tx_Flip, the rotation bit Tx_Rotation, and the polarity change bit Tx_Polarity indicates the type of transition between states. This will be referred to below. Figure 5 and Figure 6 This is described in detail.

[0053] The encoder 125 according to an example embodiment encodes a symbol consisting of 3 bits provided based on the preamble state and the control code CONTROL_CODE and outputs a transmission state Pres_St. The transmission state Pres_St may be a line state defining a signal level of three 3-phase line links according to C-PHY of MIPI.

[0054] The control code CONTROL_CODE may be stored in a register 320 outside the physical layer circuit 120. The register 320 may store a register value for component environment setting. When the component is started, the control circuit block OUIF 310 may read the control code CONTROL_CODE from the register 320 and provide it to the encoder 125. The control code CONTROL_CODE may be stored as different values ​​in the register 320 according to different coupling relationships of the plurality of line links.

[0055] The encoder 125 can encode the symbol appropriately for the coupling relationship of multiple line links based on the provided control code CONTROL_CODE. For example, in order to send the line states of +x, -x, +y, -y, +z and -z according to MIPI's C-PHY, the encoder can output the transmission state Pres_St differently according to the coupling relationship of multiple line links. For example, when the provided control code indicates A / C line switching, the encoder 125 can output the transmission states Pres_St of -y, +y, -x, +x, -z and +z to send the line states of +x, -x, +y, -y, +z and -z to the receiver according to MIPI's C-PHY. Similarly, when the provided control code indicates A / B line switching, the encoder 125 can output the transmission states Pres_St of -x, +x, -z, +z, -y and +y to send the line states of +x, -x, +y, -y, +z and -z to the receiver according to MIPI's C-PHY. In addition, when the provided control code indicates B / C line switching, the encoder 125 can output the transmission status Pres_St of -z, +z, -y, +y, -x and +x to send the line status of +x, -x, +y, -y, +z and -z to the receiver according to MIPI's C-PHY.

[0056] The pre-driver control circuit 127 provides driving signals DrivingSignal_A, DrivingSignal_B, and DrivingSignal_C to a plurality of driving drivers 129 driving a plurality of line links, respectively, based on the received transmission state Pres_St. Each driving driver 129 drives the coupled line link with one of a high level signal HIGH, a middle level signal MID, and a low level signal LOW based on each driving signal DrivingSignal_A, DrivingSignal_B, and DrivingSignal_C.

[0057] The driving signals DrivingSignal_A, DrivingSignal_B, and DrivingSignal_C of the pre-driver control circuit 127 according to example embodiments are directly provided to the plurality of driving drivers 129 , respectively.

[0058] That is, regardless of the change in the coupling relationship of the plurality of line links, each of the plurality of driving drivers 129 can drive the coupled line link based on each of the driving signals DrivingSignal_A, DrivingSignal_B, and DrivingSignal_C directly provided from the pre-driver control circuit 127. This is due to the fact that the transmission state Pres_St is calculated based on the control code CONTROL_CODE in the encoder 125 according to the example embodiment to be suitable for the changed coupling relationship of the plurality of line links.

[0059] refer to Figure 3 , unlike the encoder 125 according to the example embodiment of the present disclosure, the encoder ENC may output the transmission state State based on the provided symbols (flip bit Tx_Flip, rotation bit Tx_Rotation, and polarity change bit Tx_Polarity) without considering the changed coupling relationship of the multiple line links. In this case, the multiple drive drivers Tx_Driver of the drive driver circuit DRV may not directly receive the drive signals DS_A, DS_B, and DS_C provided by the pre-driver control circuit DCL. That is, the drive signals DS_A, DS_B, and DS_C are appropriately selected by each of the multiple analog multiplexers MX1, MX2, and MX3 based on the changed coupling relationship of the multiple line links and provided to each drive driver Tx_Driver. In this case, due to the analog multiplexers MX1, MX2, and MX3, the power consumption of the drive driver circuit DRV increases and the area occupied by the drive driver circuit DRV increases. In addition, the wiring between the multiple analog multiplexers MX1, MX2, and MX3 and the pre-driver control circuit DCL becomes very complicated. Therefore, in practice, using Figure 3 The communication interface circuit of the encoder ENC may not support various variations of the line link, but may only support some variations of the line link.

[0060] In contrast, the encoder 125 according to the example embodiment also calculates the transmission state Pres_St to be suitable for the changed coupling relationship of the plurality of line links based on the control code CONTROL_CODE. The pre-driver control circuit 127 can directly provide the plurality of driving signals DrivingSignal_A, DrivingSignal_B, and DrivingSignal_C generated based on the transmission state Pres_St to each of the plurality of driving drivers 129.

[0061] Figure 4 It shows in detail Figure 2 1 is a block diagram of an encoder 125 according to an example embodiment.

[0062] refer to Figure 4 , the encoder 125 may include a symbol encoder 125_1 and a flip-flop circuit 125_2 .

[0063] Figure 4 It is illustrated that the transmission pins TXPIN_A, TXPIN_B, and TXPIN_C are sequentially coupled to the reception pins RXPIN_A, RXPIN_B, and RXPIN_C, but the coupling relationship may be changed.

[0064] The symbol encoder 125_1 receives a symbol consisting of 3 bits. The 3 bits of the symbol may include a flip bit Tx_Flip, a rotation bit Tx_Rotation, and a polarity change bit Tx_Polarity. Each bit of the symbol may indicate a state transition from a preamble state Prev_St to a transmission state Pres_St.

[0065] The symbol encoder 125_1 according to an example embodiment encodes a symbol based on the preamble state Prev_St and the control code CONTROL_CODE and outputs a transmission state Pres_St.

[0066] The control code CONTROL_CODE may indicate a coding change based on a coupling relationship of a plurality of line links providing a data channel LANE. For example, the control code CONTROL_CODE may indicate coding based on A / C line switching, B / C line switching, and A / B line switching. The control code CONTROL_CODE may indicate coding based on changing an A / B / C line to a B / C / A line or changing an A / B / C line to a C / A / B line, respectively.

[0067] The transmission states Pres_St[0], Pres_St[1], and Pres_St[2] output by the symbol encoder 125_1 may be provided to the flip-flop circuit 125_2 and the pre-driver control circuit 127 .

[0068] The flip-flop circuit 125_2 and the pre-driver control circuit 127 operate based on the same clock signal Symbol_clk. The flip-flop circuit 125_2 may store the transmission states Pres_St[0], Pres_St[1], and Pres_St[2] provided in the first unit interval. The flip-flop circuit 125_2 may provide the transmission states Pres_St[0], Pres_St[1], and Pres_St[2] received in the first unit interval as preamble states Prev_St[0], Prev_St[1], and Prev_St[2] to the symbol encoder 125_1 in the second unit interval which is the next unit interval continuous with the first unit interval.

[0069] The pre-driver control circuit 127 according to example embodiments may directly provide a plurality of driving signals DrivingSignal_A, DrivingSignal_B, and DrivingSignal_C generated based on the received transmission states Pres_St[0], Pres_St[1], and Pres_St[2] to the plurality of driving drivers 129 .

[0070] The driving voltage level of each line link driven based on the transmission states Pres_St[0], Pres_St[1], and Pres_St[2] may be as shown in Table 1. The driving voltage level of each line link in Table 1 assumes that there is no swapping or changing of the A / B / C lines.

[0071]

[0072] VA VB VC Tx_Wire_State Rx_Wire_State HIGH LOW MIDDLE +x +x LOW HIGH MIDDLE -x -x MIDDLE HIGH LOW +y +y MIDDLE LOW HIGH -y -y LOW MIDDLE HIGH +z +z HIGH MIDDLE LOW -z -z

[0073] The high level signal HIGH, the middle level signal MID, and the low level signal LOW may be signals having 4 / 3, 1 / 2, and 1 / 4 of the reference voltage, respectively.

[0074] The encoder 125_1 according to an example embodiment may include encoding logic ENC_LOGIC. The encoding logic ENC_LOGIC encodes a symbol based on a preamble state Prev_St and a control code CONTROL_CODE and outputs a transmission state Pres_St. When the control code CONTROL_CODE indicates that the A / B / C lines will not be swapped or changed, the encoding logic ENC_LOGIC may be based on Figure 5 The state diagram shown performs the encoding.

[0075] refer to Figure 5 , the transitions between the 6 line states are shown by the symbol FRP_Symbol expressed by 3 binary bits. For example, the line state "-y" can be changed to the line state "-x" by the symbol "000". Therefore, when the control code CONTROL_CODE indicates that the A / B / C lines will not be swapped or changed, the preamble state Prev_St is "-y", and the provided symbol is "000", the encoding logic ENC_LOGIC can output the transmission state Pres_St as "-x".

[0076] refer to Figure 5, when the control code CONTROL_CODE indicates that the A / B / C line will not be swapped or changed, the encoding logic ENC_LOGIC maintains the polarity of the previous state Prev_St based on the symbol "000" represented by 3 binary bits, and the output character decreases the transmission state Pres_St by one level. The increasing ordinal number of the character describing the line state will be in the increasing order of the letters in the alphabet. Therefore, in Figure 5 In the state diagram, the symbol "000" is transformed by rotating counterclockwise from the preamble state Prev_St. The encoding logic ENC_LOGIC changes the polarity of the preamble state Prev_St based on the symbol "001" and the output character decreases the transmission state Pres_St by one level. The encoding logic ENC_LOGIC maintains the polarity of the preamble state Prev_St based on the symbol "010" and the output character increases the transmission state Pres_St by one level. The encoding logic ENC_LOGIC changes the polarity of the preamble state Prev_St based on the symbol "011" and the output character increases the transmission state Pres_St by one level.

[0077] That is to say, Figure 5 In the state diagram, when the rotation bit Tx_Rotation of the symbol FRP_Symbol expressed by 3 binary bits is "0", the encoding logic ENC_LOGIC calculates the transmission state Pres_St by rotating from the previous state Prev_St in the direction that reduces the character. When the rotation bit Tx_Rotation is "1", the encoding logic ENC_LOGIC calculates the transmission state Pres_St by rotating from the previous state Prev_St in the direction that increases the character.

[0078] exist Figure 5 In the state diagram, the encoding logic ENC_LOGIC performs operations according to Table 2 based on the flip bit Tx_Flip, the rotation bit Tx_Rotation and the polarity change bit Tx_Polarity of the symbol FRP_Symbol expressed by 3 binary bits.

[0079]

[0080] Bit Tx_Flip Tx_Rotation Tx_Polarity 0 - Decrease the size of letters. - 1 Same letters, switch symbols. Increase the size of letters. Switch symbols.

[0081] When the control code CONTROL_CODE indicates the interchange of two of the A / B / C lines, the encoding logic ENC_LOGIC according to the exemplary embodiment may be configured according to Figure 6 The state diagram is used to calculate the sending state Pres_St.

[0082] For example, the encoding logic ENC_LOGIC maintains the polarity under the preceding state Prev_St based on the symbol "000" and the output character increases the transmission state Pres_St by one level. The encoding logic ENC_LOGIC changes the polarity under the preceding state Prev_St based on the symbol "001" and the output character increases the transmission state Pres_St by one level. The encoding logic ENC_LOGIC maintains the polarity under the preceding state Prev_St based on the symbol "010" and the output character decreases the transmission state Pres_St by one level. The encoding logic ENC_LOGIC changes the polarity under the preceding state Prev_St based on the symbol "011" and the output character decreases the transmission state Pres_St by one level.

[0083] That is to say, Figure 6 In the state diagram, when the rotation bit Tx_Rotation of the symbol FRP_Symbol expressed by 3 binary bits is "0", the encoding logic ENC_LOGIC calculates the transmission state Pres_St by rotating from the previous state Prev_St in the direction that increases the character. When the rotation bit Tx_Rotation is "1", the encoding logic ENC_LOGIC calculates the transmission state Pres_St by rotating from the previous state Prev_St in the direction that decreases the character.

[0084] exist Figure 6 In the state diagram, the encoding logic ENC_LOGIC performs operations according to Table 3 based on the flip bit Tx_Flip, the rotation bit Tx_Rotation and the polarity change bit Tx_Polarity of the symbol FRP_Symbol expressed by 3 binary bits.

[0085]

[0086] Bit Tx_Flip Tx_Rotation Tx_Polarity 0 - Increase the size of letters. - 1 Same letters, switch symbols. Decrease the size of letters. Switch symbols.

[0087] Figure 7 is a block diagram illustrating the operation of the transmission interface circuit 100 according to an example embodiment according to A / C line switching. Figures 1 to 6 A detailed description of overlapping or similar parts of the description.

[0088] refer to Figure 7 The transmission interface circuit 100 may include an encoder 125, a pre-driver control circuit 127, and a driver 129. The encoder 125, the pre-driver control circuit 127, and the driver 129 may be connected to Figure 2 and Figure 4 The same as those in .

[0089] The transmission pins TXPIN_A, TXPIN_B and TXPIN_C of the transmission interface circuit 100 are sequentially coupled to the reception pins RXPIN_C, RXPIN_B and RXPIN_A of the reception interface circuit 200. That is, the lines A and C on the multiple line links providing the data channel LANE are interchanged and coupled.

[0090] The encoding logic ENC_LOGIC of the encoder 125 according to an example embodiment may be provided with a control code CONTROL_CODE indicating encoding based on A / C line switching.

[0091] Based on the control code CONTROL_CODE, the encoding logic ENC_LOGIC can encode the symbols to output the transmission status as -y, +y, -x, +x, -z and +z, corresponding to the line status Rx_Wire_State of the receiving interface circuit 200 receiving +x, -x, +y, -y, +z and -z based on MIPI's C-PHY. Figure 7 The transmission interface circuit 100 according to the example embodiment may be based on a reference Figure 6 Describes the state diagram to calculate the transmit state Tx_Wire_State.

[0092] The pre-driver control circuit 127 may generate a plurality of driving signals DrivingSignal_A, DrivingSignal_B, and DrivingSignal_C based on the transmission state Tx_Wire_State output from the encoder 125 , and provide the driving signals to the plurality of driving drivers 129 , respectively.

[0093] The driving voltage level of each wire link driven based on the transmission state Tx_Wire_State may depend on the transmitted wire state as shown in Table 4.

[0094]

[0095] VA VB VC Tx_Wire_State Rx_Wire_State MIDDLE LOW HIGH -y +x MIDDLE HIGH LOW +y -x LOW HIGH MIDDLE -x +y HIGH LOW MIDDLE +x -y HIGH MIDDLE LOW -z +z LOW MIDDLE HIGH +z -z

[0096] For example, based on the control code CONTROL_CODE indicating the encoding based on the exchange of the A / C line, the encoder 125 can encode the symbol and output the transmission state Tx_Wire_State of "-y". The middle level signal MID, the low level signal LOW and the high level signal HIGH are sequentially driven in the line links respectively coupled to the transmission pins TXPIN_A, TXPIN_B and TXPIN_C. Due to the A / C line exchange, the receiving interface circuit 200 can sequentially receive the high level signal HIGH, the low level signal LOW and the middle level signal MID from the line A, the line B and the line C, respectively, and decode them into the receiving line state Rx_Wire_State of "+x".

[0097] Figure 8 is a block diagram illustrating the operation of the transmission interface circuit 100 according to an example embodiment according to A / B line switching. Figures 1 to 7 A detailed description of overlapping or similar parts of the description.

[0098] refer to Figure 8 The transmission interface circuit 100 may include an encoder 125, a pre-driver control circuit 127, and a driver 129. The encoder 125, the pre-driver control circuit 127, and the driver 129 may be connected to Figure 2 and Figure 4 The same as those in .

[0099] The transmission pins TXPIN_A, TXPIN_B and TXPIN_C of the transmission interface circuit 100 are sequentially coupled to the reception pins RXPIN_B, RXPIN_A and RXPIN_C of the reception interface circuit 200. That is, the lines A and B on the multiple line links providing the data channel LANE are interchanged and coupled.

[0100] The encoding logic ENC_LOGIC of the encoder 125 according to example embodiments may be provided with a control code CONTROL_CODE indicating encoding based on A / B line switching.

[0101] Based on the control code CONTROL_CODE, the encoding logic ENC_LOGIC can encode the symbols to output the transmission status as -x, +x, -z, +z, -y and +y, corresponding to the line status Rx_Wire_State of the receiving interface circuit 200 receiving +x, -x, +y, -y, +z and -z based on MIPI's C-PHY. Figure 8 The transmission interface circuit 100 according to the example embodiment may be based on a reference Figure 6 Describes the state diagram to calculate the transmit state Tx_Wire_State.

[0102] The driving voltage level of each wire link driven based on the transmission state Tx_Wire_State may depend on the transmitted wire state as shown in Table 5.

[0103]

[0104] VA VB VC Tx_Wire_State Rx_Wire_State LOW HIGH MIDDLE -x +x HIGH LOW MIDDLE +x -x HIGH MIDDLE LOW -z +y LOW MIDDLE HIGH +z -y MIDDLE LOW HIGH -y +z MIDDLE HIGH LOW +y -z

[0105] For example, based on the control code CONTROL_CODE indicating the encoding based on the A / B line switching, the encoder 125 can encode the symbol and output the transmission state Tx_Wire_State of "-x". The low level signal LOW, the high level signal HIGH and the middle level signal MID are sequentially driven in the line links respectively coupled to the transmission pins TXPIN_A, TXPIN_B and TXPIN_C. Due to the A / B line switching, the receiving interface circuit 200 can sequentially receive the high level signal HIGH, the low level signal LOW and the middle level signal MID from the line A, the line B and the line C, respectively, and decode them into the receiving line state Rx_Wire_State of "+x".

[0106] Fig. 9 is a block diagram illustrating the operation of the transmission interface circuit 100 according to the B / C line switching according to the exemplary embodiment. Figures 1 to 8 A detailed description of overlapping or similar parts of the description.

[0107] refer to Fig. 9 The transmission interface circuit 100 may include an encoder 125, a pre-driver control circuit 127, and a driver 129. The encoder 125, the pre-driver control circuit 127, and the driver 129 may be connected to Figure 2 and Figure 4 The same as those in .

[0108] The transmission pins TXPIN_A, TXPIN_B and TXPIN_C of the transmission interface circuit 100 are sequentially coupled to the reception pins RXPIN_A, RXPIN_C and RXPIN_B of the reception interface circuit 200. That is, the line B and the line C on the multiple line links providing the data channel LANE are interchanged and coupled.

[0109] The encoding logic ENC_LOGIC of the encoder 125 according to an example embodiment may be provided with a control code CONTROL_CODE indicating encoding based on B / C line switching.

[0110] Based on the control code CONTROL_CODE, the encoding logic ENC_LOGIC can encode the symbols to output the transmission status as -z, +z, -y, +y, -x and +x, corresponding to the line status Rx_Wire_State of the receiving interface circuit 200 receiving +x, -x, +y, -y, +z and -z based on MIPI's C-PHY. Fig. 9 The transmission interface circuit 100 according to the example embodiment may be based on a reference Figure 6 Describes the state diagram to calculate the transmit state Tx_Wire_State.

[0111] The driving voltage level of each wire link driven based on the transmission state Tx_Wire_State may depend on the transmitted wire state as shown in Table 6.

[0112]

[0113] VA VB VC Tx_Wire_State Rx_Wire_State HIGH MIDDLE LOW -z +x LOW MIDDLE HIGH +z -x MIDDLE LOW HIGH -y +y MIDDLE HIGH LOW +y -y LOW HIGH MIDDLE -x +z HIGH LOW MIDDLE +x -z

[0114] For example, based on the control code CONTROL_CODE indicating the encoding based on the B / C line exchange, the encoder 125 can encode the symbol and output the transmission state Tx_Wire_State of "-z". The high level signal HIGH, the middle level signal MID and the low level signal LOW are sequentially driven in the line links respectively coupled to the transmission pins TXPIN_A, TXPIN_B and TXPIN_C. Due to the B / C line exchange, the receiving interface circuit 200 can sequentially receive the high level signal HIGH, the low level signal LOW and the middle level signal MID from the line A, the line B and the line C, respectively, and decode them into the receiving line state Rx_Wire_State of "+x".

[0115] Fig.10 1 is a block diagram illustrating an operation of sequentially changing line A, line B, and line C to line B, line C, and line A by the transmission interface circuit 100 according to an example embodiment. Figures 1 to 9 A detailed description of overlapping or similar parts of the description.

[0116] The transmission pins TXPIN_A, TXPIN_B and TXPIN_C of the transmission interface circuit 100 are sequentially coupled to the reception pins RXPIN_C, RXPIN_A and RXPIN_B of the reception interface circuit 200. That is, the lines A, B and C on the multiple line links providing the data channel LANE are changed and coupled to the lines B, C and A respectively.

[0117] The encoding logic ENC_LOGIC of the encoder 125 according to example embodiments may receive a control code CONTROL_CODE indicating encoding changed from lane A, lane B, and lane C to lane B, lane C, and lane A in order.

[0118] Based on the control code CONTROL_CODE, the encoding logic ENC_LOGIC can encode the symbols to output the transmission status as +y, -y, +z, -z, +x and -x, corresponding to the line status Rx_Wire_State of the receiving interface circuit 200 receiving +x, -x, +y, -y, +z and -z based on MIPI's C-PHY. Fig.10 The transmission interface circuit 100 according to the example embodiment may be based on a reference Figure 5 Describes the state diagram to calculate the transmit state Tx_Wire_State.

[0119] That is, the line state transition form when line A, line B, and line C are changed to line B, line C, and line A, respectively, is different from the line state transition form when two of line A, line B, and line C are interchanged.

[0120] The driving voltage level of each wire link driven based on the transmission state Tx_Wire_State may depend on the transmitted wire state as shown in Table 7.

[0121]

[0122] VA VB VC Tx_Wire_State Rx_Wire_State MIDDLE HIGH LOW +y +x MIDDLE LOW HIGH -y -x LOW MIDDLE HIGH +z +y HIGH MIDDLE LOW -z -y HIGH LOW MIDDLE +x +z LOW HIGH MIDDLE -x -z

[0123] For example, based on the control code CONTROL_CODE indicating the encoding based on the fact that line A, line B and line C are changed to line B, line C and line A respectively, the encoder 125 can encode the symbol and output the transmission state Tx_Wire_State of "+y". The middle level signal MID, the high level signal HIGH and the low level signal MID are sequentially driven in the line links respectively coupled to the transmission pins TXPIN_A, TXPIN_B and TXPIN_C. Due to the change from line A, line B and line C to line B, line C and line A in order, the receiving interface circuit 200 can sequentially receive the high level signal HIGH, the low level signal LOW and the middle level signal MID from line A, line B and line C respectively, and decode them into the receiving line state Rx_Wire_State of "+x".

[0124] Fig.11 1 is a block diagram illustrating an operation of sequentially changing line A, line B, and line C to line C, line A, and line B by the transmission interface circuit 100 according to an example embodiment. Figures 1 to 10 A detailed description of overlapping or similar parts of the description.

[0125] The transmission pins TXPIN_A, TXPIN_B and TXPIN_C of the transmission interface circuit 100 are sequentially coupled to the reception pins RXPIN_B, RXPIN_C and RXPIN_A of the reception interface circuit 200. That is, the lines A, B and C on the multiple line links providing the data channel LANE are changed and coupled to the lines C, A and B respectively.

[0126] The encoding logic ENC_LOGIC of the encoder 125 according to example embodiments may receive a control code CONTROL_CODE indicating encoding changed from lane A, lane B, and lane C to lane C, lane A, and lane B in order.

[0127] Based on the control code CONTROL_CODE, the encoding logic ENC_LOGIC can encode the symbols to output the transmission status as +z, -z, +x, -x, +y and -y, corresponding to the line status Rx_Wire_State of the receiving interface circuit 200 receiving +x, -x, +y, -y, +z and -z based on MIPI's C-PHY. Fig.11 The transmission interface circuit 100 according to the example embodiment may be based on a reference Figure 5 Describes the state diagram to calculate the transmit state Tx_Wire_State.

[0128] That is, the line state transition form when line A, line B, and line C are changed to line C, line A, and line B, respectively, is different from the line state transition form when two of line A, line B, and line C are interchanged.

[0129] The driving voltage level of each wire link driven based on the transmission state Tx_Wire_State may depend on the transmitted wire state as shown in Table 8.

[0130]

[0131] VA VB VC Tx_Wire_State Rx_Wire_State LOW MIDDLE HIGH +z +x HIGH MIDDLE LOW -z -x HIGH LOW MIDDLE +x +y LOW HIGH MIDDLE -x -y MIDDLE HIGH LOW +y +z MIDDLE LOW HIGH -y -z

[0132] For example, based on the control code CONTROL_CODE indicating the encoding based on the fact that line A, line B and line C are changed to line C, line A and line B, respectively, the encoder 125 can encode the symbol and output the transmission state Tx_Wire_State of "+z". The low level signal LOW, the middle level signal MID and the high level signal HIGH are sequentially driven in the line links respectively coupled to the transmission pins TXPIN_A, TXPIN_B and TXPIN_C. Due to the change from line A, line B and line C to line C, line A and line B in sequence, the receiving interface circuit 200 can sequentially receive the high level signal HIGH, the low level signal LOW and the middle level signal MID from line A, line B and line C, respectively, and decode them into the receiving line state Rx_Wire_State of "+x".

[0133] Fig.12 is a block diagram illustrating a receiving side communication interface circuit according to an example embodiment. Figures 1 to 11 A detailed description of overlapping or similar parts of the description.

[0134] refer to Fig.12 , the receiving interface circuit 200_2 may include a physical layer circuit 210 and a protocol layer circuit 220 .

[0135] The physical layer circuit 210 may receive a data signal from the transmitting interface circuit 100 of the transmitting side through the data channel LANE. The physical layer circuit 210 may receive a data signal through at least one data channel LANE. For example, the physical layer circuit 210 may receive a data signal through multiple data channels. For reference, Figure 1 The description is based on the assumption that there is one data channel LANE.

[0136] The physical layer circuit 210 may receive a reception status through a data channel LANE provided to a plurality of line links according to C-PHY defined by the MIPI Alliance.

[0137] The physical layer circuit 210 according to an example embodiment includes a decoder 213. The decoder 213 calculates a symbol based on the preamble differential signal, the reception differential signal, and the control code.

[0138] The decoder of the physical layer circuit of the conventional receiving interface circuit only calculates the symbol based on the preamble differential signal and the receiving differential signal. In contrast, the decoder 213 of the physical layer circuit 210 of the receiving interface circuit 200_2 according to the example embodiment also calculates the symbol based on the control code CONTROL_CODE. The control code is a code indicating a decoding change based on the coupling relationship of multiple three-phase line links.

[0139] That is, similar to Figure 1 The transmitting interface circuit 100 and the receiving interface circuit 200_2 support the exchange or change of the line link. When the receiving interface circuit 200_2 supports the exchange or change of the line link, the transmitting interface circuit 100_2 can send the data signal to the data channel LANE without considering the exchange or change of the line link.

[0140] The physical layer circuit 210 demaps the calculated symbols into bit codes of the reception data Rx_Data. The reception data Rx_Data output from the physical layer circuit 210 may be data in the form of packet data.

[0141] The protocol layer circuit 110 may receive the packet data Rx_Data, extract a payload based on the header and the footer, and generate data.

[0142] Depending on the coupling settings between the components, the coupling relationship between the transmit pins TXPIN_A, TXPIN_B and TXPIN_C and the receive pins RXPIN_A, RXPIN_B and RXPIN_C may change. Fig.12 It is illustrated that the transmission pins TXPIN_A, TXPIN_B, and TXPIN_C are sequentially coupled to the reception pins RXPIN_A, RXPIN_B, and RXPIN_C, respectively, but the coupling relationship may be changed.

[0143] The reception interface circuit 200_2 according to example embodiments may change decoding of a reception differential signal based on a change in a coupling relationship between the transmission pins TXPIN_A, TXPIN_B, and TXPIN_C and the reception pins RXPIN_A, RXPIN_B, and RXPIN_C.

[0144] Fig.13 is a block diagram illustrating a physical layer circuit according to an example embodiment in detail.

[0145] refer to Fig.13 The physical layer circuit 210 includes a receiver 211 , a decoder 213 , a serial-to-parallel converter 215 and a demapper 217 .

[0146] Fig.13 The illustration shows that the transmit pins TXPIN_A, TXPIN_B, and TXPIN_C are sequentially coupled to the line link A, the line link B, and the line link C, but the coupling relationship may be changed. For example, Fig.13 The physical layer circuit according to example embodiments in may support A / C line switching in which transmit pin A TXPIN_A is coupled to line link C and transmit pin C TXPIN_C is coupled to line link A. Other types of line switching of multiple line links may also be supported.

[0147] The receiver 211 outputs differential signals Rx_AB, Rx_BC, and Rx_CA based on the difference between the driving signals of each line link according to a reception state.

[0148] The decoder 213 according to the exemplary embodiment calculates a symbol consisting of 3 bits based on the differential signals Rx_AB, Rx_BC and Rx_CA and the control code CONTROL_CODE. The 3 bits may include a flip bit Rx_Flip, a rotation bit Rx_Rotation and a polarity change bit Rx_Polarity. Each bit of the symbol may indicate the type of transition from the preamble differential signal to the received differential signal.

[0149] The preamble differential signal and the reception differential signal may correspond to a line state that defines a signal level of three 3-phase line links according to C-PHY of MIPI.

[0150] The control code CONTROL_CODE may indicate a decoding change based on a coupling relationship of multiple line links. For example, the control code CONTROL_CODE may indicate decoding based on A / C line switching, B / C line switching, and A / B line switching. The control code CONTROL_CODE may indicate decoding based on changing an A / B / C line to a B / C / A line or changing an A / B / C line to a C / A / B line, respectively.

[0151] The control code CONTROL_CODE may be stored in a register outside the physical layer circuit. When the component is started, the control code CONTROL_CODE may be provided to the decoder 213. The control code CONTROL_CODE may be stored as different values ​​in the register according to different coupling relationships of the plurality of line links.

[0152] Each symbol output by the decoder 213 is provided to the serial-to-parallel converter 215, and the serial-to-parallel converter 215 illustratively provides 7 symbols to the demapper 217. The demapper 217 may demap the 7 symbols into 16 binary bit data and output the reception data Rx_Data.

[0153] Fig.14 It is illustrated in detail Fig.13 2 is a block diagram of a decoder 213 according to an example embodiment.

[0154] refer to Fig.14 , the decoder 213 may include a flip-flop circuit 213_1 and a symbol decoder 213_2 .

[0155] Fig.14It is illustrated that the transmission pins TXPIN_A, TXPIN_B, and TXPIN_C are sequentially coupled to the reception pins RXPIN_A, RXPIN_B, and RXPIN_C, but the coupling relationship may be changed.

[0156] The receiver 211 outputs differential signals Rx_AB, Rx_BC, and Rx_CA based on the reception status.

[0157] The differential signals Rx_AB, Rx_BC, and Rx_CA may be determined as shown in Table 9 based on the reception status.

[0158]

[0159] Rx_Wire_State Rx_AB Rx_BC Rx_CA +x 1 0 0 -x 0 1 1 +y 0 1 0 -y 1 0 1 +z 0 0 1 -z 1 1 0

[0160] The differential signals Rx_AB, Rx_BC, and Rx_CA output from the receiver 211 are provided to the flip-flop circuit 213_1 .

[0161] The flip-flop circuit 213_1 operates based on the clock signal Symbol_clk. The flip-flop circuit 213_1 may store the differential signals Rx_AB, Rx_BC, and Rx_CA provided in the first unit interval as preamble differential signals Prev_AB, Prev_BC, and Prev_CA. The flip-flop circuit 213_1 may provide the differential signals Rx_AB, Rx_BC, and Rx_CA received in the first unit interval as preamble differential signals Prev_AB, Prev_BC, and Prev_CA to the decoder 213_2 in the second unit interval which is the next unit interval continuous with the first unit interval.

[0162] The symbol decoder 213_2 according to an example embodiment receives the preamble differential signals Prev_AB, Prev_BC, and Prev_CA, receives the differential signals Pres_AB, Pres_BC, and Pres_CA, and the control code CONTROL_CODE.

[0163] The symbol decoder 213_2 decodes the reception differential signals Pres_AB, Pres_BC, and Pres_CA based on the preamble differential signals Prev_AB, Prev_BC, and Prev_CA and the control code CONTROL_CODE, and outputs a symbol consisting of 3 binary bits.

[0164] The three bits of the symbol may include a flip bit Rx_Flip, a rotation bit Rx_Rotation, and a polarity change bit Rx_Polarity. Each bit of the symbol may indicate a transition form from the preamble differential signals Prev_AB, Prev_BC, and Prev_CA to the reception differential signals Pres_AB, Pres_BC, and Pres_CA.

[0165] The symbol decoder 213_2 can appropriately decode the received differential signals Pres_AB, Pres_BC and Pres_CA for the coupling relationship of the multiple line links based on the provided control code CONTROL_CODE. The decoder can decode the receiving state differently according to the coupling relationship of the multiple line links and output a symbol composed of 3 binary bits.

[0166] For example, when the control code CONTROL_CODE provided indicates A / C line switching, based on Figure 6 The symbol decoder 213_2 can decode the line states -y, +y, -x, +x, -z and +z into symbols corresponding to +x, -x, +y, -y, +z and -z respectively according to MIPI's C-PHY. When the receiving interface circuit receives the receiving state of -y and the control code CONTROL_CODE indicates A / C line switching, the trigger circuit 213_1 outputs "101" as the receiving differential signals Pres_AB, Pres_BC and Pres_CA for the receiving state of -y based on Table 9. When the pre-order differential signals Prev_AB, Prev_BC and Prev_CA are, for example, "100" corresponding to the line state +x, the symbol decoder 213_2 can output Figure 6 The transition from line state +x to line state -y in the state diagram corresponds to "001" as a symbol consisting of 3 binary bits. Figure 6 Each state in the state diagram can replace the bit corresponding to the differential signal in Table 9 for use in the symbol decoder 213_2.

[0167] That is, the preamble state +x and the reception state -y received in the case of A / C line switching correspond to the preamble state -y and the reception state +x when there is no line switching, respectively. When there is no line switching, the symbol decoder 213_2 can be based on Figure 5 The state diagram and output symbol "001" decode the preamble state -y and the receive state +x. Therefore, when the control code CONTROL_CODE indicates A / C line switching, it corresponds to Figure 6 The sign of the transition from line state +x to line state -y in the state diagram of is the same as the output of "001".

[0168] Therefore, when the control code CONTROL_CODE indicates decoding based on A / C line switching, B / C line switching, and A / B line switching, the symbol decoder 213_2 may be based on Figure 6 When the control code CONTROL_CODE indicates decoding based on a change from the A / B / C line to the B / C / A line or the C / A / B line, the symbol decoder 213_2 may perform decoding based on Figure 6 The state diagram performs decoding.

[0169] Fig.15 It's a picture. Fig.13 2 is a block diagram of another example of a decoder 213 according to an example embodiment.

[0170] refer to Fig.15 , the decoder 213 may include a symbol decoder 213_3. The symbol decoder 213_3 is respectively Fig.14 The same receiver 211 and trigger circuit 213_1 in the embodiment receive the received differential signals Pres_AB, Pres_BC and Pres_CA and the preamble differential signals Prev_AB, Prev_BC and Prev_CA. In addition, the symbol interpreter 213_4 receives the control code CONTROL_CODE.

[0171] The symbol decoder 213_3 according to an example embodiment may include a symbol interpreter 213_4. The symbol interpreter 213_4 converts reception differential signals Pres_AB, Pres_BC, and Pres_CA and preamble differential signals Prev_AB, Prev_BC, and Prev_CA based on a control code CONTROL_CODE and outputs them to first and second output lines IN1 and IN2.

[0172] For example, when the control code CONTROL_CODE indicates decoding based on A / C line switching, the symbol interpreter 213_4 may receive the differential signals Pres_AB, Pres_BC and Pres_CA and the preamble differential signals Prev_AB, Prev_BC and Prev_CA as Fig.15 Referring to Table 10 showing the symbol conversion relationship based on A / C line switching, when the received differential signals Pres_AB, Pres_BC and Pres_CA are "101" generated based on the reception state of -y, the symbol interpreter 213_4 can convert them into "100" corresponding to the reception state of +x and output them to the first output line IN1. The decoding logic DEC_LOGIC can be based on Figure 5In the state diagram of when line switching is restored, the symbols Rx_Flip, Rx_Rotation and Rx_Polarity are calculated based on the current differential signals Pres_AB, Pres_BC and Pres_CA and the preceding differential signals Prev_AB, Prev_BC and Prev_CA. Therefore, Fig.15 The decoding logic DEC_LOGIC in can be different from Fig.14 Decoding logic DEC_LOGIC in.

[0173]

[0174]

[0175] Fig.16 Different operations of the symbol interpreter 213_4 corresponding to different control codes CONTROL_CODE are shown. Fig.16 In the first operation on the left side, when the control code CONTROL_CODE indicates decoding based on A / C line switching (A / CSWAP), decoding based on A / B line switching (A / B SWAP), and decoding based on B / C line switching (B / C SWAP), the symbol interpreter 213_4 can convert the received differential signals Pres_AB, Pres_BC, and Pres_CA and the preamble differential signals Prev_AB, Prev_BC, and Prev_CA, respectively. Fig.16 The second operation on the right side of , when the control code CONTROL_CODE indicates decoding based on line A, line B and line C changing to line B, line C and line A respectively (A→B, B→C and C→A transitions) and decoding based on line A, line B and line C changing to line C, line A and line B respectively (A→C, B→A and C→B transitions), the symbol interpreter 213_4 can convert the received differential signals Pres_AB, Pres_BC and Pres_CA and the preamble differential signals Prev_AB, Prev_BC and Prev_CA respectively.

[0176] The symbol interpreter 213_4 can be implemented through various schemes such as multiple multiplexers or a table-type memory device.

[0177] Fig.17 is a flow chart illustrating a method of operating a transmission-side communication interface circuit according to an example embodiment.

[0178] The communication interface circuit transmits a data signal through a data channel provided on a plurality of three-phase line links. According to an example embodiment, the data channel may be driven based on C-PHY of MIPI.

[0179] In operation S110, the communication interface circuit may process input data in the form of packet data. The communication interface circuit may generate a payload based on the input data, and insert a header and a footer suitable for transmission before and after the payload, respectively, to generate transmission data in the form of packet data.

[0180] According to example embodiments, the communication interface circuit may generate transmission data according to CSI-2, DSI, and DSI-2 defined by the MIPI Alliance.

[0181] In operation S120, the communication interface circuit may encode the transmission data as packet data and output a transmission status.

[0182] The communication interface circuit may calculate the transmission status based on the symbol to which the transmission data is mapped, the preamble status, and the control code.

[0183] The communication interface circuit can map 16 binary bits of the transmitted data to 7 symbols and then perform encoding.

[0184] Each symbol may include a flip bit Tx_Flip indicating a transition type from a preamble state to a transmission state based on a previous symbol, a rotation bit Tx_Rotation, and a polarity change bit Tx_Polarity. Therefore, a symbol may be represented by 3 binary bits.

[0185] The transmission state may be a line state that defines signal levels of three 3-phase line links according to C-PHY of MIPI.

[0186] The control code may be a code indicating a coding change based on a coupling relationship of a plurality of three-phase line links.

[0187] According to example embodiments, based on the control code, the communication interface circuit may differently perform encoding according to exchange of two of three three-phase line links (line link A, line link B, and line link C) according to C-PHY of MIPI.

[0188] For example, based on the received control code, the same symbol can be encoded into mutually different line states when line link A and line link C are switched, when line link A and line link B are switched, and when line link B and line link C are switched.

[0189] According to an example embodiment, based on the control code, the communication interface circuit may perform encoding differently according to changes in all three 3-phase line links according to C-PHY of MIPI.

[0190] The communication interface circuit can appropriately perform encoding for the changed coupling relationship of the communication link based on the control code indicating the change of the coupling relationship of the communication link. As a result, the degradation of the communication channel can be reduced, and the data signal can be stably sent. In addition, the communication interface circuit can stably send data signals by supporting various interconnections between components caused by the arrangement of the coupling terminals.

[0191] When the control code indicates that the A / B / C lines will not be swapped or changed, the communication interface circuit can be based on Figure 5 The state diagram performs the encoding.

[0192] When the control code indicates that two of the A / B / C lines are to be interchanged, the communication interface circuit can Figure 6 The state diagram performs the encoding.

[0193] The communication interface circuit may encode the symbol based on the control code indicating the encoding based on the A / C line switching. That is, the communication interface circuit may encode the symbol to output the transmission state as -y, +y, -x, +x, -z and +z on the transmission side, corresponding to the reception line states +x, -x, +y, -y, +z and -z on the reception side, respectively.

[0194] The communication interface circuit may encode the symbol based on the control code indicating the encoding based on the A / B line switching. That is, the communication interface circuit may encode the symbol to output the transmission state as -x, +x, -z, +z, -y and +y on the transmission side, corresponding to the reception line states +x, -x, +y, -y, +z and -z on the reception side, respectively.

[0195] The communication interface circuit can encode the symbol based on the control code indicating the encoding based on the B / C line exchange. That is, the communication interface circuit can encode the symbol to output the transmission state as -z, +z, -y, +y, -x and +x on the transmission side, corresponding to the reception line states +x, -x, +y, -y, +z and -z on the reception side, respectively.

[0196] The communication interface circuit may encode the symbol based on a control code indicating encoding based on the order in which line A, line B, and line C are respectively changed to line B, line C, and line A. That is, the communication interface circuit may encode the symbol to output the transmission state as +y, -y, +z, -z, +x, and -x on the transmission side, corresponding to the reception line states +x, -x, +y, -y, +z, and -z on the reception side, respectively.

[0197] The communication interface circuit may encode the symbol based on a control code indicating encoding based on the order that line A, line B, and line C are respectively changed to line C, line A, and line B. That is, the communication interface circuit may encode the symbol to output the transmission state as +z, -z, +x, -x, +y, and -y on the transmission side, corresponding to the reception line states +x, -x, +y, -y, +z, and -z on the reception side, respectively.

[0198] In operation S120 , the communication interface circuit may drive a plurality of 3-phase line links based on a transmission state and transmit a data signal to a data channel provided on the 3-phase line links.

[0199] The communication interface circuit may generate a plurality of driving signals for driving three three-phase line links based on a transmission state according to C-PHY of MIPI.

[0200] The communication interface circuit can drive the plurality of line links based on each generated driving signal regardless of the change in the coupling relationship of the plurality of line links. That is, because the transmission state is appropriately calculated based on the control code for the changed coupling relationship of the plurality of line links in operation S120, the driving signal generated based on the transmission state can directly drive each of the plurality of line links based on the driving signal.

[0201] In addition, specific example embodiments have been described above. The present disclosure may include not only the above example embodiments, but also simple design changes or easily changeable example embodiments. In addition, the present disclosure may include technologies that can easily modify and implement the example embodiments. Therefore, the scope should not be limited to the above example embodiments, but should be defined by the appended claims and the claims and equivalents.

[0202] Any functional block shown in the figures and described above may be implemented with the following items: processing circuitry, such as hardware including logic circuitry; hardware / software combination, such as a processor running software; or a combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0203] The exemplary embodiments have been described above by means of method steps that illustrate the execution of specified functions and their relationships. For ease of description, the boundaries and order of these functional components and method steps have been defined in this article. Interchangeable boundaries and orders can be defined as long as the specified functions and relationships are properly executed. Any such interchangeable boundaries or orders are therefore within the scope and spirit of the claims.

[0204] In various example embodiments herein, reference may have been made to various circuit elements, including but not limited to capacitors, resistors, inductors, switches, amplifiers, comparators, filters, triggers, drivers, and transistors. Various types of digital, analog, active and / or passive components may be used in implementing the example embodiments. For example, various transistor types may be used depending on the implementation, whether positive logic or negative logic is used, the manufacturing process used, etc. In addition, unless otherwise specifically stated herein, there are many available types of filters, comparators, switches, etc. that can be used to implement the example embodiments.

Claims

1. A communication interface circuit, the communication interface circuit comprising: a protocol layer circuit configured to generate packet data based on input data; as well as a physical layer circuit configured to encode the packet data to output a transmission state, and drive a data channel including a plurality of three-phase line links based on the transmission state, wherein the physical layer circuit comprises an encoder configured to calculate the transmission state based on a preamble state output from the encoder in a previous unit interval, a symbol mapped to the packet data, and a control code, and The control code is configured to indicate a coding change based on a coupling relationship of the plurality of three-phase line links.

2. The communication interface circuit according to claim 1, wherein: The physical layer circuit comprises: a mapping circuit configured to map the packet data to the symbols; the encoder configured to calculate the transmission state based on the preamble state, the symbol and the control code; a pre-driver control circuit configured to control a plurality of drive drivers based on the transmission state; and The plurality of driving drivers are configured to respectively drive the plurality of three-phase line links based on control of the pre-driver control circuit.

3. The communication interface circuit according to claim 2, wherein: The output of the pre-driver control circuit is provided directly to the plurality of drive drivers.

4. The communication interface circuit according to claim 1, wherein: The encoder is configured to receive the control code from an external register.

5. The communication interface circuit according to claim 1, wherein: The physical layer circuit is based on C-PHY of the mobile industrial processor interface MIPI.

6. The communication interface circuit according to claim 5, wherein: The plurality of three-phase line links include a first line link, a second line link and a third line link, The control code is configured to indicate a coding change based on a switching relationship between the first line link and the third line link, and The encoder is configured to output the transmission status as each of -y, +y, -x, +x, -z and +z, corresponding to the reception of each of the line states of +x, -x, +y, -y, +z and -z by the receiving end based on the MIPI's C-PHY.

7. The communication interface circuit according to claim 5, wherein: The plurality of three-phase line links include a first three-phase line link, a second three-phase line link and a third three-phase line link, The control code is configured to indicate a coding change based on a switching relationship between two of the first three-phase line link, the second three-phase line link, and the third three-phase line link, and The encoder is configured to output the transmission state in which the alphabet is increased from the preceding state and the polarity of the preceding state is maintained, corresponding to the symbol of the bit code "000".

8. The communication interface circuit according to claim 5, wherein: The plurality of three-phase line links include a first three-phase line link, a second three-phase line link and a third three-phase line link, The control code is configured to indicate a coding change based on a switching relationship between two of the first three-phase line link, the second three-phase line link, and the third three-phase line link, and The encoder is configured to output the transmission state in which letters are increased from the preceding state and the polarity of the preceding state is changed, corresponding to the symbol of the bit code "001".

9. The communication interface circuit according to claim 5, wherein: The plurality of three-phase line links include a first three-phase line link, a second three-phase line link and a third three-phase line link, The control code is configured to indicate a coding change based on a switching relationship between two of the first three-phase line link, the second three-phase line link, and the third three-phase line link, and The encoder is configured to output the transmission state in which the alphabet is reduced from the preceding state and the polarity of the preceding state is maintained, corresponding to the symbol of the bit code "010".

10. The communication interface circuit according to claim 5, wherein: The plurality of three-phase line links include a first three-phase line link, a second three-phase line link and a third three-phase line link, The control code is configured to indicate a coding change based on a switching relationship between two of the first three-phase line link, the second three-phase line link, and the third three-phase line link, and The encoder is configured to output the transmission state in which the alphabet is reduced from the preceding state and the polarity of the preceding state is changed, corresponding to the symbol of the bit code "011".

11. The communication interface circuit according to claim 5, wherein: The plurality of three-phase line links include a first three-phase line link, a second three-phase line link and a third three-phase line link, The control code is configured to indicate a coding change based on a relationship that the first three-phase line link is changed to the second three-phase line link, the second three-phase line link is changed to the third three-phase line link, and the third three-phase line link is changed to the first three-phase line link, The encoder is configured to output the transmission status as each of +y, -y, +z, -z, +x and -x, corresponding to the reception of each of the line states of +x, -x, +y, -y, +z and -z by the receiving end based on the MIPI's C-PHY.

12. The communication interface circuit according to claim 5, wherein: The plurality of three-phase line links include a first three-phase line link, a second three-phase line link and a third three-phase line link, The control code is configured to indicate a coding change based on a relationship that the first three-phase line link is changed to the third three-phase line link, the second three-phase line link is changed to the first three-phase line link, and the third three-phase line link is changed to the second three-phase line link, The encoder is configured to output the transmission status as each of +z, -z, +x, -x, +y and -y, corresponding to the reception of each of the line states of +x, -x, +y, -y, +z and -z by the receiving end based on the MIPI's C-PHY.

13. The communication interface circuit according to claim 5, wherein: The plurality of three-phase line links include a first three-phase line link, a second three-phase line link and a third three-phase line link, and The encoder is configured to output different transmission states based on different control codes, corresponding to the same line state received by the receiving end based on the C-PHY of the MIPI.

14. A communication interface circuit, the communication interface circuit comprising: a physical layer circuit configured to generate a plurality of differential signals based on a driving voltage of each of a plurality of three-phase line links of a data channel, and output a symbol based on the plurality of differential signals; as well as a protocol layer circuit configured to demap the symbols and output data, wherein the physical layer circuit comprises a decoder configured to calculate the symbol according to a received differential signal based on the plurality of differential signals, a preamble differential signal based on the plurality of differential signals in a previous unit interval, and a control code, and The control code is configured to indicate a decoding change based on a coupling relationship of the plurality of three-phase line links.

15. The communication interface circuit according to claim 14, wherein: The physical layer circuit is based on C-PHY of the mobile industrial processor interface MIPI.

16. The communication interface circuit according to claim 15, wherein: The plurality of three-phase line links include a first three-phase line link, a second three-phase line link and a third three-phase line link, The control code is configured to indicate a decoding change based on a switching relationship between the first three-phase line link and the third three-phase line link, and The decoder includes a symbol interpreter configured to convert a plurality of differential signals corresponding to line states of -y, +y, -x, +x, -z and +z received by the MIPI-based C-PHY into a plurality of differential signals corresponding to line states of +x, -x, +y, -y, +z and -z, respectively.

17. A method of operating a communication interface circuit, the method comprising: generating grouped data based on input data; Encoding the packet data to output a sending status; as well as driving a data channel based on the transmission state, the data channel comprising a plurality of three-phase line links, wherein encoding the packet data comprises calculating the transmission state based on a preamble state output in a previous unit interval, a symbol mapped to the packet data, and a control code, and The control code indicates a coding change based on a coupling relationship of the plurality of three-phase line links.

18. The method according to claim 17, wherein: The plurality of three-phase line links include a first three-phase line link, a second three-phase line link and a third three-phase line link, and The encoding of the packet data includes outputting different transmission states based on different control codes, corresponding to the same line state received by the receiving end based on C-PHY of the mobile industrial processor interface MIPI.

19. The method according to claim 17, wherein: Driving the data channel includes: generating a plurality of driving signals based on the transmission status to drive a plurality of driving drivers; and The plurality of drive signals are provided directly to the plurality of drive drivers.

20. The method according to claim 17, wherein: The data channel is driven based on C-PHY of the mobile industry processor interface MIPI, the plurality of three-phase line links include three three-phase line links, and the symbol includes 3 binary bits, and The method further includes: corresponding to the control code indicating the coding change based on the exchange relationship between two of the three three-phase line links, outputting the sending state of the character with the preamble state increased based on the middle bit of the symbol being "0", and outputting the sending state of the character with the preamble state reduced based on the middle bit of the symbol being "1".

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