Power semiconductor device and associated method

Abstract

A semiconductor power device includes an active region including: a drift region of a first conductivity type; the body region of the second conduction type is arranged on the drift region, and the second conduction type is opposite to the first conduction type; the groove is in contact with the body region and the drift region, and the groove comprises a grid electrode conductive region, a grid electrode conductive region and a grid electrode conductive region; a source conductive region, the source conductive region including a first connection portion and a second connection portion, the second portion of the source conductive region being disposed between the gate conductive region and the first portion of the source conductive region; a first insulating region disposed between the source conductive region and a sidewall of the trench; and a second insulating region disposed between the source conductive region and the gate conductive region, and wherein the source conductive region is configured such that a first width of the first insulating region between each of the sidewalls of the trench and the first portion of the source conductive region is greater than the second width of the first insulating region between each of the sidewalls of the trench and the source conductive region a second width between the portions, and wherein the height of the second portion is between 0.05 [mu] m and 1 / 5 of the height of the first portion of the source conductive region.

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor device and a method of manufacturing a power semiconductor device, and in particular, but not exclusively, to a shielded gate trench (SGT) metal oxide semiconductor field effect transistor (MOSFET). Background Art

[0002] Trench metal oxide semiconductor field effect transistors (MOSFETs) are well known and used in many applications. In a trench MOSFET, current is conducted vertically from one surface of the MOSFET to the other surface of the MOSFET.

[0003] Factors that affect the efficiency with which a MOSFET switches between an on state (in which current is conducted vertically) and an off state (in which no current is conducted) include the charge derived from the intrinsic capacitance of the MOSFET between the gate conduction region and the drain region of the MOSFET. In order to improve the switching efficiency of a MOSFET, it is desirable to produce a MOSFET with reduced charge between the gate conduction region and the drain or collector region. Summary of the invention

[0004] Various aspects and preferred features are set out in the appended claims.

[0005] According to a first aspect of the present disclosure, there is provided a semiconductor power device, the semiconductor power device comprising an active region, the active region comprising:

[0006] a drift region of a first conductivity type;

[0007] a body region of a second conductivity type, the body region being disposed above the drift region, wherein the second conductivity type is opposite to the first conductivity type;

[0008] A trench, the trench being in contact with the body region and the drift region, the trench comprising:

[0009] a gate conductive region;

[0010] a source conductive region, the source conductive region comprising a first connecting portion and a second connecting portion, the second portion of the source conductive region being arranged between the gate conductive region and the first portion of the source conductive region; and

[0011] a first insulating region, the first insulating region being arranged between the source conductive region and a sidewall of the trench;

[0012] a second insulating region, the second insulating region being arranged between the source conductive region and the gate conductive region; and

[0013] The source conductive region is configured such that a first width of the first insulating region between each of the side walls of the trench and the first portion of the source conductive region is greater than a second width of the first insulating region between each of the side walls of the trench and the second portion of the source conductive region, and wherein a height of the second portion is between 0.05 μm and 1 / 5 of the height of the first portion of the source conductive region.

[0014] As described above, by providing the source conductive region with the first connection portion and the second connection portion, the charge between the gate conductive region and the drain region of the device can be reduced. This can improve the switching efficiency and performance of the device.

[0015] The source conductive region may be configured such that the second portion of the source conductive region extends in a direction across the sidewall of the trench. The source conductive region may be configured such that the first portion of the source conductive region extends in a direction parallel to (e.g., substantially parallel to) the sidewall of the trench.

[0016] The width of the second portion of the source conductive region may be between 0.3 μm and 4.9 μm.

[0017] A height of the first portion of the source conduction region may be between 0.1 μm and 10 μm.

[0018] The width of the first portion of the source conductive region may be between 0.05 μm and 1 μm.

[0019] A second width of the first insulating region between each of the sidewalls of the trench and the second portion of the source conductive region may be between 5% and 95% of the first width.

[0020] A first width of the first insulating region between each of the sidewalls of the trench and the first portion of the source conductive region may be between 0.1 μm and 2 μm.

[0021] The source conductive region may be configured such that the second width is uniform along the height of the second portion of the source conductive region or varies along the height of the second portion of the source conductive region.

[0022] A shape of the second portion of the source conductive region may include at least one of: a quadrilateral shape and / or a circular shape.

[0023] The semiconductor device may include a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT).

[0024] According to a second aspect of the present disclosure, there is provided a method for manufacturing an active region of a semiconductor power device, the method comprising:

[0025] forming a trench in the semiconductor region;

[0026] forming a first insulating region in the trench;

[0027] forming a source conductive region in the trench so that the first insulating region is arranged between the source conductive region and a sidewall of the trench, the source conductive region comprising a first connecting portion and a second connecting portion, wherein the source conductive region is formed so that a first width of the first insulating region between each of the sidewalls of the trench and the first portion of the source conductive region is greater than a second width of the first insulating region between each of the sidewalls of the trench and the second portion of the source conductive region, and wherein a height of the second portion is between 0.05 μm and 1 / 5 of a height of the first portion of the source conductive region;

[0028] forming a second insulating region on the second portion of the source conduction region; and

[0029] A gate conductive region is formed in the trench such that the second portion of the source conductive region is arranged between the gate conductive region and the first portion of the source conductive region.

[0030] Forming the first insulating region in the trench may include depositing an insulating material layer on the semiconductor region and on inner walls of the trench.

[0031] Forming the source conductive region in the trench may include forming the first portion of the source conductive region. Forming the first portion of the source conductive region may include:

[0032] Depositing a conductive material layer on the insulating material layer, and partially removing the conductive material layer so that a height of the conductive material layer is smaller than a height of the groove;

[0033] partially removing the insulating material layer to expose a portion of the conductive material layer; and

[0034] The exposed portion of the conductive material layer is removed to form a cavity or recess in an upper portion of the trench.

[0035] Forming the source conductive region in the trench may include forming the second portion of the source conductive region. Forming the second portion of the source conductive region may include:

[0036] depositing the layer of conductive material in the cavity or recess formed in the upper portion of the trench, the layer of conductive material connected to the first portion of the source conductive region;

[0037] The conductive material layer is partially removed to form the second portion of the source conductive region.

[0038] According to a third aspect of the present disclosure, there is provided a method for manufacturing a semiconductor power device, the method comprising:

[0039] An active region of a semiconductor power device according to the second aspect is manufactured.

[0040] The device and manufacturing method disclosed herein have one or more of the following advantages over the prior art devices:

[0041] - The device may have improved switching efficiency and performance, for example due to the

[0042] Reduction of inter-charge;

[0043] -Can reduce the gate bounce effect of the device;

[0044] - The manufacturing steps may be compatible with existing MOSFET and / or IGBT manufacturing processes and / or may be performed using materials and processing equipment commonly found in MOSFET and / or IGBT manufacturing plants. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Some embodiments of the present disclosure will now be described, by way of example only, and with reference to the accompanying drawings, in which:

[0046] Figure 1 schematically shows a cross section of an active region of a semiconductor device;

[0047] Figure 2 schematically shows a cross section of an active region of a semiconductor device according to an embodiment of the present disclosure;

[0048] Figure 3 Schematically shows Figure 2 An exemplary trench shield portion of a device;

[0049] Figures 4 to 6 Each schematically shows Figure 2 or Figure 3 An exemplary shape of a portion of a trench shield; and

[0050] Figure 7 The steps of a method for manufacturing an active region of a semiconductor power device according to an embodiment of the present disclosure are shown. DETAILED DESCRIPTION

[0051] Figure 1 A cross section of an active region 105 of a semiconductor device 100 is schematically shown. Figure 1 The active region 105 shown can be considered as a unit cell, which can be repeated thousands of times in the device 100. In the examples described herein, the device is a silicon-based shielded gate trench MOSFET. However, it should be understood that the device can include one or more alternative semiconductor materials. For example, the device can alternatively be based on silicon carbide (SiC) or gallium nitride (GaN).

[0052] The active region 105 includes a drift region 110 of the first conductivity type. Figure 1 In the illustrated embodiment, the drift region 110 includes an n-type doped semiconductor material. The n-dopant concentration of the drift region 110 may be between about 5×10 14 cm -3 With 5×10 17 cm -3 The drift region 110 may also be referred to as an n-drift region or an n-type voltage sustaining region. The drift region 110 is formed on or above a semiconductor substrate. In this example, the drift region 110 includes one or more epitaxial layers.

[0053] The substrate may include an n-type doped semiconductor material, such as n + The n-dopant concentration of the silicon substrate may be greater than about 5×10 18 cm -3 The substrate is conductive and serves as a drain region 115. The height of the substrate may be between about 40 μm and about 100 μm. A drain contact 115a may be arranged on a lower side of the substrate (eg, a side of the substrate opposite to the drift region 110). The drain contact 115a may include a conductive material, such as a metal material.

[0054] The active region 105 includes a body region 120 of a second conductivity type. The second conductivity type is opposite to the first conductivity type. Figure 1 In the illustrated embodiment, the body region 120 includes a p-type semiconductor material. The body region 120 is arranged on or above the drift region 110 .

[0055] The active region 105 includes a trench 125. The trench 125 contacts the body region 120 and the drift region 110. For example, the body region 120 is disposed on either side of an upper portion of the trench 125. The drift region 110 is disposed on either side of a lower portion of the trench 125 and is located between the trench 125 and the substrate (e.g., the drain region 115).

[0056] The trench 125 includes a source conductive region. In the following description, the source conductive region is referred to as a trench shield 130 .

[0057] The trench 125 includes a gate conductive region 135. The height of the body region 120 may be less than the height of the gate conductive region 135. This may allow the gate conductive region 135 to provide switching along the entire length of the body region 120.

[0058] The trench 125 includes a first insulating region 140a. The first insulating region is disposed between the sidewalls of the trench 125 and between the trench shields 130. For example, the trench shield insulating region 140a may be disposed between a lower portion of the sidewalls of the trench 125 and the trench shield 130 and below the trench shield 130. The first insulating region 140a may also be referred to as a trench shield insulating region 140a.

[0059] The trench 125 includes a second insulating region 140b. The second insulating region 140b is disposed between the trench shield 130 and the gate conductive region 135. The second insulating region 140b may also be referred to as an inter-polysilicon oxide region 140b.

[0060] The trench 125 includes a third insulating region 140c. The third insulating region 140c is arranged between the sidewall of the trench 125 and the gate conductive region 135. For example, the third insulating region 140c may be arranged between the upper portion of the sidewall of the trench 125 and the gate conductive region 135 and on or above the gate conductive region 135. The third insulating region 140c may also be referred to as a gate oxide region 140c.

[0061] The device 100 (eg, active region 105) may include a fourth insulating region 140d. The fourth insulating region 140d is disposed above or on the gate conductive region 135. For example, the fourth insulating region 140d may be disposed on an upper portion of the gate oxide region 140c. The fourth insulating region may also be referred to as an interlayer dielectric layer 140d.

[0062] The trench shield 130 and the gate conductive region 135 can each be formed of a conductive material such as a metal or a doped semiconductor material. For example, the doped semiconductor material can include doped polysilicon. The metal material can include a rare metal material such as tungsten. The trench shield 130 and the gate conductive region 135 can both be formed of the same doped semiconductor material. Alternatively, the trench shield 130 can be formed of a doped semiconductor material, and the gate conductive region 135 can be formed of a metal material.

[0063] The device 100 includes a source contact region, which in this example is n + Source contact region 145. + The source contact region 145 is arranged above the body region 120 and on either side of the trench 125 and the gate conductive region 135. +The source contact region 145 is arranged above the body region 120 and on either side of the gate oxide region 140c. During operation, by applying a positive voltage to the gate conductive region 135, the gate oxide region 140c is electrically conductive. + A conductive channel is formed between the source contact region 145 and the drift region 110 .

[0064] The body region 120 includes a contact region, which in this example is a p + Contact area 150. p + The contact region 150 is formed below a contact opening or recess 152 formed on either side of the trench 125 and the gate conductive region 135 .

[0065] The device 100 may also include a source contact 154. A first portion 154a of the source contact 154 may extend into each contact opening or recess 152. The first portion 154a of the source contact may be arranged to contact the n + Source contact 145 region and p + The first portion 154a of the source contact 154 may include a conductive material, such as a metal material. The metal material may include tungsten, titanium, or a combination thereof, such as a stack of at least one layer of tungsten and at least one layer of titanium. The second portion 154b of the source contact 154 is disposed on the interlayer dielectric layer 140d. The second portion 154b of the source contact 154 may include a conductive material, such as a metal material. The metal material may include aluminum, etc.

[0066] The width of the gate oxide region 140c between the gate conductive region 135 and each of the sidewalls of the trench 125 is smaller than the width of the trench shield insulating region 140a between the trench screen 130 and each of the sidewalls of the trench 125. The relatively small width of the gate oxide region 140c between the gate conductive region 135 and each of the sidewalls of the trench 125 allows the gate conductive region 135 to act as a gate when a small positive voltage of about 5V to 10V is applied to the gate conductive region 135, for example. The width of the gate oxide region 140c may be selected so that, for example, breakdown of the gate oxide region 140c is prevented when a voltage is applied to the gate conductive region 135. For example, the width of the gate oxide region 140c may be selected so that the gate oxide region 140c withstands a voltage of about 20V applied to the gate conductive region 135.

[0067] The width of the trench shield insulating region 140a between the trench shield 130 and each of the sidewalls of the trench 125 is selected so as to prevent breakdown of the trench shield insulating region 140a, for example, when a voltage is applied to the drain region 115 and the trench shield 130. For example, during operation, the trench shield 130 and the source contact 154 are at a source potential. Since the voltage that can be applied to the drain region 115 and the trench shield 130 is greater than the voltage that can be applied to the gate conductive region 135, the width of the trench shield insulating region 140a between the trench shield 130 and each of the sidewalls of the trench 125 is greater than the width of the gate oxide region 140c between the gate conductive region 135 and each of the sidewalls of the trench 125. For example, the voltage that can be applied to the drain region 115 and the trench shield 130 can be in the range of approximately 100V to 200V.

[0068] During operation, the charge Q between the gate conductive region 135 and the drain region 115 gd This charge can be derived from the intrinsic capacitance between the gate conductive region 135 and the drain region 115 and has two components, namely, Q gd1 and Q gd2 , they are in Figure 1 shown in . first component Q gd1 It can be regarded as the charge generated due to the capacitance between the gate conductive region 135 and the drift region 110 across the gate oxide region 140c. gd2 can be considered as the charge generated due to the capacitance between the gate conductive region 135 and the drift region 110 across the inter-polysilicon oxide region 140b and the trench shield insulating region 140a. The inventors have found that Q gd2 plays an important role, and for example, in order to improve the switching efficiency of the device, it is desirable to reduce Q gd2 The value of .

[0069] Figure 1 The capacitance between the gate conductive region 135 and the trench shield 130 and the capacitance between the gate conductive region 135 and the trench shield 130 are also shown. + The charge Q generated by the capacitance between the source region 145 gs This charge includes a first component Q gs1 and the second component Q gs2 , the first component and the second component are both in Figure 1 and Figure 2 shown in . first component Q gs1 It can be considered that the gate conductive region 135 and n + The second component Q gs2The charge may be considered to be generated due to the capacitance between the gate conductive region 135 and the trench shield 130 across the inter-polysilicon oxide region 140 b .

[0070] Figure 2 The cross section of the active region 205 of the semiconductor device 200 according to an embodiment of the present disclosure is schematically shown. Figure 2 The semiconductor device 200 shown may include Figure 1 Any features of the semiconductor device 100 shown are different. Only the differences will be described below.

[0071] exist Figure 2 In the illustrated embodiment, the trench shield 230 includes a first portion 230a and a second portion 230b. The first portion 230a of the trench shield 230 is connected to the second portion 230b of the trench shield 230. The first portion 230a of the trench shield 230 may also be referred to as a columnar portion. The second portion 230b of the trench shield 230 may also be referred to as a cap portion or a rod. The trench shield 230 is arranged so that the second portion 230b of the trench shield 230 is arranged between the first portion 230a of the trench shield 230 and the gate conductive region 235. The trench shield 230 is configured so that the first width W1 of the trench shield insulating region 240a located between each of the sidewalls of the trench 225 and the first portion 230a of the trench shield 230 is greater than the second width W2 of the trench shield insulating region 240a located between each of the sidewalls of the trench 225 and the second portion 230b of the trench shield 230. For example, the first width W1 may be between about 0.1 μm and 2 μm. The second width W2 may be between about 5% and 95% of the first width W1.

[0072] Figure 3 200. An exemplary trench shield 230 that may be part of the device 200 is schematically shown in FIG. The height H2 of the second portion 230b is between 0.05 μm and 1 / 5 of the height H1 of the first portion 230a of the trench shield 230. For example, the trench shield 230 may be considered to have a "T" shape. The height H2 of the second portion 230b of the trench shield 230 and the height H1 of the first portion 230a are in the range of 0.05 μm and 1 / 5 of the height H1 of the first portion 230a. Figure 3 Shown in.

[0073] As described above, by providing the trench shield portion 230 having the second portion 230 b, the area of ​​the capacitor formed between the gate conductive region 235 and the drift region 210 across the inter-polysilicon oxide region 240 b and the trench shield insulating region 240 a can be reduced. Since the capacitance of the capacitor is proportional to the area, the charge Q between the gate conductive region 235 and the drain region 215 is gd The second component Q of gd2In this way, the second portion 230b of the trench shield 230 can be regarded as shielding the drain region 215 from the gate conductive region 235. In other words, the second portion 230b of the trench 230 can be configured to reduce or prevent the formation of electric field lines between the gate conductive region 235 and the drain region 215. This can reduce the charge Q between the gate conductive region 235 and the drain region 215. gd The second component Q of gd2 This can reduce the total charge Q between the gate conductive region 235 and the drain region 215. gd This in turn can improve the quality factor, which is equal to the product of the resistance of the device 200 and the total charge between the gate conductive region 235 and the drain region 215. The quality factor represents the conduction loss and switching loss of the device 200. For example, the inventors have found that, relative to the Figure 1 The device 100 shown determines the total charge Q between the gate conductive region 135 and the drain region 115 gd ,against Figure 2 The device 200 shown determines the total charge Q between the gate conductive region 235 and the drain region 215 gd The reduction is about 50%. Figure 2 The device 200 shown determines the quality factor relative to the Figure 1 The quality factor determined by the device 100 shown is reduced by approximately 40%. The reduction in the quality factor represents a decrease relative to Figure 1 The device 100 shown, Figure 2 The illustrated apparatus 200 improves switching efficiency and reduces energy losses.

[0074] exist Figure 2 In the device 200 shown, for example, relative to Figure 1 The capacitor area between the gate conductive region 135 and the trench shield 130 of the device 100 shown in the figure is increased, and the capacitor area between the gate conductive region 235 and the trench shield 230 is increased. Figure 2 The capacitance between the gate conductive region 235 and the trench shield 230 of the device 200 shown in FIG. + The charge Q generated by the capacitance between the source region 245 gs The second component Q of gs2 Relative to Figure 1 The same charge Q of the device 100 shown gs The second component Q of gs2 In this way, Figure 2 The device 200 shown in FIG. 2 determines the charge Q between the gate conductive region 235 and the drain region 215. gd The second component Q of gd2Due to the capacitance between the gate conductive region 235 and the trench shield portion 230 and due to the capacitance between the gate conductive region 235 and the n + The charge Q generated by the capacitance between the source region 245 gs The second component Q of gs2 The ratio Q gd2 / Q gs2 Relative to targeting Figure 1 The same ratio determined by the device 100 shown is reduced. Figure 2 The device 200 shown determines the total charge Q between the gate conductive region 235 and the drain region 215 gd Due to the capacitance between the gate conductive region 235 and the trench shield 230 and due to the capacitance between the gate conductive region 235 and the trench shield 230 + The total charge Q generated by the capacitance between the source region 245 gs The ratio Q gd / Q gs Relative to targeting Figure 1 The same ratio determined for the device 100 shown is reduced by approximately 50%. This reduction in this ratio can result in a reduction in gate bounce effects. Gate bounce effects can be caused by a capacitively coupled voltage at the gate conduction region of the device exceeding the threshold voltage of the device. This voltage can cause the formation of n + The conductive channel between the source contact region and the drift region can prevent the device from being turned off. The capacitively coupled voltage at the gate conductive region of the device may be generated due to the large increase in voltage at the drain region during the switching operation of the device. By reducing the charge Q between the gate conductive region 235 and the drain region 215 gd The second component Q of gd2 and / or increase the capacitance between the gate conductive region 235 and the trench shield portion 230 and the capacitance between the gate conductive region 235 and the trench shield portion 230 as described above. + The charge Q generated by the capacitance between the source region 245 gs The second component Q of gd2 , the capacitive coupling voltage at the gate conductive region 235 can be reduced or suppressed from increasing as the voltage at the drain region 215 increases.

[0075] In this way, relative to Figure 1 The device 100 shown, Figure 2 The illustrated apparatus 200 may be considered to have improved overall efficiency.

[0076] By configuring the trench shield 235 such that the height H2 of the second portion 230b is between 0.05 μm and 1 / 5 of the height H1 of the first portion 230a of the trench shield 230, the influence of the second portion 230b of the trench shield 230, such as the influence on the breakdown voltage of the device 200, can be reduced or prevented. The breakdown voltage of the device 200 can be understood as the voltage that can be applied between the drain region 215 and the n + The maximum voltage between the source region 245 (and the trench shield 230) without causing damage to the device 200. Thus, as described above, this configuration of the trench shield 230 can be considered to allow for improved device performance while reducing or preventing any other effects on the device 200 that may be caused by the second portion 230b of the trench shield 230.

[0077] Reference again Figure 2 and Figure 3 , the trench shield 230 can be configured such that the second portion 230b of the trench shield 230 extends in a direction across the sidewalls of the trench 225, and the first portion 230a of the trench shield 230 extends in a direction parallel to (e.g., substantially parallel to) the sidewalls of the trench 225. For example, the first portion 230a of the trench shield 230 can extend in a first direction or x-direction. The first direction or x-direction can also be understood as a direction from the body region 220 to the drift region 210 or the substrate (e.g., the drain region 215), and / or a direction parallel to the sidewalls of the trench 225. The second portion 230b of the trench shield 230 can extend in a second direction or y-direction. The second direction or y-direction is perpendicular to (e.g., substantially perpendicular to) the first direction or x-direction. The second direction or y-direction can also be understood as a lateral direction of the device 200. The first direction or x-direction and the second direction or y-direction are formed by Figure 3 The coordinate system in .

[0078] The width W3 of the second portion 230 b of the trench shield 230 may be between about 0.3 μm and about 4.9 μm.

[0079] A height H1 of the first portion 230 a of the trench shield 230 may be between about 0.1 μm and about 10 μm. A width W4 of the first portion 230 a of the trench shield 230 may be between about 0.05 μm and about 1 μm.

[0080] refer to Figure 2, the first width W1 of the trench shield insulating region 240a between each of the sidewalls of the trench 225 and the first portion 230a of the trench shield 230 can be substantially uniform along the height H1 of the first portion 230a of the trench shield 230. This can be advantageous in adjusting the doping profile of the drift region 210, for example, to achieve one or more desired device properties, such as a desired breakdown voltage and / or on-state resistance. In examples where the first width W1 of the trench shield insulating region 240a varies, it may be necessary to adjust the doping profile of the drift region 210 to achieve the desired device properties.

[0081] The second portion 230 b of the trench shield 230 may be formed in various shapes. Figures 4 to 6 Each schematically shows Figure 2 or Figure 3 An exemplary shape of the second portion 230 b of the trench shield 230 is shown.

[0082] exist Figure 4 In the example shown, the second portion 230 b of the trench shield 230 includes a quadrilateral shape, such as a rectangular shape. As a result, the second width of the trench shield insulating region 240 a between each of the sidewalls of the trench 230 and the second portion 230 b may be uniform along a height H2 of the second portion 230 b of the trench shield 230 .

[0083] exist Figure 5 In the example shown, the second portion 230b of the trench shield 230 includes a rounded shape, such as a concave-convex shape or a crescent shape. As a result, the second width of the trench shield insulating region 240a between each of the sidewalls of the trench 230 and the second portion 230b may vary along the height H2 of the second portion 230b of the trench shield 230. It should be understood that in other embodiments, the second portion of the trench shield may include a flat-convex shape, a bowl-like shape, or other rounded shapes.

[0084] exist Figure 6 In the example shown, the second portion 230 b of the trench shield 230 includes a quadrilateral shape, such as a trapezoidal shape. Thus, the second width of the trench shield insulating region 240 a between the sidewall of the trench 230 and the second portion 230 b may vary along a height H2 of the second portion 230 b of the trench shield 230 .

[0085] It should be understood that the second portion 230b of the trench shield 230 is not limited to including Figures 4 to 6 For example, in other embodiments, the second portion of the trench shield can have a different shape than described herein.

[0086] Figure 7(a) to Figure 7 (j) shows the steps of a method of manufacturing an active region of a semiconductor power device according to an embodiment of the present disclosure (such as the active region 205 of the device 200 described above). Many features and Figure 2 , and therefore have the same reference numerals. It should be understood that Figure 7 The steps shown may show a subset of all the steps of manufacturing the device, and the method may also include being in Figure 7 Additional steps before or after the step. Figure 7 The steps of fabricating an active area having one trench 225 are shown, but it will be appreciated that the method may be used to fabricate more than one trench.

[0087] In step (a), the method includes forming a trench 225 in a semiconductor region 300. The semiconductor region 300 may include a drift region 210. As described below, a body region 220 may be formed in the semiconductor region 300. The semiconductor region includes one or more epitaxial layers that have been formed on a substrate (e.g., a drain region 215). The trench 225 may be formed by depositing a mask material layer 305 on the semiconductor region 300. The mask material may include an oxide material such as TEOS (tetraethyl orthosilicate), a nitride material (e.g., Si3N4), or a combination thereof, such as a stack of a TEOS layer and a nitride material layer. The mask material layer 305 may be patterned, for example, using a material removal process such as a dry etching process or a wet etching process. The patterned layer of the mask material may act as a hard mask or a resist layer to define the trench 225 during a material removal process such as a dry etching process, thereby forming the trench 225 in the semiconductor region 300.

[0088] After forming the trench 225, the mask material layer may be removed, for example, using a material removal process (such as a wet etching process). The trench 225 may include a height H3 between about 0.1 μm and about 20 μm. The trench 225 may include a width W5 between about 0.3 μm and about 5 μm. The sidewalls may be formed at an angle α relative to the surface of the substrate (such as the drain region 215). The angle may be between about 80 degrees and about 90 degrees.

[0089] In steps (b) to (d), the method includes forming a trench shielding insulating region 240 a in the trench 225 .

[0090] In step (b), a first insulating material layer 310 is deposited on the inner wall of the trench 225 and on the semiconductor region 300 (such as the upper surface of the semiconductor region), for example, using a deposition process. The inner wall of the trench 225 includes the sidewall and the lower inner wall of the trench 225. The first insulating material layer 310 can serve as a liner for the trench 225. The insulating material may include an oxide material, such as silicon dioxide (SiO2). In other embodiments, the insulating material may include an oxide material having a dielectric constant higher than that of SiO2. For example, in such other embodiments, the oxide material may include hafnium oxide (HfO2).

[0091] In steps (c) to (f), the method includes forming a trench shield 230. For example, in steps (c) to (e), the method includes forming a first portion 230a of the trench shield 230. The first portion 230a of the trench shield 230 may be formed by depositing a conductive material layer 315 on the first insulating material layer 310 in the trench 225, for example, using a deposition process. The method includes partially removing the conductive material layer 315 so that the height of the conductive material layer 315 is less than the height H3 of the trench 225. The conductive material layer 315 may be partially removed by using a material removal process, such as a dry etching process. The conductive material may include a doped semiconductor material, such as polysilicon.

[0092] In step (d), the method includes partially removing the first insulating material layer 310 from the upper portion 320 of the trench 225. The upper portion of the trench 225 may also be referred to as the open end portion of the trench. A portion 310a of the first insulating material layer 310 may remain in the upper portion 320 of the trench 225. The remaining portion of the first insulating material layer 310 may have a thickness less than the thickness of the first insulating material layer 310 in the lower portion of the trench 225. The first insulating material layer 310 located in the lower portion of the trench 225 forms a trench shielding insulating region 240a.

[0093] The first insulating material layer 310 may be partially removed, for example, using a material removal process such as a wet etching process, to expose a portion of the conductive material layer 315. The exposed portion of the conductive material layer 315 may extend or protrude from the remaining portion of the insulating material layer 310 located in the lower portion of the trench 225. Partially removing the first insulating material layer 310 from the upper portion 320 of the trench 225 may include shaping of a surface 310b of the remaining portion of the first insulating material layer 310 in the trench 225. The shaped surface 310b of the remaining portion of the first insulating material layer 310 in the trench 225 may facilitate the formation and / or shaping of the second portion 230b of the trench shield 230.

[0094] In step (e), the method includes removing the exposed portion of the conductive material layer 315, for example using a material removal process (such as a wet etching process), to form a cavity or recess 325 in the upper portion 320 of the trench 215, such as Figure 7 (e) The conductive material layer 315 remaining in the trench 225 forms the first portion 230 a of the trench shield 230 .

[0095] In step (f), the method includes forming the second portion 230b of the trench shield 230. The method includes depositing a conductive material layer 315 into the cavity or recess 325, for example, using a deposition process. This can facilitate the manufacture of the device 200. The conductive material layer 315 deposited in this step is connected to the same conductive material 315 deposited and processed in the above steps (c) to (e) to form the trench shield 230 in the trench 225. After depositing the conductive material layer 315 into the cavity or recess 325, the conductive material layer 315 can be partially removed, for example, using a material removal process (such as a dry etching process) to form the second portion 230b of the trench shield 230. For example, the remaining portion of the conductive material layer 315 can form the second portion 230b of the trench shield.

[0096] In steps (g) and (h), the method includes forming an inter-polysilicon oxide region 240b and a gate conductive region 235. For example, in step (g), the method includes depositing a second insulating material layer 330 on the second portion 230b of the trench shield 230, for example using a deposition process. The insulating material may include an oxide material, such as silicon dioxide (SiO2). The second insulating material layer 330 may be deposited to fill the upper portion 320 of the trench 225.

[0097] In step (h), the method includes partially removing the second insulating material layer 330 so that a portion 330a of the second insulating material layer 330 remains on the second portion 230b of the trench shield 230. The portion 330a of the second insulating material layer forms an inter-polysilicon oxide region 240b. The method may also include removing a portion 310a of the first insulating material layer 310 from the upper portions of both sidewalls of the trench 225 and the upper surface of the semiconductor region 300. The second insulating material layer 330 and the portion 310a of the first insulating material layer 310 may be removed by using a material removal process (e.g., including a polishing process and a dry etching or wet etching process). The inter-polysilicon oxide region 240b and the trench shield insulating region 240a may define a surface on which a gate conductive region 235 may be formed.

[0098] The method includes forming a third insulating material layer 335 along the upper portion of the sidewalls of the trench 225 and the upper surface of the semiconductor region 300, for example, by oxidizing the semiconductor region 300. For example, the upper portion of the sidewalls of the trench 225 can be exposed to air. The upper surface of the semiconductor region 300 can also be exposed to air. A thermal oxidation process can be used to form a portion of the gate oxide region 240c on the exposed upper portion of the sidewalls of the trench 225 and the exposed upper surface of the semiconductor region 300. The thermal oxidation process can include a dry oxidation process (for example, in a pure oxidation atmosphere), a wet oxidation process (such as hydrothermal treatment), or a combination of a dry oxidation process and a wet oxidation process. The third insulating material layer 335 can define a portion of the gate oxide region 240c.

[0099] The method includes depositing a conductive material layer on a surface defined by the trench shield insulating region 240a and the inter-polysilicon oxide region 240b, for example, using a deposition process, to form a gate conductive region 235. The conductive material may be the same as or different from the conductive material of the trench shield 230. The gate conductive region 235 may be planarized using a polishing process or a dry etching process.

[0100] In step (i), the method includes forming the body region 220. The method includes forming a fourth insulating material layer 340 on the gate conductive region 235 and the semiconductor region 300, for example to complete the gate oxide region 240c. The fourth insulating material layer 340 can be formed on the upper surface of the gate conductive region 235 and the semiconductor region, for example, by oxidizing the semiconductor region 300 and the gate conductive region 235. The fourth insulating material layer 340 can be regarded as a part of the gate oxide region 240c.

[0101] The method includes implanting a p-type dopant (eg, boron) into the semiconductor region 300 below the fourth insulating material layer 340 to form a body region 220. The p-type dopant concentration of the body region 220 may be between about 10 15 cm -3 With about 10 18 cm -3 between.

[0102] The method includes implanting n-type dopants (eg, phosphorus or arsenic) above the body region 220 and below the fourth insulating material layer 340 to form an n + Source contact region 245. + The n-dopant concentration of the source contact region 245 may be greater than 5×10 18 cm -3 .

[0103] The method includes depositing a fifth insulating material layer on the fourth insulating material layer 340 using a deposition process, for example. The fifth insulating material layer may include an oxide material, such as TEOS (tetraethyl orthosilicate). The fifth insulating material layer forms an interlayer dielectric layer 240d.

[0104] The method includes forming contact openings or recesses 252, for example, on either side of the gate conductive region 235, using a material removal process. For example, the contact openings or recesses 252 may be formed by etching through the gate conductive region 235. + The source contact region 245 extends to the body region 220 to form a contact opening or recess 252. A p-type dopant (eg, boron or boron difluoride) may be implanted under each contact opening or recess 252 to form a p-type dopant. + Contact area 250. p + The p-dopant concentration of the contact region 250 may be greater than 5×10 18 cm -3 .

[0105] In step (j), the method includes forming a source contact 254. For example, the source contact 254 may be formed by depositing a second conductive material layer into each contact opening or recess, for example, to form a first portion 254a of the source contact 254. The method may include depositing a third conductive material layer on the interlayer dielectric layer 240d, for example, to form a second portion 254b of the source contact 254.

[0106] The dry etching process may include a reactive ion etching process or another dry etching process.

[0107] The above-mentioned deposition process may include a chemical vapor deposition process or another deposition process.

[0108] The polishing process includes a chemical mechanical polishing process or another polishing process.

[0109] It should be understood that the term "width" as used herein encompasses the lateral direction (e.g. Figure 3 The size, dimension, or extension of a part or feature in the y-direction (in the y direction).

[0110] It should be understood that the term "height" as used herein encompasses the longitudinal direction (e.g. Figure 3 The size, dimension, or extension of a part or feature in the x-direction and / or in a direction perpendicular to the lateral direction.

[0111] Those skilled in the art will appreciate that in the foregoing description and the appended claims, positional terms such as "above," "overlapping," "below," "lateral," and the like are set forth with reference to conceptual illustrations of the device (such as those showing standard cross-sectional perspective views and those shown in the accompanying drawings). These terms are used for ease of reference and are not intended to be limiting. Therefore, these terms should be understood to refer to the device in the orientation shown in the drawings.

[0112] It should be understood that all of the doping polarities described above may be reversed and the resulting device still conform to embodiments of the present invention.

[0113] Although the above description relates to a device including a MOSFET, it will be appreciated that in other embodiments, the device may include an insulated gate bipolar transistor (IGBT). Any of the features described above may also apply to an IGBT. In such other embodiments, the term "drain region" may be replaced with the term "collector region", and the term "source" used above may be replaced with the term "emitter".

[0114] In this document, dimensions are provided as indicative examples only and are not limiting.

[0115] It should be understood that Figures 1 to 7 are schematic diagrams of some embodiments of the present disclosure and may not be drawn to scale.

[0116] Although specific embodiments have been described above, the claims are not limited to these embodiments. In view of this disclosure, those skilled in the art will be able to make modifications and substitutions, which are deemed to fall within the scope of the appended claims. Each feature disclosed may be incorporated into any described embodiment alone or in appropriate combination with other features disclosed herein.

[0117] Reference Number 135 gate conductive area

[0118] 100 device 140a trench shielding insulation region

[0119] 105 active region 140b inter-polysilicon oxide region

[0120] 110 drift region 140c gate oxide region

[0121] 115 drain region 140d interlayer dielectric layer

[0122] 120 body area 145n + Source Region

[0123] 125 groove 150p + Contact area 150

[0124] 130 The trench shield portion 152 contacts the opening or groove

[0125] 154 source contact 235 gate conductive region

[0126] 154a First portion of source contact 240a Trench shielding isolation region 154b Second portion of source contact 240b Inter-polysilicon oxide region

[0127] 240c Gate oxide region

[0128] 240d interlayer dielectric layer

[0129] 200 device 245n + Source Region 205 active area 250p + Contact area 150

[0130] 210 drift region 252 contact opening or groove

[0131] 215 drain region 254 source contact

[0132] 220 body region 254a first portion of source contact 225 trench 254b second portion of source contact 230 groove shield

[0133] 230a The first portion of the trench shield

[0134] W1 first width 300 semiconductor region W2 second width 305 mask material layer W3 The width of the second portion of the trench shield 310 The first insulating material layer W4 Width of the first portion of the trench shield 310a Portion of the first insulating material layer The width of the W5 groove is 310b.

[0135] H1 Height of the first portion of the trench shield 315 Conductive material layer H2 The height of the second portion of the trench shield 320 The upper portion of the trench H3 Groove height 325 cavity or groove The angle of the sidewall of the α trench is 330° and the second insulating material layer is

[0136] 330a A portion of the second insulating material layer

[0137] 335 third insulating material layer 230b the second portion 340 of the trench shield is a fourth insulating material layer.

Claims

1. A semiconductor power device (200), comprising an active region, wherein the active region (205) comprises: A drift region (210) of a first conductivity type; a body region (220) of a second conductivity type, the body region being disposed above the drift region (210), wherein the second conductivity type is opposite to the first conductivity type; A trench (225), the trench being in contact with the body region (220) and the drift region (210), the trench (225) comprising: a gate conductive region (235); A source conductive region (230), the source conductive region comprising a first connecting portion and a second connecting portion (230a, 230b), the second portion (230b) of the source conductive region (230) being arranged between the gate conductive region (235) and the first portion (230a) of the source conductive region (230); A first insulating region (240a), the first insulating region being arranged between the source conductive region (230) and a side wall of the trench (225); a second insulating region (240b), the second insulating region being arranged between the source conductive region (230) and the gate conductive region (235); and The source conductive region (230) is configured such that a first width (W1) between each of the side walls of the trench (225) and the first portion (230a) of the source conductive region (230) is greater than a second width (W2) between each of the side walls of the trench (225) and the second portion (230b) of the source conductive region (230), and a height (H2) of the second portion (230b) is between 0.05 μm and 1 / 5 of a height (H1) of the first portion (230a) of the source conductive region (230).

2. The semiconductor power device (200) according to claim 1, wherein the source conductive region (230) is configured such that the second portion (230b) of the source conductive region (230) extends in a direction across the side wall of the trench (225), and the first portion (230a) of the source conductive region (230) extends in a direction parallel to the side wall of the trench (225).

3. The semiconductor power device (200) according to any preceding claim, wherein a width (W3) of the second portion (230b) of the source conduction region (230) is between 0.3 μm and 4.9 μm.

4. The semiconductor power device (200) according to any preceding claim, wherein the height (H1) of the first portion (230a) of the source conduction region (230) is between 0.1 μm and 10 μm.

5. The semiconductor power device (200) according to any preceding claim, wherein a width (W4) of the first portion (230a) of the source conduction region (230) is between 0.05 μm and 1 μm.

6. The semiconductor power device (200) according to any preceding claim, wherein the second width (W2) is between 5% and 95% of the first width (W1).

7. The semiconductor power device (200) according to any preceding claim, wherein the first width (W1) is between 0.1 μm and 2 μm.

8. A semiconductor power device (200) according to any preceding claim, wherein the source conductive region (230) is configured such that the second width (W2) is uniform along the height (H2) of the second portion (230b) of the source conductive region (230), or varies along the height (H2) of the second portion (230b) of the source conductive region (230).

9. The semiconductor power device (200) according to any preceding claim, wherein a shape of the second portion (230b) of the source conduction region (230) comprises at least one of the following: a quadrilateral shape and / or a circular shape.

10. The semiconductor power device (200) of any preceding claim, wherein the semiconductor device comprises a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT).

11. A method for manufacturing an active region (205) of a semiconductor power device (200), the method comprising: forming a trench (225) in a semiconductor region (300); forming a first insulating region in the trench (225); A source conductive region (230) is formed in the trench (225), so that the first insulating region (240a) is arranged between the source conductive region (230) and the sidewall of the trench (225), and the source conductive region (230) includes a first connecting portion and a second connecting portion, wherein the source conductive region (230) is formed so that the first insulating region (240a) is connected to each of the sidewalls of the trench (225) and the sidewalls of the source conductive region (230). The first width (W1) between the first portions (230a) is greater than a second width (W2) between each of the side walls of the trench (225) of the first insulating region (240a) and the second portion (230b) of the source conductive region (230), and the height (H2) of the second portion (230b) is between 0.05 μm and 1 / 5 of the height (H1) of the first portion (230a) of the source conductive region (230); forming a second insulating region (240b) on the second portion (230b) of the source conductive region (230); and A gate conductive region (235) is formed in the trench (225) such that the second portion (230b) of the source conductive region (230) is arranged between the gate conductive region (235) and the first portion (230a) of the source conductive region (230).

12. A method for manufacturing an active area (205) of a semiconductor power device (200) according to claim 11, wherein forming the first insulating region (240a) in the trench (225) includes depositing an insulating material layer (310) on the semiconductor region (300) and on the inner wall of the trench (225).

13. The method for manufacturing an active region (205) of a semiconductor power device (200) according to claim 12, wherein forming the source conductive region (230) in the trench (225) comprises forming the first portion (230a) of the source conductive region (230), wherein forming the first portion (230a) of the source conductive region (230) comprises: Depositing a conductive material layer (315) on the insulating material layer (310), and partially removing the conductive material layer so that the height of the conductive material layer is smaller than the height of the groove (225); Partially removing the insulating material layer (310) to expose a portion of the conductive material layer; as well as The exposed portion of the conductive material layer is removed to form a cavity or recess (325) in an upper portion (320) of the trench (225).

14. The method for manufacturing an active region (205) of a semiconductor power device (200) according to claim 13, wherein forming the source conductive region (230) in the trench (225) comprises forming the second portion (230b) of the source conductive region (230), wherein forming the second portion (230b) of the source conductive region (230) comprises: depositing a layer of conductive material (315) in the cavity or recess (325) formed in the upper portion (320) of the trench (225), the layer of conductive material being connected to the first portion (230a) of the source conductive region (230); The conductive material layer is partially removed to form the second portion (230b) of the source conductive region (230).

15. A method for manufacturing a semiconductor power device (200), the method comprising: An active region (205) of a semiconductor power device (200) according to any one of claims 11 to 14 is manufactured.

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