Test data time delay deterministic transmission method of TTE integrated Ethernet

Abstract

The invention discloses a TTE integrated Ethernet test data time delay deterministic transmission method, which comprises the following steps that: a time synchronization core module is designed in a TTE protocol by utilizing an FPGA (Field Programmable Gate Array), and the module can process a received protocol control frame (PCF) to realize multi-node high-precision time synchronization; the state and other core signals are controlled by adopting a command-condition interaction method; a maximum matching algorithm combined with cut-off priority is used for generating a scheduling table, and the method comprises the eight steps of scheduling parameter input, period calculation, shortest path calculation, cut-off priority preprocessing, maximum matching sorting, message distribution, conflict detection and scheduling table loading. The FPGA is used for loading the scheduling table to the scheduling configuration module, Ethernet transmission is fused, periodic time slot distribution is carried out on links, and the stability of time synchronization and the time delay certainty of test data transmission are ensured. According to the method, the link load can be balanced on the premise of reducing the real-time data packet loss rate.

Description

Technical Field

[0001] The invention belongs to the fields of electronic engineering and computer science, and in particular relates to a time-delay deterministic transmission method for test data of a TTE-fused Ethernet. Background Art

[0002] In the current era of big data with information explosion, the reasonable collection, screening, processing and analysis of data are very important. The current transmission and processing of real-time data is a pain point in typical test scenarios, including high-precision spatiotemporal services, interconnection and interoperability, and real-time fusion perception. The premise for the smooth implementation of upper-level real-time decision-making is to ensure that key data is delivered to the decision-making center in real time. For scenarios where high-speed deterministic transmission of test data is required in test tests, there are extremely strong time requirements for the deterministic transmission of real-time data. If the time-delay deterministic transmission of real-time data cannot be guaranteed, it may cause major problems such as poor real-time decision-making or test results that do not conform to reality. How to achieve time-delay deterministic transmission of test data is one of the key issues supporting upper-level decision-making.

[0003] With the development of information technology, many data transmission protocol standards have emerged, including the commonly used industrial Ethernet, Modbus and Zigbee. However, in terms of the delay determinism of data transmission, the best method is to achieve time synchronization between the communicating parties through a time synchronization protocol. On the basis of maintaining a common time standard between the two parties, the transmission is triggered according to the schedule to achieve delay deterministic data transmission.

[0004] Time-triggered Ethernet (TTE) is a network protocol designed to meet real-time and high reliability requirements. It manages data transmission through a time-triggered mechanism to ensure predictability and determinism of communication. The protocol supports two communication modes: time-triggered and event-triggered. It can efficiently manage bandwidth, prioritize the transmission of real-time data streams, and avoid data conflicts and network congestion. This method can achieve high-precision time synchronization. As a programmable hardware logic device, FPGA has a high degree of parallel processing and hardware acceleration characteristics, which is conducive to the realization of TTE converged Ethernet.

[0005] However, there is little research on how to use FPGA to implement the TTE protocol with high time synchronization accuracy, generate a scheduling table through an efficient algorithm, and integrate it into the traditional Ethernet. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a test data delay deterministic transmission method of TTE fused Ethernet, uses FPGA to design the time synchronization core module in the TTE protocol, the module can process the received protocol control frame PCF, and realize high-precision time synchronization of multiple nodes through transparent clock update, solidification and compression algorithm, and adopts the command-condition interaction method to realize the control of state and other core signals; uses the maximum matching algorithm combined with cutoff priority to generate a scheduling table, including five steps of scheduling parameter input, shortest path calculation, cutoff priority preprocessing, maximum matching sorting and message allocation, so as to reduce the packet loss rate of real-time data and balance the link load; uses FPGA to load the scheduling table into the scheduling configuration module, integrates Ethernet transmission, and periodically allocates time slots to the link, which are protocol control frames, real-time data and non-real-time data in turn, so as to ensure the stability of time synchronization and the delay determinism of TT stream transmission.

[0007] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0008] A method for transmitting test data with time delay deterministically of TTE-fused Ethernet comprises the following steps:

[0009] Step 1: Design the time synchronization core module in accordance with the TTE protocol, process the received protocol control frame PCF, implement high-precision time synchronization of multiple nodes through transparent clock update, solidification and compression algorithms, and use the command-condition interaction method to control the status and other core signals. The specific implementation is as follows:

[0010] Design the PCF receiving module to parse the UDP data packets obtained by the network layer, extract the integration period, member group, synchronization priority, synchronization domain, PCF frame type and transparent clock field; design the PCF sending module to obtain the integration period, member group, synchronization priority, synchronization domain, PCF frame type and transparent clock field according to the core signal parameters of the current system after the sending condition is triggered, and frame it into a UDP data packet and send it to the network layer;

[0011] Design transparent clock update, solidification and compression algorithms. The transparent clock update is used to record the cumulative transmission delay update in the entire link transmission, including dynamic and static delays. The solidification algorithm is used to reorder the receiving time points and transparent clock values ​​of the PCF frames on each link to ensure that the receiving and sending order of each PCF frame are the same, and the sending and receiving intervals are equal. The compression algorithm is used to integrate the PCF frames received by the CM device from multiple SM devices, obtain the local clock difference of each SM based on the solidified time point in each PCF frame, and execute the compression algorithm to obtain a weighted and unified compression time point, which is used as the standard to correct the local clock of each device.

[0012] Design the time synchronization core module, execute the corresponding algorithm and complete the management of local state and other core signals according to the command-condition interaction method. The solidification processing module and the compression processing module execute the corresponding solidification and compression algorithms. The state control module manages the local state jump and maintains the state core signal. The timeout module detects whether the time in the current state exceeds the threshold limit and maintains the time_out core signal. The clustering detection module detects whether the number of local member groups exceeds the threshold limit and maintains the local_member core signal. The local time control module controls the local time count and jump, maintains the local_clk core signal, and the local cycle control module controls the local cycle count and jump, maintains the local_cycle core signal. The synchronous calculation module calculates the correction value of the local time according to the input parameters and maintains the clk_correct core signal.

[0013] Step 2: Generate a scheduling table using the maximum matching algorithm combined with cutoff priority, including eight steps: scheduling parameter input, cycle calculation, shortest path calculation, cutoff priority preprocessing, maximum matching sorting, message allocation, conflict detection and scheduling table loading, to reduce the packet loss rate of real-time data and balance the link load. The specific implementation is as follows:

[0014] Input message model parameters, including terminal node information, switch information, transmission link information, and parameters of all TT message information;

[0015] Cycle calculation, based on the idea of ​​TDMA time division multiple access, the TT message is allocated periodic time slots, and the matrix cycle MC and the basic cycle BC are defined. A TT message is sent at least once in an MC, and a TT message is sent at most once in a BC;

[0016] For the shortest path calculation, the Dijkstra algorithm is used to generate a shortest path tree for each message source node and determine the shortest path for each TT message;

[0017] Deadline priority preprocessing, pre-prioritizes all TT messages in order of deadline from small to large;

[0018] Maximum matching sorting, re-sorting all TT messages based on the in-and-out degrees of all nodes, defining the node with the largest out-degree as the sending node and the node with the smallest in-degree as the receiving node, and assigning priority to the TT messages of the source node and the target node consisting of the sending node and the receiving node;

[0019] Message allocation, assigning each TT message to a matrix cycle according to the pre-sorted priority;

[0020] Conflict detection: Check whether each TT message exceeds the deadline. If there is a conflict, it means that the current input message model parameters are unreasonable. The input message model parameters are readjusted. If there is no conflict, a scheduling table is generated.

[0021] Load the schedule, design the schedule configuration module, and deploy the generated schedule to the schedule configuration module.

[0022] Step 3: Use FPGA to load the scheduling table into the scheduling configuration module, integrate Ethernet transmission, and periodically allocate time slots to the link, first for protocol control frames, real-time data, and non-real-time data, to ensure the stability of time synchronization and the delay determinism of TT stream transmission. The specific implementation is as follows:

[0023] Calculate the cycle time and obtain the time required for protocol control frame transmission through the design of the time synchronization core module , the time required to transmit real-time data is obtained through the message model parameters , set the time required to transmit non-real-time data to be the same as the time required to transmit real-time data The superposition of the three parts of the transmission protocol control frame, real-time data, and non-real-time data is used as the time cycle time for transmitting information in the link. ;

[0024] Protocol control frame sending, in the first part of each time period, according to the management and control of the time synchronization core module, a protocol control frame PCF is sent;

[0025] Real-time data transmission, in the second part of each time cycle, the time synchronization core module provides local time, and according to the matching relationship between real-time data and transmission time in the schedule table, a transmission instruction is output when a specific time node is reached to guide the transmission of real-time data in the Ethernet data cache, namely, the TT time trigger flow;

[0026] Non-real-time data transmission: In the third part of each time period, non-real-time data in the Ethernet data buffer is sent, including RC rate limiting flow and BE best effort forwarding flow.

[0027] The method for transmitting test data delay deterministically of a TTE-fused Ethernet designed by the present invention is applicable to an ARTIX-7 FPGA chip of Xilinx, model XC7A200T-2FBG484I, and a PHY chip of RealtekRTL8211EG.

[0028] The beneficial effects of the present invention are:

[0029] (1) The self-designed time synchronization core module adopts a command-condition interactive signal control scheme and optimizes the previous FPGA-based time-triggered Ethernet implementation scheme, so that the time synchronization accuracy of multiple nodes can reach 50ns and has long-term stability.

[0030] (2) The scheduling table is generated by combining the maximum matching algorithm with the cutoff priority. It has the advantages of both the cutoff priority and the maximum matching algorithm. It can balance the link load while reducing the real-time data packet loss rate, and can support complex environments with dynamic changes and large traffic throughput.

[0031] (3) FPGA is used to integrate the time synchronization function and schedule generation function into the traditional Ethernet, and the protocol control frames, real-time data and non-real-time data are transmitted periodically. On the basis of time synchronization, it can be compatible with the functions of the traditional Ethernet and realize the time-deterministic transmission of the real-time data TT stream. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a principle block diagram of a method for transmitting test data delay deterministically of TTE-fused Ethernet in the present invention;

[0033] Figure 2 This is a schematic diagram of the time synchronization core module of the present invention;

[0034] Figure 3 Generating a flow chart for the schedule of the present invention;

[0035] Figure 4 This is the architecture diagram of the TTE fused Ethernet system of the present invention. DETAILED DESCRIPTION

[0036] The present invention is described in further detail below in conjunction with the accompanying drawings.

[0037] like Figure 1As shown, the present invention discloses a test data delay deterministic transmission method of TTE fused Ethernet, the method comprising: using FPGA to design a time synchronization core module in the TTE protocol, the module can process the received protocol control frame PCF, realize high-precision time synchronization of multiple nodes through transparent clock update, solidification and compression algorithm, and use the command-condition interaction method to realize the control of state and other core signals; using the maximum matching algorithm combined with cutoff priority to generate a scheduling table, including scheduling parameter input, cycle calculation, shortest path calculation, cutoff priority algorithm preprocessing, maximum matching algorithm reordering, message allocation, conflict detection and scheduling table loading eight steps, reduce the packet loss rate of real-time data and balance the link load; using FPGA to load the scheduling table into the scheduling configuration module, integrate Ethernet transmission, and periodically allocate time slots to the link, which are protocol control frames, real-time data and non-real-time data in turn, to ensure the stability of time synchronization and the delay determinism of TT stream transmission. The chip used is Xilinx's ARTIX-7 FPGA chip, model XC7A200T-2FBG484I, and the PHY chip is Realtek RTL8211EG. The specific implementation contents are as follows:

[0038] 1. Time synchronization core module: The module follows the AS6802 protocol under the TTE standard to synchronize the time of both parties. The module can process the received protocol control frame PCF, and achieve high-precision time synchronization of multiple nodes through transparent clock update, solidification and compression algorithms. At the same time, the command-condition interaction method is used to realize the control of the status and other core signals. The module structure is as follows: Figure 2 shown.

[0039] The module design has three advantages: First, the module has clear PCF process processing. After entering the receiving module, the solidification and compression algorithms are executed in sequence, and then the sending module is entered. Second, the module uses the command-condition interaction method to realize the control of the state and other core signals, that is, the input condition signal and output command method of statectrl interacting with other modules. Third, the module leads to the local_clk output, which represents the time node of the device. It can be used to compare with other devices to calibrate the time synchronization accuracy, and also to support the specific time scheduling of TT messages.

[0040] The functions of each module are as follows:

[0041] ① PCF receiving module PR (PCFReceive): extracts the relevant information of the PCF frame from PCF_RX and splices it into PCF_aRX, and also has the function of caching data.

[0042] ②PermanentProc (PP) module: The received PCF_aRX PCF frame is processed by the curing algorithm to obtain the PCF_perm curing PCF frame. It should have channels for executing multiple curing algorithms in parallel.

[0043] ③Compression processing module CP (CompressProc): Executes compression algorithm on the received PCF_perm solidified PCF frame to obtain PCF_comp compressed PCF frame. It should have channels for executing multiple compression algorithms in parallel.

[0044] ④PCF sending module PT (PCFTransmit): The received PCF_comp compressed PCF frame is combined with the sending instruction information COM_TX to form a PCF frame for sending.

[0045] ⑤Timeout control module TO (TimeOut): Generates a local timer and timeout signal based on the current state.

[0046] ⑥Clique Detection Module CD (CliqueDetect): Performs synchronous and asynchronous clique detection at corresponding time nodes according to instructions, and generates local synchronous and asynchronous member group vectors.

[0047] ⑦ Synchronous calculation module SCP (SyncCompute): performs frame synchronization calculations at corresponding time nodes according to instructions and generates clock correction values.

[0048] ⑧Local clock control module LCC (LocalClkCtrl): updates the local clock according to instructions and status, and has the function of clock correction.

[0049] ⑨Local integration cycle control module LCYC (LocalCycleCtrl): updates the local integration cycle according to instructions and status.

[0050] ⑩State control module SC (StateCtrl): updates the current state and sends instructions to each module based on the current local maintenance signal.

[0051] 2. Combined with the maximum matching algorithm with cutoff priority: This method can generate a scheduling table, which refers to the matching relationship between the real-time data TT flow and the sending time, which can reduce the packet loss rate of real-time data and balance the link load. The method flow is as follows Figure 3 .

[0052] The process is described as follows:

[0053] Input message model parameters, including terminal node information, switch information, transmission link information, and parameters of all TT message information;

[0054] Cycle calculation, based on the idea of ​​TDMA time division multiple access, the TT message is allocated periodic time slots, and the matrix cycle MC and the basic cycle BC are defined. A TT message is sent at least once in an MC, and a TT message is sent at most once in a BC;

[0055] For the shortest path calculation, the Dijkstra algorithm is used to generate a shortest path tree for each message source node and determine the shortest path for each TT message;

[0056] Deadline priority preprocessing, pre-prioritizes all TT messages in order of deadline from small to large;

[0057] Maximum matching sorting, re-sorting all TT messages based on the in-and-out degrees of all nodes, defining the node with the largest out-degree as the sending node and the node with the smallest in-degree as the receiving node, and giving priority to the TT messages whose source and target nodes are composed of the sending and receiving nodes;

[0058] Message allocation, assigning each TT message to a matrix cycle according to the pre-sorted priority;

[0059] Conflict detection: Check whether each TT message exceeds the deadline. If there is a conflict, it means that the current input message model parameters are unreasonable. The input message model parameters are readjusted. If there is no conflict, a scheduling table is generated.

[0060] Load the schedule, design the schedule configuration module, and deploy the generated schedule to the schedule configuration module.

[0061] 3. TTE fusion Ethernet system architecture: This architecture uses FPGA to load the scheduling table into the scheduling configuration module, integrates Ethernet transmission, and periodically allocates time slots to the link, which are protocol control frames, real-time data, and non-real-time data in turn, ensuring the stability of time synchronization and the delay determinism of TT stream transmission. The system architecture is as follows Figure 4 .

[0062] Workflow: The system interacts with the outside world through the onboard PHY chip to exchange data via the network cable, and converts the RGMII and GMII formats through the conversion module. After receiving the message, it will be diverted to the ARP or UDP or time synchronization core module according to its category. Specifically, the ARP frame enters the ARP processing module, the RC, BE and TT flow information enters the UDP processing module, and the PCF frame enters the time synchronization core module. The output data of the three will be transmitted to the Ethernet control module, and the gate-level control determines whose data is sent to the output port. The schedule configuration module will read the generated schedule and the local clock of the time synchronization core module. When the receiving time point of a certain message is reached, it will give the receiving module a receiving trigger signal to open the window for reception. When the sending time point of a certain message is reached, it will give the UDP processing module a trigger signal to command it to send the corresponding TT message to guide the sending of real-time data.

[0063] The functions of each module are as follows:

[0064] ①GMII2RGMII conversion module: realizes data format conversion inside and outside the FPGA. The FPGA receives network port data through the PHY chip, which adopts dual-edge sampling, that is, 4-bit data is collected on the rising and falling edges of the clock, while the internal logic of the FPGA is only performed on the rising edge of the clock. Therefore, this module is needed to convert the dual-edge four-bit RGMII signal to the single-edge eight-bit GMII signal.

[0065] ②Data receiving module: implements MAC layer deframing, error checking and data diversion operations, and diverts data into ARP, UDP or time synchronization core modules according to their categories. Specifically, ARP frames enter the ARP processing module, RC, BE and TT flow information enter the UDP processing module, and PCF frames enter the time synchronization core module.

[0066] ③ARP processing module: Follow the ARP protocol to obtain the physical MAC address of the device connected to the network cable.

[0067] ④UDP processing module: transmits Ethernet frames according to IP / UDP protocol.

[0068] ⑤Time synchronization core module: It follows the AS6802 protocol transmission protocol control frame PCF under the TTE standard, maintains the time synchronization of the communicating parties through data interaction, and outputs the local time to provide the time standard.

[0069] ⑥ Ethernet control module: The Ethernet control module will decide to send the output data of the ARP module, UDP module or time synchronization core module to the network port through door-level control according to the current working status of the device.

[0070] ⑦Data sending module: implements MAC layer framing operations.

[0071] ⑧Schedule table configuration module: The schedule table configuration module will read the generated schedule table and the local clock of the time synchronization core module. When the receiving time point of a certain message is reached, a trigger signal will be given to the receiving module to open the window for receiving. When the sending time point of a certain message is reached, a trigger signal will be given to the UDP processing module to command it to send the corresponding TT message to guide the sending of real-time data.

[0072] The design of this system makes signal processing clearer. The time synchronization core module integrates the time synchronization function with traditional Ethernet. The scheduling table configuration module integrates the generated scheduling table scheme with traditional Ethernet. On the basis of time synchronization, it can be compatible with the functions of traditional Ethernet and realize the time-delay deterministic transmission of real-time data TT stream.

[0073] The contents not described in detail in the specification of the present invention belong to the prior art known to the professional and technical personnel in this field.

[0074] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for transmitting test data with time delay deterministic in TTE-converged Ethernet, characterized in that: The method comprises: Step 1: Design the time synchronization core module in accordance with the TTE protocol, process the received protocol control frame PCF, implement high-precision time synchronization of multiple nodes through transparent clock update, solidification and compression algorithms, and use the command-condition interaction method to control the status and core signals; Step 2: Generate a scheduling table using a maximum matching algorithm combined with a cutoff priority, wherein the scheduling table is used to characterize the matching relationship between the real-time data TT flow and the sending time; Step 3: Use FPGA to load the scheduling table into the scheduling configuration module, and combine it with the time synchronization core module to periodically allocate time slots for protocol control frames, real-time data, and non-real-time data in turn.

2. The method for transmitting test data with time delay deterministic in TTE-converged Ethernet according to claim 1, characterized in that: The step one comprises: Design the PCF receiving module to parse the UDP data packets obtained by the network layer, extract the integration period, member group, synchronization priority, synchronization domain, PCF frame type and transparent clock field; design the PCF sending module to obtain the integration period, member group, synchronization priority, synchronization domain, PCF frame type and transparent clock field according to the core signal parameters of the current system after the sending condition is triggered, and frame it into a UDP data packet and send it to the network layer; Design transparent clock update, solidification and compression algorithms. The transparent clock update is used to record the cumulative transmission delay update in the entire link transmission, including dynamic and static delays. The solidification algorithm is used to reorder the receiving time points and transparent clock values ​​of the PCF frames on each link to ensure that the receiving and sending order of each PCF frame are the same, and the sending and receiving intervals are equal. The compression algorithm is used to integrate the PCF frames received by the CM device from multiple SM devices, obtain the local clock difference of each SM based on the solidified time point in each PCF frame, and execute the compression algorithm to obtain a weighted and unified compression time point, which is used as the standard to correct the local clock of each device. Design the time synchronization core module, execute the corresponding algorithm and complete the management of local status and core signals according to the command-condition interaction method.

3. The method for transmitting test data with time delay deterministic in TTE-converged Ethernet according to claim 2, characterized in that: The method of executing the corresponding algorithm and completing the management of the local state and core signal according to the command-condition interaction method includes: the solidification processing module and the compression processing module execute the corresponding solidification and compression algorithms, the state control module manages the local state jump, maintains the state core signal, the timeout module detects whether the time in the current state exceeds the threshold limit, maintains the time_out core signal, the clustering detection module detects whether the number of local member groups exceeds the threshold limit, maintains the local_member core signal, the local time control module controls the local time count and jump, maintains the local_clk core signal, the local cycle control module controls the local cycle count and jump, maintains the local_cycle core signal, the synchronization calculation module and the step calculation module calculate the correction value of the local time according to the input parameters, and maintains the clk_correct core signal.

4. The method for transmitting test data with time delay deterministic in TTE-converged Ethernet according to claim 1, characterized in that: The second step comprises: Input message model parameters, including terminal node information, switch information, transmission link information, and parameters of all TT message information; Cycle calculation, based on the idea of ​​TDMA time division multiple access, the TT message is allocated periodic time slots, and the matrix cycle MC and the basic cycle BC are defined. A TT message is sent at least once in a matrix cycle MC, and a TT message is sent at most once in a matrix cycle BC; For the shortest path calculation, the Dijkstra algorithm is used to generate a shortest path tree for each message source node and determine the shortest path for each TT message; Deadline priority preprocessing, pre-prioritizes all TT messages in order of deadline from small to large; Maximum matching sorting, re-sorting all TT messages based on the in-and-out degrees of all nodes, defining the node with the largest out-degree as the sending node and the node with the smallest in-degree as the receiving node, and assigning priorities to the TT messages of the source node and the target node, which are composed of the sending node and the receiving node; Message allocation, assigning each TT message to a matrix cycle according to the pre-sorted priority; Conflict detection: Check whether each TT message exceeds the deadline. If there is a conflict, it means that the current input message model parameters are unreasonable. The input message model parameters are readjusted. If there is no conflict, a scheduling table is generated. Load the schedule, design the schedule configuration module, and deploy the generated schedule to the schedule configuration module.

5. The method for transmitting test data with time delay deterministic in TTE-converged Ethernet according to claim 1, characterized in that: The step three comprises: Calculate the cycle time, obtain the time required for protocol control frame transmission through the design of the time synchronization core module, obtain the time required for real-time data transmission through the message model parameters, set the time required for non-real-time data transmission to be the same as the time required for real-time data transmission, and use the superposition of the three parts of the time for transmission of protocol control frames, real-time data, and non-real-time data as the time cycle time for transmitting information in the link; Protocol control frame sending, in the first part of each time period, according to the management and control of the time synchronization core module, a protocol control frame PCF is sent; Real-time data transmission, in the second part of each time cycle, the time synchronization core module provides local time, and according to the matching relationship between real-time data and transmission time in the schedule table, a transmission instruction is output when a specific time node is reached to guide the transmission of real-time data in the Ethernet data cache, namely, the TT time trigger flow; Non-real-time data transmission: In the third part of each time period, non-real-time data in the Ethernet data buffer is sent, including RC rate limiting flow and BE best effort forwarding flow.

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