Variable-width negative capacitance layer double-gate fin type field effect transistor and preparation method thereof

Abstract

The invention discloses a variable-width negative capacitance layer double-gate fin type field effect transistor and a preparation method thereof. The variable-width negative capacitance layer double-gate fin type field effect transistor comprises a semiconductor substrate, a buried oxide layer, a fin type active region, a gate oxide layer, a variable-width negative capacitance layer, an isolation oxide layer, a metal gate and a side wall, the fin type active region comprises a source region, a channel region and a drain region which are sequentially arranged along the length direction; the variable-width negative capacitance layer is symmetrically arranged outside the gate oxide layer, and the widths of the two ends of the variable-width negative capacitance layer are unequal. The two sides of the gate oxide layer are covered with the negative capacitance layer with the width changing along the channel, and the gate voltage is variably amplified and then applied to the two sides of the gate oxide layer by means of the variable voltage amplification effect and the gate-drain coupling effect of the variable width negative capacitance layer, so that the channel control capacity of the fin field effect transistor is improved, and the reliability of the fin field effect transistor is improved. The subthreshold swing of the transistor is reduced, the saturation region current of the transistor is improved, and the common negative differential resistance phenomenon in the negative capacitance field effect transistor is weakened, so that the power consumption of the transistor is reduced, and the performance of the transistor and the performance in a logic circuit are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, in particular to a variable-width negative capacitance layer double-gate fin field effect transistor and a preparation method thereof. Background Art

[0002] With the development of Moore's Law, the device feature size continues to shrink. The continued development of nano MOSFET faces many technical challenges. The continued reduction in size brings about mobility degradation, leakage current and power consumption continue to increase, gate control weakens, performance degradation and other problems. New materials and new device structures are urgently needed to solve the above problems.

[0003] Structures such as fin field-effect transistors (FinFETs) have alleviated the above problems. However, as device size continues to decrease, it is still affected by the short channel effect, and leakage current and power consumption rise again. The subthreshold swing (SS) of the transistor still cannot break through the limit of 60mV / dec under the Boltzmann distribution, which has become a key technical challenge faced by devices such as FinFETs.

[0004] The next generation of low-power circuits and systems require new semiconductor devices that can overcome the Boltzmann limit and have a value lower than the theoretical limit of 60mV / dec at room temperature. Negative capacitance fin field effect transistor (NC-FinFET) is becoming a powerful device to achieve this breakthrough. It introduces a ferroelectric layer that can cause a negative capacitance effect in the gate, and introduces the ferroelectric capacitance into the gate capacitance. Under appropriate working conditions, NC-FinFET can amplify the gate voltage and act on the interface between the negative capacitance ferroelectric layer and the gate oxide layer, thereby breaking through the subthreshold swing limit of 60mV / dec.

[0005] However, the potential at the interface between the negative capacitance ferroelectric layer and the gate oxide layer is not only affected by the gate voltage, but also by the parasitic capacitance near the drain electrode, which is coupled with the gate capacitance and will have a significant impact on the potential at the interface between the negative capacitance ferroelectric layer and the gate oxide layer. At present, although the amplification effect of the negative capacitance FinFET for the gate voltage is consistent at the source and drain ends, the gate-drain coupling effect is inconsistent at the source and drain ends. The presence of the drain voltage causes the gate to reduce its control ability over the channel and causes a significant negative differential resistance (NDR) phenomenon. Therefore, the performance of improving the subthreshold characteristics of the transistor or reducing the static power consumption is limited, resulting in limited performance improvement of the transistor. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a variable width negative capacitance layer double-gate fin field effect transistor and a preparation method thereof in view of the deficiencies of the above-mentioned prior art. The variable width negative capacitance layer double-gate fin field effect transistor and the preparation method thereof can enable the gate voltage to produce a linear amplification effect in the fin channel region through the negative capacitance layer whose width varies along the channel. At the same time, by changing the width of the negative capacitance layer, the inhibitory effect of the gate-drain coupling effect on the voltage amplification effect is reduced, the gate control capability of the fin field effect transistor is improved, the subthreshold swing of the device is reduced and the saturation region current is increased.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0008] A variable width negative capacitance layer double-gate fin-type field effect transistor comprises a semiconductor substrate, a buried oxide layer, a fin-type active area, a gate oxide layer, a variable width negative capacitance layer, an isolation oxide layer, a metal gate and a side wall.

[0009] The semiconductor substrate, the buried oxide layer and the fin-type active area are coaxially arranged in sequence from bottom to top.

[0010] The fin-type active region includes a source region, a channel region and a drain region which are sequentially arranged along the length direction.

[0011] The gate oxide layer is symmetrically arranged on both sides of the channel region.

[0012] The variable width negative capacitance layer is symmetrically arranged outside the gate oxide layer; the widths of the two ends of the variable width negative capacitance layer are not equal.

[0013] The isolation oxide layer is located above the channel region, the gate oxide layer and the variable width negative capacitor layer.

[0014] The metal gate covers the outer sides of the isolation oxide layer and the variable width negative capacitor layer.

[0015] The side walls are symmetrically arranged on both sides of the metal grid.

[0016] The width of the variable width negative capacitance layer adjacent to the source region end is greater than the width of the variable width negative capacitance layer adjacent to the drain region end.

[0017] The width of the variable width negative capacitance layer adjacent to the source region end is smaller than the width of the variable width negative capacitance layer adjacent to the drain region end.

[0018] The two variable width negative capacitance layers located outside the gate oxide layer are respectively the front gate side negative capacitance layer and the back gate side negative capacitance layer; the cross sections of the front gate side negative capacitance layer and the back gate side negative capacitance layer are both right-angled trapezoids; the cross section of the isolation oxide layer is an isosceles trapezoid.

[0019] The materials of the semiconductor substrate and the fin-type active region are any one of silicon, germanium, silicon germanium, gallium arsenide, gallium nitride, silicon carbide and indium phosphide.

[0020] The material of the metal gate is any one of aluminum, copper, silver, gold, polysilicon, titanium nitride or tantalum nitride.

[0021] The material of the sidewall spacer is any one of silicon nitride, silicon oxynitride and silicon oxycarbide.

[0022] A method for preparing a double-gate fin field effect transistor with a variable width negative capacitance layer comprises the following steps.

[0023] Step 1, preparing a fin-type active area: preparing a buried oxide layer on a semiconductor substrate, and preparing a fin-type active area above the buried oxide layer;

[0024] Step 2, depositing a gate oxide layer and a polysilicon layer: depositing a gate oxide layer on the top surface and both side surfaces of the channel region of the fin-type active region; and then depositing a polysilicon layer on both sides and the top of the gate oxide layer.

[0025] Step 3, prepare a polysilicon pseudo gate: use photoresist to protect the polysilicon layer in the longitudinal section where the channel area is located, and etch the polysilicon layer in the longitudinal section where the source area and the drain area are located, so that the polysilicon layer in the longitudinal section where the channel area is located is formed into a polysilicon pseudo gate.

[0026] Step 4, depositing a nitride mask: remove the photoresist, and deposit nitride on both sides of the polysilicon pseudo gate to form a nitride mask flush with the top surface of the polysilicon pseudo gate.

[0027] Step 5, prepare a nitride hard mask 1: deposit a layer of nitride on the top of the polysilicon pseudo gate and the nitride mask, and form a nitride hard mask 1 with a right-angle trapezoidal cross-section by photolithography; wherein, the nitride hard mask 1 is located on one side of the fin active area, and the hypotenuse of the nitride hard mask 1 faces the fin active area.

[0028] Step 6, prepare nitride hard mask 2: use photoresist to protect nitride hard mask 1, deposit nitride on the top of the polysilicon pseudo gate and nitride mask corresponding to nitride hard mask 1, and remove the photoresist to form nitride hard mask 2; nitride hard mask 1 and nitride hard mask 2 are symmetrically arranged about the vertical plane where the fin active area is located.

[0029] Step 7, etching deep trenches: using nitride hard mask 1, nitride hard mask 2, and the nitride masks on both sides of the polysilicon pseudo gate as masks, etch the polysilicon pseudo gate downward to form deep trenches with the same shape as the variable width negative capacitor layer; wherein the widths of the two ends of the deep trenches are not equal.

[0030] Step 8, depositing a variable width negative capacitor layer: depositing a variable width negative capacitor layer in the deep trench, and depositing an isolation oxide layer on the variable width negative capacitor layer.

[0031] Step 9, removing the polysilicon dummy gate: removing the nitride hard mask 1, the nitride hard mask 2 and the polysilicon dummy gate.

[0032] Step 10, depositing a metal gate: depositing a metal gate around the variable width negative capacitor layer and the isolation oxide layer.

[0033] Step 11, LDD implantation: the nitride mask in step 4 and the gate oxide layer around the source region and the drain region are removed by etching; then, ion implantation is performed in both the source region and the drain region to form LDD implantation.

[0034] Step 12: depositing sidewalls on both sides of the metal gate, and performing ion implantation again in the source region and the drain region to form heavily doped source region and drain region.

[0035] In step 1, a fin-type active region is formed on the buried oxide layer using a self-aligned double patterning (SADP) technique.

[0036] In step 7, a deep groove is etched on both sides of the channel region, and the cross section of each deep groove is a right-angled trapezoid. The vertical plane where the trapezoidal hypotenuse of each deep groove is located coincides with the vertical plane where the trapezoidal hypotenuse of nitride hard mask 1 or nitride hard mask 2 is located.

[0037] The present invention has the following beneficial effects:

[0038] (1) The variable width negative capacitance layer dual-gate fin field effect transistor proposed in the present invention is different from the conventional constant width negative capacitance dual-gate fin field effect transistor. Negative capacitance layers whose width varies linearly along the channel are arranged on both sides of the gate oxide layer, which can cause the gate voltage to produce a linear voltage amplification effect in the fin channel region, thereby reducing the subthreshold swing of the device to below 60mV / dec.

[0039] (2) In the variable width negative capacitance layer dual-gate fin field effect transistor proposed in the present invention, when the width of the negative capacitance layer at the source end is greater than that at the drain end, the width of the negative capacitance layer is changed to reduce the inhibitory effect of the gate-drain coupling effect on the voltage amplification effect, weaken the negative differential resistance (NDR) phenomenon, improve the device output characteristics, and facilitate the application in logic circuits such as CMOS inverters.

[0040] (3) The variable width negative capacitance layer dual-gate fin field effect transistor proposed in the present invention can utilize the enhanced gate-drain coupling effect to achieve lower leakage current when the transistor is in the off state when the negative capacitance layer width at the drain end is greater than that at the source end. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic structural diagram of a variable width negative capacitance layer double-gate fin field effect transistor of the present invention is shown.

[0042] Figure 2 The horizontal cross-sectional view along the middle of the channel region of the variable width negative capacitance layer double-gate fin field effect transistor of the present invention is shown.

[0043] Figure 3 The figure shows the voltage amplification effect of the variable width negative capacitance layer and the gate oxide layer interface along the channel region of the variable width negative capacitance layer double gate fin field effect transistor of the present invention at different voltages compared with the conventional negative capacitance double gate fin field effect transistor; wherein (a), (b) and (c) correspond to the drain voltage V D They are 0.05V, 0.8V and 2.4V respectively.

[0044] Figure 4 The figure shows the comparison of the transfer characteristics of the variable width negative capacitance layer double-gate fin field effect transistor of the present invention at different voltages with the conventional negative capacitance double-gate fin field effect transistor; wherein (a), (b) and (c) correspond to the voltage V D They are 0.05V, 0.8V and 2.4V respectively.

[0045] Figure 5 A comparison diagram showing the output characteristics of the variable width negative capacitance layer double-gate Fin field effect transistor of the present invention and the conventional negative capacitance double-gate Fin field effect transistor is shown.

[0046] Figure 6 The structure diagram of step 1 in the method for preparing a double-gate fin field effect transistor with a variable width negative capacitance layer of the present invention is shown.

[0047] Figure 7 The structure diagram of step 2 in the method for preparing a double-gate fin field effect transistor with a variable width negative capacitance layer of the present invention is shown.

[0048] Figure 8 The structure diagram of step 3 in the method for preparing a double-gate fin field effect transistor with a variable width negative capacitance layer of the present invention is shown.

[0049] Fig. 9 The structure diagram of step 4 in the method for preparing a double-gate fin field effect transistor with a variable width negative capacitance layer of the present invention is shown.

[0050] Fig.10 The structure diagram of step 5 in the method for preparing a double-gate fin field effect transistor with a variable width negative capacitance layer of the present invention is shown.

[0051] Fig.11 The structure diagram of step 6 in the method for preparing a double-gate fin field effect transistor with a variable width negative capacitance layer of the present invention is shown.

[0052] Fig.12 The structure diagram of step 7 in the method for preparing a double-gate fin field effect transistor with a variable width negative capacitance layer of the present invention is shown.

[0053] Fig.13The cross-sectional view of the variable width negative capacitance layer double-gate fin field effect transistor of the present invention at the center of the channel along the vertical channel plane after step 7 is shown.

[0054] Fig.14 The structure diagram of step 8 in the method for preparing a double-gate fin field effect transistor with a variable width negative capacitance layer of the present invention is shown.

[0055] Fig.15 The cross-sectional view of the variable width negative capacitance layer double-gate fin field effect transistor of the present invention after step 8 is shown at the center of the channel along the vertical channel plane.

[0056] Fig.16 The structure diagram of step 9 in the method for preparing a double-gate fin field effect transistor with a variable width negative capacitance layer of the present invention is shown.

[0057] Fig.17 The structure diagram of step 10 in the method for preparing a double-gate fin field effect transistor with a variable width negative capacitance layer of the present invention is shown.

[0058] Fig.18 The structure diagram of step 11 in the method for preparing a double-gate fin field effect transistor with a variable width negative capacitance layer of the present invention is shown.

[0059] Fig.19 The cross-sectional view of the variable width negative capacitance layer double-gate fin field effect transistor of the present invention at the center of the channel along the vertical channel plane after step 11 is shown.

[0060] Fig. 20 The structure diagram of step 12 in the method for preparing a double-gate fin field effect transistor with a variable width negative capacitance layer of the present invention is shown.

[0061] Among them are:

[0062] 1. Semiconductor substrate; 2. Buried oxide layer; 3. Fin active area; 4. Gate oxide layer; 5. Polysilicon layer;

[0063] 6. Polysilicon pseudo gate hard mask;

[0064] 7. Polysilicon pseudo gate; 7-1. Front gate side pseudo gate; 7-2. Back gate side pseudo gate;

[0065] 8-1, source region nitride mask; 8-2, drain region nitride mask;

[0066] 9. Nitride hard mask 1; 10. Photoresist; 11. Nitride hard mask 2;

[0067] 12-1, negative capacitance layer on the front gate side; 12-2, negative capacitance layer on the rear gate side;

[0068] 13. Isolation oxide layer; 14. Metal gate;

[0069] 15-1, gate oxide layer on the front gate side; 15-2, gate oxide layer on the back gate side;

[0070] 16. Source region; 17. Drain region; 18. Channel region; 19. Side wall. DETAILED DESCRIPTION

[0071] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific preferred embodiments.

[0072] In the description of the present invention, it should be understood that the terms "left side", "right side", "upper part", "lower part" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. "First", "second" and the like do not indicate the importance of the components, and therefore cannot be understood as limiting the present invention. The specific dimensions used in this embodiment are only for illustrating the technical solution, and do not limit the scope of protection of the present invention.

[0073] like Figure 1 As shown, a variable width negative capacitance layer double gate fin field effect transistor includes a semiconductor substrate 1, a buried oxide layer 2, a fin active area 3, a gate oxide layer 4, a variable width negative capacitance layer, an isolation oxide layer 13, a metal gate 14 and a sidewall 19.

[0074] The semiconductor substrate, the buried oxide layer and the fin-type active area are coaxially arranged from bottom to top, wherein the materials of the semiconductor substrate and the fin-type active area are any one of silicon, germanium, silicon germanium, gallium arsenide, gallium nitride, silicon carbide and indium phosphide.

[0075] like Figure 2 As shown, the fin-type active region includes a source region 16 , a channel region 18 and a drain region 17 which are sequentially arranged along the length direction.

[0076] The gate oxide layer is symmetrically arranged on both sides of the channel region.

[0077] The variable width negative capacitance layer is symmetrically arranged outside the variable width negative capacitance layer of the gate oxide layer, and includes a front gate side negative capacitance layer 12 - 1 and a rear gate side negative capacitance layer 12 - 2 .

[0078] The widths of the two ends of the variable width negative capacitance layer are not equal. In this embodiment, the cross-sections of the front gate side negative capacitance layer 12-1 and the rear gate side negative capacitance layer 12-2 are preferably right-angled trapezoids, and specifically have the following two preferred embodiments.

[0079] Example 1

[0080] The width of the variable width negative capacitance layer adjacent to the source region is greater than that of the variable width negative capacitance layer adjacent to the drain region, that is, the long bottom side of the right-angled trapezoid is set at the source region. At this time, by changing the width of the negative capacitance layer, the inhibitory effect of the gate-drain coupling effect on the voltage amplification effect is reduced, the negative differential resistance (NDR) phenomenon is weakened, the device output characteristics are improved, and it is conducive to the application in logic circuits such as CMOS inverters.

[0081] Example 2

[0082] The width of the variable width negative capacitance layer adjacent to the source region is smaller than that of the variable width negative capacitance layer adjacent to the drain region, that is, the long bottom side of the right-angled trapezoid is set at the drain region. At this time, by changing the width of the negative capacitance layer, the inhibitory effect of the gate-drain coupling effect on the voltage amplification effect is reduced, the negative differential resistance (NDR) phenomenon is weakened, the device output characteristics are improved, and it is conducive to the application in logic circuits such as CMOS inverters.

[0083] The isolation oxide layer is located above the channel region, the gate oxide layer and the variable width negative capacitance layer, and the cross section of the isolation oxide layer is preferably an isosceles trapezoid.

[0084] The metal gate covers the outside of the isolation oxide layer and the variable width negative capacitor layer, and the material of the metal gate is preferably any one of aluminum, copper, silver, gold, polysilicon, titanium nitride or tantalum nitride.

[0085] The sidewalls are symmetrically arranged on both sides of the metal gate, and the material of the sidewalls is preferably any one of silicon nitride, silicon oxynitride and silicon oxycarbide.

[0086] In the embodiment, variable width negative capacitance layers (also referred to as negative capacitance layers) are arranged on both sides of the gate oxide layer, and an external electric field causes the negative capacitance layer to produce polarization characteristics, and different widths are used to adjust the voltage amplification and gate-drain coupling characteristics. Figure 3 As shown, a voltage V is applied to the metal layer. G Finally, by changing the width of the negative capacitance layer, the voltage at the interface between the gate oxide layer and the negative capacitance layer can be changed from V int,S (interface potential on the source side) changes to V int,D (interface potential on the drain side) voltage distribution.

[0087] like Figure 4 As shown, when the width of the negative capacitance layer at the source end is greater than that at the drain end, the inhibitory effect of the gate-drain coupling effect on the voltage amplification effect is reduced by changing the width of the negative capacitance layer, thereby achieving a steeper subthreshold region drain-source current-gate voltage curve, indicating a smaller subthreshold swing; when the width of the negative capacitance layer at the drain end is greater than that at the source end, the enhanced gate-drain coupling effect can be utilized to achieve a lower leakage current when the transistor is in the off state.

[0088] like Figure 5As shown, when the width of the negative capacitance layer at the source end is greater than that at the drain end, the width of the negative capacitance layer changes, thereby reducing the inhibitory effect of the gate-drain coupling effect on the voltage amplification effect, weakening the negative differential resistance (NDR) phenomenon, and improving the device output characteristics.

[0089] A method for preparing a double-gate fin field effect transistor with a variable width negative capacitance layer comprises the following steps.

[0090] Step 1: Prepare the fin-type active area: Figure 6 As shown, a buried oxide layer is prepared on a semiconductor substrate, and a fin-type active region is formed above the buried oxide layer preferably using SADP technology.

[0091] Step 2: Deposit gate oxide layer and polysilicon layer: Figure 7 As shown, uniform silicon dioxide is formed as a gate oxide layer on the top surface and both sides of the channel region of the fin-type active area; then, a polysilicon layer 5 (also called a polysilicon pseudo gate precursor) is preferably deposited on both sides and the top of the gate oxide layer using chemical vapor deposition.

[0092] Step 3: Prepare polysilicon pseudo gate: Figure 8 As shown, the polysilicon layer in the longitudinal section where the channel region is located is protected by photoresist, and the polysilicon layer in the longitudinal section where the source region and the drain region are located is etched, so that the polysilicon layer in the longitudinal section where the channel region is located is formed into a polysilicon pseudo gate.

[0093] Step 4: Deposit a nitride mask: Fig. 9 As shown, the photoresist is removed, and nitride is preferably deposited on both sides of the polysilicon pseudo gate by chemical vapor deposition, and the surface is preferably flattened by chemical mechanical polishing to form a nitride mask flush with the top surface of the polysilicon pseudo gate.

[0094] Step 5: Prepare a nitride hard mask 1: Fig.10 As shown, a layer of nitride is preferably deposited on top of the polysilicon pseudo gate and the nitride mask by chemical vapor deposition, and a nitride hard mask 1 with a right-angle trapezoidal cross section is formed by photolithography. The nitride hard mask 1 is located on one side of the fin active area, and the hypotenuse of the nitride hard mask 1 faces the fin active area.

[0095] Step 6: Prepare nitride hard mask 2: Fig.11 As shown, photoresist is used to protect nitride hard mask one, and part of the photoresist is removed after exposure. Nitride is preferably deposited on the top of the polysilicon pseudo gate and the nitride mask corresponding to nitride hard mask one by chemical vapor deposition, and chemical mechanical polishing is performed using nitride hard mask one as a stop layer, and the photoresist is removed to form nitride hard mask two.

[0096] The nitride hard mask 1 and the nitride hard mask 2 are preferably right-angled trapezoids symmetrically arranged about the vertical plane where the fin-type active region is located, and the hypotenuses are arranged facing each other.

[0097] Step 7: Etching deep grooves: Fig.12 and 13 As shown, using nitride hard mask 1, nitride hard mask 2, and the nitride masks on both sides of the polysilicon pseudo gate as masks, the polysilicon pseudo gate is etched downward to form a deep groove with the same shape as the variable width negative capacitor layer in the area of ​​the variable width negative capacitor layer; wherein the widths of the two ends of the deep groove are not equal.

[0098] A deep groove is etched on both sides of the channel region, and the cross section of each deep groove is a right-angle trapezoid. The vertical plane where the trapezoidal hypotenuse of each deep groove is located coincides with the vertical plane where the trapezoidal hypotenuse of the nitride hard mask 1 or the nitride hard mask 2 is located.

[0099] Step 8: Deposit a variable width negative capacitance layer: Fig.14 and 15 As shown, a variable width negative capacitor layer is preferably deposited in the deep groove by atomic layer deposition, the height of the negative capacitor layer is controlled by back etching, and an isolation oxide layer is preferably deposited above the variable width negative capacitor layer by atomic layer deposition or chemical vapor deposition.

[0100] In an embodiment, when depositing the negative capacitance layer, the top height of the negative capacitance layer cannot exceed the fin. In addition to strictly controlling the time during the deposition process, back etching can be used to assist in adjusting the height.

[0101] In an embodiment, the formation quality of the negative capacitance layer may be improved by rapid thermal annealing (RTA).

[0102] In an embodiment, the thickness of the negative capacitance layer near the source is greater than that near the drain (SFWV-NC-DG-FinFET), or the thickness of the negative capacitance layer near the drain is greater than that near the source (DFWV-NC-DG-FinFET).

[0103] Step 9: Remove the polysilicon pseudo gate: Fig.16 As shown, the nitride hard mask 1, the nitride hard mask 2 and the polysilicon dummy gate are preferably removed by chemical mechanical polishing.

[0104] Step 10: Deposit metal gate: Fig.17 As shown, a metal gate is deposited in the deep trench, preferably by atomic layer deposition or physical vapor deposition, around the variable width negative capacitor layer and the isolation oxide layer.

[0105] Step 11, LDD injection: Fig.18 and 19As shown, the nitride mask in step 4 and the gate oxide layer around the source region and the drain region are removed by etching; then, ion implantation is performed in both the source region and the drain region to form LDD implantation.

[0106] Step 12: Fig. 20 As shown, sidewalls are deposited on both sides of the metal gate, and high-dose ion implantation is performed in the source region and the drain region to form a heavily doped source region and the drain region.

[0107] The present invention covers both sides of the gate oxide layer with a negative capacitance layer whose width varies along the channel, utilizes the voltage amplification effect and gate-drain coupling effect of the variable width negative capacitance layer, and variably amplifies the gate voltage and applies it to both sides of the gate oxide layer, so as to improve the channel control capability of the fin field effect transistor, reduce the subthreshold swing of the transistor, increase the saturation region current of the transistor and weaken the negative differential resistance phenomenon commonly seen in the negative capacitance field effect transistor, thereby reducing the power consumption of the transistor and improving the transistor performance and the performance in the logic circuit.

[0108] The preferred embodiments of the present invention are described in detail above; however, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all belong to the protection scope of the present invention.

Claims

1. A variable width negative capacitance layer double gate fin field effect transistor, characterized in that: It includes a semiconductor substrate, a buried oxide layer, a fin-type active area, a gate oxide layer, a variable-width negative capacitance layer, an isolation oxide layer, a metal gate and a sidewall; The semiconductor substrate, the buried oxide layer and the fin-type active area are coaxially arranged in sequence from bottom to top; The fin-type active region includes a source region, a channel region and a drain region arranged in sequence along the length direction; The gate oxide layer is symmetrically arranged on both sides of the channel region; The variable width negative capacitance layer is symmetrically arranged outside the gate oxide layer; the widths of the two ends of the variable width negative capacitance layer are not equal; The isolation oxide layer is located above the channel region, the gate oxide layer and the variable width negative capacitance layer; The metal gate covers the outer sides of the isolation oxide layer and the variable width negative capacitance layer; The side walls are symmetrically arranged on both sides of the metal grid.

2. The variable width negative capacitance layer dual-gate fin field effect transistor according to claim 1, characterized in that: The width of the variable width negative capacitance layer adjacent to the source region end is greater than the width of the variable width negative capacitance layer adjacent to the drain region end.

3. The variable width negative capacitance layer dual gate fin field effect transistor according to claim 1, characterized in that: The width of the variable width negative capacitance layer adjacent to the source region end is smaller than the width of the variable width negative capacitance layer adjacent to the drain region end.

4. The variable width negative capacitance layer dual-gate fin field effect transistor according to claim 1, characterized in that: The two variable width negative capacitance layers located outside the gate oxide layer are respectively the front gate side negative capacitance layer and the back gate side negative capacitance layer; the cross sections of the front gate side negative capacitance layer and the back gate side negative capacitance layer are both right-angled trapezoids; the cross section of the isolation oxide layer is an isosceles trapezoid.

5. The variable width negative capacitance layer dual gate fin field effect transistor according to claim 1, characterized in that: The materials of the semiconductor substrate and the fin-type active region are any one of silicon, germanium, silicon germanium, gallium arsenide, gallium nitride, silicon carbide and indium phosphide.

6. The variable width negative capacitance layer dual gate fin field effect transistor according to claim 1, characterized in that: The material of the metal gate is any one of aluminum, copper, silver, gold, polysilicon, titanium nitride or tantalum nitride.

7. The variable width negative capacitance layer dual gate fin field effect transistor according to claim 1, characterized in that: The material of the sidewall spacer is any one of silicon nitride, silicon oxynitride and silicon oxycarbide.

8. A method for preparing a variable width negative capacitance layer dual-gate fin field effect transistor according to any one of claims 1 to 7, characterized in that: The steps include: Step 1, preparing a fin-type active area: preparing a buried oxide layer on a semiconductor substrate, and preparing a fin-type active area above the buried oxide layer; Step 2, depositing a gate oxide layer and a polysilicon layer: depositing a gate oxide layer on the top surface and both sides of the channel region of the fin-type active region; and then depositing a polysilicon layer on both sides and the top of the gate oxide layer; Step 3, preparing a polysilicon pseudo gate: using photoresist to protect the polysilicon layer in the longitudinal section where the channel region is located, etching the polysilicon layer in the longitudinal section where the source region and the drain region are located, so that the polysilicon layer in the longitudinal section where the channel region is located is formed into a polysilicon pseudo gate; Step 4, depositing a nitride mask: removing the photoresist, and depositing nitride on both sides of the polysilicon pseudo gate to form a nitride mask flush with the top surface of the polysilicon pseudo gate; Step 5, preparing a nitride hard mask 1: depositing a layer of nitride on top of the polysilicon pseudo gate and the nitride mask, and forming a nitride hard mask 1 with a right-angle trapezoidal cross section by photolithography; wherein the nitride hard mask 1 is located on one side of the fin active area, and the hypotenuse of the nitride hard mask 1 faces the fin active area; Step 6, preparing a second nitride hard mask: using a photoresist to protect the first nitride hard mask, depositing nitride on the top of the polysilicon pseudo gate and the nitride mask corresponding to the first nitride hard mask, and removing the photoresist to form a second nitride hard mask; the first nitride hard mask and the second nitride hard mask are symmetrically arranged about the vertical plane where the fin-type active area is located; Step 7, etching deep grooves: using the nitride hard mask 1, the nitride hard mask 2, and the nitride masks on both sides of the polysilicon pseudo gate as masks, etching the polysilicon pseudo gate downward to form deep grooves of the same shape as the variable width negative capacitor layer; wherein the widths of the two ends of the deep grooves are not equal; Step 8, depositing a variable width negative capacitor layer: depositing a variable width negative capacitor layer in the deep trench, and depositing an isolation oxide layer on the variable width negative capacitor layer; Step 9, removing the polysilicon pseudo gate: removing the nitride hard mask 1, the nitride hard mask 2 and the polysilicon pseudo gate; Step 10, depositing a metal gate: depositing a metal gate around the variable width negative capacitor layer and the isolation oxide layer; Step 11, LDD implantation: etching and removing the nitride mask in step 4, as well as the gate oxide layer around the source region and the drain region; then, performing ion implantation in both the source region and the drain region to form LDD implantation; Step 12: depositing sidewalls on both sides of the metal gate, and performing ion implantation again in the source region and the drain region to form heavily doped source region and drain region.

9. The method for preparing a variable width negative capacitance layer double gate fin field effect transistor according to claim 8, characterized in that: In step 1, a fin-type active region is formed on the buried oxide layer using a self-aligned double patterning (SADP) technique.

10. The method for preparing a double-gate fin field effect transistor with a variable width negative capacitance layer according to claim 8, characterized in that: In step 7, a deep groove is etched on both sides of the channel region, and the cross section of each deep groove is a right-angled trapezoid. The vertical plane where the trapezoidal hypotenuse of each deep groove is located coincides with the vertical plane where the trapezoidal hypotenuse of nitride hard mask 1 or nitride hard mask 2 is located.

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