Time sequence control method and circuit for FPGA BRAM read-write conflict

Abstract

The invention provides a time sequence control method and circuit for FPGA BRAM read-write conflict, and the method comprises the steps: employing two time sequence circuits for generating a working time sequence during the read-write conflict, enabling an initial clock to act on a first time sequence circuit, enabling the first time sequence circuit to generate a read operation time sequence, and enabling the initial clock to act on a second time sequence circuit after the read operation of the first time sequence circuit is completed; and controlling the second time sequence circuit to generate a write operation time sequence, thereby achieving the purpose of controlling read-write by using one time sequence path, avoiding competition caused by read-write conflicts, and improving the memory access efficiency of the BRAM.

Description

Technical Field

[0001] The invention belongs to the field of timing control, and in particular relates to a timing control method and circuit for FPGA BRAM read-write conflict. Background Art

[0002] Field-Programmable Gate Array (FPGA) is a general-purpose programmable logic device with high flexibility and high parallelism. It usually includes programmable logic blocks (CLB), programmable interconnect resources (CR), input and output blocks (IOB) and other IP resources, such as block RAM (BRAM), digital signal processor (DSP), etc. It provides users with system programmable or reconfigurable capabilities.

[0003] As the main block storage resource in FPGA, BRAM is mainly composed of static random access memory (SRAM). It not only provides a large amount of storage space for FPGA, but also has the advantages of flexible storage mode, high compatibility, and no need for periodic refresh, providing internal support for the high flexibility of FPGA. FPGA BRAM has a single-port and dual-port working structure. During the working process, there is a situation where read and write operations need to be performed on the same storage address in the same cycle, which leads to read-write conflicts. It is determined according to the needs whether to read out the old number stored in this storage address and then write new data, or directly read the new number to be written. There is a conflict.

[0004] BRAM read-write conflicts generally include three situations: First, in the BRAM dual-port working mode, the same storage address needs to be read and written in the same cycle, such as port A performs a write operation and port B performs a read operation. This situation corresponds to the read-write conflict (mix_old_data) configuration bit in the configuration judgment circuit module; Second, in the BRAM single-port working mode, reading and writing cannot be performed at the same time, so it is necessary to decide whether to read out the data stored in the address before the write operation. This situation corresponds to the read old number (read_old_data) configuration bit in the configuration judgment circuit module; Third, when the read enable (read_enable) configuration bit in the configuration judgment circuit module is valid, there may be a situation where read and write operations are performed simultaneously. If the three read-write conflict situations are all controlled by using a timing path, it is difficult to avoid the competition caused by read-write conflicts, thereby limiting the memory access efficiency of BRAM. Summary of the invention

[0005] The technical problem to be solved by the present invention is how to avoid BRAM read-write conflicts and improve the development efficiency of BRAM. A timing control method and circuit for FPGA BRAM read-write conflicts are proposed.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A timing control method for FPGA BRAM read-write conflict, when there is a read-write conflict, two timing circuits are used to generate working timing, a first timing circuit and a second timing circuit, the FPGA initial clock acts on the first timing circuit, the first timing circuit generates a read operation timing, after the first timing circuit completes the read operation, the second timing circuit is controlled to generate a write operation timing; When there is no read-write conflict, the first sequential circuit completes the corresponding read or write operation.

[0007] After the read operation of the first timing circuit is completed, the method of controlling the second timing circuit to generate a write operation timing is to track the read operation duration of the first timing circuit, and after the read operation tracking is completed, give a trigger signal of tracking completion, and send the trigger signal to the second timing circuit, so that the second timing circuit generates a working clock signal to start working.

[0008] The method for tracking the read operation duration of the first timing circuit is: using a tracking circuit to simulate the reading and writing duration of the storage address unit corresponding to the storage array of the BRAM static random access memory, the first working clock signal generated by the first timing circuit is input to the tracking circuit, and the tracking circuit gives a trigger signal after the tracking is completed, and the trigger signal is sent to the second timing circuit as the second timing circuit generates a second working clock signal to start working.

[0009] The structure of the tracking circuit includes a row decoding circuit, a row analog tracking circuit, and a column analog tracking circuit; The row decoding circuit is used to determine which row of cells in the storage array of the static random access memory is selected to generate a word line signal WL for operation, and at the same time provide a signal for tracking the operation time of the cells in this row; The row simulation tracking circuit uses n pairs of NMOS tubes to simulate the opening time of n units in a row of the storage array of the static random access memory. The gates of the n pairs of NMOS tubes are respectively connected to the row tracking start signal. The row tracking start signal is generated by the global working clock signal after the row decoding circuit determines which row of units are working and generates a high level. The source and drain of the n pairs of NMOS tubes are connected to the ground signal. After the n pairs of NMOS tubes are charged, a row tracking completion feedback signal is given. The column simulation tracking circuit uses m NMOS tubes to simulate the read and write working time of a column of m units in the storage array of the static random access memory, and the column tracking start signal is respectively input into the source ends of the m NMOS tubes, and the gates and drains of the m NMOS tubes are connected to the ground signal; The column tracking start signal is triggered by the row tracking completion feedback signal. The column tracking start signal completes the tracking after charging of m NMOS tubes and gives a trigger signal for the pull-down level.

[0010] Furthermore, it also includes a delay circuit, which is used to delay the trigger signal when the second timing circuit starts writing after the first timing circuit finishes reading, so as to meet the timing control of the write operation of the second timing circuit module after the timing of the first timing circuit module controlling the read operation is fully completed.

[0011] Furthermore, when the FPGA initial clock acts on the first timing circuit, it needs to be logically combined with the BRAM work enable signal and the power-on clear signal to generate a first working clock signal; The clock signal of the second timing circuit is given by the trigger signal of the tracking circuit, and the BRAM work enable signal of the second timing circuit is generated after the read-write conflict configuration bit, the read old number configuration bit, the read enable configuration bit and the write configuration bit through combination logic. The power-on clear signal of the second timing circuit is connected to the power-on clear signal of the first timing circuit. The second timing circuit performs a logical combination of the clock signal, the BRAM work enable signal and the power-on clear signal to generate a second working clock signal.

[0012] Furthermore, after the working clock signals of the first timing circuit and the second timing circuit, they also pass through a pulse width control circuit respectively, which is used to control the pulse width length of the working clock signal at a high level. The first working clock signal generated by the first timing circuit forms a first global working clock signal after passing through the first pulse width control circuit. The first global working clock signal is input into the tracking circuit. When the analog tracking of the read and write duration of the storage address unit corresponding to the storage array of the static random access memory of the BRAM is completed and a first trigger signal is given, the first trigger signal is input into the first pulse width control circuit to pull down the high level of the first global working clock. The second working clock signal generated by the second timing circuit forms a second global working clock signal after passing through the second pulse width control circuit. The second global working clock signal is input into the tracking circuit. When the analog tracking of the read and write duration of the storage address unit corresponding to the storage array of the static random access memory of the BRAM is completed and a second trigger signal is given, the second trigger signal is input into the second pulse width control circuit to pull down the high level of the second global working clock signal. The first trigger signal is also input into the delay circuit at the same time and then input into the second timing circuit after a delay.

[0013] Furthermore, the pulse width control circuit module structure includes a third inverter 3 and a first inverter 1 with a low level retainer, and a second inverter 2 with a high level retainer. The output ends of the first inverter 1 and the second inverter 2 are connected to the third inverter 3. The output end of the third inverter 3 is a global working clock signal. The working clock signal is input into the second inverter 2, and the trigger signal of the falling edge is input into the first inverter 1.

[0014] Further, the first inverter 1 with a low level keeper includes a fourth inverter 10 composed of a first NMOS tube 11 and a first PMOS tube 12, a second NMOS tube 13 and a fifth inverter 14, the source terminal of the first NMOS tube 11 is connected to the drain of the second NMOS tube 13, the source of the second NMOS tube 13 is grounded, and the output terminal of the fourth inverter 10 is connected to the fifth inverter 14 and then input to the gate of the second NMOS tube 13, and the output terminal of the fourth inverter 10 is connected to the output terminal of the second inverter 2 and then input to the third inverter 3 to form a global working clock signal; The second inverter 2 with a high level keeper includes a sixth inverter 20 composed of a third NMOS tube 21 and a third PMOS tube 22, a second PMOS tube 23 and a seventh inverter 24, wherein the source terminal of the third PMOS tube 22 is connected to the drain of the second PMOS tube 23, the source of the second PMOS tube 23 is connected to the power supply, and the output terminal of the sixth inverter 20 is connected to the seventh inverter 24 and then input to the gate of the second PMOS tube 23, and the output terminal of the sixth inverter 20 is connected to the output terminal of the fourth inverter 10 and then input to the third inverter 3 to form a global working clock signal.

[0015] The present invention also provides a timing control circuit for FPGA BRAM read-write conflicts, and a timing control method for FPGA BRAM read-write conflicts, comprising a first timing circuit module, a second timing circuit module, a delay circuit module, a configuration judgment circuit module, and a tracking circuit module; The first timing circuit module forms a first working clock signal that enables the BRAM to start working under the combination of the combinational logic switch at the rising edge of the original clock signal, the BRAM working enable signal, and the power-on clear signal; The configuration judgment circuit module is used to determine which conflict configuration bit is, and together with the write configuration bit, forms a working enable signal of the second timing circuit module through a combinational logic switch; The tracking circuit module is used to simulate and track the read and write duration of the storage address unit corresponding to the storage array of the static random access memory of the BRAM. The first working clock signal generated by the first timing circuit module is input into the tracking circuit to start the read and write duration simulation tracking of the storage address unit corresponding to the storage array of the static random access memory. After the tracking is completed, a trigger signal is given, and the trigger signal is input into the delay circuit as the clock signal of the second timing circuit; The second sequential circuit module is used to form a second working clock signal that enables the BRAM to start working under the combination of the combinational logic switch at the rising edge of the clock signal, the BRAM working enable signal, and the power-on clear signal, and the power-on clear signal of the second sequential circuit is connected to the power-on clear signal of the first sequential circuit; The delay circuit is used to delay the trigger signal for a certain period of time and then input the clock signal into the second timing circuit.

[0016] Furthermore, the working clock signals of the first timing circuit module and the second timing circuit module also pass through a pulse width control circuit respectively, which is used to control the pulse width length of the working clock signal at a high level. The first working clock signal generated by the first timing circuit module forms a first global working clock signal after passing through the first pulse width control circuit. The first global working clock signal is input into the tracking circuit. When the analog tracking of the read and write duration of the storage address unit corresponding to the storage array of the static random access memory of the BRAM is completed and a first trigger signal is given, the first trigger signal is input into the first pulse width control circuit to pull down the high level of the first global working clock. The second working clock signal generated by the second timing circuit module forms a second global working clock signal after passing through the second pulse width control circuit. The second global working clock signal is input into the tracking circuit. When the analog tracking of the read and write duration of the storage address unit corresponding to the storage array of the static random access memory of the BRAM is completed and a second trigger signal is given, the second trigger signal is input into the second pulse width control circuit to pull down the high level of the second global working clock signal. The first trigger signal is also input into the delay circuit at the same time and then input into the second timing circuit after delay.

[0017] By adopting the above technical solution, the present invention has the following beneficial effects: The present invention provides a timing control method and circuit for FPGA BRAM read-write conflict. When there is a read-write conflict, two timing circuits are used to generate a working timing. The initial clock acts on the first timing circuit, and the first timing circuit generates a read operation timing. After the read operation of the first timing circuit is completed, the second timing circuit is controlled to generate a write operation timing, thereby achieving the goal of using one timing path to control reading and writing, avoiding competition caused by read-write conflicts, and improving the memory access efficiency of BRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1It is a schematic diagram of the control structure of the timing circuit of the present invention; Figure 2 This is a schematic diagram of the pulse width for completing reading and writing within one cycle of the original clock; Figure 3 It is a schematic diagram of the tracking circuit structure; Figure 4 It is a schematic diagram of the SRAM storage array; Figure 5 It is a schematic diagram of the structure of a unit in the SRAM storage array; Figure 6 Schematic diagram of the line tracking circuit structure; Figure 7 is a schematic diagram of the column tracking circuit structure; Figure 8 This is a schematic diagram of adding a pulse width control circuit after the timing circuit; Fig. 9 It is a schematic diagram of the circuit structure of the timing control circuit module; Fig.10 It is a schematic diagram of the timing control circuit module; Fig.11 It is a schematic diagram of the structure of the timing control circuit of the present invention; Fig.12 This is a schematic diagram of the operation of the row tracking start signal and the column tracking start signal. DETAILED DESCRIPTION

[0019] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] Figures 1 to 12The present invention shows a specific embodiment of a timing control method for FPGA BRAM read-write conflict. When there is a read-write conflict, two timing circuits are used to generate working timing, a first timing circuit and a second timing circuit. The FPGA initial clock acts on the first timing circuit, and the first timing circuit generates a read operation timing. After the first timing circuit completes the read operation, the second timing circuit is controlled to generate a write operation timing; when there is no read-write conflict, the first timing circuit completes the corresponding read or write operation. By using two timing circuits, after the first timing circuit completes the read, the other second timing circuit is controlled to write, so as to achieve the purpose of using one timing path to control read and write, avoiding competition caused by read-write conflicts, and improving the memory access efficiency of BRAM. In this embodiment, when the FPGA initial clock acts on the first timing circuit, it is necessary to combine the BRAM work enable signal (men) and the power-on clear signal (por_reset) for logical combination to generate a first working clock signal (clk1); the clock signal of the second timing circuit is given by the trigger signal of the tracking circuit, as shown in Table 1, the BRAM work enable signal (men) of the second timing circuit is generated by the read-write conflict configuration bit (mix_old_data), the read old number configuration bit (read_old_data), the read enable configuration bit (read_enable) and the write configuration bit (wen) after combinational logic. As long as there is a conflict bit and when the write configuration bit is 1, it is necessary to select the timing path generated by the second timing circuit. The power-on clear signal (por_reset) of the second timing circuit is connected to the power-on clear signal of the first timing circuit. The second timing circuit performs a logical combination of the clock signal, the BRAM work enable signal (men), and the power-on clear signal (por_reset) to generate a working clock signal, as shown in Table 1. Figure 2 As shown, within one cycle of the original clock (clk), the read enable signal (read) is given first, and then the write configuration bit enable signal (wen) is given. WL is the SRAM word line signal. The first pulse is the read pulse width, and the second pulse expresses the write pulse width. The width between the two pulses is the width of the delay module.

[0021] Table 1 Selection of the first sequential circuit and the second sequential circuit under read-write conflict

[0022] In this embodiment, Figure 1As shown, after the first sequential circuit completes the read operation, the method for controlling the second sequential circuit to generate the write operation timing is to track the read operation duration of the first sequential circuit, and after the read operation tracking is completed, give a first trigger signal (Rstb1) of the tracking completion, and send the first trigger signal to the second sequential circuit, so that the second sequential circuit generates a working clock signal to start working. The method for tracking the read operation duration of the first sequential circuit is: use a tracking circuit to simulate the read and write duration of the corresponding storage address unit of the SRAM storage array of the BRAM, input the working clock signal generated by the first sequential circuit to the tracking circuit, and give a first trigger signal after the tracking is completed, and send the first trigger signal to the second sequential circuit. By simulating the reading and writing duration of the SRAM storage unit, it is possible to know how long the SRAM storage unit performs the read operation, and give a trigger signal after the tracking is completed, so that the second sequential circuit starts to work and perform the write operation.

[0023] In this embodiment, Figure 3 As shown, the structure of the tracking circuit includes a row decoding circuit, a row analog tracking circuit, and a column analog tracking circuit; The row decoding circuit is used to determine which row of cells in the static random access memory SRAM storage array is selected to generate a word line signal WL for operation, and at the same time provide a signal for tracking the operation time of the cells in this row; like Figure 4 As shown, the number of cells in the SRAM storage array is m rows and n columns; Figure 5 and Figure 6 As shown, the row simulation tracking circuit uses n pairs of NMOS tubes to simulate the opening time of n units in a row of the word line (WL) in the SRAM storage array. The gates of the n pairs of NMOS tubes are respectively connected to the row tracking start signal. The row tracking start signal is generated by the global working clock signal through the row decoding circuit to determine which row of units are working and then generates a high level. The source and drain of n pairs, that is, 2n NMOS tubes, are connected to the ground signal. After the n pairs of NMOS tubes are charged, a row tracking completion feedback signal is given to trigger the column tracking start signal.

[0024] like Figure 7 The column simulation tracking circuit shown uses m NMOS tubes to simulate the read and write working time of a bit line (BL) in a column of m units in an SRAM storage array. The column tracking start signal is respectively input into the source terminals of the m NMOS tubes, and the gates and drains of the m NMOS tubes are connected to the ground signal; the column tracking start signal is triggered by the feedback signal of the row tracking completion to give the column tracking start signal; the column tracking start signal completes the tracking after the charging of the m NMOS tubes is completed, and gives a trigger signal of the pull-down level.

[0025] In this embodiment, before tracking, it is necessary to pre-count the number of rows m and columns n of the SRAM storage array in the BRAM, such as Figure 4 As shown, the number of NMOS tubes used in the tracking circuit can be determined according to the number of rows m and the number of columns n. Figure 3 In the timing circuit module, the rising edge of the working clock (clk1) is generated. When the rising edge of the working clock (clk1) arrives, it passes through the row decoding circuit and obtains which row of cells in the SRAM storage array in the BRAM needs to be selected to work. On the one hand, the word line (WL) is given to open the cells in the selected row in the SRAM. On the other hand, the row decoding circuit simultaneously gives the row tracking signal TKWL1 to start the row analog tracking circuit to simulate the working time of the word line. Therefore, the row analog tracking circuit is also called the WL tracking circuit. Fig.12 As shown, the row decoding circuit adopts the commonly used row decoding circuit, and generates the word line WL signal of the m row by the x-bit row address encoding, where the relationship between x and m is When the row decoding circuit encodes the x-bit row address to generate the word line WL signal of the m-row, the row tracking start signal TKWL1 for row tracking is triggered, so that the row tracking simulation starts when the word line WL opens a row of cells in the SRAM storage array.

[0026] In this embodiment, Figure 5 The schematic diagram of the structure of a unit in the SRAM storage array shown in the figure, when the word line is high, a pair of NMOS tubes PGL0 and PGR0 in a unit are turned on. In order to simulate the time when the word line turns on all NMOS tubes in a row, there are n units in a row from the previous statistics, so the row simulation tracking circuit is as follows Figure 6 As shown, n pairs of NMOS tubes are used to simulate the opening time of n units on a word line. The gates of the n pairs of NMOS tubes are respectively connected to the line tracking start signal TKWL1. The source and drain of the n pairs, i.e., 2n NMOS tubes, are connected to the ground signal Tielow. When the line tracking start signal is at a high level, the n pairs of NMOS tubes start charging. The completion of charging means that the opening time of each unit is completed. In this embodiment, Figure 6 The source and drain grounding of the NMOS tube in the bank tracking simulation circuit is a wiring method for simulating the cell in the SRAM storage array. This embodiment uses the capacitance between the source and the gate to simulate the parasitic capacitance at the BL bit line in the unit cell, which has no functional effect, only charging and discharging effects. Fig.12 As shown, after the row tracking simulation is completed, the row tracking completion feedback signal TKWLFB1 is given to trigger the column tracking start signal TKBL1. The column tracking start signal starts the simulation tracking of the bit line (BL) in the SRAM storage array, so the column tracking circuit is also called the BL tracking circuit. Fig.12The feedback signal TKWLFB1 of row tracking completion is also given, which passes through a two-stage inverter to give a trigger signal of the column tracking start signal TKBL1. The two-stage inverter is used to strengthen the driving force.

[0027] Figure 4 In the example, each bit line is input and output from the source terminal of the NMOS tube PGL0, so the column analog tracking circuit is as follows Figure 7 As shown, m NMOS tubes are used to simulate the read and write working time of the PGL0 NMOS tube of m cells in a column and m rows in a SRAM storage array. Figure 4 In the figure, BL and BLN carry a pair of opposite data, which come in at the same time and are consistent in time, so there is no need to simulate BLN to PGR0. When the SRAM is working, after the row decoding circuit chooses to open all the cells in the word line of a row, the column decoding circuit opens the corresponding bit lines at the same time according to the number of bits of data to be written. Therefore, the read and write time of multiple columns is consistent with that of one column, so m NMOS tubes in a column can be used for simulation. The column tracking start signal TKBL1 is input to the source of the m NMOS tubes, and the gate and drain are connected to the ground signal Tielow. The reason for this design is that in this embodiment, the m NMOS tubes only use the capacitance between the source and the gate to simulate the parasitic capacitance at the BL bit line in the cell. It has no functional effect, only charging and discharging effects. The gate is connected to the ground signal Tielow to make the NMOS tube in a non-conducting state. Secondly, from Figure 5It can be seen from the unit cell shown that the values ​​of the two points Q and QB in the cell must be one 0 and one 1, so the drain of one of the PGL0 NMOS tube and the PGR0 NMOS tube is always connected to 0. Since the cell is symmetrical, the PGL0 NMOS tube and the PGR0 NMOS tube are operated at the same time, so the simulation of the cell working process time only needs to simulate the NMOS tube on one side, so in the column tracking circuit, the drain of the NMOS tube is also connected to the ground signal tielow. In the SRAM storage array, the BL bit line is connected to the source of the NMOS tube, so in this embodiment, the column tracking start signal TKBL1 is connected to the source of m NMOS tubes. In addition, when the BRAM is working, only one row in the SRAM storage array will be opened at a time, that is, only one of the m PGL0 NMOS tubes on the BL bit line will be opened, and the gates of the other m-1 PGL0 NMOS are all closed at low voltage. In this embodiment, since the number of rows m of cells in the SRAM is a large value when designed, and when a large number of NMOS tubes are used in the same way, the time required for charging the source and gate capacitors when the gate of one NMOS tube is turned on and the time required for charging the source and gate capacitors when the gate of one NMOS tube is not turned on are very similar, m NMOS tube gates are connected to tielow to simulate m rows of cells. The column tracking start signal completes the tracking after the charging of the m NMOS tubes is completed. After the column simulation tracking is completed, a trigger signal (Rstb1) is given to complete the tracking and pull down the high-level global clock working signal (clkint1). When the trigger signal (Rstb1) is low, the global clock working signal (clkint1) is pulled down to a low level to complete the control of the pulse width.

[0028] from Figure 3 It can also be seen that BRAM is completely symmetrical. Before using BRAM, it is necessary to configure whether to use a single port or a dual port. In the case of a single port, use the tracking circuit on the corresponding side of the port for tracking. Use WL, BL and the global clock working signal (clkint1), or use WR, BR and the global clock working signal (clkint2). If dual ports are configured, then the tracking circuits on both sides need to be used to track the ports on each side respectively.

[0029] In this embodiment, Figure 1 As shown, in order to prevent the read operation from being incomplete when the trigger signal generated by the tracking circuit enters the second timing circuit, a delay circuit is also used. When the first trigger signal for the second timing circuit to start writing is given after the first timing circuit has finished reading, the first trigger signal is delayed to meet the timing control of the write operation of the second timing circuit module after the timing of the first timing circuit module controlling the read operation is fully completed.

[0030] In this embodiment, after the working clock signals of the first sequential circuit and the second sequential circuit, they also pass through a pulse width control circuit respectively, such as Figure 8 , Fig. 9 and Fig.10 As shown, it is used to control the pulse width length of the working clock signal at a high level. The first working clock signal (clk1) generated by the first timing circuit forms a first global working clock signal (clkint1) after passing through the first pulse width control circuit. The first global working clock signal (clkint1) is input into the tracking circuit. When the analog tracking of the read and write duration of the corresponding storage address unit of the SRAM storage array of the BRAM is completed and a trigger signal (Rstb1) is given, the trigger signal (Rstb1) is input into the first pulse width control circuit to pull down the high level of the global working clock (clkint1). The second timing circuit The generated second working clock signal (clk2) forms a second global working clock signal (clkint2) after passing through the second pulse width control circuit. The second global working clock signal (clkint2) is input into the tracking circuit. When the analog tracking of the read and write duration of the corresponding storage address unit of the SRAM storage array of the BRAM is completed and the second trigger signal (Rstb2) is given, the second trigger signal (Rstb2) is input into the second pulse width control circuit to pull down the high level of the global working clock (clkint2). The first trigger signal (Rstb1) is also input into the delay circuit and then input into the second timing circuit after delay. The first timing circuit and the first pulse width control circuit are referred to as the first timing control circuit, and the second timing circuit and the second pulse width control circuit are referred to as the second timing control circuit.

[0031] In this embodiment, Figure 8 As shown, the pulse width control circuit module structure includes a third inverter 3 and a first inverter 1 with a low level keeper, and a second inverter 2 with a high level keeper. The output ends of the first inverter 1 and the second inverter 2 are connected to the third inverter 3. The output end of the third inverter 3 is a global working clock signal (clkint1). The working clock signal (clk1) is input into the second inverter 2, and the trigger signal of the falling edge is input into the first inverter 1.

[0032] The first inverter 1 with a low level keeper includes a fourth inverter 10 composed of a first NMOS tube 11 and a first PMOS tube 12, a second NMOS tube 13 and a fifth inverter 14, the source terminal of the first NMOS tube 11 is connected to the drain of the second NMOS tube 13, the source of the second NMOS tube 13 is grounded, and the output terminal of the fourth inverter 10 is connected to the fifth inverter 14 and then input to the gate of the second NMOS tube 13, the output terminal of the fourth inverter 10 is connected to the output terminal of the second inverter 2 and then input to the third inverter 3 to form a global working clock signal (clkint1); The second inverter 2 with a high level keeper includes a sixth inverter 20 composed of a third NMOS tube 21 and a third PMOS tube 22, a second PMOS tube 23 and a seventh inverter 24, wherein the source terminal of the third PMOS tube 22 is connected to the drain of the second PMOS tube 23, the source of the second PMOS tube 23 is connected to the power supply, and the output terminal of the sixth inverter 20 is connected to the seventh inverter 24 and then input to the gate of the second PMOS tube 23, and the output terminal of the sixth inverter 20 is connected to the output terminal of the fourth inverter 10 and then input to the third inverter 3 to form a global working clock signal (clkint1).

[0033] By using the pulse width control circuit module, the length of the high level of the global working clock signal (clkint1) at a high level can be controlled. The specific working principle is as follows: when clk1 is at a high level, it is converted to a low level through the sixth inverter 20. Figure 8 As can be seen from the figure, at this time, clkintb1 is at a low level, so the output terminal signal (clkintb1) of the sixth inverter 20 is at a low level and changes to a high level after passing through the seventh inverter 24, and the second PMOS tube 23 is turned off. In the first inverter 1 with a low level maintainer, the low level signal (clkintb1) is input into the fifth inverter 14 and changes to a high level, and the second NMOS tube 13 is turned on. Since the source of the second NMOS tube 13 is grounded, the output terminal signal (clkintb1) of the sixth inverter 20 is always maintained at a low level, and the low level signal (clkintb1) is the global clock working signal (clkint1) after passing through the inverter and is always maintained at a high level.

[0034] The present invention also provides a timing control circuit for FPGA BRAM read-write conflicts, using the aforementioned timing control method for FPGA BRAM read-write conflicts, such as Figure 1 As shown, it includes a first sequential circuit module, a second sequential circuit module, a delay circuit module, a configuration judgment circuit module and a tracking circuit module; The first timing circuit module forms a first working clock signal (clk1) to start the BRAM working under the combination of the combinational logic switch at the rising edge of the original clock signal (clk) and the BRAM working enable signal (men) and the power-on clear signal (por_reset); The configuration judgment circuit module is used to judge which type of conflicting configuration bit it is, and together with the write configuration bit, forms a working enable signal (men) of the second sequential circuit module through a combinational logic switch; the conflicting configuration bits in this embodiment include a read-write conflict configuration bit (mix_old_data), a read old number configuration bit (read_old_data), a read enable configuration bit (read_enable) and a write configuration bit (wen), which are generated after combinational logic. When the second sequential circuit is used, the write configuration bit (wen) is 1.

[0035] The tracking circuit module is used to simulate the read and write duration of the storage address unit corresponding to the SRAM storage array of the BRAM. The first working clock signal (clk1) generated by the first timing circuit module is input into the tracking circuit to start the simulation tracking of the read and write duration of the storage address unit corresponding to the SRAM storage array. After the tracking is completed, the first trigger signal (Rstb1) is given, and the first trigger signal (Rstb1) is input into the delay circuit as the clock signal (clk) of the second timing circuit. The second sequential circuit module is used to form a second working clock signal (clk2) for starting the BRAM to work under the combination of the combinational logic switch at the rising edge of the clock signal (clk) and the BRAM working enable signal (men) and the power-on clear signal (por_reset), and the power-on clear signal (por_reset) of the second sequential circuit is connected to the power-on clear signal (por_reset) of the first sequential circuit; The delay circuit is used to delay the trigger signal (Rstb1) for a certain period of time and then input the clock signal into the second timing circuit.

[0036] like Fig.11As shown, the working clock signals of the first timing circuit module and the second timing circuit module also pass through a pulse width control circuit respectively, which is used to control the pulse width length of the working clock signal at a high level. After the first working clock signal (clk1) generated by the first timing circuit module passes through the first pulse width control circuit, a first global working clock signal (clkint1) is formed. The first global working clock signal (clkint1) is input into the tracking circuit. When the analog tracking of the read and write duration of the corresponding storage address unit of the SRAM storage array of the BRAM is completed and the first trigger signal (Rstb1) is given, the first trigger signal (Rstb1) is input into the first pulse width control circuit to convert the first global working clock signal The high level of (clkint1) is pulled down, and the second working clock signal (clk2) generated by the second timing circuit module passes through the second pulse width control circuit to form a second global working clock signal (clkint2). The second global working clock signal (clkint2) is input into the tracking circuit. When the read and write duration simulation tracking of the corresponding storage address unit of the SRAM storage array of the BRAM is completed and the second trigger signal (Rstb2) is given, the second trigger signal (Rstb2) is input into the second pulse width control circuit to pull down the high level of the second global working clock signal (clkint2). The first trigger signal (Rstb1) is also input into the delay circuit at the same time, and then input into the second timing circuit after delay.

[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A timing control method for FPGA BRAM read-write conflict, characterized in that: When there is a read-write conflict, two timing circuits are used to generate the working timing, the first timing circuit and the second timing circuit. The FPGA initial clock acts on the first timing circuit, and the first timing circuit generates the read operation timing. After the read operation of the first timing circuit is completed, the second timing circuit is controlled to generate the write operation timing. When there is no read-write conflict, the first sequential circuit completes the corresponding read or write operation; After the first sequential circuit completes the read operation, the method of controlling the second sequential circuit to generate the write operation timing is to track the read operation duration of the first sequential circuit, and after the read operation tracking is completed, give a trigger signal of tracking completion, and send the trigger signal to the second sequential circuit, so that the second sequential circuit generates a working clock signal to start working; The method for tracking the read operation duration of the first sequential circuit is as follows: a tracking circuit is used to simulate the read and write duration of the storage address unit corresponding to the storage array of the static random access memory of the BRAM, the first working clock signal generated by the first sequential circuit is input to the tracking circuit, the tracking circuit gives a trigger signal after the tracking is completed, and the trigger signal is sent to the second sequential circuit as the second sequential circuit generates a second working clock signal to start working; The structure of the tracking circuit includes a row decoding circuit, a row analog tracking circuit, and a column analog tracking circuit; The row decoding circuit is used to determine which row of cells in the storage array of the static random access memory is selected to generate a word line signal WL for operation, and at the same time provide a signal for tracking the operation time of the cells in this row; The row simulation tracking circuit uses n pairs of NMOS tubes to simulate the opening time of n units in a row of the storage array of the static random access memory. The gates of the n pairs of NMOS tubes are respectively connected to the row tracking start signal. The row tracking start signal is generated by the global working clock signal after the row decoding circuit determines which row of units are working and generates a high level. The source and drain of the n pairs of NMOS tubes are connected to the ground signal. After the n pairs of NMOS tubes are charged, a row tracking completion feedback signal is given. The column simulation tracking circuit uses m NMOS tubes to simulate the read and write working time of a column of m units in the storage array of the static random access memory, and the column tracking start signal is respectively input into the source ends of the m NMOS tubes, and the gates and drains of the m NMOS tubes are connected to the ground signal; The column tracking start signal is triggered by the row tracking completion feedback signal. The column tracking start signal completes the tracking after charging of m NMOS tubes and gives a trigger signal for the pull-down level.

2. The method according to claim 1, characterized in that It also includes a delay circuit, which is used to delay the trigger signal when the second timing circuit starts writing after the first timing circuit finishes reading, so as to enter the write operation timing control of the second timing circuit module after the timing of the first timing circuit module controlling the read operation is fully completed.

3. The method according to claim 2, characterized in that When the FPGA initial clock acts on the first timing circuit, it needs to be logically combined with the BRAM work enable signal and the power-on clear signal to generate the first working clock signal; The clock signal of the second timing circuit is given by the trigger signal of the tracking circuit, and the BRAM work enable signal of the second timing circuit is generated after the read-write conflict configuration bit, the read old number configuration bit, the read enable configuration bit and the write configuration bit through combination logic. The power-on clear signal of the second timing circuit is connected to the power-on clear signal of the first timing circuit. The second timing circuit performs a logical combination of the clock signal, the BRAM work enable signal and the power-on clear signal to generate a second working clock signal.

4. The method according to claim 3, characterized in that After the working clock signals of the first timing circuit and the second timing circuit, they also pass through a pulse width control circuit respectively, which is used to control the pulse width length of the working clock signal at a high level. The first working clock signal generated by the first timing circuit forms a first global working clock signal after passing through the first pulse width control circuit. The first global working clock signal is input into the tracking circuit. When the analog tracking of the read and write duration of the storage address unit corresponding to the storage array of the static random access memory of the BRAM is completed and a first trigger signal is given, the first trigger signal is input into the first pulse width control circuit to pull down the high level of the first global working clock. The second working clock signal generated by the second timing circuit forms a second global working clock signal after passing through the second pulse width control circuit. The second global working clock signal is input into the tracking circuit. When the analog tracking of the read and write duration of the storage address unit corresponding to the storage array of the static random access memory of the BRAM is completed and a second trigger signal is given, the second trigger signal is input into the second pulse width control circuit to pull down the high level of the second global working clock signal. The first trigger signal is also input into the delay circuit at the same time and then input into the second timing circuit after delay.

5. The method according to claim 4, characterized in that The pulse width control circuit module structure comprises a third inverter (3), a first inverter (1) with a low level keeper, and a second inverter (2) with a high level keeper, the output ends of the first inverter (1) and the second inverter (2) are connected to the third inverter (3), the output end of the third inverter (3) is a global working clock signal, the working clock signal is input into the second inverter (2), and the trigger signal of the falling edge is input into the first inverter (1).

6. The method according to claim 5, characterized in that The first inverter (1) with a low-level keeper comprises a fourth inverter (10) composed of a first NMOS tube (11) and a first PMOS tube (12), a second NMOS tube (13) and a fifth inverter (14); the source terminal of the first NMOS tube (11) is connected to the drain of the second NMOS tube (13); the source of the second NMOS tube (13) is grounded; the output terminal of the fourth inverter (10) is connected to the fifth inverter (14) and then input to the gate of the second NMOS tube (13); the output terminal of the fourth inverter (10) is connected to the output terminal of the second inverter (2) and then input to the third inverter (3) to form a global working clock signal; The second inverter (2) with a high level keeper comprises a sixth inverter (20) composed of a third NMOS tube (21) and a third PMOS tube (22), a second PMOS tube (23) and a seventh inverter (24); the source terminal of the third PMOS tube (22) is connected to the drain of the second PMOS tube (23); the source of the second PMOS tube (23) is connected to a power supply; the output terminal of the sixth inverter (20) is connected to the seventh inverter (24) and then input to the gate of the second PMOS tube (23); the output terminal of the sixth inverter (20) is connected to the output terminal of the fourth inverter (10) and then input to the third inverter (3) to form a global working clock signal.

7. A timing control circuit for FPGA BRAM read / write conflicts, using a timing control method for FPGA BRAM read / write conflicts according to any one of claims 1 to 6, characterized in that: It includes a first sequential circuit module, a second sequential circuit module, a delay circuit module, a configuration judgment circuit module and a tracking circuit module; The first timing circuit module forms a first working clock signal that enables the BRAM to start working under the combination of the rising edge of the original clock signal, the BRAM working enable signal, and the power-on clear signal through the combinational logic switch; The configuration judgment circuit module is used to determine which conflict configuration bit is, and together with the write configuration bit, forms a working enable signal of the second timing circuit module through a combinational logic switch; The tracking circuit module is used to simulate and track the read and write duration of the storage address unit corresponding to the storage array of the static random access memory of the BRAM. The first working clock signal generated by the first timing circuit module is input into the tracking circuit to start the read and write duration simulation tracking of the storage address unit corresponding to the storage array of the static random access memory. After the tracking is completed, a trigger signal is given, and the trigger signal is input into the delay circuit as the clock signal of the second timing circuit; The second sequential circuit module is used to form a second working clock signal that enables the BRAM to start working under the combination of the combinational logic switch at the rising edge of the clock signal, the BRAM working enable signal, and the power-on clear signal, and the power-on clear signal of the second sequential circuit is connected to the power-on clear signal of the first sequential circuit; The delay circuit is used to delay the trigger signal for a certain period of time and then input the clock signal into the second timing circuit.

8. The timing control circuit according to claim 7, characterized in that: The working clock signals of the first sequential circuit module and the second sequential circuit module also pass through a pulse width control circuit respectively, which is used to control the pulse width length of the working clock signal at a high level. The first working clock signal generated by the first sequential circuit module forms a first global working clock signal after passing through the first pulse width control circuit. The first global working clock signal is input into the tracking circuit. When the analog tracking of the read and write duration of the storage address unit corresponding to the storage array of the static random access memory of the BRAM is completed and a first trigger signal is given, the first trigger signal is input into the first pulse width control circuit to pull down the high level of the first global working clock. The second working clock signal generated by the second sequential circuit module forms a second global working clock signal after passing through the second pulse width control circuit. The second global working clock signal is input into the tracking circuit. When the analog tracking of the read and write duration of the storage address unit corresponding to the storage array of the static random access memory of the BRAM is completed and a second trigger signal is given, the second trigger signal is input into the second pulse width control circuit to pull down the high level of the second global working clock signal. The first trigger signal is also input into the delay circuit at the same time and then input into the second sequential circuit after delay.

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