True random sequence generation circuit, true random number generator and memory

Abstract

The invention provides a true random sequence generation circuit, a true random number generator and a memory. The true random sequence generation circuit comprises a low-frequency oscillator, a first high-frequency oscillator and a double-edge sampling circuit, a low frequency oscillator configured to generate a low frequency pulse signal; a first high frequency oscillator configured to generate a first high frequency pulse signal; the periodic jitter value of the low-frequency pulse signal is greater than the oscillation period value of the first high-frequency pulse signal; and the double-edge sampling circuit is connected with the low-frequency oscillator and the first high-frequency oscillator, and is configured to receive the low-frequency pulse signal and the first high-frequency pulse signal, sample the first high-frequency pulse signal according to the low-frequency pulse signal and an inversion signal of the low-frequency pulse signal, and output a first true random sequence.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a true random sequence generation circuit, a true random number generator and a memory. Background Art

[0002] Random number generators are divided into pseudo-random number generators (PRNG) and true random number generators (TRNG). Pseudo-random number generators are used in many digital systems. Pseudo-random number generators generally use mathematical algorithms to generate random number sequences. When using a pseudo-random generator, a "seed" (initial value) must be provided, and then the random number generator generates a random number sequence according to this "seed". In this way, if the "seed" is stolen by an attacker, the random number sequence will no longer be random, greatly reducing the unpredictability of the random sequence.

[0003] In a memory, a defense circuit for resisting a row hammer attack and other types of circuits generally utilize a random signal sampling circuit for random sampling. If the random signal sampling circuit uses a pseudo-random number generator, the defense capability of the circuit will be reduced. Summary of the invention

[0004] In view of this, the embodiments of the present disclosure provide a true random sequence generation circuit, a true random number generator and a memory to improve the randomness of true random numbers.

[0005] The technical solution of the present invention is achieved in this way:

[0006] The present disclosure provides a true random sequence generating circuit, comprising: a low-frequency oscillator, a first high-frequency oscillator and a double-edge sampling circuit; wherein the low-frequency oscillator is configured to generate a low-frequency pulse signal; the first high-frequency oscillator is configured to generate a first high-frequency pulse signal; wherein the period jitter value of the low-frequency pulse signal is greater than the oscillation period value of the first high-frequency pulse signal; the double-edge sampling circuit is connected to the low-frequency oscillator and the first high-frequency oscillator, configured to receive the low-frequency pulse signal and the first high-frequency pulse signal, and samples the first high-frequency pulse signal according to the low-frequency pulse signal and the inverted signal of the low-frequency pulse signal, and outputs a first true random sequence.

[0007] In the above scheme, the true random sequence generating circuit also includes a logic operation circuit; the logic operation circuit is connected to the double-edge sampling circuit and the low-frequency oscillator, and is configured to receive a first true random sequence and a low-frequency pulse signal, and perform a logic operation on the first true random sequence and the low-frequency pulse signal to generate a second true random sequence.

[0008] In the above scheme, the logic operation circuit is an XOR gate, an XNOR gate or an AND gate.

[0009] In the above scheme, the double-edge sampling circuit includes: a first trigger, a second trigger, a first selector and a first inverter; wherein the first trigger is connected to the low-frequency oscillator and the first high-frequency oscillator, and is configured to receive a low-frequency pulse signal and a first high-frequency pulse signal, and samples the first high-frequency pulse signal according to the low-frequency pulse signal, and outputs a first sampling signal; the first inverter is connected to the low-frequency oscillator, and is configured to receive the low-frequency pulse signal and generate an inverted signal of the low-frequency pulse signal; the second trigger is connected to the first inverter and the first high-frequency oscillator, and is configured to receive the inverted signal of the low-frequency pulse signal and the first high-frequency pulse signal, and samples the first high-frequency pulse signal according to the inverted signal of the low-frequency pulse signal, and outputs a second sampling signal; the first selector is connected to the first trigger, the second trigger and the low-frequency oscillator, and is configured to receive the first sampling signal, the second sampling signal and the low-frequency pulse signal, and based on the low-frequency pulse signal, selects to output the first sampling signal or the second sampling signal to generate a first true random sequence.

[0010] In the above scheme, the low-frequency oscillator includes: a voltage-controlled oscillator and a Boolean oscillator; wherein the voltage-controlled oscillator includes: a current-controlled inverter, a Schmitt trigger and a second inverter; the output end of the current-controlled inverter is connected to the input end of the Schmitt trigger, and the output end of the Schmitt trigger is connected to the second inverter; the voltage-controlled oscillator is configured to receive an input signal and generate a sampling clock signal based on the input signal; the Boolean oscillator is connected to the voltage-controlled oscillator, configured to receive the sampling clock signal and the input signal, generate an initial low-frequency pulse signal according to the input signal, and sample the initial low-frequency pulse signal according to the sampling clock signal to generate a low-frequency pulse signal.

[0011] In the above scheme, the first high-frequency oscillator includes: a Fibonacci oscillation ring and a two-frequency division circuit; wherein the Fibonacci oscillation ring is configured to generate an initial first high-frequency pulse signal; the two-frequency division circuit is connected to the Fibonacci oscillation ring, configured to receive the initial first high-frequency pulse signal, and processes the initial first high-frequency pulse signal to generate a first high-frequency pulse signal.

[0012] The present disclosure also provides a true random number generator, including the true random sequence generating circuit in the above scheme; the true random number generator also includes: a second high-frequency oscillator and a counting circuit; wherein the second high-frequency oscillator is configured to generate a second high-frequency pulse signal; the counting circuit is connected to the second high-frequency oscillator and the true random sequence generating circuit, and is configured to receive a counting enable signal and a second high-frequency pulse signal, and count the second high-frequency pulse signal when the counting enable signal is at a high level and / or a low level, and output a true random number; the counting enable signal is the first true random sequence or the second true random sequence.

[0013] In the above scheme, the counting circuit includes: a first counting subcircuit, a second counting subcircuit, a third inverter and a second selector; wherein the first counting subcircuit is connected to the second high-frequency oscillator and the true random sequence generating circuit, and is configured to receive a counting enable signal, and count the second high-frequency pulse signal according to the counting enable signal to generate a first counting result;

[0014] The third inverter is connected to the true random sequence generating circuit, configured to receive a counting enable signal and generate an inverted signal of the counting enable signal; the second counting sub-circuit is connected to the second high-frequency oscillator and the third inverter, configured to receive the inverted signal of the counting enable signal, and count the second high-frequency pulse signal according to the inverted signal of the counting enable signal to generate a second counting result; the second selector is connected to the first counting sub-circuit and the second counting sub-circuit, configured to receive the first counting result and the second counting result, and select to output the first counting result or the second counting result according to the counting enable signal to generate a true random number.

[0015] In the above scheme, the counting trigger condition of the first counting sub-circuit and the counting reset condition of the second counting sub-circuit are both receiving a high level of the counting enable signal; the counting reset condition of the first counting sub-circuit and the counting trigger condition of the second counting sub-circuit are both receiving a high level of the inverted signal of the counting enable signal.

[0016] In the above scheme, the first counting subcircuit includes: a first AND gate and a first counter; the second counting subcircuit includes: a second AND gate and a second counter; wherein the input end of the first AND gate is connected to the output end of the second high-frequency oscillator and the true random sequence generating circuit, and the output end of the first AND gate is connected to the input end of the first counter; the control end of the first counter is connected to the output end of the true random sequence generating circuit; the output end of the first counter is connected to the input end of the second selector; the input end of the second AND gate is connected to the output end of the second high-frequency oscillator and the third inverter, and the output end of the second AND gate is connected to the input end of the second counter; the control end of the second counter is connected to the output end of the true random sequence generating circuit; and the output end of the second counter is connected to the input end of the second selector.

[0017] The present disclosure provides a memory, which includes the true random number generator in the above solution.

[0018] The present disclosure provides a true random sequence generation circuit, comprising: a low-frequency oscillator, a first high-frequency oscillator and a double-edge sampling circuit; wherein the low-frequency oscillator is configured to generate a low-frequency pulse signal; the first high-frequency oscillator is configured to generate a first high-frequency pulse signal; wherein the period jitter value of the low-frequency pulse signal is greater than the oscillation period value of the first high-frequency pulse signal; the double-edge sampling circuit is connected to the low-frequency oscillator and the first high-frequency oscillator, and is configured to receive the low-frequency pulse signal and the first high-frequency pulse signal, and sample the first high-frequency pulse signal according to the low-frequency pulse signal and the inverted signal of the low-frequency pulse signal, and output a first true random sequence. In this way, the double-edge sampling circuit can sample both the rising edge and the falling edge of the low-frequency pulse signal, so that, compared with the method of sampling using only one of the rising edge and the falling edge of the low-frequency pulse signal, the randomness of the true random sequence in the present disclosure comes from the phase jitter of the rising edge and the falling edge of the low-frequency pulse signal, and the number of edges of the randomness source is more, so that the randomness of the true random sequence can be further improved. At the same time, the present disclosure improves the sampling rate of the low-frequency pulse signal, thereby being able to reduce the oscillation period value of the true random sequence and improve the bit rate of the true random sequence. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of a circuit structure of a true random sequence generation circuit provided in an embodiment of the present disclosure Figure 1 ;

[0020] Figure 2 A timing diagram of a true random sequence generation circuit provided in an embodiment of the present disclosure;

[0021] Figure 3 A schematic diagram of a circuit structure of a true random sequence generation circuit provided in an embodiment of the present disclosure Figure 2 ;

[0022] Figure 4 A schematic diagram of the circuit structure of a double-edge sampling circuit provided in an embodiment of the present disclosure;

[0023] Figure 5 A schematic diagram of the circuit structure of a low frequency oscillator provided in an embodiment of the present disclosure Figure 1 ;

[0024] Figure 6 A schematic diagram of the circuit structure of a low frequency oscillator provided in an embodiment of the present disclosure Figure 2 ;

[0025] Figure 7 A schematic diagram of the circuit structure of a first high frequency oscillator provided in an embodiment of the present disclosure;

[0026] Figure 8 A schematic diagram of the circuit structure of a true random number generator provided in an embodiment of the present disclosure Figure 1 ;

[0027] Fig. 9 A timing diagram of a true random number generator provided in an embodiment of the present disclosure;

[0028] Fig.10 A schematic diagram of the circuit structure of a counting circuit provided in an embodiment of the present disclosure;

[0029] Fig.11 A schematic diagram of the circuit structure of a second high frequency oscillator provided in an embodiment of the present disclosure;

[0030] Fig.12 A schematic diagram of the circuit structure of a true random number generator provided in an embodiment of the present disclosure Figure 2 ;

[0031] Fig.13 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0033] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0034] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0036] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0037] The following is an explanation of the terms used in the embodiments of the present disclosure.

[0038] Period jitter: It is defined as the deviation of the signal cycle time from a certain number of randomly selected ideal clock signal cycles.

[0039] Phase jitter: It is defined as the deviation between the actual edge position and the ideal edge position.

[0040] The oscillation period is defined as the time interval during which a periodic signal repeats periodically.

[0041] Figure 1 is a circuit schematic diagram of an optional true random sequence generation circuit provided by an embodiment of the present disclosure, refer to Figure 1 , the true random sequence generation circuit 100 includes: a low frequency oscillator (Low Frequency Oscillator) 10, a first high frequency oscillator (Fast Oscillator 1) 20 and a double edge sampling circuit 30. Among them, the low frequency oscillator 10 is configured to generate a low frequency pulse signal L (Input_L). The first high frequency oscillator 20 is configured to generate a first high frequency pulse signal H1 (Input_H1). The period jitter value of the low frequency pulse signal L is greater than the oscillation period value of the first high frequency pulse signal H1. The double edge sampling circuit 30 is connected to the low frequency oscillator 10 and the first high frequency oscillator 20, and is configured to receive the low frequency pulse signal L and the first high frequency pulse signal H1, and according to the low frequency pulse signal L and the inverted signal of the low frequency pulse signal L, the first high frequency pulse signal H1 is sampled, and the first true random sequence P1 (Pulse1) is output.

[0042] It should be noted that, in the embodiments of the present disclosure, reference is made to Figure 1, when the period jitter value of the low-frequency pulse signal L is greater than the oscillation period value of the first high-frequency pulse signal H1, the first high-frequency pulse signal H1 is sampled using the low-frequency pulse signal L, and the generated sampling signal will have true randomness. The jitter standard deviation of the low-frequency pulse signal L can be more than 10 times the oscillation period value of the first high-frequency pulse signal H1.

[0043] In the present disclosure, continue to refer to Figure 1 , the low-frequency oscillator 10 can generate a low-frequency pulse signal L, and the first high-frequency oscillator 20 can generate a first high-frequency pulse signal H1. The double-edge sampling circuit 30 samples the first high-frequency pulse signal H1 according to the low-frequency pulse signal L and the inverted signal of the low-frequency pulse signal L, and outputs a first true random sequence P1. For example, the double-edge sampling circuit 30 samples the first high-frequency pulse signal H1 with the rising edge of the low-frequency pulse signal L and the rising edge of the inverted signal of the low-frequency pulse signal L as the trigger conditions for sampling. Since the rising edge of the inverted signal of the low-frequency pulse signal L is equivalent to the falling edge of the low-frequency pulse signal L, that is, the double-edge sampling circuit 30 samples the first high-frequency pulse signal H1 with the rising edge and the falling edge of the low-frequency pulse signal L as the trigger conditions for sampling, and outputs the first true random sequence P1. In this way, the randomness of the first true random sequence P1 comes from the phase jitter of the rising edge and the falling edge of the low-frequency pulse signal L.

[0044] It can be understood that in the embodiment of the present disclosure, the randomness of the first true random sequence P1 comes from the phase jitter of the rising edge and the falling edge of the low-frequency pulse signal L (phase jitter of two edges); compared with the true random sequence whose randomness comes from periodic jitter (phase jitter of a single edge), the number of edges from which the randomness of the first true random sequence of the present disclosure comes is greater, thereby being able to further improve the randomness of the true random sequence.

[0045] At the same time, in the embodiment of the present disclosure, the double-edge sampling circuit 30 can sample both the rising edge and the falling edge of the low-frequency pulse signal L; compared with the method of using only one of the rising edge and the falling edge of the low-frequency pulse signal L for sampling, the present disclosure has more sampling times within one oscillation cycle, thereby being able to improve the sampling rate of the low-frequency pulse signal L, thereby reducing the oscillation period value of the true random sequence and improving the bit rate of the true random sequence.

[0046] Figure 2 It is a circuit schematic diagram of another optional true random sequence generating circuit provided in an embodiment of the present disclosure.

[0047] In some embodiments of the present disclosure, reference Figure 2The true random sequence generating circuit 100 further includes a logic operation circuit 40. The logic operation circuit 40 is connected to the double-edge sampling circuit 30 and the low-frequency oscillator 10, and is configured to receive the first true random sequence P1 and the low-frequency pulse signal L, and perform a logic operation on the first true random sequence P1 and the low-frequency pulse signal L to generate a second true random sequence P2 (Pulse2).

[0048] Figure 3 is a timing diagram of an optional true random sequence generating circuit 100 provided in an embodiment of the present disclosure. It should be noted that, referring to Figure 3 , if the setup time and hold time of the trigger are not met, metastability may occur. At this time, the output of the trigger is in an uncertain state for a long time after the rising edge or falling edge, causing the output signal to have hazard. Since the first true random sequence P1 and the low-frequency pulse signal L can both come from the output of the trigger, the first true random sequence P1 and the low-frequency pulse signal L will both exist. Figure 3 The burr shown.

[0049] In the present disclosure, continue to refer to Figure 2 , the logic operation circuit 40 performs a logic operation on the first true random sequence P1 and the low-frequency pulse signal L to generate a second true random sequence P2. Figure 3 As shown, an XOR operation is performed on the first true random sequence P1 and the low-frequency pulse signal L to generate a second true random sequence P2; Figure 3 There are no glitches in the second true random sequence P2. In this way, the glitches of the first true random sequence P1 and the low-frequency pulse signal L will be filtered out by the gate circuit (such as an XOR gate, etc.) in the logic operation circuit 40, thereby improving the signal quality of the second true random sequence P2. At the same time, the glitches of the first true random sequence P1 and the low-frequency pulse signal L can provide a metastable state, increase the randomness of the logic operation result, and the logic operation circuit 40 can effectively superimpose the phase jitter of the first true random sequence P1 and the low-frequency pulse signal L; that is, the randomness of the phase jitter of the second true random sequence P2 is increased, thereby further improving the randomness of the second true random sequence P2.

[0050] In some embodiments of the present disclosure, reference Figure 2 , the logic operation circuit 40 is an XOR gate, an XNOR gate or an AND gate.

[0051] In the present disclosure, continue to refer to Figure 2 , the logic operation circuit 40 is an XOR gate, an XNOR gate or an AND gate. Figure 3As shown, when the logic operation circuit 40 is an XOR gate, when the level states of the first true random sequence P1 and the low-frequency pulse signal L are the same, the first true random sequence 104 is a low level; when the level states of the first true random sequence P1 and the low-frequency pulse signal L are opposite, the first true random sequence 104 is a high level.

[0052] Figure 4 3 is a schematic diagram of the circuit structure of an optional double-edge sampling circuit 30 provided in an embodiment of the present disclosure. It should be noted that both the first trigger 310 and the second trigger 320 can be D-type triggers (Data Flip-Flop, DFF). CLK is the clock terminal, D is the input terminal, and Q is the output terminal.

[0053] In some embodiments of the present disclosure, reference Figure 4 The double-edge sampling circuit 30 includes: a first trigger 310, a second trigger 320, a first selector 330 and a first inverter 340. The first trigger 310 is connected to the low-frequency oscillator 10 and the first high-frequency oscillator 20, and is configured to receive the low-frequency pulse signal L and the first high-frequency pulse signal H1, and samples the first high-frequency pulse signal H1 according to the low-frequency pulse signal L, and outputs a first sampling signal. The first inverter 340 is connected to the low-frequency oscillator 10, and is configured to receive the low-frequency pulse signal L, and generate an inverted signal of the low-frequency pulse signal L. The second trigger 320 is connected to the first inverter 340 and the first high-frequency oscillator 20, and is configured to receive the inverted signal of the low-frequency pulse signal L and the first high-frequency pulse signal H1, and samples the first high-frequency pulse signal H1 according to the inverted signal of the low-frequency pulse signal L, and outputs a second sampling signal. The first selector 330 is connected to the first trigger 310, the second trigger 320 and the low-frequency oscillator 10, and is configured to receive the first sampling signal, the second sampling signal and the low-frequency pulse signal L, and based on the low-frequency pulse signal L, selects to output the first sampling signal or the second sampling signal to generate a first true random sequence P1.

[0054] In the present disclosure, continue to refer to Figure 4, the input terminal D of the first trigger 310 and the input terminal D of the second trigger 320 are both connected to the first high-frequency oscillator 20 to receive the first high-frequency pulse signal H1 generated by the first high-frequency oscillator 20, that is, the first high-frequency pulse signal H1 is the input signal of the first trigger 310 and the second trigger 320. The clock terminal CLK of the first trigger 310 is connected to the low-frequency oscillator 10, and the clock terminal CLK of the second trigger 320 is connected to the low-frequency oscillator 10 through the first inverter 340. For example, the first trigger 310 uses the low-frequency pulse signal L as the clock signal, and takes the rising edge of the low-frequency pulse signal L as the trigger condition to sample the first high-frequency pulse signal H1 to generate a first sampling signal. The second trigger 320 uses the inverted signal of the low-frequency pulse signal L as the clock signal, and takes the rising edge of the inverted signal of the low-frequency pulse signal L as the trigger condition to sample the first high-frequency pulse signal H1 to generate a second sampling signal.

[0055] Further, continue to refer to Figure 4 , the first selector 330 can select to output the first sampling signal or the second sampling signal based on the low-frequency pulse signal L to generate a first true random sequence P1. For example, when the low-frequency pulse signal L is at a high level, the first sampling signal is output; when the low-frequency pulse signal L is at a low level, the second sampling signal is output. In this way, the first true random sequence P1 is equivalent to the result of sampling the first high-frequency pulse signal H1 along the rising edge and the falling edge of the low-frequency pulse signal L. Therefore, the randomness of the first true random sequence P1 comes from the phase jitter of the rising edge and the falling edge of the low-frequency pulse signal L. Compared with the true random sequence whose randomness comes from periodic jitter, the present disclosure can further improve the randomness of the true random sequence. At the same time, the double-edge sampling method further improves the sampling rate of the low-frequency pulse signal, thereby reducing the oscillation period value of the true random sequence and improving the bit rate of the true random sequence.

[0056] Figure 5 and Figure 6 is a schematic diagram of a circuit structure of an optional low-frequency oscillator provided in an embodiment of the present disclosure. It should be noted that: Figure 5 Specifically shown is a voltage controlled oscillator 110, Figure 6 Specifically shown is a Boolean oscillator 120; Figure 5 The medium voltage controlled oscillator 110 may include an odd number of current controllable inverters 111, a Schmitt trigger 112 and an odd number of second inverters 113; the input signal V1 (Vin) may come from thermal noise, may be generated by the voltage controlled oscillator 110, or may be a controllable signal generated by other circuits.

[0057] In some embodiments of the present disclosure, Figure 5 and Figure 6, the low-frequency oscillator includes: a voltage-controlled oscillator 110 and a Boolean oscillator 120. The voltage-controlled oscillator 110 includes: a current-controlled inverter 111, a Schmitt trigger 112, and a second inverter 113. Among them, the output end of the current-controlled inverter 111 is connected to the input end of the Schmitt trigger 112, and the output end of the Schmitt trigger 112 is connected to the second inverter 113. The voltage-controlled oscillator 110 is configured to receive an input signal V1 and generate a sampling clock signal V3 (Slow_Vout) based on the input signal V1. The Boolean oscillator 120 is connected to the voltage-controlled oscillator 110, and is configured to receive the sampling clock signal V3 and the input signal V1, and generate an initial low-frequency pulse signal ( Figure 6 ), and, sampling the initial low-frequency pulse signal according to the sampling clock signal V3 to generate a low-frequency pulse signal L.

[0058] In the embodiments of the present disclosure, reference Figure 5 , the current controllable inverter 111 can change the propagation delay, and thus, the embodiment of the present disclosure uses the current controllable inverter 111 to control the frequency of the low-frequency pulse signal L. For example, when the voltage V2 (Vcont) is reduced, the current controllable inverter 111 will reduce the discharge current, thereby increasing the high to low delay t_PHL (High to Low Delay), thereby being able to change the frequency of the low-frequency pulse signal L.

[0059] In the embodiments of the present disclosure, reference Figure 5 In view of the fact that the randomness of the voltage-controlled oscillator 110 requires a certain amount of time to accumulate, the embodiment of the disclosure connects the output of the current-controlled inverter 111 to the input of the Schmitt trigger 112, and the output of the Schmitt trigger 112 to the second inverter 113, so that the low-frequency oscillator 10 can oscillate, generate the sampling clock signal V3 and output it to the Boolean oscillator 120. That is, the output of the voltage-controlled oscillator 110 is used as Figure 6 The sampling clock signal V3 of the Boolean oscillator 120 is used to sample the initial low-frequency pulse signal generated by the Boolean oscillator 120 based on the sampling clock signal V3, thereby quickly acquiring the low-frequency pulse signal L. At the same time, the Schmitt trigger 112 can accelerate the signal flipping at the output end of the current-controlled inverter 111, and eliminate the short-circuit current generated by the current-controlled inverter 111 at a low operating current; thereby, circuit failure can be avoided.

[0060] Figure 7 Schematic diagram of a circuit structure of an optional first high-frequency oscillator 20 provided in an embodiment of the present disclosure.

[0061] In some embodiments of the present disclosure, reference Figure 7The first high-frequency oscillator 20 includes: a Fibonacci oscillation ring 210 and a two-frequency dividing circuit 220. The Fibonacci oscillation ring 210 is configured to generate an initial first high-frequency pulse signal. The two-frequency dividing circuit 220 is connected to the Fibonacci oscillation ring 210, configured to receive the initial first high-frequency pulse signal, and process the initial first high-frequency pulse signal to generate a first high-frequency pulse signal H1.

[0062] It should be noted that the reference Figure 7 The frequency divider circuit 220 processes the initial first high-frequency pulse signal generated by the Fibonacci oscillation ring 210, and makes the frequency of the first high-frequency pulse signal H1 half of the frequency of the initial first high-frequency pulse signal. At the same time, the frequency divider circuit 220 can shape the initial first high-frequency pulse signal to prevent the generated first high-frequency pulse signal H1 from interfering with the sampling process of the subsequent double-edge sampling circuit.

[0063] In the present disclosure, continue to refer to Figure 7 , the Fibonacci oscillation ring 210 is configured to generate an initial first high-frequency pulse signal ( Figure 7 Then, the initial first high-frequency pulse signal is processed by the two-frequency dividing circuit 220 to generate the first high-frequency pulse signal H1. In this way, the Fibonacci oscillation ring 210, as the entropy source of the first high-frequency pulse signal H1, can improve the reliability of the first high-frequency pulse signal H1.

[0064] Figure 8 is a schematic diagram of a circuit structure of an optional true random number generator 200 provided in an embodiment of the present disclosure, with reference to Figure 8 The true random number generator 200 includes a second high-frequency oscillator (Fast Osacillator 2) 50, a counting circuit 60, and the true random sequence generating circuit 100 in the above embodiment. The second high-frequency oscillator 50 is configured to generate a second high-frequency pulse signal H2 (Input_H2). The counting circuit 60 is connected to the second high-frequency oscillator 50 and the true random sequence generating circuit 100, and is configured to receive a counting enable signal P and a second high-frequency pulse signal H2, and count the second high-frequency pulse signal H2 when the counting enable signal P is at a high level and / or a low level, and output a true random number RN (Random Number). The counting enable signal P can be any one of the first true random sequence P1 and the second true random sequence P2 in the above embodiment.

[0065] In the present disclosure, continue to refer to Figure 8, the second high frequency oscillator 50 can generate a second high frequency pulse signal H2. The counting circuit 60 uses any one of the first true random sequence P1 and the second true random sequence P2 as a counting enable signal P to count the second high frequency pulse signal H2 and output a true random number RN. Fig. 9 As shown, the counting circuit 60 uses the high level and low level of the second true random sequence P2 as counting trigger conditions, counts the number of high levels of the second high-frequency pulse signal H2, and generates a true random number RN. In this way, the true random number generator 200 can output random numbers when the counting enable signal P is at a low level and a high level, thereby improving the utilization efficiency of the counting enable signal P and the generation rate of true random numbers.

[0066] In the present disclosure, continue to refer to Figure 8 , the counting circuit 60 uses any one of the first true random sequence P1 and the second true random sequence P2 as the counting enable signal P to count the second high-frequency pulse signal H2. Since the first true random sequence P1 and the second true random sequence P2 generated by the true random sequence generating circuit 100 are formed based on the double-edge sampling method, it is possible to avoid the counting enable signal P being in the high level stage or the low level stage for a long time. For example, if the counting enable signal P is generated by the single-edge sampling method, and the corresponding generated random number is 6, then when the counting enable signal P is generated by the double-edge sampling method, there is phase jitter on the edge, and the time that the counting enable signal P is in the high level stage or the low level stage will be randomly reduced, and correspondingly, the random number will become 2 / 4 or 3 / 3 or 4 / 2, etc. Thereby, the randomness of the true random number can be further increased.

[0067] In some embodiments of the present disclosure, reference Figure 8 , the counting trigger condition of the first counting subcircuit 610 and the counting reset condition of the second counting subcircuit 620 may both be receiving a high level of the counting enable signal P. The counting reset condition of the first counting subcircuit 610 and the counting trigger condition of the second counting subcircuit 620 may both be receiving a high level of the inverted signal of the counting enable signal P.

[0068] In the present disclosure, continue to refer to Figure 8, the counting trigger condition of the first counting subcircuit 610 and the counting reset condition of the second counting subcircuit 620 may both be receiving the high level of the counting enable signal P. In this way, when the first counting subcircuit 610 and the second counting subcircuit 620 receive the high level of the counting enable signal P, the first counting subcircuit 610 starts counting and the second counting subcircuit 620 stops counting. The counting reset condition of the first counting subcircuit 610 and the counting trigger condition of the second counting subcircuit 620 may both be receiving the high level of the inverted signal of the counting enable signal P. In this way, when the first counting subcircuit 610 and the second counting subcircuit 620 receive the high level of the inverted signal of the counting enable signal P, the first counting subcircuit 610 stops counting and the second counting subcircuit 620 starts counting. That is to say, the first counting subcircuit 610 can count in the high level stage of the counting enable signal P; correspondingly, the second counting subcircuit 620 counts in the low level stage of the counting enable signal P.

[0069] Fig.10 Schematic diagram of a circuit structure of an optional true random number generator 200 provided in an embodiment of the present disclosure.

[0070] In some embodiments of the present disclosure, reference Fig.10 The counting circuit 60 includes: a first counting subcircuit 610, a second counting subcircuit 620, a third inverter 630 and a second selector 640. The first counting subcircuit 610 is connected to the second high-frequency oscillator 50 and the true random sequence generation circuit 100, and is configured to receive the counting enable signal P, and count the second high-frequency pulse signal H2 according to the counting enable signal P to generate a first counting result. The third inverter 630 is connected to the true random sequence generation circuit 100, and is configured to receive the counting enable signal P, and generate an inverted signal of the counting enable signal P. The second counting subcircuit 620 is connected to the second high-frequency oscillator 50 and the third inverter 630, and is configured to receive the inverted signal of the counting enable signal P, and count the second high-frequency pulse signal H2 according to the inverted signal of the counting enable signal P to generate a second counting result. The second selector 640 is connected to the first counting subcircuit 610 and the second counting subcircuit 620, and is configured to receive the first counting result and the second counting result, and select to output the first counting result or the second counting result according to the counting enable signal P to generate a true random number RN.

[0071] It should be noted that, continue to refer to Fig.10 The first counting sub-circuit 610 and the second counting sub-circuit 620 can both count any one of the high level, the low level and the oscillation period of the second high-frequency pulse signal H2.

[0072] In the present disclosure, continue to refer to Fig.10The first counting subcircuit 610 can use the high level of the counting enable signal P as a counting trigger condition, and the low level of the counting enable signal P as a counting reset condition, to sample the number of high levels of the second high-frequency pulse signal H2, and generate a first counting result. The second counting subcircuit 610 can use the high level of the inverted signal of the counting enable signal P as a counting trigger condition, and the low level of the inverted signal of the counting enable signal P as a counting reset condition, to count the number of high levels of the second high-frequency pulse signal H2, and generate a second counting result.

[0073] Further, continue to refer to Fig.10 , the second selector 640 can select to output the first counting result or the second counting result based on the counting enable signal P to generate a true random number RN. For example, when the counting enable signal P is at a high level, the first counting result is output; when the counting enable signal P is at a low level, the second counting result is output. In this way, random numbers are generated in both the high level stage and the low level stage of the counting enable signal P. Thus, the utilization efficiency of the counting enable signal P is improved, and the generation rate of the output true random number is improved.

[0074] In the present disclosure, continue to refer to Fig.10 There can be two second high-frequency oscillators 50, each generating its own second high-frequency pulse signal H2. Then, the signals are input into the first counting subcircuit 610 and the second counting subcircuit 620 respectively. In this way, the second high-frequency pulse signals H2 generated by the two second high-frequency oscillators 50 may have differences such as phase difference, so that the corresponding counting results generated may change, thereby further increasing the randomness of the true random number.

[0075] It should be noted that there may be only one second high-frequency oscillator 50, and the second high-frequency pulse signal H2 generated by the oscillator may be the first counting subcircuit 610 and the second counting subcircuit 620, thereby simplifying the circuit structure of the true random number generator 200 and improving the integration.

[0076] Fig.11 is a schematic diagram of a circuit structure of an optional second high-frequency oscillator 50 provided in an embodiment of the present disclosure. In the embodiment of the present disclosure, reference is made to Fig.11 The second high-frequency oscillator 50 may include a ring oscillator and a divide-by-two circuit. The ring oscillator is configured to generate an initial second high-frequency pulse signal ( Fig.11 Then, the initial second high-frequency pulse signal is processed by a two-frequency dividing circuit to generate a second high-frequency pulse signal H2.

[0077] In some embodiments of the present disclosure, reference Fig.10, the first counting subcircuit 610 includes: a first AND gate 611 and a first counter 612. The second counting subcircuit 620 includes: a second AND gate 621 and a second counter 622. The input end of the first AND gate 611 is connected to the output end of the second high-frequency oscillator 50 and the true random sequence generation circuit 100, and the output end of the first AND gate 611 is connected to the input end of the first counter 612. The control end of the first counter 612 is connected to the output end of the true random sequence generation circuit 100; the output end of the first counter 612 is connected to the input end of the second selector 640. The input end of the second AND gate 621 is connected to the output end of the second high-frequency oscillator 50 and the third inverter 630, and the output end of the second AND gate 621 is connected to the input end of the second counter 622; the control end of the second counter 622 is connected to the output end of the true random sequence generation circuit 100; the output end of the second counter 622 is connected to the input end of the second selector 640.

[0078] It should be noted that Fig.10 RS (Rest) is the control terminal of the counter, which is used to receive the count enable signal P. For example, when both the first counter 612 and the second counter 622 receive the rising edge of the count enable signal P, the first counter 612 starts counting and the second counter 622 stops counting.

[0079] In the present disclosure, continue to refer to Fig.10 , the input end of the first AND gate 611 is connected to the output end of the second high-frequency oscillator 50 and the true random sequence generation circuit 100. In this way, the first AND gate 611 receives the second high-frequency pulse signal H2 and the counting enable signal P, and performs an "AND" operation on the second high-frequency pulse signal H2 and the counting enable signal. For example, the counting enable signal P can be a second true random sequence, the second high-frequency pulse signal H2 and the second true random sequence are both high level, and the first AND gate 611 outputs a high level; otherwise, the first AND gate 611 outputs a low level. The output end of the first AND gate 611 is connected to the input end of the first counter 612. The control end of the first counter 612 is connected to the output end of the true random sequence generation circuit 100; the output end of the first counter 612 is connected to the input end of the second selector 640. In this way, the first counter 612 can receive the counting enable signal P, and start or stop counting according to the counting enable signal P, and input the corresponding first counting result to the second selector 640. For example, the counting enable signal P may be a second true random sequence, and the first counter 612 starts counting when receiving a rising edge of the second true random sequence; and the first counter 612 resets and stops counting when receiving a falling edge of the second true random sequence.

[0080] In the present disclosure, continue to refer to Fig.10, the input end of the second AND gate 621 is connected to the output end of the second high-frequency oscillator 50 and the third inverter 630. In this way, the second AND gate 621 receives the second high-frequency pulse signal H2 and the inverted signal of the count enable signal P, and performs an AND operation on the second high-frequency pulse signal H2 and the inverted signal of the count enable signal P. For example, the count enable signal P can be a second true random sequence, the second high-frequency pulse signal H2 and the inverted signal of the second true random sequence are both high level, and the second AND gate 621 outputs a high level; otherwise, the second AND gate 621 outputs a low level. The output end of the second AND gate 621 is connected to the input end of the second counter 622; the control end of the second counter 622 is connected to the output end of the true random sequence generation circuit 100; and the output end of the second counter 622 is connected to the input end of the second selector 640. In this way, the second counter 622 can receive the count enable signal P, and start or stop counting according to the count enable signal P, and input the corresponding second counting result to the second selector 640. For example, the counting enable signal P may be a second true random sequence, and the second counter 622 starts counting when receiving a falling edge of the second true random sequence; when the second counter 622 receives a rising edge of the second true random sequence, the second counter 622 is reset and stops counting.

[0081] Fig.12: is a schematic diagram of the circuit structure of an optional true random number generator 200 provided by an embodiment of the present disclosure. In some embodiments of the present disclosure, the first high-frequency pulse signal H1 is an input signal of the first trigger 310 and the second trigger 320. The first trigger 310 can use the rising edge of the low-frequency pulse signal L as a trigger condition to sample the first high-frequency pulse signal H1 to generate a first sampling signal. The second trigger 320 can use the rising edge of the inverted signal of the low-frequency pulse signal L as a trigger condition to sample the first high-frequency pulse signal H1 to generate a second sampling signal. Then, the first selector 330 can select to output the first sampling signal or the second sampling signal based on the low-frequency pulse signal L to generate a first true random sequence P1. Then, the logic operation circuit 40 performs a logic operation on the first true random sequence P1 and the low-frequency pulse signal L to generate a second true random sequence P2. Then, the first counting subcircuit 610 can use the second true random sequence P2 as a counting enable signal, and the high level of the second true random sequence P2 as a counting trigger condition, and the high level of the inverted signal of the second true random sequence P2 as a counting reset condition, and sample the number of high levels of the second high-frequency pulse signal H2 to generate a first counting result. The second counting subcircuit 620 can use the high level of the inverted signal of the second true random sequence P2 as a counting trigger condition, and the high level of the second true random sequence P2 as a counting reset condition, and count the number of high levels of the second high-frequency pulse signal H2 to generate a second counting result. Finally, the second selector 640 can select and output the first counting result or the second counting result based on the second true random sequence P2 to generate a true random number RN.

[0082] Fig.13 is a schematic diagram of the structure of a memory 300 provided in an embodiment of the present disclosure, such as Fig.13 As shown, the memory 300 includes the true random number generator 200 in the above embodiment.

[0083] In the embodiments of the present disclosure, reference Fig.13 The memory 300 can be any one of static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM) and the like.

[0084] In the present disclosure, continue to refer to Fig.13 , the memory may also include a random signal sampling circuit ( Fig.13 (not shown in the figure), the true random number generator 200 is used to provide true random numbers to the random signal sampling circuit. For example, the random signal sampling circuit can be used to resist the row hammer attack, thereby improving the memory's defense capability against the row hammer attack.

[0085] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0086] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A true random sequence generating circuit, characterized in that: include: A low frequency oscillator, a first high frequency oscillator and a double edge sampling circuit; wherein, The low frequency oscillator is configured to generate a low frequency pulse signal; The first high-frequency oscillator is configured to generate a first high-frequency pulse signal; wherein the period jitter value of the low-frequency pulse signal is greater than the oscillation period value of the first high-frequency pulse signal; The double-edge sampling circuit is connected to the low-frequency oscillator and the first high-frequency oscillator, and is configured to receive the low-frequency pulse signal and the first high-frequency pulse signal, and sample the first high-frequency pulse signal according to the low-frequency pulse signal and the inverted signal of the low-frequency pulse signal, and output a first true random sequence.

2. The true random sequence generating circuit according to claim 1, characterized in that: The true random sequence generating circuit also includes a logic operation circuit; The logic operation circuit is connected to the double-edge sampling circuit and the low-frequency oscillator, and is configured to receive the first true random sequence and the low-frequency pulse signal, and perform a logic operation on the first true random sequence and the low-frequency pulse signal to generate a second true random sequence.

3. The true random sequence generating circuit according to claim 2, characterized in that: The logic operation circuit is an XOR gate, an XNOR gate or an AND gate.

4. The true random sequence generating circuit according to claim 1, characterized in that: The double-edge sampling circuit comprises: a first trigger, a second trigger, a first selector and a first inverter; wherein, The first trigger is connected to the low-frequency oscillator and the first high-frequency oscillator, and is configured to receive the low-frequency pulse signal and the first high-frequency pulse signal, and to sample the first high-frequency pulse signal according to the low-frequency pulse signal, and output a first sampling signal; The first inverter is connected to the low frequency oscillator and is configured to receive the low frequency pulse signal and generate an inverted signal of the low frequency pulse signal; The second trigger is connected to the first inverter and the first high-frequency oscillator, and is configured to receive the inverted signal of the low-frequency pulse signal and the first high-frequency pulse signal, and to sample the first high-frequency pulse signal according to the inverted signal of the low-frequency pulse signal, and output a second sampling signal; The first selector is connected to the first trigger, the second trigger and the low-frequency oscillator, and is configured to receive the first sampling signal, the second sampling signal and the low-frequency pulse signal, and based on the low-frequency pulse signal, selects to output the first sampling signal or the second sampling signal to generate the first true random sequence.

5. The true random sequence generating circuit according to claim 1, characterized in that: The low frequency oscillator includes: a voltage controlled oscillator and a Boolean oscillator; wherein, The voltage-controlled oscillator comprises: a current-controlled inverter, a Schmitt trigger and a second inverter; the output end of the current-controlled inverter is connected to the input end of the Schmitt trigger, and the output end of the Schmitt trigger is connected to the second inverter; The voltage controlled oscillator is configured to receive an input signal and generate a sampling clock signal based on the input signal; The Boolean oscillator is connected to the voltage-controlled oscillator and is configured to receive the sampling clock signal and the input signal, generate an initial low-frequency pulse signal according to the input signal, and sample the initial low-frequency pulse signal according to the sampling clock signal to generate the low-frequency pulse signal.

6. The true random sequence generating circuit according to claim 1, characterized in that: The first high-frequency oscillator comprises: a Fibonacci oscillation ring and a two-frequency division circuit; wherein, The Fibonacci oscillation ring is configured to generate an initial first high-frequency pulse signal; The two-frequency dividing circuit is connected to the Fibonacci oscillation ring, and is configured to receive the initial first high-frequency pulse signal and process the initial first high-frequency pulse signal to generate the first high-frequency pulse signal.

7. A true random number generator, characterized in that: A true random sequence generating circuit comprising any one of claims 1 to 6; The true random number generator further includes: a second high frequency oscillator and a counting circuit; wherein, The second high-frequency oscillator is configured to generate a second high-frequency pulse signal; The counting circuit is connected to the second high-frequency oscillator and the true random sequence generating circuit, and is configured to receive a counting enable signal and the second high-frequency pulse signal, and count the second high-frequency pulse signal when the counting enable signal is at a high level and / or a low level, and output a true random number; the counting enable signal is a first true random sequence or a second true random sequence.

8. The true random number generator according to claim 7, characterized in that: The counting circuit comprises: a first counting subcircuit, a second counting subcircuit, a third inverter and a second selector; wherein, The first counting subcircuit is connected to the second high-frequency oscillator and the true random sequence generating circuit, and is configured to receive the counting enable signal, and count the second high-frequency pulse signal according to the counting enable signal to generate a first counting result; The third inverter is connected to the true random sequence generating circuit and is configured to receive the counting enable signal and generate an inverted signal of the counting enable signal; The second counting subcircuit is connected to the second high-frequency oscillator and the third inverter, and is configured to receive the inverted signal of the counting enable signal, and count the second high-frequency pulse signal according to the inverted signal of the counting enable signal to generate a second counting result; The second selector is connected to the first counting subcircuit and the second counting subcircuit, and is configured to receive the first counting result and the second counting result, and select to output the first counting result or the second counting result according to the counting enable signal to generate the true random number.

9. The true random number generator according to claim 8, characterized in that: The counting trigger condition of the first counting sub-circuit and the counting reset condition of the second counting sub-circuit are both receiving a high level of the counting enable signal; the counting reset condition of the first counting sub-circuit and the counting trigger condition of the second counting sub-circuit are both receiving a high level of the inverted signal of the counting enable signal.

10. The true random number generator according to claim 8, characterized in that: The first counting subcircuit includes: a first AND gate and a first counter; the second counting subcircuit includes: a second AND gate and a second counter; wherein, The input end of the first AND gate is connected to the output end of the second high-frequency oscillator and the true random sequence generating circuit, and the output end of the first AND gate is connected to the input end of the first counter; the control end of the first counter is connected to the output end of the true random sequence generating circuit; the output end of the first counter is connected to the input end of the second selector; The input end of the second AND gate is connected to the output end of the second high-frequency oscillator and the third inverter, and the output end of the second AND gate is connected to the input end of the second counter; the control end of the second counter is connected to the output end of the true random sequence generating circuit; and the output end of the second counter is connected to the input end of the second selector.

11. A memory, characterized in that: A true random number generator comprising any one of claims 7 to 10.

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