Embedded software SPI interface memory virtualization device and method

Abstract

The invention belongs to the technical field of aviation electromechanics, and particularly relates to an embedded software SPI interface memory virtualization device and method. The system is composed of an SPI bus module, a monitoring module, a storage module and a configuration module, and the SPI bus module is composed of a chip selection signal line, a clock signal line, an input data line and an output data line and used for being cross-linked with an SPI interface of a virtual processor; the monitoring module is crosslinked with the SPI bus module and the storage module at the same time; the storage module is crosslinked with the SPI bus module and the monitoring module at the same time; and the configuration module is crosslinked with the monitoring module and the storage module. The method provided by the invention does not aim at a specific hardware platform, can be suitable for any hardware platform after abstracting the hardware model, and does not need hardware investment due to the adoption of the virtualization method, so that the economic benefit is good, and the application and popularization value is relatively high.

Description

Technical Field

[0001] The invention belongs to the field of aviation electromechanical technology, and in particular relates to an embedded software SPI interface memory virtualization device and method. Background Art

[0002] With the rapid development of information technology, avionics equipment is undergoing unprecedented changes. The integration of aviation airborne equipment is becoming increasingly higher, and the complexity is growing exponentially. Since software in smart devices carries more and more system functions, the complexity of airborne equipment software is also becoming increasingly complex.

[0003] In the traditional airborne equipment software (embedded software) development process, since embedded software relies on hardware to run, the development and debugging of embedded software are often restricted by hardware. Complete functional verification and testing can only be carried out after the hardware equipment is available, which brings certain challenges to the development of embedded software and even the progress of the entire project. At the same time, due to the increase in the complexity of airborne equipment, the equipment has also transitioned from single redundancy, dual redundancy to quadruple redundancy. Even in single redundancy equipment, there are multiple processors. The debugging method used in reality can only control a single microprocessor through an emulator. If you want to access multiple microprocessors, you need multiple computers to do it at the same time. However, even so, it is difficult to achieve effective testing and verification of complex equipment. Therefore, the method of virtualization of embedded devices has emerged. However, in many virtualized devices, only functional simulation is realized, and details are not paid attention to. For example, the simulation of the memory of the SPI interface only realizes the reading and writing of data, but the state of the signal on the bus and the state of the memory are not simulated, resulting in a large deviation from the physical hardware, which brings great doubts to the credibility of virtualization testing.

[0004] The present invention proposes an embedded software SPI interface memory virtualization device and method, which not only realizes the virtualization of the SPI interface and the memory, but also simulates the signal state of the SPI bus and the state of the memory in a nearly realistic manner, greatly improving the effectiveness of the SPI interface memory virtual simulation, and can perform a nearly realistic virtualization test on the embedded software. Summary of the invention

[0005] The purpose of the present invention is to provide an embedded software SPI interface memory virtualization device and method. The present invention virtualizes the memory of the SPI interface. In addition to supporting the simulation verification of the storage function of the embedded software SPI interface, it can also support the detection of the SPI interface communication parameters, and can more realistically and effectively replace the physical environment for virtualization verification.

[0006] Technical solution of the present invention: According to a first aspect of the present invention, an embedded software SPI interface memory virtualization device is proposed, the device consists of four parts: an SPI bus module, a monitoring module, a storage module, and a configuration module, wherein the SPI bus module consists of a chip select signal line, a clock signal line, an input data line, and an output data line, and is used to be cross-linked with the SPI interface of the virtual processor; the monitoring module is cross-linked with the SPI bus module and the storage module at the same time; the storage module is cross-linked with the SPI bus module and the monitoring module at the same time; the configuration module is cross-linked with the monitoring module and the storage module.

[0007] In a possible example, an embedded software SPI interface memory virtualization device is composed of four parts: a SPI bus module, a monitoring module, a storage module, and a configuration module;

[0008] In a possible example, the SPI bus module is used to interact with the SPI interface of the virtual microprocessor module;

[0009] In a possible example, the monitoring module is used to monitor the SPI interface and identify normal and abnormal data of the SPI interface;

[0010] In a possible example, the monitoring module enables the storage module to perform a data storage operation on normal data from the SPI interface;

[0011] In a possible example, if the data from the SPI interface is abnormal data, the monitoring module enables the storage module to return 0xFFFF data to the SPI interface data line;

[0012] In a possible example, the monitoring module can monitor the chip select signal on the SPI interface, and if the chip select signal is invalid, the storage module is enabled to return 0xFFFF data to the SPI interface data line;

[0013] In a possible example, the monitoring module can monitor the clock signal on the SPI interface, and can monitor and display the communication baud rate of the SPI interface in real time;

[0014] In a possible example, if the baud rate of the SPI interface clock signal is not within a reasonable range, it is considered as a baud rate abnormality, and the monitoring module enables the storage module to return 0xFFFF data to the SPI interface data line;

[0015] In a possible example, the monitoring module can monitor the polarity and phase on the SPI interface. If the monitored polarity and phase are inconsistent with the configured polarity and phase, it is considered that the polarity and phase are abnormal, and the storage module is enabled to return the misaligned data to the SPI interface data line according to the specific situation of the polarity and phase;

[0016] In a possible example, if the storage module is currently in a reading, writing or erasing state, then the current busy state is returned, otherwise the current not busy state is returned to the data bus;

[0017] In a possible example, if the storage module receives a read operation instruction, it returns data to the monitoring module, and the monitoring module returns the data to the SPI interface data bus;

[0018] In a possible example, the storage module, if receiving an erase data operation, erases data in a specified sector and updates the data to a local file when idle;

[0019] In a possible example, the storage module, if receiving a write data operation, writes the current input into the designated address data area, and updates it to the local file when idle;

[0020] In a possible example, if the storage module receives a data write operation but the designated write address is not in an erased state, the corresponding data cannot be written normally;

[0021] In a possible example, the storage module, when receiving an operation to read a memory ID or memory information, returns corresponding data to the monitoring module, and the monitoring module returns the data to the SPI interface data bus;

[0022] In a possible example, the configuration module can write the baud rate of the SPI bus communication and the information of the reasonable range of the baud rate into the monitoring module, so that the monitoring module can effectively monitor the SPI bus;

[0023] In a possible example, the configuration module can write information such as ID information, sector information, capacity, and operation instructions of the memory into the memory so as to respond to commands from the SPI bus.

[0024] According to a second aspect of the present invention, a method for virtualizing an embedded software SPI interface memory is proposed, using the above-mentioned embedded software virtualization verification device, and comprising the following steps:

[0025] Step 1: Configure the baud rate of the SPI bus through the configuration module, and configure the ID information, sector information, capacity, operation instructions and other information of the storage module;

[0026] Step 2: The monitoring module monitors the chip select signal status on the SPI interface bus. If the chip select signal is invalid, the storage module is enabled to return 0xFFFF data to the SPI interface data line;

[0027] Step 3: The monitoring module monitors the SPI interface bus signal. If the chip select signal is valid, the monitoring module monitors the clock signal and displays the clock signal baud rate in real time. If the clock signal baud rate is not within a reasonable range, the storage module is enabled to return 0xFFFF data to the SPI interface data line.

[0028] Step 4: The monitoring module monitors the SPI interface bus signal. If the polarity and phase on the bus are incorrect, the monitoring module should enable the storage module to return the data to the SPI interface data line after dislocation;

[0029] Step 5: The monitoring module monitors the SPI interface bus signal. If the data on the bus interface is correct, the monitoring module enables the storage module to process the data;

[0030] Step 6: If the data received from the SPI bus is a read operation, the storage module returns the corresponding data to the SPI interface data line;

[0031] Step 7: If the received data is an erase operation, the storage module erases the data of the specified sector and updates it to the local file at idle time;

[0032] Step 8: If the received data is a write operation, the storage module writes the data to the specified address and updates it to the local file when idle;

[0033] Step 9: If the received data is a write operation, but the designated storage address is in an unerased state, the storage module ignores the writing of the address data;

[0034] Step 10: The monitoring module monitors the working state of the storage module. If the storage module is currently in a read, write or erase operation, it returns that it is currently in a busy state. Otherwise, it returns that it is currently in a not busy state to the data bus.

[0035] Step 11: If the received data is for reading the memory ID or memory information, the storage module returns the corresponding data to the SPI interface data line;

[0036] Step 12: Complete the data reading and writing of the memory and end the storage operation.

[0037] Beneficial technical effects of the present invention

[0038] The present invention provides an embedded software SPI interface memory virtualization device and method, which realizes full-state access to the memory of the SPI interface in a virtualization platform. Compared with the traditional method that only realizes the writing and reading of data logically without considering the state of the SPI bus and the memory, the method provided by the present invention monitors the state of the SPI bus on the one hand, specifically including: monitoring the state of the SPI bus chip select enable signal, the polarity and phase of the clock and the baud rate of the SPI bus; on the other hand, the erase, write and read states of the memory are monitored, and according to the physical state of the current SPI bus and the memory, the input is truly responded to, which greatly improves the authenticity of the SPI interface memory virtualization simulation close to the physical simulation, and improves the effectiveness of the virtualization simulation. The method provided by the present invention is not targeted at a specific hardware platform, and can be applied to any hardware platform after the hardware model is abstracted, and since the virtualization method does not require hardware investment, it has good economic benefits and high application promotion value. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a flow chart of the method of the present invention;

[0040] Figure 2 It is a schematic diagram of the structure of the device of the present invention. Specific implementation methods

[0042] In order to make the purpose, technical scheme and advantages of the implementation of the present invention clearer, the technical scheme in the embodiment of the present invention will be described in more detail in combination with the embodiment of the present invention. In the example, the same or similar reference numerals throughout represent the same or similar originals or elements with the same or similar functions. The described embodiments are part of the embodiments of the present invention, not all of them. The embodiments described below by reference are exemplary and intended to be used to explain the present invention, and should not be construed as limitations on the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. The following is a detailed description in combination with the embodiments of the present invention.

[0043] The present invention provides an embedded software SPI interface memory virtualization device, the device is composed of four parts: an SPI bus module, a monitoring module, a storage module, and a configuration module, wherein the SPI bus module is composed of a chip selection signal line, a clock signal line, an input data line, and an output data line, and is used to be cross-linked with the SPI interface of the virtual processor; the monitoring module is cross-linked with the SPI bus module and the storage module at the same time; the storage module is cross-linked with the SPI bus module and the monitoring module at the same time; the configuration module is cross-linked with the monitoring module and the storage module. The specific implementation steps of the present invention are as follows:

[0044] Step 1: Configure the baud rate of the SPI bus through the configuration module, and configure the ID information, sector information, capacity, operation instructions and other information of the storage module;

[0045] Step 2: The monitoring module monitors the chip select signal status on the SPI interface bus. If the chip select signal is invalid, the storage module is enabled to return 0xFFFF data to the SPI interface data line;

[0046] Step 3: The monitoring module monitors the SPI interface bus signal. If the chip select signal is valid, the monitoring module monitors the clock signal and displays the clock signal baud rate in real time. If the clock signal baud rate is not within a reasonable range, the storage module is enabled to return 0xFFFF data to the SPI interface data line.

[0047] Step 4: The monitoring module monitors the SPI interface bus signal. If the polarity and phase on the bus are incorrect, the monitoring module should enable the storage module to return the data to the SPI interface data line after dislocation;

[0048] Step 5: The monitoring module monitors the SPI interface bus signal. If the data on the bus interface is correct, the monitoring module enables the storage module to process the data;

[0049] Step 6: If the data received from the SPI bus is a read operation, the storage module returns the corresponding data to the SPI interface data line;

[0050] Step 7: If the received data is an erase operation, the storage module erases the data of the specified sector and updates it to the local file at idle time;

[0051] Step 8: If the received data is a write operation, the storage module writes the data to the specified address and updates it to the local file when idle;

[0052] Step 9: If the received data is a write operation, but the designated storage address is in an unerased state, the storage module ignores the writing of the address data;

[0053] Step 10: The monitoring module monitors the working state of the storage module. If the storage module is currently in a read, write or erase operation, it returns that it is currently in a busy state. Otherwise, it returns that it is currently in a not busy state to the data bus.

[0054] Step 11: If the received data is for reading the memory ID or memory information, the storage module returns the corresponding data to the SPI interface data line;

[0055] Step 12: Complete the data reading and writing of the memory and end the storage operation.

[0056] Implementation Examples

[0057] In conjunction with a certain SPI interface memory example, the baud rate to be adopted by the SPI interface is 1M bps, the reasonable range of the baud rate is: (100K, 2M) bps, the ID of the memory is 0x2B3A, the size of the memory sector is 64k words, and the number of sectors is 256. The specific real-time steps of the present invention are as follows:

[0058] Step 1: Configure the baud rate of the SPI bus to 1M bps through the configuration module. The reasonable range of the SPI bus baud rate is: (100K, 2M) bps;

[0059] Step 2: Configure the storage module through the configuration module. The information is as follows: the memory ID is 0x2B3A, the size of the memory sector is 64k words, and the number of sectors is 256;

[0060] Step 3: The monitoring module monitors the chip select signal status on the SPI interface bus. If the chip select signal is invalid, the storage module is enabled to return 0xFFFF data to the SPI interface data line;

[0061] Step 4: The monitoring module monitors the SPI interface bus signal. If the chip select signal is valid, the clock signal is monitored and the clock signal baud rate is displayed in real time. If the clock signal baud rate is not within a reasonable range, the storage module is enabled to return 0xFFFF data to the SPI interface data line.

[0062] Step 5: The monitoring module monitors the SPI interface bus signal. If the polarity and phase on the bus are incorrect, the monitoring module should enable the storage module to return the data to the SPI interface data line after dislocation;

[0063] Step 6: The monitoring module monitors the SPI interface bus signal. If the data on the bus interface is correct, the monitoring module enables the storage module to process the data;

[0064] Step 7: The virtual microprocessor module sends and reads the data at address 0x2000 through the virtual SPI interface, and the storage module returns the data at address 0x2000 to the SPI interface data line;

[0065] Step 8: The virtual microprocessor module sends an operation instruction to erase the first sector through the virtual SPI interface, and the storage module erases the data of the first sector and updates it to the local file in idle time;

[0066] Step 9: The virtual microprocessor module sends an operation instruction to write data 0x1234 to address 0x3000 through the virtual SPI interface, and the storage module writes data 0x1234 to 0x3000 and updates it to the local file when idle;

[0067] Step 10: The monitoring module monitors the working state of the storage module. If the storage module is currently in a read, write or erase operation, it returns that it is currently in a busy state. Otherwise, it returns that it is currently in a not busy state to the data bus.

[0068] Step 11: When the virtual microprocessor module sends an operation instruction to read the memory ID information through the virtual SPI interface, the memory module returns 0x2B3A to the SPI interface data line;

[0069] Step 12: Complete the data reading and writing of the memory and end the storage operation.

[0070] It is understood by those skilled in the art that, unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as the general understanding of ordinary technicians in the field to which the present invention belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and unless defined as here, will not be interpreted with idealized or overly formal meanings. The specific implementation methods described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the present invention. Within the spirit and principle of the present invention, any technician familiar with the profession may use the above disclosed technical content to change or modify it into an equivalent embodiment of equivalent changes for application in other fields, but any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the technical solution content of the present invention, any modification, equivalent replacement, improvement, etc., made according to the technical essence of the present invention, should be included in the protection scope of the present invention.

Claims

1. An embedded software SPI interface memory virtualization device, characterized in that: The device is composed of four parts: an SPI bus module, a monitoring module, a storage module, and a configuration module. The SPI bus module is composed of a chip selection signal line, a clock signal line, an input data line, and an output data line, and is used to interconnect with the SPI interface of the virtual processor. The monitoring module is cross-linked with the SPI bus module and the storage module at the same time; the storage module is cross-linked with the SPI bus module and the monitoring module at the same time; the configuration module is cross-linked with the monitoring module and the storage module.

2. The device according to claim 1, characterized in that The monitoring module is used to monitor the SPI interface and identify normal and abnormal data of the SPI interface.

3. The device according to claim 2, characterized in that The monitoring module enables the storage module to perform data storage operations on normal data from the SPI interface.

4. The device according to claim 3, characterized in that If the data from the SPI interface is abnormal data, the monitoring module enables the storage module to return 0xFFFF data to the SPI interface data line.

5. The device according to claim 4, characterized in that The monitoring module can monitor the chip select signal on the SPI interface. If the chip select signal is invalid, the storage module is enabled to return 0xFFFF data to the SPI interface data line.

6. The device according to claim 5, characterized in that The monitoring module can monitor the clock signal on the SPI interface and can monitor and display the communication baud rate of the SPI interface in real time.

7. The device according to claim 6, characterized in that If the baud rate of the SPI interface clock signal is not within a reasonable range, it is regarded as a baud rate abnormality, and the monitoring module enables the storage module to return 0xFFFF data to the SPI interface data line; the monitoring module can monitor the polarity and phase on the SPI interface. If the monitored polarity and phase are inconsistent with the configured polarity and phase, it is regarded as a polarity and phase abnormality, and the storage module is enabled to return misaligned data to the SPI interface data line based on the specific situation of the polarity and phase.

8. The device according to claim 7, characterized in that If the storage module is currently in the read, write or erase state, it returns the current busy state, otherwise it returns the current not busy state to the data bus; The storage module, if receiving a read operation instruction, returns data to the monitoring module, and the monitoring module returns the data to the SPI interface data bus; The storage module, if receiving a data erase operation, erases the data of the specified sector and updates it to the local file when idle; The storage module, if receiving a write data operation, writes the current input into the designated address data area, and updates it to the local file when idle; If the storage module receives a data write operation but the specified write address is not in an erased state, the corresponding data cannot be written normally; The storage module, when receiving an operation to read the memory ID or memory information, returns the corresponding data to the monitoring module, and the monitoring module returns the data to the SPI interface data bus.

9. The device according to claim 8, characterized in that The configuration module can write the baud rate of SPI bus communication and the reasonable range of baud rate information into the monitoring module so that the monitoring module can effectively monitor the SPI bus; the configuration module can write the ID information, sector information, capacity size, and operation instruction information of the memory into the memory so as to respond to commands from the SPI bus.

10. A method for virtualizing the device as claimed in claim 9, characterized in that: The steps include: Step 1: Configure the baud rate of the SPI bus through the configuration module, and configure the ID information, sector information, capacity size, and operation instruction information of the storage module; Step 2: The monitoring module monitors the chip select signal status on the SPI interface bus. If the chip select signal is invalid, the storage module is enabled to return 0xFFFF data to the SPI interface data line; Step 3: The monitoring module monitors the SPI interface bus signal. If the chip select signal is valid, the monitoring module monitors the clock signal and displays the clock signal baud rate in real time. If the clock signal baud rate is not within a reasonable range, the storage module is enabled to return 0xFFFF data to the SPI interface data line. Step 4: The monitoring module monitors the SPI interface bus signal. If the polarity and phase on the bus are incorrect, the monitoring module should enable the storage module to return the data to the SPI interface data line after dislocation; Step 5: The monitoring module monitors the SPI interface bus signal. If the data on the bus interface is correct, the monitoring module enables the storage module to process the data; Step 6: If the data received from the SPI bus is a read operation, the storage module returns the corresponding data to the SPI interface data line; Step 7: If the received data is an erase operation, the storage module erases the data of the specified sector and updates it to the local file at idle time; Step 8: If the received data is a write operation, the storage module writes the data to the specified address and updates it to the local file when idle; Step 9: If the received data is a write operation, but the designated storage address is in an unerased state, the storage module ignores the writing of the address data; Step 10: The monitoring module monitors the working state of the storage module. If the storage module is currently in a read, write or erase operation, it returns that it is currently in a busy state. Otherwise, it returns that it is currently in a not busy state to the data bus. Step 11: If the received data is for reading the memory ID or memory information, the storage module returns the corresponding data to the SPI interface data line; Step 12: Complete the data reading and writing of the memory and end the storage operation.

Images