Reverse search method and device for row address and nonvolatile storage medium

Abstract

The invention discloses a row address reverse search method and device and a nonvolatile storage medium. The method comprises the steps that a target row address space in a register set is determined, and each target row address in the target row address space is not actively accessed by an operating system; under the condition that the error row address occurs in the register set, a correct row address corresponding to the error row address is determined through a preset row address mapping table, and the correct row address is a row address in the target row address space; and under the condition that the wrong row address is misjudged, determining the misjudged wrong row address corresponding to the correct row address through a preset row address mapping table. According to the method and the device, the technical problem that the row address which is misjudged to be wrong cannot be accessed due to the fact that reverse search cannot be performed on the row address is solved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a reverse search method and device for a row address, and a non-volatile storage medium. Background Art

[0002] The widely used Double Data Rate Synchronous Dynamic Random Access Memory (SDRAM, also known as Dynamic Random Access Memory, DRAM) standard is used for DDR4 and DDR5 memory and provides a channel that can support dual in-line memory module (DIMM) devices on both rising and falling clock edges. DDR5 DRAM supports failed row address repair. Two methods are provided in DDR5: hard post-packet repair (hPPR) for permanent row repair and soft post-packet repair (sPPR) for temporary row repair. With hPPR, DDR5 can correct at least one row address for each BG; with sPPR, DDR5 can repair one row address for each BG. If the hPPR resources of a BG are exhausted, the bank group will have no more soft PPR resources available.

[0003] Typically, after a faulty row address is mapped to a redundant row address, the faulty row address cannot be accessed again without disabling the faulty row replacement mechanism. Disabling faulty row replacement even for one row can be very costly because the data in the mapped redundant row can be valuable.

[0004] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0005] The embodiments of the present application provide a method and device for reverse searching a row address, and a non-volatile storage medium, so as to at least solve the technical problem of being unable to access a row address that is misjudged as an error due to being unable to reverse search the row address.

[0006] According to one aspect of an embodiment of the present application, a reverse search method for a row address is provided, comprising: determining a target row address space in a register set, wherein each target row address in the target row address space will not be actively accessed by an operating system; in the case where an error row address appears in the register set, determining a correct row address corresponding to the error row address through a preset row address mapping table, wherein the correct row address is a row address in the target row address space; in the case where the error row address is misjudged, determining the misjudged error row address corresponding to the correct row address through a preset row address mapping table.

[0007] Optionally, after determining the correct row address corresponding to the erroneous row address, the method further includes: sending the correct row address to a target row address space in the register set.

[0008] Optionally, after sending the correct row address to the register set, the method further includes: accessing the error row address to confirm whether the error row address is misjudged.

[0009] Optionally, accessing the error row address to confirm whether the error row address is misjudged includes: accessing the error row address to confirm whether the error row address is misjudged through a preset target operating system routine with permission to access the target row address space.

[0010] Optionally, after determining the misjudged error row address corresponding to the correct row address, the method further includes: sending the misjudged error row address to a register set.

[0011] Optionally, the preset row address mapping table is stored in a register clock driver.

[0012] Optionally, the reverse search method of the row address is applied to at least one of a register clock driver, a high bandwidth register clock driver or a multi-way register clock driver.

[0013] According to another aspect of the embodiments of the present application, a reverse search device for a row address is also provided, including: a first determination module, used to determine a target row address space in a register set, wherein each target row address in the target row address space will not be actively accessed by an operating system; a second determination module, used to determine a correct row address corresponding to the erroneous row address through a preset row address mapping table when an erroneous row address appears in the register set, wherein the correct row address is an address in the target row address space; and a third determination module, used to determine a misjudged erroneous row address corresponding to the correct row address through a preset row address mapping table when the erroneous row address is misjudged.

[0014] According to another aspect of the embodiments of the present application, a non-volatile storage medium is provided, the storage medium includes a stored program, wherein when the program is executed, the device where the storage medium is located is controlled to execute the above reverse search method for row addresses.

[0015] According to another aspect of the embodiments of the present application, there is further provided an electronic device, including: a memory and a processor, the processor being configured to run a program stored in the memory, wherein the above reverse search method of row addresses is executed when the program is run.

[0016] In an embodiment of the present application, a target row address space in a register set is determined, wherein each target row address in the target row address space will not be actively accessed by the operating system; in the case where an error row address appears in the register set, a correct row address corresponding to the error row address is determined by a preset row address mapping table, wherein the correct row address is a row address in the target row address space; in the case where the error row address is misjudged, the misjudged error row address corresponding to the correct row address is determined by a preset row address mapping table. By determining the correct row address corresponding to the error row address by a preset row address mapping table when an error row address appears in the register set; in the case where the error row address is misjudged, the misjudged error row address corresponding to the correct row address is determined by a preset row address mapping table, thereby achieving the purpose of reverse searching the row address, thereby realizing the technical effect of accessing the misjudged row address, and further solving the technical problem of being unable to access the row address misjudged as an error due to the inability to reverse search the row address. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 is a flow chart of a reverse search method for a row address according to an embodiment of the present application;

[0019] Figure 2 is a schematic diagram of another row address reverse search method according to an embodiment of the present application;

[0020] Figure 3 is a schematic diagram of a computer system running a reverse search method for a row address according to an embodiment of the present application;

[0021] Figure 4 is a schematic diagram of a computer system running another row address reverse search method according to an embodiment of the present application;

[0022] Figure 5 is a schematic diagram of a computer system running another row address reverse search method according to an embodiment of the present application;

[0023] Figure 6 is a structural diagram of a row address reverse search device according to an embodiment of the present application;

[0024] Figure 7 It is a hardware structure block diagram of a computer terminal (or electronic device) according to a reverse search method of a row address in an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] According to an embodiment of the present application, a method embodiment of a reverse search method for a row address is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0028] Figure 1 is a flow chart of a reverse search method for a row address according to an embodiment of the present application. Figure 1 As shown, the method comprises the following steps:

[0029] Step S102, determining a target row address space in the register set, wherein each target row address in the target row address space will not be actively accessed by the operating system.

[0030] According to some optional embodiments of the present application, the register set is a set (bank) of one or more registers in a register clock driver, and the register set can be accessed or written at the same time. By using the bank, parallel read and write operations can be implemented to improve the performance of the system. Each bank usually contains multiple registers, each register has its own address, and can be read or written individually.

[0031] The target row address space is the redundant row address in the register clock driver. The redundant row address refers to the additional row address added to improve reliability. The redundant row address can be used to detect and correct errors in the memory, such as bit flips or memory cell failures. Redundant row addresses are generally implemented by adding additional bits. In each memory cell, in addition to the bit storing the data, a redundant bit can be added. This redundant bit can be used to store a checksum or other redundant information. When the data is read, the redundant row address will be passed to the redundant row address detection and correction circuit together with the read data. This circuit can compare the read data with the checksum stored in the redundant row address, so that errors can be detected and corrected. Redundant row addresses can improve the reliability of memory, which is especially important for critical applications and systems with high data integrity requirements. Help detect and correct errors in memory, thereby reducing the probability of system failure.

[0032] Step S104, when an erroneous row address appears in the register set, a correct row address corresponding to the erroneous row address is determined through a preset row address mapping table, wherein the correct row address is a row address in the target row address space.

[0033] When an erroneous row address appears in the register set, a correct row address corresponding to the erroneous row address is determined through a preset row address mapping table, and the correct row address is sent to a target row address space in the register set.

[0034] To determine the correct row address corresponding to the error row address through the preset row address mapping table and send the correct row address to the target row address space in the register set, the following steps can be followed: 1. Create a row address mapping table, in which each entry contains the error row address and the corresponding correct row address. This mapping table can be an array, dictionary or other data structure; 2. When an error row address occurs, use the error row address as an index to find the corresponding correct row address in the mapping table; 3. If the correct row address is found, send it to the target row address space in the register set; 4. If the correct row address is not found, you can choose to perform some error handling operations, such as prompting an error or taking other corrective measures.

[0035] Step S106 , when the error row address is misjudged, determine the misjudged error row address corresponding to the correct row address through a preset row address mapping table.

[0036] In the case where the error row address is misjudged, the misjudged error row address corresponding to the correct row address can be determined through a preset row address mapping table, wherein the preset row address mapping table is prepared in advance based on system characteristics and experience, and records the correct row address and the corresponding error row address. When the row address is misjudged, the system can query the preset row address mapping table according to the actual situation, find the error row address corresponding to the correct row address, and then send the misjudged error row address to the register set.

[0037] According to the above steps, when an error row address appears in the register set, the correct row address corresponding to the error row address is determined by using the preset row address mapping table; when the error row address is misjudged, the misjudged error row address corresponding to the correct row address is determined by using the preset row address mapping table, thereby achieving the purpose of reverse searching the row address, thereby realizing the technical effect of accessing the misjudged row address.

[0038] Figure 2 is a schematic diagram of another reverse search method for row addresses according to an embodiment of the present application, such as Figure 2 As shown, the solid line is the forward extension direction of normal fault row replacement, and the dashed line is the backward search direction for accessing the original error row address, wherein the forward mapping and the backward mapping are active simultaneously.

[0039] According to some optional embodiments of the present application, after determining the correct row address corresponding to the error row address, it is also necessary to: send the correct row address to the target row address space in the register set.

[0040] According to some other optional embodiments of the present application, after sending the correct row address to the register set, it is also necessary to: access the error row address to confirm whether the error row address is misjudged.

[0041] In some optional embodiments of the present application, accessing the error row address and confirming whether the error row address is misjudged can be achieved by the following method: accessing the error row address and confirming whether the error row address is misjudged through a preset target operating system routine with permission to access the target row address space.

[0042] As some optional embodiments of the present application, after determining the misjudged error row address corresponding to the correct row address, it is also necessary to: send the misjudged error row address to a register set.

[0043] In some optional embodiments of the present application, the preset row address mapping table is stored in a register clock driver.

[0044] As other optional embodiments of the present application, the reverse search method of the row address is applied to at least one of a register clock driver, a high-bandwidth register clock driver or a multi-channel register clock driver.

[0045] A register clock driver (RCD) is a circuit or chip that drives the clock signal in a register. Register clock drivers are commonly used in digital systems, especially in central processing units and other processors. RCD is responsible for providing clock signals to synchronize and control the read and write operations of registers. RCD usually has multiple clock input ports that can receive clock signals from different sources. RCD also provides multiple clock output ports for passing clock signals to registers that require clock signals. These output ports can be configured with different clock frequencies and phases as needed. In addition to providing clock signals, register clock drivers may also provide other functions such as clock division, clock delay, clock phase adjustment, etc. These functions can help optimize system performance and timing requirements. Register clock drivers play an important role in digital systems, ensuring the synchronization and correctness of register operations. Correctly selecting and configuring register clock drivers is critical to designing high-performance and reliable digital systems.

[0046] A high bandwidth register clock driver (HBRCD) is a circuit used to drive a high-speed register clock signal. The register clock signal is used to synchronize the data input and output operations to the register, and the high bandwidth register clock driver can provide a high-speed and stable clock signal. A high bandwidth register clock driver usually includes one or more clock generators, clock dividers, and clock buffers. The clock generator is used to generate a high-frequency clock signal, and the clock divider is used to divide the high-frequency clock signal into a lower frequency to meet different application requirements. The clock buffer is used to amplify and drive the clock signal to ensure that the clock signal can be accurately transmitted to the register. The design of the high bandwidth register clock driver takes into account factors such as signal transmission delay, jitter, and power consumption. HBRCD usually uses a low-delay, low-jitter clock generator and buffer to ensure that the clock signal can be accurately transmitted to the register and can meet the requirements of high-speed data input and output. In addition, the high bandwidth register clock driver can also reduce power consumption and improve performance by optimizing the circuit structure and adopting advanced process technology.

[0047] A multi-register clock driver (MRCD) is a circuit or chip used to drive the clock signal of multiple registers. MRCDs are often used in synchronous circuits, such as register files in microprocessors or digital signal processors. The main function of a multi-register clock driver is to provide a synchronized clock signal to each register to ensure that they operate in the same clock cycle. MRCDs usually have multiple clock inputs and multiple clock outputs, and can distribute one clock signal to multiple registers. Multi-register clock drivers usually have the following features: 1. Clock distribution: One input clock signal can be distributed to multiple registers to ensure that they operate in the same clock cycle; 2. Clock delay: An adjustable clock delay can be provided for each register to meet the timing requirements between different registers; 3. Clock frequency: It can support different clock frequencies and provide different clock divisions as needed; 4. Power supply noise filtering: It usually has a power supply noise filtering function to reduce noise interference of the clock signal.

[0048] Figure 3 is a schematic diagram of a computer system running a row address reverse search method according to an embodiment of the present application, such as Figure 3 As shown, a computer system 960 includes: a host central processing unit (CPU) 970, a memory controller (MC) 980, and a sub-channel of a dual in-line memory module (DIMM) 300, wherein the DIMM can be a JEDEC standard DDR5. The DIMM includes two sub-channels. Each sub-channel includes 20 dynamic random access memory chips (DRAM) 341-345 and a host data bus 301-305. There is a registered clock driver (RCD) 330 in the DIMM, which will be shared by two sub-channels. The command / address bus 320 connects the MC and the RCD. The RCD is capable of performing forward / reverse error row address to redundant row addressing mapping.

[0049] Figure 4 is a schematic diagram of a computer system running another row address reverse search method according to an embodiment of the present application, such as Figure 4As shown, a computer system 930 includes: a host central processing unit (CPU) 940, a memory controller (MC) 950, and a sub-channel of a DIMM 200, wherein the DIMM can be a JEDEC standard DDR5 high-bandwidth DIMM (HBDIMM) or a hybrid DIMM defined in reference 8. The DIMM includes two sub-channels. Each sub-channel includes 20 or 18-DRAM chips 241-245, 5 high-bandwidth data buffers (HBDB) 211-215, a host data bus 201-205, and a data bus 221-225 between the HBDB and the DRAM chips. The bus 221-225 runs at half the data rate of the bus 201-205. There is a high-bandwidth registered clock driver (HBRCD) 230 in the DIMM, which will be shared by the two sub-channels. The command / address bus 220 connects the MC and the HBRCD. The HBRCD is capable of performing forward / reverse error row address to redundant row addressing mapping.

[0050] Figure 5 is a schematic diagram of a computer system running another row address reverse search method according to an embodiment of the present application, such as Figure 5 As shown, the computer system 900 includes: a host central processing unit (CPU) 910, a memory controller (MC) 920, and a sub-channel of a DDR5 multiple rank dual inline memory module (Multiple Rank Dual Inline Memory Module, MRDIMM) 100. The MRDIMM includes two sub-channels. Each sub-channel includes 20x4 DRAM chips 141-145, 5 multiple data buffers (MDBs) 111-115, a host data bus 101-105, and a data bus 121-125 between the MDB and the DRAM chips. The bus 121-125 runs at half the data rate of the bus 101-105. There is a multiple registered clock driver (MRCD) 130 in the MRDIMM, which will be shared by two sub-channels. The command / address bus 120 connects the MC and the MRCD. The MRCD is capable of performing forward / reverse error row address to redundant row addressing mapping.

[0051] Figure 6 is a structural diagram of a row address reverse search device according to an embodiment of the present application, such as Figure 6 As shown, the device comprises:

[0052] A first determination module 60, configured to determine a target row address space in the register set, wherein each target row address in the target row address space will not be actively accessed by the operating system;

[0053] A second determination module 62 is used to determine a correct row address corresponding to the erroneous row address by using a preset row address mapping table when an erroneous row address appears in the register set, wherein the correct row address is an address in the target row address space;

[0054] The third determination module 64 is used to determine the misjudged error row address corresponding to the correct row address by using a preset row address mapping table when the error row address is misjudged.

[0055] It should be noted that the above Figure 6 The modules in the embodiment may be program modules (e.g., a set of program instructions for implementing a specific function) or hardware modules. For the latter, they may be expressed in the following forms, but are not limited thereto: the expression form of the above modules is a processor, or the functions of the above modules are implemented by a processor.

[0056] It should be noted that Figure 6 The preferred implementation of the illustrated embodiment can be found in Figure 1 The relevant description of the illustrated embodiment will not be repeated here.

[0057] Optionally, after determining the correct row address corresponding to the erroneous row address, the method further includes: sending the correct row address to a target row address space in the register set.

[0058] Optionally, after sending the correct row address to the register set, the method further includes: accessing the error row address to confirm whether the error row address is misjudged.

[0059] Optionally, accessing the error row address to confirm whether the error row address is misjudged includes: accessing the error row address to confirm whether the error row address is misjudged through a preset target operating system routine with permission to access the target row address space.

[0060] Optionally, after determining the misjudged error row address corresponding to the correct row address, the method further includes: sending the misjudged error row address to a register set.

[0061] Optionally, the preset row address mapping table is stored in a register clock driver.

[0062] Optionally, the reverse search method of the row address is applied to at least one of a register clock driver, a high bandwidth register clock driver or a multi-way register clock driver.

[0063] Figure 7 The hardware structure block diagram of a computer terminal (or mobile device) for implementing a reverse search method for a row address is shown. Figure 7As shown, the computer terminal 70 (or mobile device 70) may include one or more (shown as 702a, 702b, ..., 702n in the figure) processors 702 (the processor 702 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 704 for storing data, and a transmission module 706 for communication functions. In addition, it may also include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of the BUS bus), a network interface, a power supply and / or a camera. It can be understood by those skilled in the art that Figure 7 The structure shown is only for illustration and does not limit the structure of the above electronic device. Figure 7 More or fewer components as shown, or with Figure 7 Different configurations are shown.

[0064] It should be noted that the one or more processors 702 and / or other data processing circuits described above may generally be referred to herein as "data processing circuits". The data processing circuits may be embodied in whole or in part as software, hardware, firmware, or any other combination thereof. In addition, the data processing circuit may be a single independent processing module, or may be incorporated in whole or in part into any of the other components in the computer terminal 70 (or mobile device). As described in the embodiments of the present application, the data processing circuit acts as a processor control (e.g., selection of a variable resistor terminal path connected to an interface).

[0065] The memory 704 can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to the reverse search method of the row address in the embodiment of the present application. The processor 702 executes various functional applications and data processing by running the software programs and modules stored in the memory 704, that is, the reverse search method of the row address is realized. The memory 704 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 704 may further include a memory remotely arranged relative to the processor 702, and these remote memories may be connected to the computer terminal 70 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0066] The transmission module 706 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the computer terminal 70. In one example, the transmission module 706 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission module 706 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0067] The display may be, for example, a touch screen liquid crystal display (LCD) that enables a user to interact with a user interface of the computer terminal 70 (or mobile device).

[0068] It should be noted that, in some optional embodiments, the above Figure 7 The computer device (or electronic device) shown may include hardware elements (including circuits), software elements (including computer code stored on a computer-readable medium), or a combination of hardware elements and software elements. It should be noted that Figure 7 This is merely one example of a particular embodiment and is intended to illustrate the types of components that may be present in the above-described computer device (or electronic device).

[0069] It should be noted that Figure 7 The electronic device shown is used to perform Figure 1 The reverse search method of the row address shown in the figure, therefore the relevant explanations in the execution method of the above command are also applicable to the electronic device and will not be repeated here.

[0070] An embodiment of the present application further provides a non-volatile storage medium, which includes a stored program, wherein when the program is executed, the device where the storage medium is located is controlled to execute the above reverse search method for row addresses.

[0071] A program for a non-volatile storage medium to perform the following functions: determining a target row address space in a register set, wherein each target row address in the target row address space will not be actively accessed by an operating system; in the case where an error row address appears in the register set, determining a correct row address corresponding to the error row address through a preset row address mapping table, wherein the correct row address is a row address in the target row address space; in the case where the error row address is misjudged, determining the misjudged error row address corresponding to the correct row address through a preset row address mapping table.

[0072] An embodiment of the present application further provides an electronic device, including: a memory and a processor, wherein the processor is used to run a program stored in the memory, wherein the above reverse search method of the row address is executed when the program is running.

[0073] The processor is used to run a program that performs the following functions: determining a target row address space in a register set, wherein each target row address in the target row address space will not be actively accessed by an operating system; in the case where an error row address appears in the register set, determining a correct row address corresponding to the error row address through a preset row address mapping table, wherein the correct row address is a row address in the target row address space; in the case where the error row address is misjudged, determining the misjudged error row address corresponding to the correct row address through a preset row address mapping table.

[0074] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0075] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0076] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0077] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0078] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0079] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the relevant technology or all or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk, etc. Various media that can store program codes.

[0080] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A reverse search method for a row address, characterized in that: include: Determine a target row address space in the register set, wherein each target row address in the target row address space will not be actively accessed by the operating system; In the case where an erroneous row address appears in the register set, determining a correct row address corresponding to the erroneous row address through a preset row address mapping table, wherein the correct row address is a row address in the target row address space; In the case where the error row address is misjudged, the misjudged error row address corresponding to the correct row address is determined by using the preset row address mapping table.

2. The method according to claim 1, characterized in that After determining the correct row address corresponding to the error row address, the method further includes: The correct row address is sent to the target row address space in the register set.

3. The method according to claim 2, characterized in that After sending the correct row address to the register set, the method further includes: The error row address is accessed to confirm whether the error row address is misjudged.

4. The method according to claim 3, characterized in that Accessing the error row address to confirm whether the error row address is misjudged includes: The error row address is accessed through a preset target operating system routine having permission to access the target row address space to confirm whether the error row address is misjudged.

5. The method according to claim 1, characterized in that: After determining the misjudged error row address corresponding to the correct row address, the method further includes: The misjudged error row address is sent to the register set.

6. The method according to claim 1, characterized in that The preset row address mapping table is stored in a register clock driver.

7. The method according to any one of claims 1 to 6, characterized in that: The reverse search method of the row address is applied to at least one of a register clock driver, a high bandwidth register clock driver or a multi-channel register clock driver.

8. A reverse search device for row addresses, characterized in that: include: A first determination module is used to determine a target row address space in a register set, wherein each target row address in the target row address space will not be actively accessed by an operating system; A second determination module is used to determine, when an erroneous row address appears in the register set, a correct row address corresponding to the erroneous row address by using a preset row address mapping table, wherein the correct row address is an address in the target row address space; The third determination module is used to determine the misjudged error row address corresponding to the correct row address through the preset row address mapping table when the error row address is misjudged.

9. A non-volatile storage medium, characterized in that: The non-volatile storage medium includes a stored program, wherein when the program is executed, the device where the non-volatile storage medium is located is controlled to execute the reverse search method for row addresses according to any one of claims 1 to 7.

10. An electronic device, characterized in that: include: A memory and a processor, wherein the processor is used to run a program stored in the memory, wherein the program executes the reverse search method for row addresses as described in any one of claims 1 to 7 when running.

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