Differential current compensation level shift circuit applied to high-speed power supply system
By designing a differential current compensation level shift circuit in a high-speed power supply system, using a current mirror and latch module with a cross-coupled structure, combined with a differential current compensation module, the level shift error problem caused by dv/dt voltage interference in the power supply system is solved, and an efficient level shift circuit with anti-dv/dt change performance and low power consumption is realized.
Patent Information
- Application Number
- CN202411705341.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2025-03-07
AI Technical Summary
In the power supply system of the third generation semiconductor gallium nitride, the dv/dt voltage interference introduced by the high-speed SW node voltage changes leads to errors in the latch signal of the level shift circuit, resulting in errors in the bridge logic output on the Buck circuit.
A differential current compensation level shift circuit is designed, using a current mirror and a latch module with a cross-coupled structure, combined with a differential current compensation module, to improve the anti-dv/dt change performance of the circuit.
While not affecting the signal transmission speed, the anti-dv/dt change performance of the level shift circuit is improved, static power consumption is reduced, and the output logic voltage of the level shift circuit is stabilized.
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Figure CN119582578A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of power supplies, and in particular to a differential current compensation level shifting circuit applied to a high-speed power supply system. Background Art
[0002] In the third-generation semiconductor gallium nitride power supply system, the high-speed SW node voltage change will introduce a large dv / dt voltage interference, causing errors in the latch signal of the level shift circuit, leading to errors in the upper bridge logic output of the Buck circuit.
[0003] Specifically, in the traditional Dual-NMOS high-voltage half-bridge structure, gallium nitride power transistors are now used to replace the original MOS power tubes as switch tubes. The bootstrap capacitor cap is charged when the low-side driver tube is turned on. When the low-voltage driver tube is driven, the bootstrap capacitor is charged. Then the high-side circuit module is powered by the bootstrap voltage. Due to the existence of the floating common mode ground VSW, the previous level shift circuit (levelshift) is required to have good anti-dv / dt characteristics, such as Figure 1 As shown, since the output voltage changes from 0 to Vin in a very short time, a large dv / dt change is formed. This change will be coupled to the capacitors C1 and C2 of the previous stage through the bootstrap capacitor (C1 and C2 are the parasitic capacitors of LDMOS tubes HN1 and HN2). When the power rail undergoes a dv / dt change, the power supply will charge the parasitic capacitor, generate a large current, and the voltage at point A will drop, causing the subsequent driver to output an erroneous logic level. Therefore, the level shifter design must have a large anti-dv / dt characteristic to ensure that when the power rail undergoes dv / dt, the output of the level shifter circuit remains stable.
[0004] In summary, due to the existence of factors such as process mismatch and inconsistent parasitic capacitance, the level shift circuit based on the current mirror has low resistance to dv / dt changes; and the secondary locked level shift circuit uses a constant current compensation structure, which will increase the signal transmission delay to a certain extent. Summary of the invention
[0005] In view of the above technical problems, the present invention provides a differential current compensation level shift circuit applied to a high-speed power supply system, which improves the dv / dt variation resistance of the level shift circuit without affecting the signal transmission speed.
[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.
[0007] The present invention discloses a differential current compensation level shift circuit applied to a high-speed power supply system, the circuit comprising:
[0008] A level shift module, the level shift module comprising a current mirror with a cross-coupling structure, wherein a main branch and a slave branch of the current mirror are respectively connected to sources of different high-voltage LDMOS tubes, and gates of the two high-voltage LDMOS tubes are respectively input with level signals to be latched, the current mirror comprises two first current mirror units and two second current mirror units, both of which constitute a symmetrical structure, the first current mirror unit comprising a first driving tube of a P-type structure connected to one of the high-voltage LDMOS tubes, and two first replica tubes for replicating the first driving tube, and the second current mirror unit comprising a second driving tube of an N-type structure connected to the output of the first replica tube, and a second replica tube for replicating the second driving tube;
[0009] A latch module, the latch module is used to latch the level signal output by the current mirror, and includes two first inverters and two second inverters, wherein the two first inverters are interconnected to form a storage unit, and the positive input ends of the other two second inverters are connected to the storage unit, and are respectively connected to the outputs of the two first current mirror units.
[0010] Furthermore, the circuit also includes a differential current compensation module, and the differential current compensation module is connected to the outputs of the two second inverters to improve the circuit's ability to resist voltage change rate.
[0011] Furthermore, the differential current compensation module is specifically started when the circuit outputs a high level, and is used to introduce a compensation current to offset the unequal currents when the parasitic currents of the high-voltage LDMOS tubes of the level shift module are unequal.
[0012] Furthermore, the level signal is obtained by triggering a narrow pulse.
[0013] The technical solution disclosed in this disclosure has the following beneficial effects:
[0014] The level shift circuit adopts a current differential structure, which improves the resistance of the output logic voltage of the level shift circuit to the influence of the dv / dt voltage change of the floating power rail without affecting the transmission speed of the original level shift circuit; the level shift circuit can be triggered by a narrow pulse input signal to reduce the static power consumption of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 This is a schematic diagram of the effect of dv / dt interference on output logic in the background technology of this specification;
[0016] Figure 2 is a schematic diagram of a differential current compensation level shift circuit applied to a high-speed power supply system in an embodiment of this specification;
[0017] Figure 3 is a schematic diagram of a differential current compensation module in an embodiment of this specification;
[0018] Figure 4 It is a schematic diagram of the effect of negative dv / dt on the circuit in the embodiments of this specification;
[0019] Figure 5 This is a schematic diagram of the effect of positive dv / dt on the circuit in the embodiments of this specification;
[0020] Figure 6 It is an equivalent diagram of the current compensation principle in the embodiments of this specification. DETAILED DESCRIPTION
[0021] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.
[0022] like Figure 2-6 As shown, an embodiment of this specification provides a differential current compensation level shift circuit applied to a high-speed power supply system, and the circuit includes:
[0023] A level shift module 1, the level shift module 1 comprises a current mirror with a cross-coupling structure, the main branch and the slave branch of the current mirror are respectively connected to the source of different high-voltage LDMOS tubes (HN1-HN2), the gates of the two high-voltage LDMOS tubes are respectively input with the level signals to be latched, the current mirror comprises two first current mirror units and two second current mirror units, both of which constitute a symmetrical structure, the first current mirror unit comprises a first driving tube (PM1, PM4) of a P-type structure connected to one of the high-voltage LDMOS tubes, two first replica tubes (PM2, PM3, PM5, PM6) for replicating the first driving tube, the second current mirror unit comprises a second driving tube (NM2, NM3) of an N-type structure connected to the output of the first replica tube, and a second replica tube (NM1, NM4) for replicating the second driving tube;
[0024] Latch module 2, latch module 2 is used to latch the level signal output by the current mirror, which includes two first inverters and two second inverters, wherein the two first inverters are interconnected to form a storage unit, and the positive input ends of the other two second inverters are connected to the storage unit, and are respectively connected to the outputs of the two first current mirror units.
[0025] The circuit further includes a differential current compensation module, which is connected to the outputs of the two second inverters to improve the circuit's ability to resist voltage change rate.
[0026] The differential current compensation module is specifically started when the circuit outputs a high level, and is used to introduce a compensation current to offset the unequal current when the parasitic currents of the high-voltage LDMOS tubes of the level shift module are unequal.
[0027] Specifically, the present invention provides a novel level shift circuit based on differential current compensation, such as Figure 2 shown. Figure 2 The level shift circuit in the circuit includes a level shift module and a latch module. HN1 and HN2 are high-voltage LDMOS tubes. PM1-PM6 and NM1-NM4 form a cross-coupling structure of a current mirror. This structure can offset the current caused by the parasitic capacitance of the high-voltage tubes HN1 and HN2 to a certain extent. The latch is composed of the first inverter inv1 and inv2, and the second inverter inv3 and inv4. It has a fast transmission speed. Figure 3 It is a specific implementation of differential current.
[0028] In the level shift module, the input signals Vin1 and Vin2 of the level shift circuit can be triggered by narrow pulses, and then the signals can be latched by the internal latch (inverters inv1-inv4), such as Figure 4 As shown, when Vin1=1, Vin2=0, the voltage at point G1 drops, PM1 turns on, PM4 turns off, PM2 and PM3 mirror PM1, PM5 and PM6 turn off, PM3 pulls up Vout2, NM2 pulls down Vout1, Vout2=1, Vout1=0, the latch module latches the values of Vout2 and Vout1. When Vin1=0, Vin2=1, the voltage at point G2 drops, PM4 turns on, PM1 turns off, PM5 and PM6 mirror the current of PM4, PM2 and PM3 turn off, NM3 pulls down Vout2, PM6 pulls up Vout1, Vout2=0, Vout1=1, the latch module latches the values of Vout2 and Vout1, the power supply voltage jumps downward, that is, the circuit has a negative; dv / dt, such as Figure 5As shown, the voltage at points G1 and G2 increases, and the gate voltage of PM1 and PM4 will not exceed VDDH+Vf. Vf is the voltage generated by the parasitic diode between the source and the substrate. PM2 and PM5 are in the cut-off state. Other MOS tubes have no mirror current and will not affect the latch. Therefore, this circuit has a good anti-negative dv / dt characteristic. When the power supply voltage jumps upward, that is, when the circuit has a positive dv / dt, as shown in Figure 5 As shown, when the parasitic capacitances of the high-voltage transistors HM1 and HM2 are completely matched, the parasitic current caused by the positive dv / dt can be eliminated. However, due to process reasons, the parasitic capacitances of the high-voltage transistors HN1 and HN2 cannot be completely matched, which may result in the parasitic currents IA and IB not being able to completely cancel each other out. The signal level is affected by dv / dt, which may cause the signal transmitted from the original low-voltage domain to the high-voltage domain to change, and the latch latches the wrong signal, resulting in the output of the wrong logic level. Therefore, this embodiment introduces a novel differential current compensation module to perform current compensation when positive dv / dt occurs to stabilize the output of the level shifting circuit.
[0029] like Figure 3 and 6 As shown, the differential current implementation principle is that when the level shift circuit output is high (capacitor C1 is high, capacitor C2 is low), the differential current compensation circuit is started, and when positive dv / dt occurs, parasitic currents IB and IA are generated. When IB is greater than IA, a differential current is introduced for compensation. The differential current is subtracted by introducing another compensation current to offset the current generated by the different parasitic capacitances of the high-voltage tube, and the output signal of the latch is stabilized (C1 is the output). The compensation current I1 cannot be greater than the current flowing through the high-voltage MOS tube when the level shifter changes from a high potential to a low potential, otherwise it will affect the output delay of the shift level. When the level shifter changes from a high output level to a low level, since the compensation module is in a closed state, it will not affect the falling delay of the level shifter.
[0030] IA and IB are parasitic currents generated by the level shifter when dv / dt occurs. The following formula can be obtained from the current charging formula. C3 and C4 are the parasitic capacitances of the high-voltage tubes HN1 and HN2 respectively.
[0031]
[0032]
[0033] The relationship between the difference between the compensation current and the parasitic capacitance and dv / dt can be deduced as shown in the following equation:
[0034] I 1 -(I B -I A)+I A =I B ;
[0035] From this we can deduce:
[0036]
[0037] in:
[0038] when When , the voltages at Vout1 and Vout2 will not change. When , due to the short dv / dt time, a small positive pulse voltage will be generated at Vout2, and a small negative pulse voltage will be generated at Vout1, and then the normal level logic will be restored. Since the pulse voltages of Vout1 and Vout2 do not meet the minimum input voltage requirement of the latch, the output value of the level shift circuit will not change. When the voltage at points Vout1 and Vout2 changes rapidly, the latch latches the wrong logic level, resulting in an output error in the level shifting circuit. When positive dv / dt occurs, the different parasitic currents introduced by the mismatch of the high-voltage tube will affect the output signal. In order to eliminate this effect as much as possible, a differential current compensation module is proposed to offset the mismatch current and the introduced differential current. The circuit's anti-dv / dt performance can be improved without changing the original structure. When C1=0 and C2=1, the compensation module fails. On the contrary, when C1=1 and C2=0, the differential current compensation module plays a current compensation role in the level shifting circuit. At the same time, the influence on the transmission delay of the original structure can be ignored. This structure has universal applicability and can be applied to various types of level shifting circuits.
[0039] Beneficial effects:
[0040] The present invention adopts a level shift circuit with a current differential structure, which improves the resistance of the output logic voltage of the level shift circuit to the influence of the dv / dt voltage change of the floating power rail without affecting the transmission speed of the original level shift circuit; and can use a narrow pulse input signal mode to trigger the level shift circuit, thereby reducing the static power consumption of the circuit.
[0041] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.
Claims
1. A differential current compensation level shift circuit applied to a high-speed power supply system, characterized in that: The circuit comprises: A level shift module, the level shift module comprising a current mirror with a cross-coupling structure, wherein a main branch and a slave branch of the current mirror are respectively connected to sources of different high-voltage LDMOS tubes, and gates of the two high-voltage LDMOS tubes are respectively input with level signals to be latched, the current mirror comprises two first current mirror units and two second current mirror units, both of which constitute a symmetrical structure, the first current mirror unit comprising a first driving tube of a P-type structure connected to one of the high-voltage LDMOS tubes, and two first replica tubes for replicating the first driving tube, and the second current mirror unit comprising a second driving tube of an N-type structure connected to the output of the first replica tube, and a second replica tube for replicating the second driving tube; A latch module, the latch module is used to latch the level signal output by the current mirror, and includes two first inverters and two second inverters, wherein the two first inverters are interconnected to form a storage unit, and the positive input ends of the other two second inverters are connected to the storage unit, and are respectively connected to the outputs of the two first current mirror units.
2. The differential current compensation level shift circuit for high-speed power supply system according to claim 1, characterized in that: The circuit further includes a differential current compensation module, which is connected to the outputs of the two second inverters to improve the circuit's ability to resist voltage change rate.
3. The differential current compensation level shift circuit for high-speed power supply system according to claim 2, characterized in that: The differential current compensation module is specifically started when the circuit outputs a high level, and is used to introduce a compensation current to offset the unequal currents when the parasitic currents of the high-voltage LDMOS tubes of the level shift module are unequal.
4. The differential current compensation level shift circuit for high-speed power supply system according to claim 1, characterized in that: The level signal is obtained by triggering a narrow pulse.