Crystal oscillation circuit and crystal oscillator

Abstract

The invention relates to the technical field of integrated circuit design, and discloses a crystal oscillation circuit and a crystal oscillator, and the crystal oscillation circuit comprises a core oscillation circuit which is configured to output oscillation voltage; the voltage amplitude detection circuit is connected with the core oscillation circuit and is configured to detect the amplitude of the oscillation voltage and output direct current voltage according to the amplitude of the oscillation voltage; the first bias circuit is respectively connected with the voltage amplitude detection circuit and the core oscillation circuit and is configured to output a first bias current according to the direct current voltage; the second bias circuit is connected with the core oscillation circuit and is configured to output a second bias current according to the temperature change; wherein the first bias current and the second bias current act on the core oscillation circuit and provide bias current for the core oscillation circuit. According to the crystal oscillation circuit, the circuit power consumption after crystal oscillation starting can be reduced under the condition of realizing rapid crystal oscillation starting.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, for example, to a crystal oscillator circuit and a crystal oscillator. Background Art

[0002] In chips that require high-precision timing control, such as MCU (Microcontroller Uni, micro control unit) chips, digital control chips, integrated systems on chip, etc., a high-precision clock source is required to perform high-precision timing control or clock generation on the chip. This high-precision clock source generally uses a constant temperature crystal oscillator, an external frequency source chip, or a passive crystal oscillator. Among them, both the constant temperature crystal oscillator and the external frequency source chip need to be powered, which is inconvenient to use and expensive, and is not conducive to low-cost applications. The passive crystal oscillator only needs a passive crystal and is used in conjunction with the easily integrated Pierce oscillator on the chip to generate a high-precision clock. It is easy to implement and easy to use. At the same time, the crystal is cheap, making it an ideal clock generation solution for MCU chips, wireless communication chips, etc.

[0003] Combination Figure 1 As shown, in the related art, the crystal oscillator circuit adopts the design of an off-chip passive crystal Crystal and an on-chip Pierce oscillator circuit. Among them, the on-chip Pierce oscillator circuit includes a seventh resistor R7, a seventh capacitor C7, an eighth capacitor C8, and an eighth NMOS tube NM8. The on-chip Pierce oscillator circuit has a negative input impedance and adopts a fixed DC bias to provide oscillation energy for the off-chip crystal Crystal. In order to ensure that the crystal starts oscillating quickly, the bias current IDC needs to be set to be large enough, so as to provide sufficient energy to the crystal per unit time and reduce the crystal startup time.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] The related technology uses a fixed DC bias. A larger bias current can achieve rapid crystal oscillation. However, after the crystal is started, it only needs to maintain the crystal oscillation and does not need to consume too much current. Therefore, a larger bias current will cause the circuit to still generate large power consumption after the crystal is quickly started.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a crystal oscillator circuit and a crystal oscillator, so as to reduce the power consumption of the circuit after the crystal oscillation is completed while achieving rapid crystal oscillation.

[0009] In some embodiments, the crystal oscillator circuit includes: a core oscillator circuit, configured to output an oscillation voltage; a voltage amplitude detection circuit, connected to the core oscillator circuit, configured to detect the amplitude of the oscillation voltage and output a DC voltage according to the amplitude of the oscillation voltage; a first bias circuit, connected to the voltage amplitude detection circuit and the core oscillator circuit, respectively, configured to output a first bias current according to the DC voltage; a second bias circuit, connected to the core oscillator circuit, configured to output a second bias current according to temperature changes; wherein the first bias current and the second bias current act on the core oscillator circuit to provide bias current for the core oscillator circuit.

[0010] Optionally, the core oscillation circuit includes: a first resistor, a first capacitor, a second capacitor, a first NMOS tube, and a crystal; the first end of the first resistor, the first end of the first capacitor, and the gate of the first NMOS tube are connected to output an oscillation voltage and are connected to the first end of the crystal; the second end of the first resistor, the drain of the first NMOS tube, and the first end of the second capacitor are connected to receive a bias current and are connected to the second end of the crystal; the second end of the first capacitor, the source of the first NMOS tube, and the second end of the second capacitor are all grounded.

[0011] Optionally, the voltage amplitude detection circuit includes: a third capacitor, a fourth capacitor, and a second resistor; the first end of the third capacitor receives an oscillating voltage; the second end of the third capacitor is connected to the first end of the second resistor; the second end of the second resistor is connected to the second end of the fourth capacitor and to the first bias circuit; the first end of the fourth capacitor is connected to a power supply.

[0012] Optionally, the first bias circuit includes: a first bias current control circuit, including a second PMOS tube, the first bias current control circuit is configured to generate a first dynamic bias current at the drain of the second PMOS tube according to a DC voltage; a first bias current output circuit, including a third PMOS tube, the first bias current output circuit is connected to the first bias current control circuit, and is configured to amplify the first dynamic bias current and output the first bias current at the drain of the third PMOS tube; wherein the second PMOS tube and the third PMOS tube are a common source and common gate structure.

[0013] Optionally, the first bias current control circuit also includes: a first PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, and a third resistor; the source of the first PMOS tube is connected to the power supply; the gate of the first PMOS tube is connected to the second end of the third capacitor; the drain of the first PMOS tube is connected to the drain of the second NMOS tube, the drain of the third NMOS tube, the gate of the third NMOS tube, the gate of the second PMOS tube, and the second end of the fourth capacitor; the source of the second PMOS tube is connected to the power supply; the drain of the second PMOS tube is connected to the first end of the third resistor and the gate of the fourth NMOS tube; the gate of the second NMOS tube is connected to the source of the third NMOS tube, the second end of the third resistor, and the drain of the fourth NMOS tube; the source of the second NMOS tube is grounded; the source of the fourth NMOS tube is grounded.

[0014] Optionally, the first bias current output circuit also includes: a fourth resistor and a fifth capacitor; the first end of the fourth resistor is connected to the gate of the second PMOS tube; the second end of the fourth resistor is connected to the second end of the fifth capacitor and the gate of the third PMOS tube; the first end of the fifth capacitor is connected to the power supply; the source of the third PMOS tube is connected to the power supply; and the drain of the third PMOS tube outputs the first bias current.

[0015] Optionally, the second bias circuit includes: a second bias current control circuit, including a fifth PMOS tube, the second bias current control circuit is configured to generate a second dynamic bias current at the drain of the fifth PMOS tube according to temperature changes; a second bias current output circuit, including a sixth PMOS tube, the second bias current output circuit is connected to the second bias current control circuit, and is configured to amplify the second dynamic bias current and output the second bias current at the drain of the sixth PMOS tube; wherein the fifth PMOS tube and the sixth PMOS tube are a common source and common gate structure.

[0016] Optionally, the second bias current control circuit also includes: a fourth PMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, and a fifth resistor; the source of the fourth PMOS tube is connected to the power supply; the gate of the fourth PMOS tube is connected to the gate of the fifth PMOS tube, the drain of the fourth PMOS tube, the drain of the fifth NMOS tube, the drain of the sixth NMOS tube, and the gate of the sixth NMOS tube; the source of the fifth PMOS tube is connected to the power supply; the drain of the fifth PMOS tube is connected to the first end of the fifth resistor and the gate of the seventh NMOS tube; the gate of the fifth NMOS tube is connected to the source of the sixth NMOS tube, the second end of the fifth resistor, and the drain of the seventh NMOS tube; the source of the fifth NMOS tube is grounded; and the source of the seventh NMOS tube is grounded.

[0017] Optionally, the second bias current output circuit also includes: a sixth resistor and a sixth capacitor; the first end of the sixth resistor is connected to the gate of the fifth PMOS tube; the second end of the sixth resistor is connected to the second end of the sixth capacitor and the gate of the sixth PMOS tube; the first end of the sixth capacitor is connected to the power supply; the source of the sixth PMOS tube is connected to the power supply; and the drain of the sixth PMOS tube outputs the second bias current.

[0018] In some embodiments, the crystal oscillator includes: a crystal oscillator circuit as described above.

[0019] The crystal oscillator circuit and crystal oscillator provided by the embodiments of the present disclosure can achieve the following technical effects:

[0020] The crystal oscillator circuit includes a core oscillator circuit, a voltage amplitude detection circuit, a first bias circuit, and a second bias circuit. The core oscillator circuit outputs an oscillation voltage for starting the crystal. The voltage amplitude detection circuit can output a DC voltage according to the amplitude of the oscillation voltage. The larger the amplitude of the oscillation voltage, the higher the output DC voltage. The first bias circuit can output a first bias current according to the DC voltage. The higher the DC voltage, the smaller the first bias current. Therefore, when the crystal starts to oscillate, the amplitude of the oscillation voltage is small, and the DC voltage output by the voltage amplitude detection circuit is also small, so that the first bias circuit can output a larger first bias current, and the first bias current acts on the core oscillator circuit to accelerate the crystal oscillation. As the amplitude of the oscillation voltage increases, the first bias current will gradually decrease. After the crystal oscillation is completed, the first bias current is close to zero, thereby reducing the circuit power consumption after the crystal oscillation is completed while achieving rapid crystal oscillation. In addition, the second bias circuit can detect temperature changes and generate a second bias current with positive temperature characteristics, which is used to compensate for the problem of transconductance deterioration of NMOS devices in the circuit at high temperatures. After the crystal starts oscillating, the second bias circuit can also continue to provide the second bias current to the core oscillation circuit to maintain circuit stability.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0023] Figure 1 It is a circuit diagram of a crystal oscillator circuit in the related art;

[0024] Figure 2 is a circuit block diagram of a crystal oscillator circuit provided by an embodiment of the present disclosure;

[0025] Figure 3 is a circuit block diagram of another crystal oscillator circuit provided by an embodiment of the present disclosure;

[0026] Figure 4 is a circuit diagram of a voltage amplitude detection circuit and a first bias circuit in a crystal oscillator circuit provided by an embodiment of the present disclosure;

[0027] Figure 5 is a circuit diagram of a second bias circuit in a crystal oscillator circuit provided by an embodiment of the present disclosure;

[0028] Figure 6 It is a circuit diagram of a crystal oscillator circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0030] The terms "first", "second", etc. in the technical solutions described in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the disclosed embodiments described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0031] Unless otherwise stated, the term "plurality" means two or more.

[0032] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0033] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0034] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0035] The present disclosure provides a crystal oscillator circuit. Figure 2As shown, the crystal oscillator circuit includes a core oscillator circuit 10 , a voltage amplitude detection circuit 20 , a first bias circuit 30 and a second bias circuit 40 .

[0036] The core oscillator circuit 10 is configured to output an oscillation voltage. The voltage amplitude detection circuit 20 is connected to the core oscillator circuit 10, configured to detect the amplitude of the oscillation voltage, and output a DC voltage according to the amplitude of the oscillation voltage. The first bias circuit 30 is connected to the voltage amplitude detection circuit 20 and the core oscillator circuit 10, respectively, and configured to output a first bias current according to the DC voltage. The second bias circuit 40 is connected to the core oscillator circuit 10, and configured to output a second bias current according to temperature changes. The first bias current and the second bias current act on the core oscillator circuit 10 to provide bias currents for the core oscillator circuit 10.

[0037] The core oscillator circuit 10 outputs an oscillation voltage for starting the crystal. The voltage amplitude detection circuit 20 can output a DC voltage according to the amplitude of the oscillation voltage. The larger the amplitude of the oscillation voltage, the higher the output DC voltage. The first bias circuit 30 can output a first bias current according to the DC voltage. The higher the DC voltage, the smaller the first bias current. Therefore, when the crystal starts to oscillate, the amplitude of the oscillation voltage is small, and the DC voltage output by the voltage amplitude detection circuit 20 is also small, so that the first bias circuit 30 can output a larger first bias current, and the first bias current acts on the core oscillator circuit 10 to accelerate the crystal oscillation. As the amplitude of the oscillation voltage increases, the first bias current will gradually decrease. After the crystal oscillation is completed, the first bias current is close to zero, thereby reducing the circuit power consumption after the crystal oscillation is completed while achieving rapid crystal oscillation. In addition, the second bias circuit 40 can detect temperature changes and generate a second bias current with a positive temperature characteristic to compensate for the problem of transconductance deterioration of NMOS devices in the circuit at high temperatures. After the crystal oscillation is completed, the second bias circuit 40 can also continue to provide the second bias current to the core oscillator circuit 10 to maintain circuit stability.

[0038] Optionally, combined Figure 3 As shown, the core oscillator circuit 10 includes: a first resistor R1, a first capacitor C1, a second capacitor C2, a first NMOS transistor NM1, and a crystal Cr. The first end of the first resistor R1, the first end of the first capacitor C1, and the gate of the first NMOS transistor NM1 are connected to output an oscillation voltage and are connected to the first end of the crystal Cr; the second end of the first resistor R1, the drain of the first NMOS transistor NM1, and the first end of the second capacitor C2 are connected to receive a bias current and are connected to the second end of the crystal Cr; the second end of the first capacitor C1, the source of the first NMOS transistor NM1, and the second end of the second capacitor C2 are all grounded.

[0039] In this embodiment, the core oscillator circuit 10 is a Pierce oscillator circuit structure, and the first NMOS transistor NM1, the first capacitor C1, and the second capacitor C2 form an equivalent input negative impedance for providing oscillation energy for the passive crystal.

[0040] Input negative impedance R N The formula is:

[0041]

[0042] Wherein, ω is the desired oscillation frequency; C1 is the capacitance of the first capacitor C1; C2 is the capacitance of the second capacitor C2; the capacitance of the first capacitor C1 and the second capacitor C2 is only related to the selection of the crystal Cr; g m is the transconductance of the first NMOS tube NM1.

[0043] The transconductance of the first NMOS tube NM1 is m Determined by the following formula:

[0044]

[0045] Among them, μ n is the electron mobility of the first NMOS tube NM1; C ox I is the gate oxide capacitance of the first NMOS transistor NM1; DC1 is the bias current; W / L is the width-to-length ratio of the first NMOS transistor NM1.

[0046] In order to ensure that the crystal Cr can oscillate normally, it is necessary to ensure that the input negative impedance R N The absolute value is greater than the input resistance R of the external crystal Cr p , that is, |R N |>R P Therefore, it is necessary to increase the transconductance of the first NMOS tube NM1. m In order to ensure the good frequency characteristics of the first NMOS tube NM1, the bias current I DC1 In some scenarios where the oscillation frequency of the crystal Cr is high, the oscillation frequency ω is large, which will cause the input negative impedance R N Rapidly decreases, requiring a larger bias current I DC1 To ensure that the crystal Cr starts to oscillate quickly, |R N | Designed to be larger, so that | R N | Much larger than R p, so as to ensure the rapid start of crystal Cr. Therefore, in the initial stage of crystal Cr oscillation, the first bias circuit 30 can provide a large first bias current, and after the crystal Cr oscillation is completed, the first bias current is reduced to reduce the circuit power consumption. In addition, in a high temperature environment, such as 125°C working conditions, due to the normal temperature characteristics of NMOS devices, the transconductance g of the first NMOS tube NM1 m In order to ensure that the crystal Cr can start oscillating quickly under high temperature conditions, the second bias circuit 40 can provide a second bias current for the core oscillation circuit 10 according to temperature changes to compensate for the deterioration of the transconductance of the first NMOS device under high temperature conditions.

[0047] Optionally, combined Figure 4 and Figure 6 As shown, the voltage amplitude detection circuit 20 includes: a third capacitor C3, a fourth capacitor C4, and a second resistor R2. The first end of the third capacitor C3 receives the oscillation voltage; the second end of the third capacitor C3 is connected to the first end of the second resistor R2; the second end of the second resistor R2 is connected to the second end of the fourth capacitor C4, and is connected to the first bias circuit 30; the first end of the fourth capacitor C4 is connected to the power supply.

[0048] In this embodiment, the third capacitor C3 couples the oscillation voltage output by the core oscillation circuit 10 by means of AC coupling. The second resistor R2 and the fourth capacitor C4 form a low-pass filter structure to filter out the AC signal. When the amplitude of the oscillation voltage output by the core oscillation circuit 10 is large, the fourth capacitor C4 is discharged in the negative half cycle of the oscillation voltage, thereby increasing the DC voltage output by the fourth capacitor C4. Therefore, the larger the amplitude of the oscillation voltage output by the core oscillation circuit 10, the higher the DC voltage output by the fourth capacitor C4.

[0049] Optionally, combined Figure 4 and Figure 6 As shown, the first bias circuit 30 includes: a first bias current control circuit 31 and a first bias current output circuit 32. The first bias current control circuit 31 includes a second PMOS transistor PM2, and the first bias current control circuit 31 is configured to generate a first dynamic bias current at the drain of the second PMOS transistor PM2 according to a DC voltage. The first bias current output circuit 32 includes a third PMOS transistor PM3, and the first bias current output circuit 32 is connected to the first bias current control circuit 31, and is configured to amplify the first dynamic bias current and output the first bias current at the drain of the third PMOS transistor PM3; wherein the second PMOS transistor PM2 and the third PMOS transistor PM3 are of a common source and common gate structure.

[0050] In this embodiment, the first bias current control circuit 31 can dynamically adjust the magnitude of the first dynamic bias current generated by the drain of the second PMOS transistor PM2 according to the DC voltage output by the voltage amplitude detection circuit 20, thereby achieving the purpose of adaptively and dynamically adjusting the first bias current following the amplitude of the oscillation voltage of the core oscillation circuit 10. The first dynamic bias current can be amplified by the common source and common gate structure formed by the second PMOS transistor PM2 and the third PMOS transistor PM3, and finally the first bias current is output at the drain of the third PMOS transistor PM3.

[0051] Optionally, combined Figure 4 and Figure 6 As shown, the first bias current control circuit 31 also includes: a first PMOS transistor PM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, and a third resistor R3. The source of the first PMOS transistor PM1 is connected to the power supply; the gate of the first PMOS transistor PM1 is connected to the second end of the third capacitor C3; the drain of the first PMOS transistor PM1 is connected to the drain of the second NMOS transistor NM2, the drain of the third NMOS transistor NM3, the gate of the third NMOS transistor NM3, the gate of the second PMOS transistor PM2, and the second end of the fourth capacitor C4; the source of the second PMOS transistor PM2 is connected to the power supply; the drain of the second PMOS transistor PM2 is connected to the first end of the third resistor R3 and the gate of the fourth NMOS transistor NM4; the gate of the second NMOS transistor NM2 is connected to the source of the third NMOS transistor NM3, the second end of the third resistor R3, and the drain of the fourth NMOS transistor NM4; the source of the second NMOS transistor NM2 is grounded; and the source of the fourth NMOS transistor NM4 is grounded.

[0052] In this embodiment, the third capacitor C3 couples the oscillation voltage output by the core oscillation circuit 10 to the gate of the first PMOS transistor PM1, thereby reducing the gate-source voltage of the first PMOS transistor PM1 in the negative half cycle of the oscillation voltage, and at this time, the fourth capacitor C4 is discharged, thereby increasing the DC voltage output by the fourth capacitor C4. The DC voltage output by the fourth capacitor C4 is directly loaded on the gate of the second PMOS transistor PM2. The higher the gate voltage of the second PMOS transistor PM2, the lower the source-drain current of the second PMOS transistor PM2. Therefore, the drain-source current of the second PMOS transistor PM2, that is, the first dynamic bias current, gradually decreases as the amplitude of the oscillation voltage output by the core oscillation circuit 10 increases.

[0053] Optionally, combined Figure 4 and Figure 6As shown, the first bias current output circuit 32 further includes: a fourth resistor R4 and a fifth capacitor C5. The first end of the fourth resistor R4 is connected to the gate of the second PMOS transistor PM2; the second end of the fourth resistor R4 is connected to the second end of the fifth capacitor C5 and the gate of the third PMOS transistor PM3; the first end of the fifth capacitor C5 is connected to the power supply; the source of the third PMOS transistor PM3 is connected to the power supply; and the drain of the third PMOS transistor PM3 outputs the first bias current.

[0054] In this embodiment, the fourth resistor R4 and the fifth capacitor C5 form a low-pass filter circuit structure, and the voltage signal output by the fourth capacitor C4 is low-pass filtered to suppress the influence of noise on the oscillation frequency performance. The second PMOS tube PM2 and the third PMOS tube PM3 are common source and common gate structures, so the third PMOS tube PM3 and the second PMOS tube PM2 maintain the same gate-source voltage, and the third PMOS tube PM3 will copy the drain-source current of the second PMOS tube PM2 according to a certain proportion. Therefore, the output current of the third PMOS tube PM3 will also gradually decrease as the amplitude of the oscillation voltage output by the core oscillation circuit 10 increases. Moreover, after the core oscillator is started, the output current of the third PMOS tube PM3 becomes extremely low, close to zero, thereby achieving the purpose of reducing power consumption.

[0055] Optionally, combined Figure 5 and Figure 6 As shown, the second bias circuit 40 includes: a second bias current control circuit 41 and a second bias current output circuit 42. The second bias current control circuit 41 includes a fifth PMOS transistor PM5, and the second bias current control circuit 41 is configured to generate a second dynamic bias current at the drain of the fifth PMOS transistor PM5 according to temperature changes. The second bias current output circuit 42 includes a sixth PMOS transistor PM6, and the second bias current output circuit 42 is connected to the second bias current control circuit 41, and is configured to amplify the second dynamic bias current and output the second bias current at the drain of the sixth PMOS transistor PM6; wherein the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 are of a common source and common gate structure.

[0056] In this embodiment, similar to the first bias circuit 30, the second bias current control circuit 41 in the second bias circuit 40 can dynamically adjust the drain current of the fifth PMOS transistor PM5 according to temperature changes, and output the second bias current at the drain of the sixth PMOS transistor PM6 after being amplified by the common source and common gate structure of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6, so as to compensate for the deterioration of the transconductance of the first NMOS transistor NM1 under high temperature conditions.

[0057] Optionally, combined Figure 5 and Figure 6As shown, the second bias current control circuit 41 also includes: a fourth PMOS transistor PM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, and a fifth resistor R5. The source of the fourth PMOS transistor PM4 is connected to the power supply; the gate of the fourth PMOS transistor PM4 is connected to the gate of the fifth PMOS transistor PM5, the drain of the fourth PMOS transistor PM4, the drain of the fifth NMOS transistor NM5, the drain of the sixth NMOS transistor NM6, and the gate of the sixth NMOS transistor NM6; the source of the fifth PMOS transistor PM5 is connected to the power supply; the drain of the fifth PMOS transistor PM5 is connected to the first end of the fifth resistor R5 and the gate of the seventh NMOS transistor NM7; the gate of the fifth NMOS transistor NM5 is connected to the source of the sixth NMOS transistor NM6, the second end of the fifth resistor R5, and the drain of the seventh NMOS transistor NM7; the source of the fifth NMOS transistor NM5 is grounded; and the source of the seventh NMOS transistor NM7 is grounded.

[0058] In this embodiment, the second dynamic bias current is the drain current of the fifth PMOS tube PM5, and is also the current flowing through the fifth resistor R5. The two ends of the fifth resistor R5 are respectively connected to the gate of the seventh NMOS tube NM7 and the gate of the fifth NMOS tube NM5. The gate of the fifth NMOS tube NM5 is also connected to the source of the sixth NMOS tube NM6. As the temperature changes, the threshold voltage of the sixth NMOS tube NM6 will change, thereby changing the source voltage of the sixth NMOS tube NM6. The higher the temperature, the lower the source voltage of the sixth NMOS tube NM6, thereby increasing the current flowing through the fifth resistor R5. Therefore, the second bias current control circuit 41 adopts a circuit structure in which a conventional NMOS device and a resistor jointly generate a positive temperature coefficient current, and can provide a second dynamic bias current that changes with temperature. The higher the temperature, the higher the second dynamic bias current. The second bias current control circuit 41 only provides a second dynamic bias current that changes with temperature, and after the core oscillation circuit 10 is stable, it continues to provide the second bias current to the core oscillation circuit 10.

[0059] Optionally, combined Figure 5 and Figure 6 As shown, the second bias current output circuit 42 further includes: a sixth resistor R6 and a sixth capacitor C6. The first end of the sixth resistor R6 is connected to the gate of the fifth PMOS transistor PM5; the second end of the sixth resistor R6 is connected to the second end of the sixth capacitor C6 and the gate of the sixth PMOS transistor PM6; the first end of the sixth capacitor C6 is connected to the power supply; the source of the sixth PMOS transistor PM6 is connected to the power supply; and the drain of the sixth PMOS transistor PM6 outputs the second bias current.

[0060] The crystal oscillator circuit provided by the embodiment of the present disclosure can adaptively control the bias current according to the crystal oscillation situation under the premise of achieving rapid crystal oscillation. The amplitude of the crystal oscillation voltage is detected in real time, and the magnitude of the first bias current is adaptively controlled according to the amplitude of the oscillation voltage. At the beginning of startup, a large bias current is provided to ensure rapid crystal oscillation. As the amplitude of the crystal oscillation voltage increases, the magnitude of the bias current is gradually reduced until the bias circuit outputs the lowest bias current after the crystal startup is completed. By outputting a smooth bias current, the instability problem that may be caused by a drastic mutation of the bias current of the core oscillation circuit 10 can be reduced. In addition, the second bias circuit 40 can also output a second bias current that changes positively with temperature to compensate for the problem of reduced transconductance of the NMOS device under high temperature conditions, thereby reducing the working power consumption at normal temperature and low temperature.

[0061] An embodiment of the present disclosure provides a crystal oscillator, comprising the crystal oscillator circuit as described above.

[0062] The above description and accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the technical solutions recorded in this application. As used in the technical solutions recorded in this application, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

Claims

1. A crystal oscillator circuit, characterized in that: include: A core oscillator circuit is configured to output an oscillating voltage; A voltage amplitude detection circuit is connected to the core oscillation circuit and is configured to detect the amplitude of the oscillation voltage and output a DC voltage according to the amplitude of the oscillation voltage; A first bias circuit is connected to the voltage amplitude detection circuit and the core oscillation circuit respectively, and is configured to output a first bias current according to the DC voltage; A second bias circuit connected to the core oscillator circuit and configured to output a second bias current according to temperature changes; The first bias current and the second bias current act on the core oscillation circuit to provide bias current for the core oscillation circuit.

2. The crystal oscillator circuit according to claim 1, characterized in that: The core oscillation circuit includes: a first resistor, a first capacitor, a second capacitor, a first NMOS tube, and a crystal; The first end of the first resistor, the first end of the first capacitor, and the gate of the first NMOS tube are connected to output an oscillation voltage and are connected to the first end of the crystal; the second end of the first resistor, the drain of the first NMOS tube, and the first end of the second capacitor are connected to receive a bias current and are connected to the second end of the crystal; the second end of the first capacitor, the source of the first NMOS tube, and the second end of the second capacitor are all grounded.

3. The crystal oscillator circuit according to claim 1, characterized in that: The voltage amplitude detection circuit includes: a third capacitor, a fourth capacitor, and a second resistor; The first end of the third capacitor receives the oscillating voltage; the second end of the third capacitor is connected to the first end of the second resistor; the second end of the second resistor is connected to the second end of the fourth capacitor and to the first bias circuit; the first end of the fourth capacitor is connected to the power supply.

4. The crystal oscillator circuit according to claim 3, characterized in that: The first bias circuit comprises: A first bias current control circuit includes a second PMOS tube, and the first bias current control circuit is configured to generate a first dynamic bias current at the drain of the second PMOS tube according to a DC voltage; A first bias current output circuit, comprising a third PMOS tube, the first bias current output circuit is connected to the first bias current control circuit, and is configured to amplify the first dynamic bias current and output the first bias current at the drain of the third PMOS tube; The second PMOS tube and the third PMOS tube are of a common-source and common-gate structure.

5. The crystal oscillator circuit according to claim 4, characterized in that: The first bias current control circuit also includes: a first PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a third resistor; The source of the first PMOS tube is connected to the power supply; the gate of the first PMOS tube is connected to the second end of the third capacitor; the drain of the first PMOS tube is connected to the drain of the second NMOS tube, the drain of the third NMOS tube, the gate of the third NMOS tube, the gate of the second PMOS tube, and the second end of the fourth capacitor; the source of the second PMOS tube is connected to the power supply; the drain of the second PMOS tube is connected to the first end of the third resistor and the gate of the fourth NMOS tube; the gate of the second NMOS tube is connected to the source of the third NMOS tube, the second end of the third resistor, and the drain of the fourth NMOS tube; the source of the second NMOS tube is grounded; the source of the fourth NMOS tube is grounded.

6. The crystal oscillator circuit according to claim 5, characterized in that: The first bias current output circuit further includes: a fourth resistor and a fifth capacitor; The first end of the fourth resistor is connected to the gate of the second PMOS tube; the second end of the fourth resistor is connected to the second end of the fifth capacitor and the gate of the third PMOS tube; the first end of the fifth capacitor is connected to the power supply; the source of the third PMOS tube is connected to the power supply; the drain of the third PMOS tube outputs the first bias current.

7. The crystal oscillator circuit according to claim 1, characterized in that: The second bias circuit comprises: A second bias current control circuit, comprising a fifth PMOS tube, the second bias current control circuit being configured to generate a second dynamic bias current at the drain of the fifth PMOS tube according to temperature changes; A second bias current output circuit, comprising a sixth PMOS tube, the second bias current output circuit is connected to the second bias current control circuit, and is configured to amplify the second dynamic bias current and output the second bias current at the drain of the sixth PMOS tube; The fifth PMOS tube and the sixth PMOS tube are of a common-source and common-gate structure.

8. The crystal oscillator circuit according to claim 7, characterized in that: The second bias current control circuit further includes: a fourth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a fifth resistor; The source of the fourth PMOS tube is connected to the power supply; the gate of the fourth PMOS tube is connected to the gate of the fifth PMOS tube, the drain of the fourth PMOS tube, the drain of the fifth NMOS tube, the drain of the sixth NMOS tube, and the gate of the sixth NMOS tube; the source of the fifth PMOS tube is connected to the power supply; the drain of the fifth PMOS tube is connected to the first end of the fifth resistor and the gate of the seventh NMOS tube; the gate of the fifth NMOS tube is connected to the source of the sixth NMOS tube, the second end of the fifth resistor, and the drain of the seventh NMOS tube; the source of the fifth NMOS tube is grounded; the source of the seventh NMOS tube is grounded.

9. The crystal oscillator circuit according to claim 8, characterized in that: The second bias current output circuit further includes: a sixth resistor and a sixth capacitor; The first end of the sixth resistor is connected to the gate of the fifth PMOS tube; the second end of the sixth resistor is connected to the second end of the sixth capacitor and the gate of the sixth PMOS tube; the first end of the sixth capacitor is connected to the power supply; the source of the sixth PMOS tube is connected to the power supply; the drain of the sixth PMOS tube outputs the second bias current.

10. A crystal oscillator, characterized in that: include: A crystal oscillator circuit as claimed in any one of claims 1 to 9.

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