Power semiconductor device with deep energy level acceptor impurity p base region and manufacturing method

Abstract

The invention discloses a power semiconductor chip with a deep-energy-level acceptor impurity p base region and a manufacturing method, and belongs to the field of power semiconductor preparation. According to the power semiconductor device chip, deep energy level acceptor impurities are adopted in a p base region to form a p + base region covered by a whole cell, or additional deep energy level acceptor impurities are added on the basis of traditional p + base region doping to form the p + + base region covered by the whole cell; wherein the distance between the energy level position of the deep-energy-level acceptor impurity in silicon and the valence band top EV is more than 0.1 eV. Compared with a traditional power semiconductor device structure, the current turn-off capability of the IGCT device can be effectively improved, and the conduction voltage drop is obviously reduced compared with a traditional structure; the contradiction between the p + base region doping concentration of the IGCT and the current turn-off capability and the conduction voltage drop of the device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of power semiconductor devices, and in particular to a power semiconductor device chip having a deep energy level acceptor impurity p+ base region or p++ base region, a manufacturing method thereof, a semiconductor device and an electronic device. Background Art

[0002] Integrated Gate-Commutated Thyristor (IGCT) is a new type of high-voltage and high-power power electronic device with the advantages of high voltage, high current, and low voltage drop. It is widely used in the field of power electronics. IGCT is a device that integrates the improved GTO chip with the gate drive circuit. It is essentially a thyristor device. When it is turned on, it has a strong conductivity modulation effect to ensure low on-state voltage drop and high current capacity. At the same time, due to the introduction of transparent anode, field stop layer and hard drive technology, it has fast and reliable switching characteristics, and no buffer circuit is required when it is used. The design concept of IGCT was first proposed by ABB of Switzerland in 1996. Compared with the insulated gate bipolar transistor (IGBT), the switching frequency of IGCT is lower (<1kHz), but it has the advantages of higher withstand voltage, greater current capacity, lower on-state voltage drop, higher reliability and lower manufacturing cost. In fact, compared with AC grid applications, key equipment such as medium- and high-voltage large-capacity AC-DC converters, DC transformers, and DC circuit breakers in DC grids have many new features, such as: the switching frequency of modular multi-level AC-DC converters is very low, the dual-active full-bridge DC transformer has soft switching capability, and the DC circuit breaker only requires a single operation, etc. These features largely avoid the disadvantage of low operating frequency of IGCT, bringing opportunities for the application of IGCT in DC grids.

[0003] Although IGCT has excellent performance, in practical applications, there are many factors that restrict the further expansion of IGCT's safe operating area (SOA), and the reliability of IGCT needs to be improved, especially the shutdown process of IGCT is often accompanied by shutdown failure or even device damage. When IGCT is turned off under high voltage and high current conditions, due to the influence of excess carriers in the base region, the device is prone to dynamic avalanche at a voltage much lower than the static blocking voltage, causing the device to fail to shut down or even cause irreversible electrothermal breakdown.

[0004] In 2013, ABB published a paper pointing out two main failure mechanisms when IGCT is turned off: when the DC side voltage is low, hard drive failure is the main failure mechanism; when the DC side voltage is high, dynamic avalanche is the main failure mechanism, such asFigure 1 As shown. This paper conducts an in-depth study on the previously established IGCT three-dimensional simulation model and explains the failure mechanism of IGCT. It is pointed out that in the initial stage of shutdown, the mobile charge in the area below the cathode of the IGCT is quickly depleted and the injection is interrupted. In the next stage of shutdown, the depletion of excess carriers penetrates deep into the p-base and n-base regions, and the dynamic avalanche maintains the concentration of free carriers at a high level. The carrier density under the cathode is greater, which in turn causes the conduction current to be concentrated near that location. This increased lateral current density strongly increases the quasi-Fermi potential difference in the middle of the cathode p-base junction. At the beginning of the fault, the flowing current becomes large enough to locally compensate for the potential barrier of the junction and cause the thyristor to be triggered again, which fills the nearby area with plasma, the depletion layer completely collapses, and the highly conductive area takes over the entire load current and leads to the final failure of the device.

[0005] The main reason for the hard drive failure mechanism when the IGCT is turned off is that the working principle of the IGCT requires the gate drive unit to commutate all the anode current to the gate unit in a very short time, so the inductance and impedance requirements of the IGCT gate drive circuit are very high, that is, the gate resistance R G and parasitic inductance L G Must be very small to ensure hard drive operation of the IGCT.

[0006] For the dynamic avalanche failure mechanism when IGCT is turned off, the current main methods are to reduce the risk of cathode re-triggering caused by IGCT dynamic avalanche and improve the turn-off capability of IGCT devices by optimizing structures such as wavy junction p-base structure, strip enhancement structure, and gate carrier extraction enhancement structure.

[0007] In 2007, ABB first proposed the concept of corrugated p-base IGCT. Figure 2 As shown. The test results show that the wavy junction p-base IGCT can effectively improve the current shutoff capability of the device, especially the current shutoff capability of the device at room temperature. At 25°C, the current shutoff capability of the wavy junction p-base IGCT is increased from 5kA to 7.2kA; however, at 125°C, the current shutoff capability of the wavy junction p-base IGCT is not significantly improved, from 6kA to about 6.7kA.

[0008] In 2014, ABB proposed the Stripe Fortified GCT chip structure, such as Figure 3As shown in . The design concept of this structure is to make the p-base region low-doped to achieve a high gate-cathode breakdown voltage, and the p+ buried layer set inside the p-base region is intended to restore the lateral resistance of this region to reduce the risk of thyristor latching when the device is turned off and improve the current shutdown capability of the device. Three strip enhancement structures are designed in this paper, namely the structure located under the gate, the structure located under the cathode, and the whole cell covering structure. The simulation results show that the whole cell covering strip enhancement chip structure has the strongest current shutdown capability, and there is an optimal value (30μm) between the p+ region and the chip surface. The maximum current shutdown capability can be increased from 4000A to 5200A.

[0009] In 2015, Tsinghua University's Chinese patent CN105590959B proposed the use of a dual p-base gate cathode structure to improve the current shutoff capability of IGCT. Figure 4 As shown, the p-base region 2 of the structure adopts the epitaxial method, and the concentration can be set lower than that of the p-base region 1, so as to increase the gate cathode breakdown voltage and increase the commutation speed. The p+ short base region will not affect the gate cathode breakdown voltage, and the peak concentration of the p+ short base region can be increased to form a low-resistance channel for current transfer and achieve fast commutation. The design concept of this patent is similar to the strip-enhanced IGCT structure proposed by ABB.

[0010] CRRC Corporation proposed the gate carrier extraction enhancement structure (CEET) in 2016. Figure 5 As shown in , the doping concentration distribution of the p-base region below the gate is optimized so that the doping concentration of the p2+ base region is greater than that of the p1+ base region, forming a lateral barrier. During the shutdown process, the high-concentration p2+ base region allows carriers to be quickly extracted to the gate, thereby improving the shutdown capability of the device. In a specific embodiment, the width of the p2+ base region can increase with the distance between the cathode comb bar and the gate ring.

[0011] It can be seen that several methods for improving the turn-off performance of IGCT have been proposed in the prior art, among which there are still more or less defects such as complex processing technology, high processing cost, or limited performance improvement, and the need to further improve the performance. In addition, it should be pointed out that the improvement of the turn-off capability often leads to an increase in the conduction voltage drop of the device, but the above-mentioned inventive structure often avoids this shortcoming, resulting in the final design of the device needing to make a trade-off between the turn-off capability and the conduction characteristics. To this end, the inventors have taken a different approach and used a deep energy level impurity p+ base region or p++ base region to develop a new power semiconductor device chip and manufacturing method, which better solves the defects and deficiencies of the prior art. Summary of the invention

[0012] In view of this, the main purpose of the present invention is to provide a power semiconductor device chip with a deep energy level impurity p-base region and a manufacturing method thereof, in order to at least partially solve the above technical problems.

[0013] In order to achieve the above-mentioned object, as a first aspect of the present invention, a power semiconductor device chip is proposed, wherein the power semiconductor device chip uses deep energy level acceptor impurities in the p-base region to form a layer covering the entire cell; wherein the energy level position of the deep energy level acceptor impurities in silicon is 1000 nm away from the valence band top E V Above 0.1eV.

[0014] As a second aspect of the present invention, a method for preparing a power semiconductor device chip is also proposed, comprising the following steps:

[0015] A deep energy level acceptor impurity is doped into the p-base region formed on the n-base region by a high energy ion implantation process to form a layer covering the entire cell; wherein the energy level position of the deep energy level acceptor impurity in silicon is 1000 nm away from the valence band top E V Above 0.1eV;

[0016] Annealing is performed to activate the layer formed by the deep energy level acceptor impurities; and the preparation of the power semiconductor device chip is completed.

[0017] As a third aspect of the present invention, a power semiconductor device chip manufactured based on the manufacturing method of the power semiconductor device chip as described above is also proposed.

[0018] As a fourth aspect of the present invention, a power semiconductor device comprising the power semiconductor chip as described above is also proposed, wherein the power semiconductor device is a GCT, an IGCT or a GTO.

[0019] As a fifth aspect of the present invention, an electronic device using the power semiconductor device as described above is also proposed.

[0020] Based on the above technical solution, it can be seen that the power semiconductor device with a deep energy level acceptor impurity p+ base region or p++ base region and the manufacturing method thereof of the present invention have at least one of the following beneficial effects compared with the prior art:

[0021] The present invention proposes a technical means for improving the turn-off performance of IGCT which is different from the prior art. The implementation of the means is relatively simple, and it is only to simply add a deep energy level impurity p+ base region or p++ base region. The preparation process is simple, and the improvement effect is relatively significant.

[0022] Compared with the traditional structure 1, the IGCT of the present invention can effectively improve the current shutoff capability of the IGCT device; compared with the traditional structure 2, the current shutoff capability of the IGCT of the present invention is equivalent to that of the traditional structure 2, but the on-state voltage drop of the IGCT of the present invention is significantly lower than that of the traditional structure 2. The present invention can improve the contradiction between the p+ base region doping concentration of the IGCT and the device current shutoff capability and on-state voltage drop. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below.

[0024] Figure 1 It is a distribution diagram of two main failure mechanisms when the IGCT of the prior art is turned off;

[0025] Figure 2 It is a schematic diagram of the structure of a wave junction p-base region IGCT of the prior art;

[0026] Figure 3 It is a structural schematic diagram of a strip-enhanced IGCT chip in the prior art;

[0027] Figure 4 It is a schematic diagram of the structure of an IGCT chip with a double p-base gate cathode structure in the prior art;

[0028] Figure 5 It is a structural schematic diagram of an IGCT chip with a gate carrier extraction enhancement structure in the prior art;

[0029] Figure 6 1 is a schematic structural diagram of an asymmetric IGCT chip with a deep energy level acceptor impurity p++ base region according to Embodiment 1 of the present invention;

[0030] Figure 7 It is a schematic diagram of the structure of a conventional asymmetric IGCT chip (conventional structure 1) in the prior art;

[0031] Figure 8 It is a schematic diagram of the structure of the ABB strip-enhanced IGCT chip (traditional structure 2) of the prior art;

[0032] Fig. 9 is a schematic structural diagram of a reverse resistance type IGCT chip according to Embodiment 2 of the present invention;

[0033] Fig.10 is a schematic structural diagram of an asymmetric IGCT chip with a wavy junction according to Embodiment 3 of the present invention;

[0034] Fig.11 yes Figure 8 The curve variation diagram of the total doping concentration in the IGCT of the conventional structure 2 and the doping concentration activated at 300K and 400K;

[0035] Fig.12 yes Figure 6 The total doping concentration of the IGCT of the present invention and the curve variation of the doping concentration activated at 300K and 400K are shown;

[0036] Fig.13It is a comparison diagram of the conduction characteristics of the conventional structure 1, the conventional structure 2 and the IGCT of the present invention at a temperature of 300K (normal temperature);

[0037] Fig.14A , 14B They are the overall circuit diagram of the IGCT switch circuit established for simulation and study of the turn-off characteristics and the local circuit diagram containing two GCT chips (cells);

[0038] Fig.15 It is a waveform comparison diagram of the traditional structure 1, the traditional structure 2 and the IGCT structure of the present invention when being turned off.

[0039] The above-mentioned Figure 6-10 In the figure, the meanings of the reference numerals are as follows:

[0040] 01 is the n-base region; 02 is the n-type buffer layer; 03 is the p+ anode region; 04 is the p base region; 05 is the p+ base region; 06 is the p++ base region; 106 is the p++ base region formed by using deep energy level acceptor impurities in the present invention; 07 is the n+ cathode region; 08 is the gate metal; 09 is the cathode metal; 10 is the anode metal. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0042] In the prior art, the main failure mechanism of IGCT when it is turned off has been studied in depth. For example, ABB pointed out that when the DC side voltage is low, hard drive failure is the main failure mechanism; when the DC side voltage is high, dynamic avalanche is the main failure mechanism. Several methods for improving the turn-off performance of IGCT have also been proposed in the prior art, but there are still more or less problems and defects such as complex processing technology, high processing cost, or limited performance improvement, and the need to further improve performance. It is particularly important to point out that the improvement of the turn-off capability often leads to an increase in the conduction voltage drop of the device, but the above-mentioned inventive structure often avoids this shortcoming, resulting in the final design of the device needing to make a trade-off between the turn-off capability and the conduction characteristics. To this end, the inventors have conducted in-depth research and developed a new power semiconductor device chip and manufacturing method by taking a different approach, using a deep energy level acceptor impurity p+ base region or p++ base region to better solve the above-mentioned defects and deficiencies of the prior art.

[0043] Specifically, the present invention proposes an IGCT chip structure with a deep-level acceptor impurity p+ base region or a p++ base region, wherein the p+ base region of the IGCT is formed by deep-level acceptor impurities; or the p+ base region of the IGCT is doped with additional deep-level acceptor impurities on the basis of the existing traditional p+ base region, that is, an additional p++ base region is formed by deep-level acceptor impurities. The present invention has two advantages over the traditional IGCT structure: (1) The activation rate of deep-level impurities is very low at room temperature, which is beneficial to improving the emitter injection efficiency on the cathode side and reducing the on-state voltage drop of the chip; (2) The activation rate of deep-level impurities is relatively high at high temperatures, which is beneficial to reducing the sheet resistance of the p-base region, effectively reducing the risk of dynamic avalanche re-triggering of the IGCT during the shutdown process, and improving the shutdown capability of the IGCT chip.

[0044] Since the carrier lifetime increases with increasing temperature, the parasitic gain of the transistor inside the IGCT increases at high temperatures, making it more likely to fail to re-trigger when turned off. The present invention can improve the contradiction between the p+ base region doping concentration of the IGCT and the device current shutoff capability and the conduction voltage drop (i.e., increasing the doping concentration of the p+ base region is beneficial to improving the device's shutoff capability, but will increase the conduction voltage drop; vice versa). And by reasonably setting the p+ base region peak formed by deep energy level impurities at a position far away from the J3 junction inside the IGCT, the gate-cathode blocking voltage of the device is not affected.

[0045] When the energy level of the impurity element in the semiconductor is located at a distance from the bottom of the conduction band E C or valence band top E V When the distance is far, the ionization energy of the impurity is large, and incomplete ionization is prone to occur. Table 1 shows the commonly used doping elements in silicon materials and their energy level positions. Phosphorus and arsenic are commonly used shallow energy level donor impurities in silicon, and are often used to form N-type doping in silicon; selenium and sulfur are deep energy level donor impurities in silicon, and exhibit non-complete ionization characteristics at room temperature. Boron and aluminum are commonly used shallow energy level acceptor impurities in silicon, and are often used to form p-type doping in silicon; indium and thallium are deep energy level donor impurities in silicon, and exhibit non-complete ionization characteristics at room temperature.

[0046] Table 1

[0047] Impurity Elements <![CDATA[Energy level position (from E C )]]> <![CDATA[Energy level position (from E V )]]> Phosphorus 0.045eV Arsenic 0.05eV Selenium 0.31eV Sulfur 0.32eV Boron 0.044eV Aluminum 0.069eV Gallium 0.073eV Indium 0.16eV Thallium 0.25eV

[0048] Figure 6 The present invention proposes an asymmetric IGCT chip structure with a deep energy level impurity p-base region, wherein 01 is an n-base region, 02 is an n-type buffer layer, 03 is a p+ anode region, 04 is a p-base region, 05 is a p+ base region, 106 is a p++ base region formed by using deep energy level acceptor impurities proposed in the present invention, 07 is an n+ cathode region, 08 is a gate metal, 09 is a cathode metal, and 10 is an anode metal.

[0049] 106 is a p++ base region formed by using deep energy level acceptor impurities proposed in the present invention. The energy level position of the impurity element in silicon is 1.5 m from the top of the valence band E V It should be above 0.1eV, and preferably, the impurity element is indium and thallium. The deep energy level acceptor impurity exhibits the characteristic of non-complete ionization at room temperature, which can effectively reduce the effective doping concentration of the p-base region activated at room temperature of the IGCT, improve the emitter injection efficiency on the cathode side, and reduce the on-state voltage drop of the chip; the activation rate of the impurity element is high at high temperature, which is conducive to reducing the sheet resistance of the p-base region, effectively reducing the risk of dynamic avalanche re-triggering of the IGCT during the shutdown process, and improving the shutdown capability of the IGCT chip.

[0050] The p++ base region formed by the deep energy level acceptor impurity should be kept 2 to 30 μm away from the n+ cathode region of the device to prevent the p-type impurity elements that are additionally ionized at high temperature from affecting the gate-cathode blocking voltage of the IGCT device. When indium is used as the deep energy level acceptor impurity of this layer, preferably, the peak doping concentration is 2E17 to 9E17 cm -3 The peak concentration position is 3 to 10 μm away from the junction depth of the n+ cathode region. The p++ base region structure formed by the deep energy level acceptor impurities can be realized using high energy ion implantation process and annealing activation.

[0051] The present invention can improve the contradiction between the p+ base region doping concentration of the IGCT and the device current shutoff capability and the on-state voltage drop.

[0052] In a specific embodiment, the present invention provides a power semiconductor device chip, wherein the power semiconductor device chip uses deep energy level acceptor impurities in the p-base region to form a layer covering the entire cell; wherein the energy level position of the deep energy level acceptor impurities in silicon is 1000 nm away from the valence band top E V Above 0.1eV.

[0053] The power semiconductor device is, for example, a GCT, a GTO or an IGCT.

[0054] The layer covered by the whole cell formed by deep-level acceptor impurities is a p+ base region, or a p++ base region formed inside or below a p+ base region formed by doping an existing p base region.

[0055] The power semiconductor device chip includes, for example, a p-base region formed on an n-base region, a p++ base region formed by deep-level acceptor impurities, a p+ base region, a gate electrode, and a cathode electrode.

[0056] The deep energy level acceptor impurities include, for example, indium (In) and thallium (Tl), but are not limited thereto. From the implementation principle, the present invention may also include other deep energy level acceptor impurities as long as they meet the activation rate and ionization characteristics at different temperatures.

[0057] The p++ base region formed by the deep energy level acceptor impurities maintains a distance of 2 to 30 μm from the bottom surface of the n+ cathode region of the power semiconductor device chip, for example.

[0058] When indium is used as a deep level acceptor impurity, the peak doping concentration of the indium element can be selected in the range of 2E17 to 9E17 cm -3 The distance between the peak concentration position and the junction depth of the n+ cathode region is 3 to 10 μm.

[0059] The p++ base region formed by the deep energy level acceptor impurities is prepared, for example, by a high energy ion implantation process and annealing activation.

[0060] In a specific embodiment, the present invention further provides a method for preparing a power semiconductor device chip, comprising the following steps:

[0061] A p-base region formed on an n-base region is doped with deep energy level acceptor impurities by a high energy ion implantation process to form a p+ base region covered by a whole cell, or a p-base region formed on an n-base region is doped with conventional impurities to form a p+ base region, and then a deep energy level acceptor impurity is doped on the basis thereof to form a p++ base region covered by a whole cell; wherein the energy level position of the deep energy level acceptor impurity in silicon is 1000 nm from the valence band top E V Above 0.1eV;

[0062] Annealing is performed to activate the p+ base region or p++ base region formed by the deep energy level acceptor impurities; and the preparation of the power semiconductor device chip is completed.

[0063] The power semiconductor device is, for example, a GCT, a GTO or an IGCT.

[0064] The preparation method, for example, further includes the step of forming a gate and a cathode on the p++ base region formed by the deep energy level acceptor impurities.

[0065] The deep energy level acceptor impurities include, for example, indium (In) or thallium (Tl), but are not limited thereto. In principle, the present invention may also include other deep energy level acceptor impurities as long as they meet the activation rate and ionization characteristics at different temperatures.

[0066] The p++ base region formed by the deep energy level acceptor impurities maintains a distance of 2 to 30 μm from the lower surface (bottom surface) of the n+ cathode region of the power semiconductor device chip, for example.

[0067] When indium is used as a deep level acceptor impurity, the peak doping concentration of the indium element can be selected in the range of 2E17 to 9E17 cm -3 The distance between the peak concentration position and the junction depth of the n+ cathode region is 3 to 10 μm.

[0068] In a specific embodiment, the present invention further proposes a power semiconductor chip manufactured based on the above-mentioned power semiconductor chip manufacturing method.

[0069] The present invention also discloses a power semiconductor device comprising the power semiconductor chip, wherein the power semiconductor device is, for example, a GCT, an IGCT, a GTO, etc.

[0070] The present invention also discloses an electronic device using the power semiconductor device, such as a rectifier, a converter, an inverter, a power switch, a switching circuit device, etc.

[0071] The present invention will be further described below through specific examples. It should be noted that the following examples are only for illustration and are not intended to limit the present invention.

[0072] Example 1

[0073] Figure 6 This is an asymmetric IGCT chip structure with a deep energy level acceptor impurity p++ base region of this embodiment, wherein 01 is an n-base region, 02 is an n-type buffer layer, 03 is a p+ anode region, 04 is a p base region, 05 is a p+ base region, 106 is a p++ base region formed by using deep energy level acceptor impurities proposed by the present invention, 07 is an n+ cathode region, 08 is a gate metal, 09 is a cathode metal, and 10 is an anode metal. This structure can improve the current shutoff capability of the IGCT device, while having little effect on the on-state voltage drop of the IGCT.

[0074] Example 2

[0075] Fig. 9 It is a reverse resistance type IGCT chip structure of this embodiment. Among them, 01 is n-base region, 03 is p+ anode region, 11 is p-type anode region, 04 is p base region, 05 is p+ base region, 106 is p++ base region formed by deep energy level acceptor impurities proposed in the present invention, 07 is n+ cathode region, 08 is gate metal, 09 is cathode metal, and 10 is anode metal.

[0076] Example 3

[0077] Fig.10 This is an asymmetric IGCT chip structure with a wavy junction in this embodiment. 01 is an n-base region, 02 is an n-type buffer layer, 03 is a p+ anode region, 12 is a wavy junction p base region, 05 is a p+ base region, 106 is a p++ base region formed by using deep energy level acceptor impurities proposed in the present invention, 07 is an n+ cathode region, 08 is a gate metal, 09 is a cathode metal, and 10 is an anode metal.

[0078] Comparative Example 1

[0079] Figure 7 This is the conventional asymmetric IGCT chip structure (conventional structure 1) of this comparative example, wherein 01 is the n-base region, 02 is the n-type buffer layer, 03 is the p+ anode region, 04 is the p-base region, 05 is the p+ base region, 07 is the n+ cathode region, 08 is the gate metal, 09 is the cathode metal, and 10 is the anode metal.

[0080] Comparative Example 2

[0081] Figure 8 This is the strip-enhanced IGCT chip structure (traditional structure 2) proposed by ABB in this comparative example. 01 is the n-base region, 02 is the n-type buffer layer, 03 is the p+ anode region, 04 is the p base region, 05 is the p+ base region, 06 is the p++ base region, 07 is the n+ cathode region, 08 is the gate metal, 09 is the cathode metal, and 10 is the anode metal. This structure can improve the current shutoff capability of the IGCT device, but at the same time it will increase the on-state voltage drop of the IGCT and weaken the current flow capacity of the device.

[0082] Technical effect comparison

[0083] Fig.11 The total doping concentration of the IGCT of the conventional structure 2 and the doping concentration activated at 300K and 400K are shown in the figure. The p++ base region is doped with the conventional boron element. Fig.11 It can be seen that due to the small impurity ionization energy of boron, the total amount of impurity activation of boron does not change much at temperatures of 300K and 400K, and the impurity activation rate is above 85%.

[0084] Fig.12 The total doping concentration of the IGCT of the present invention and the doping concentration activated at 300K and 400K are shown in Figure 1. The p++ base region is doped with indium elements having a deep energy level. Fig.12 It can be seen that due to the large impurity ionization energy of indium, at 300K, the total amount of impurity activation of indium impurity elements is small, and the impurity activation rate is only 18%; at 400K, the total amount of impurity activation of indium impurity elements increases, and the impurity activation rate reaches 45%. The temperature dependence of the deep energy level impurity activation rate can be used to control the on-state voltage drop and current shutdown capability of IGCT.

[0085] Fig.13 The figure is a comparison of the conduction characteristics of the conventional structure 1, the conventional structure 2 and the IGCT of the present invention at 300K temperature (normal temperature). Fig.13It can be seen that the conduction characteristics of the IGCT of the present invention are significantly better than those of the traditional structure 2, and because the IGCT of the present invention only activates a small amount of deep energy level p-type doping at room temperature, it has little effect on the forward conduction characteristics, and the conduction voltage drop is only slightly higher than that of the traditional structure 1.

[0086] Simulation Circuit Comparison

[0087] The IGCT switch circuit is established, and the advantages of the IGCT structure of the present invention in terms of current shutoff capability are simulated and studied. The IGCT switch circuit established in the present invention includes a current limiting inductor and an RCD snubber circuit, such as Fig.14A As shown in , DUT is the IGCT device under test. The IGCT device contains two GCT chips, such as Fig. 14B As shown in the figure, they are named GCT1 and GCT2, GCT2 represents the IGCT cell far from the gate contact ring, and GCT1 represents the IGCT cell in other areas. GCT2 has an additional gate inductance R compared to GCT1. diff and gate inductance L diff , the area ratio of GCT1 and GCT2 is 83:17.

[0088] The IGCT device used in the simulation is a 6.5kV asymmetric IGCT device. The switch test conditions are: bus voltage VDC = 2800V, and the total anode current of the shutdown is 4500A.

[0089] Fig.15 The waveform comparison diagram of the conventional structure 1, conventional structure 2 and the IGCT structure of the present invention when they are turned off is shown. Since the areas close to the gate contact and far from the gate contact in the IGCT always have slightly different gate impedances, there will be a slight time offset between the cathode rings of each IGCT during the current shutdown, which will cause the current to be redistributed during the shutdown process. The cathode ring of the IGCT far from the gate contact (i.e., GCT2) is prone to current crowding and thus failure. For ease of comparison, Fig.15 Only the cathode currents of the conventional structure 1, conventional structure 2 and GCT2 in the IGCT of the present invention are shown in the shutdown process. After the cathode to gate commutation is completed during the shutdown process of the IGCT, if the cathode current exceeds 10% of its conduction current, it can be determined that the cathode re-triggering fails. Fig.15 It can be seen that the cathode current of GCT2 in conventional structure 1 increased significantly, and cathode re-triggering failure occurred. However, under the same circuit parameters and the same voltage and current stress, the cathode current of GCT2 in conventional structure 2 and the IGCT of the present invention did not increase significantly and was successfully shut down.

[0090] Therefore, compared with the traditional structure 1, the IGCT of the present invention can effectively improve the current shutoff capability of the IGCT device; compared with the traditional structure 2, the current shutoff capability of the IGCT of the present invention is equivalent to that of the traditional structure 2, but the on-state voltage drop of the IGCT of the present invention is significantly lower than that of the traditional structure 2. The present invention can improve the contradiction between the p+ base region doping concentration of the IGCT and the device current shutoff capability and on-state voltage drop.

[0091] The above description is only a preferred embodiment of the embodiment of the present invention and is not intended to limit the embodiment of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiment of the present invention should be included in the scope of protection of the embodiment of the present invention.

Claims

1. A power semiconductor device chip, characterized in that: The power semiconductor device chip uses deep energy level acceptor impurities in the p-base region to form a layer covering the entire cell; wherein the energy level position of the deep energy level acceptor impurities in silicon is 1000 nm away from the valence band top E V Above 0.1eV.

2. The power semiconductor device chip according to claim 1, characterized in that: The layer covered by the whole cell formed by deep energy level acceptor impurities is a p+ base region, or a p++ base region formed inside or below a p+ base region formed by doping an existing p base region.

3. The power semiconductor device chip according to claim 2, characterized in that: The power semiconductor device chip includes a p-base region formed on an n-base region, a p++ base region formed by deep energy level acceptor impurities, a p+ base region, a gate electrode and a cathode; and / or The deep level acceptor impurities include indium or thallium; and / or The p++ base region formed by the deep energy level acceptor impurities is prepared by high energy ion implantation and annealing activation; and / or The p++ base region formed by the deep energy level acceptor impurities is kept at a distance of 2 to 30 μm from the n+ cathode region of the power semiconductor device chip; and / or The p-base region in the power semiconductor device chip is a wavy junction.

4. The power semiconductor device chip according to claim 3, characterized in that: When indium is used as a deep energy level acceptor impurity, the peak doping concentration of the indium element can be selected in the range of 2E17 to 9E17 cm -3 The distance between the peak concentration position and the junction depth of the n+ cathode region is 3 to 10 μm.

5. A method for preparing a power semiconductor device chip, characterized in that: The steps include: A deep energy level acceptor impurity is doped into the p-base region formed on the n-base region by a high energy ion implantation process to form a layer covering the entire cell; wherein the energy level position of the deep energy level acceptor impurity in silicon is 1000 nm away from the valence band top E V Above 0.1eV; Annealing to activate the layer formed by the deep level acceptor impurities; The preparation of the power semiconductor device chip is completed.

6. The preparation method according to claim 5, characterized in that: The layer covered by the whole cell formed by deep-level acceptor impurities is a p+ base region, or a p++ base region formed inside or below a p+ base region formed by doping an existing p base region; and / or The deep level acceptor impurities include indium or thallium; and / or The preparation method further comprises the step of forming a gate electrode and a cathode; and / or The p++ base region formed by the deep energy level acceptor impurities maintains a distance of 2 to 30 μm from the n+ cathode region of the power semiconductor device chip; The p-base region in the power semiconductor device chip is a wavy junction.

7. The preparation method according to claim 6, characterized in that: When indium is used as a deep energy level acceptor impurity, the peak doping concentration of the indium element can be selected in the range of 2E17 to 9E17 cm -3 The distance between the peak concentration position and the junction depth of the n+ cathode region is 3 to 10 μm.

8. A power semiconductor device chip manufactured based on the method for manufacturing a power semiconductor device chip according to any one of claims 5 to 7.

9. A power semiconductor device comprising the power semiconductor chip according to any one of claims 1 to 4 and 8, wherein the power semiconductor device is a GCT, an IGCT or a GTO.

10. An electronic device using the power semiconductor device according to claim 9.

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