Low dropout regulator based on damping coefficient control

Abstract

The invention discloses a low-dropout linear voltage regulator based on damping coefficient control, and belongs to the technical field of linear voltage regulators. The low dropout linear regulator comprises a first-stage amplification circuit, a second-stage amplification circuit, a power-stage circuit and a damping coefficient control circuit. The damping control circuit is added between the second-stage amplifier circuit and the power-stage circuit to adjust a damping factor, so that the linear voltage regulator can obtain good stability and transient characteristics, and in addition, the structure can be used for a structure without an off-chip capacitor and can also be used for a structure with the off-chip capacitor. And the outer capacitor structure is arranged outside the outer capacitor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low voltage drop linear regulator based on damping coefficient control. Background Art

[0002] Low voltage drop linear regulator is the core module of power management chip. It is widely integrated in the system on chip to power its core module and provide stable voltage. Its power consumption, noise, transient response, efficiency and other performance indicators are very important. It plays a vital role in the entire chip system.

[0003] In traditional low-dropout linear regulators, a large microfarad capacitor is connected to the chip output, which can improve the stability and transient performance of the system. However, with the increasing degree of device integration, it is hoped that this large external capacitor can be removed, which will face the challenge of poor stability and transient characteristics of low-dropout linear regulators without output capacitors.

[0004] In view of this, how to solve the problem of poor stability and poor transient characteristics of the output capacitor-free low-dropout linear regulator is a major technical challenge in this field. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a low-dropout linear regulator based on damping coefficient control.

[0006] The objective of the present invention is achieved through the following technical solutions: A low voltage drop linear regulator based on damping coefficient control comprises a first-stage amplifier circuit, a second-stage amplifier circuit, a damping coefficient control circuit and a power stage circuit which are connected in sequence; The first-stage amplifier circuit is used to provide high gain and output a stable voltage value; The second-stage amplifier circuit is used to increase the gain and swing of the amplifier, and adopts push-pull output to enhance the swing rate; The power stage circuit is connected to the second stage amplifier circuit and is used to bear a large current load and output a stable voltage; The damping coefficient control circuit is used to control the damping coefficient of the circuit.

[0007] Further, the first-stage amplifier circuit includes: a first PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh NMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first PMOS tube, a twenty-second PMOS tube, a twenty-fifth NMOS tube, and a twenty-sixth NMOS tube; wherein: The gate of the first PMOS tube is connected to the power supply voltage Vref3, and the drain of the first PMOS tube is connected to the drain of the second NMOS tube, the gate of the fourth NMOS tube, the gate of the fifth NMOS tube, the gate of the fifteenth NMOS tube, the gate of the twenty-fifth NMOS tube, and the gate of the twenty-sixth NMOS tube; The gate of the second NMOS tube is connected to the gate of the third NMOS tube, the gate and drain of the tenth NMOS tube, the gate of the fourteenth NMOS tube, the gate of the twenty-third NMOS tube and the gate of the twenty-fourth NMOS tube, and the source of the second NMOS tube is connected to the drain of the fourth NMOS tube; The drain of the third NMOS tube is connected to the gate of the sixth PMOS tube, the gate of the seventh PMOS tube, the drain of the eighth PMOS tube, the gate of the sixteenth PMOS tube, the gate of the nineteenth PMOS tube, and the gate of the twentieth PMOS tube, and the source of the third NMOS tube is connected to the drain of the fifth NMOS tube; The drain of the sixth PMOS tube is connected to the source of the eighth PMOS tube; The drain of the seventh PMOS tube is connected to the source of the ninth PMOS tube; The gate of the eighth PMOS tube is connected to the gate of the ninth PMOS tube, the gate of the thirteenth PMOS tube, the drain of the thirteenth PMOS tube, the gate of the twenty-first PMOS tube and the gate of the twenty-second PMOS tube; The drain of the ninth PMOS tube is connected to the drain of the tenth NMOS tube and the gate of the tenth NMOS tube; The source of the tenth PMOS tube is connected to the drain of the eleventh NMOS tube and the gate of the eleventh NMOS tube; The gate of the twelfth PMOS tube is connected to the drain of the twelfth PMOS tube and the source of the thirteenth PMOS tube; The drain of the thirteenth PMOS tube is connected to the drain of the fourteenth NMOS tube; The source of the fourteenth NMOS tube is connected to the drain of the fifteenth NMOS tube; The drain of the sixteenth PMOS tube is connected to the source of the seventeenth PMOS tube and the source of the eighteenth PMOS tube; The drain of the seventeenth PMOS tube is connected to the source of the twenty-third NMOS tube and the drain of the twenty-fifth NMOS tube; The gate of the eighteenth PMOS tube is connected to the power supply voltage Vref1, and the drain of the eighteenth PMOS tube is connected to the source of the twenty-fourth NMOS tube and the drain of the twenty-sixth NMOS tube; The drain of the nineteenth PMOS tube is connected to the source of the twenty-first PMOS tube; The drain of the 20th PMOS tube is connected to the source of the 22nd PMOS tube; The drain of the twenty-first PMOS tube is connected to the drain of the twenty-third NMOS tube; The drain of the twenty-second PMOS tube is connected to the drain of the twenty-fourth NMOS tube; The source of the first PMOS tube, the source of the sixth PMOS tube, the source of the seventh PMOS tube, the source of the twelfth PMOS tube, the source of the sixteenth PMOS tube, the source of the nineteenth PMOS tube and the source of the twentieth PMOS tube are all connected to the power supply VDD; The source stages of the fourth NMOS tube, the fifth NMOS tube, the eleventh NMOS tube, the fifteenth NMOS tube, the twenty-fifth NMOS tube, and the twenty-sixth NMOS tube are all connected to the ground.

[0008] Further, the second-stage amplifier circuit includes a twenty-seventh PMOS tube, a twenty-eighth NMOS tube, a twenty-ninth NMOS tube, a thirtieth NMOS tube, a thirty-first NMOS tube, a thirty-second PMOS tube and a thirty-third PMOS tube, wherein: The drain and gate of the twenty-seventh PMOS tube are connected to the drain of the third NMOS tube in the first amplifier circuit, and the drain of the twenty-seventh PMOS tube is connected to the drain of the twenty-eighth NMOS tube, the drain of the twenty-ninth NMOS tube, the gate of the twenty-ninth NMOS tube, and the gate of the thirty-first NMOS tube; The gate of the twenty-eighth NMOS tube is connected to the gate of the thirtieth NMOS tube and the drain of the twenty-second PMOS tube in the first-stage amplifier circuit; The drain of the 30th PMOS tube is connected to the drain of the 32nd PMOS tube, the gate of the 32nd PMOS tube and the gate of the 33rd PMOS tube; The drain of the thirty-first NMOS tube is connected to the drain of the thirty-third PMOS tube; The source of the twenty-eighth NMOS tube, the source of the twenty-ninth NMOS tube, the source of the thirtieth NMOS tube, and the source of the thirty-first NMOS tube are connected to the ground; The source stage of the twenty-seventh PMOS tube, the source stage of the thirty-second PMOS tube and the source stage of the thirty-third PMOS tube are connected to the power supply VDD.

[0009] Further, the power stage circuit includes: a thirty-fourth PMOS tube, a first resistor, a second resistor, a first capacitor and a second capacitor; The source of the thirty-fourth PMOS tube is connected to the power supply VDD, the gate of the thirty-fourth PMOS tube is connected to the drain of the thirty-first NMOS tube, and the drain of the thirty-fourth PMOS tube is connected to one end of the first capacitor, one end of the first resistor, and one end of the second capacitor; The other end of the first capacitor is connected to the drain of the twenty-sixth NMOS transistor in the first amplifier circuit; The first resistor and the second resistor are connected in series, the second capacitor is connected in parallel with the first resistor, and the other end of the second resistor is connected to the ground; The other end of the second capacitor is connected to the drain of the seventeenth NMOS tube in the first amplifier circuit.

[0010] Further, the damping coefficient control circuit includes a thirty-fifth PMOS tube, a thirty-sixth PMOS tube, a thirty-seventh NMOS tube, a thirty-eighth NMOS tube, a thirty-ninth NMOS tube, a forty-first NMOS tube, a forty-second PMOS tube, a forty-third PMOS tube, a forty-fourth PMOS tube, a forty-fifth PMOS tube and a third capacitor, wherein: The gate of the thirty-fifth PMOS tube is connected to the gate of the thirty-sixth PMOS tube, the drain of the thirty-sixth PMOS tube, the drain of the thirty-seventh NMOS tube, and the gate of the forty-fifth PMOS tube, and the drain of the thirty-fifth PMOS tube is connected to the drain of the thirty-ninth NMOS tube, the gate of the thirty-ninth NMOS tube, and the gate of the fortieth NMOS tube; The source of the thirty-seventh NMOS tube is connected to the drain of the forty-first NMOS tube and the source of the thirty-eighth NMOS tube; the gate of the thirty-seventh NMOS tube is connected to one end of the third capacitor, the drain of the forty-fourth NMOS tube and the drain of the forty-fifth PMOS tube; The gate of the thirty-eighth NMOS tube is connected to the power supply voltage Vref2, the drain of the thirty-eighth NMOS tube is connected to the drain of the forty-second PMOS tube, and the gate of the forty-second PMOS tube is connected to the gate of the forty-third PMOS tube; The drain of the 40th NMOS tube is connected to the drain of the 43rd PMOS tube; The gate of the forty-first NMOS tube is connected to the drain of the first PMOS tube in the first amplifier circuit; The gate of the 44th PMOS tube is connected to the other end of the third capacitor and the drain of the 31st NMOS tube in the second amplifier circuit; The source stage of the thirty-fifth PMOS tube, the source stage of the thirty-sixth PMOS tube, the source stage of the forty-second PMOS tube, the source stage of the forty-third PMOS tube and the source stage of the forty-fifth PMOS tube are connected to the power supply VDD; The source stage of the thirty-ninth NMOS tube, the source stage of the fortieth NMOS tube, the source stage of the forty-first NMOS tube, and the source stage of the forty-fourth PMOS tube are connected to the ground.

[0011] The beneficial effects of the present invention are: 1) Cascode frequency compensation is used to block the influence of the feedforward path and eliminate the zero point of the right half plane caused by the Maitreya capacitor compensation, making the entire circuit easier to compensate and more stable. Compared with Maitreya compensation, the compensation capacitor used in Cascode frequency compensation is smaller, saving chip area and tape-out cost.

[0012] 2) Use a symmetrical amplifier with smaller mismatch to clamp the input voltage at a fixed voltage, which approximately compensates for a low-frequency left half plane zero point for the circuit, making the circuit stable. In addition, through transistor parameter design, the damping factor coefficient of the circuit system can be set. When the damping factor coefficient is about 0.7, the transient response of the circuit system reaches the best.

[0013] 3) The second-stage amplifier adopts push-pull output and transconductance enhancement technology, and designs the width-to-length ratio of the MOS tube, which can improve the output slew rate, that is, the power stage input can respond to load changes more quickly, and the circuit can obtain better transient response performance.

[0014] 4) The current mirror adopts cascode common source and common gate form to eliminate the channel length modulation effect BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A system circuit diagram of a low voltage drop linear regulator based on damping coefficient control provided by the present invention; Figure 2 A circuit schematic diagram of a low voltage dropout linear regulator based on damping coefficient control provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0017] See also Figure 1-Figure 2 , the present invention provides a technical solution: like Figure 1, a low voltage drop linear regulator based on damping coefficient control, comprising a first-stage amplifier circuit, a second-stage amplifier circuit, a damping coefficient control circuit and a power stage circuit connected in sequence; The first-stage amplifier circuit is used to provide high gain and output a stable voltage value; The second-stage amplifier circuit is used to improve the gain and swing of the amplifier, and adopts push-pull output to enhance the slew rate; when the output voltage jumps, the resistor network samples the jump voltage and feeds it back to the positive port of the first-stage amplifier circuit, and outputs a stable voltage through feedback control of the overall circuit.

[0018] The power stage circuit is connected to the second stage amplifier circuit and is used to bear a large current load and output a stable voltage; The damping coefficient control circuit is used to control the damping coefficient of the circuit.

[0019] In one embodiment, Figure 2 As shown, the first-stage amplifier circuit includes: a first PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh NMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first PMOS tube, a twenty-second PMOS tube, a twenty-fifth NMOS tube, and a twenty-sixth NMOS tube; wherein: The gate of the first PMOS tube is connected to the power supply voltage Vref3, and the drain of the first PMOS tube is connected to the drain of the second NMOS tube, the gate of the fourth NMOS tube, the gate of the fifth NMOS tube, the gate of the fifteenth NMOS tube, the gate of the twenty-fifth NMOS tube, and the gate of the twenty-sixth NMOS tube; The gate of the second NMOS tube is connected to the gate of the third NMOS tube, the gate and drain of the tenth NMOS tube, the gate of the fourteenth NMOS tube, the gate of the twenty-third NMOS tube and the gate of the twenty-fourth NMOS tube, and the source of the second NMOS tube is connected to the drain of the fourth NMOS tube; The drain of the third NMOS tube is connected to the gate of the sixth PMOS tube, the gate of the seventh PMOS tube, the drain of the eighth PMOS tube, the gate of the sixteenth PMOS tube, the gate of the nineteenth PMOS tube, and the gate of the twentieth PMOS tube, and the source of the third NMOS tube is connected to the drain of the fifth NMOS tube; The drain of the sixth PMOS tube is connected to the source of the eighth PMOS tube; The drain of the seventh PMOS tube is connected to the source of the ninth PMOS tube; The gate of the eighth PMOS tube is connected to the gate of the ninth PMOS tube, the gate of the thirteenth PMOS tube, the drain of the thirteenth PMOS tube, the gate of the twenty-first PMOS tube and the gate of the twenty-second PMOS tube; The drain of the ninth PMOS tube is connected to the drain of the tenth NMOS tube and the gate of the tenth NMOS tube; The source of the tenth PMOS tube is connected to the drain of the eleventh NMOS tube and the gate of the eleventh NMOS tube; The gate of the twelfth PMOS tube is connected to the drain of the twelfth PMOS tube and the source of the thirteenth PMOS tube; The drain of the thirteenth PMOS tube is connected to the drain of the fourteenth NMOS tube; The source of the fourteenth NMOS tube is connected to the drain of the fifteenth NMOS tube; The drain of the sixteenth PMOS tube is connected to the source of the seventeenth PMOS tube and the source of the eighteenth PMOS tube; The drain of the seventeenth PMOS tube is connected to the source of the twenty-third NMOS tube and the drain of the twenty-fifth NMOS tube; The gate of the eighteenth PMOS tube is connected to the power supply voltage Vref1, and the drain of the eighteenth PMOS tube is connected to the source of the twenty-fourth NMOS tube and the drain of the twenty-sixth NMOS tube; The drain of the nineteenth PMOS tube is connected to the source of the twenty-first PMOS tube; The drain of the 20th PMOS tube is connected to the source of the 22nd PMOS tube; The drain of the twenty-first PMOS tube is connected to the drain of the twenty-third NMOS tube; The drain of the twenty-second PMOS tube is connected to the drain of the twenty-fourth NMOS tube; The source of the first PMOS tube, the source of the sixth PMOS tube, the source of the seventh PMOS tube, the source of the twelfth PMOS tube, the source of the sixteenth PMOS tube, the source of the nineteenth PMOS tube and the source of the twentieth PMOS tube are all connected to the power supply VDD; The source stages of the fourth NMOS tube, the fifth NMOS tube, the eleventh NMOS tube, the fifteenth NMOS tube, the twenty-fifth NMOS tube, and the twenty-sixth NMOS tube are all connected to the ground.

[0020] In one embodiment, Figure 2 As shown, the second-stage amplifier circuit includes a twenty-seventh PMOS tube, a twenty-eighth NMOS tube, a twenty-ninth NMOS tube, a thirtieth NMOS tube, a thirty-first NMOS tube, a thirty-second PMOS tube and a thirty-third PMOS tube, wherein: The drain and gate of the twenty-seventh PMOS tube are connected to the drain of the third NMOS tube in the first amplifier circuit, and the drain of the twenty-seventh PMOS tube is connected to the drain of the twenty-eighth NMOS tube, the drain of the twenty-ninth NMOS tube, the gate of the twenty-ninth NMOS tube, and the gate of the thirty-first NMOS tube; The gate of the twenty-eighth NMOS tube is connected to the gate of the thirtieth NMOS tube and the drain of the twenty-second PMOS tube in the first-stage amplifier circuit; The drain of the 30th PMOS tube is connected to the drain of the 32nd PMOS tube, the gate of the 32nd PMOS tube and the gate of the 33rd PMOS tube; The drain of the thirty-first NMOS tube is connected to the drain of the thirty-third PMOS tube; The source of the twenty-eighth NMOS tube, the source of the twenty-ninth NMOS tube, the source of the thirtieth NMOS tube, and the source of the thirty-first NMOS tube are connected to the ground; The source stage of the twenty-seventh PMOS tube, the source stage of the thirty-second PMOS tube and the source stage of the thirty-third PMOS tube are connected to the power supply VDD.

[0021] In one embodiment, Figure 2 As shown, the power stage circuit includes: a thirty-fourth PMOS tube, a first resistor, a second resistor, a first capacitor and a second capacitor; The source of the thirty-fourth PMOS tube is connected to the power supply VDD, the gate of the thirty-fourth PMOS tube is connected to the drain of the thirty-first NMOS tube, and the drain of the thirty-fourth PMOS tube is connected to one end of the first capacitor, one end of the first resistor, and one end of the second capacitor; The other end of the first capacitor is connected to the drain of the twenty-sixth NMOS transistor in the first amplifier circuit; The first resistor and the second resistor are connected in series, the second capacitor is connected in parallel with the first resistor, and the other end of the second resistor is connected to the ground; The other end of the second capacitor is connected to the drain of the seventeenth NMOS tube in the first amplifier circuit.

[0022] In one embodiment, Figure 2 As shown, the damping coefficient control circuit includes a thirty-fifth PMOS tube, a thirty-sixth PMOS tube, a thirty-seventh NMOS tube, a thirty-eighth NMOS tube, a thirty-ninth NMOS tube, a forty-first NMOS tube, a forty-second PMOS tube, a forty-third PMOS tube, a forty-fourth PMOS tube, a forty-fifth PMOS tube and a third capacitor, wherein: The gate of the thirty-fifth PMOS tube is connected to the gate of the thirty-sixth PMOS tube, the drain of the thirty-sixth PMOS tube, the drain of the thirty-seventh NMOS tube, and the gate of the forty-fifth PMOS tube, and the drain of the thirty-fifth PMOS tube is connected to the drain of the thirty-ninth NMOS tube, the gate of the thirty-ninth NMOS tube, and the gate of the fortieth NMOS tube; The source of the thirty-seventh NMOS tube is connected to the drain of the forty-first NMOS tube and the source of the thirty-eighth NMOS tube; the gate of the thirty-seventh NMOS tube is connected to one end of the third capacitor, the drain of the forty-fourth NMOS tube and the drain of the forty-fifth PMOS tube; The gate of the thirty-eighth NMOS tube is connected to the power supply voltage Vref2, the drain of the thirty-eighth NMOS tube is connected to the drain of the forty-second PMOS tube, and the gate of the forty-second PMOS tube is connected to the gate of the forty-third PMOS tube; The drain of the 40th NMOS tube is connected to the drain of the 43rd PMOS tube; The gate of the forty-first NMOS tube is connected to the drain of the first PMOS tube in the first amplifier circuit; The gate of the 44th PMOS tube is connected to the other end of the third capacitor and the drain of the 31st NMOS tube in the second amplifier circuit; The source stage of the thirty-fifth PMOS tube, the source stage of the thirty-sixth PMOS tube, the source stage of the forty-second PMOS tube, the source stage of the forty-third PMOS tube and the source stage of the forty-fifth PMOS tube are connected to the power supply VDD; The source stage of the thirty-ninth NMOS tube, the source stage of the fortieth NMOS tube, the source stage of the forty-first NMOS tube, and the source stage of the forty-fourth PMOS tube are connected to the ground.

[0023] The damping coefficient control circuit is between the second-stage amplifier circuit and the power stage. Its principle is similar to that the circuit introduces a low-frequency zero point to compensate for the influence of the secondary pole to ensure the stability of the circuit. In addition, through the design of transistor parameters, the damping factor coefficient of the circuit system can be set. When the damping factor coefficient is about 0.7, the second-order circuit system is in an underdamped state. At this time, the circuit response speed is fast, and the circuit response oscillation is not serious. The transient response of the circuit system is optimal.

[0024] The present invention adjusts the damping factor by adding a damping control circuit between the second-stage amplifier circuit and the power stage circuit, so that the linear regulator can obtain good stability and transient characteristics. In addition, the structure can be used for both a structure without an off-chip capacitor and a structure with an off-chip capacitor. External capacitor structure External capacitor structure External capacitor structure External capacitor structure External capacitor structure

[0025] Among them, Cascode frequency compensation is adopted to block the influence of the feedforward path, eliminate the zero point of the right half plane brought by the Maitreya capacitor compensation, make the whole circuit easier to compensate, and have better stability. Compared with Maitreya compensation, the compensation capacitor used for Cascode frequency compensation is smaller, saving chip area and tape-out cost. The current mirror adopts the Cascode common source and common gate form to eliminate the channel length modulation effect. The present invention adopts a symmetrical amplifier with a smaller mismatch, so that the input voltage is clamped at a fixed voltage, which is approximately the zero point of the left half plane of a low frequency for circuit compensation, so that the circuit is stable. In addition, by transistor parameter design, the damping factor coefficient of the circuit system can be set, and when the damping factor coefficient is about 0.7, the transient response of the circuit system reaches the best. The second-stage amplifier adopts push-pull output and transconductance enhancement technology, and the width-to-length ratio of the MOS tube is designed, which can improve the output slew rate, that is, the power stage input can respond to load changes faster, and the circuit can obtain better transient response performance.

[0026] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present invention, and shall be within the scope of protection of the claims attached to the present invention.

Claims

1. A low-dropout linear regulator based on damping coefficient control, characterized in that: It includes a first-stage amplifier circuit, a second-stage amplifier circuit, a damping coefficient control circuit and a power stage circuit which are connected in sequence; The first-stage amplifier circuit is used to provide high gain and output a stable voltage value; The second-stage amplifier circuit is used to increase the gain and swing of the amplifier, and adopts push-pull output to enhance the swing rate; The power stage circuit is connected to the second stage amplifier circuit and is used to bear a large current load and output a stable voltage; The damping coefficient control circuit is used to control the damping coefficient of the circuit.

2. A low-dropout linear regulator based on damping coefficient control according to claim 1, characterized in that: The first-stage amplifier circuit includes: a first PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh NMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first PMOS tube, a twenty-second PMOS tube, a twenty-fifth NMOS tube, and a twenty-sixth NMOS tube; wherein: The gate of the first PMOS tube is connected to the power supply voltage Vref3, and the drain of the first PMOS tube is connected to the drain of the second NMOS tube, the gate of the fourth NMOS tube, the gate of the fifth NMOS tube, the gate of the fifteenth NMOS tube, the gate of the twenty-fifth NMOS tube, and the gate of the twenty-sixth NMOS tube; The gate of the second NMOS tube is connected to the gate of the third NMOS tube, the gate and drain of the tenth NMOS tube, the gate of the fourteenth NMOS tube, the gate of the twenty-third NMOS tube and the gate of the twenty-fourth NMOS tube, and the source of the second NMOS tube is connected to the drain of the fourth NMOS tube; The drain of the third NMOS tube is connected to the gate of the sixth PMOS tube, the gate of the seventh PMOS tube, the drain of the eighth PMOS tube, the gate of the sixteenth PMOS tube, the gate of the nineteenth PMOS tube, and the gate of the twentieth PMOS tube, and the source of the third NMOS tube is connected to the drain of the fifth NMOS tube; The drain of the sixth PMOS tube is connected to the source of the eighth PMOS tube; The drain of the seventh PMOS tube is connected to the source of the ninth PMOS tube; The gate of the eighth PMOS tube is connected to the gate of the ninth PMOS tube, the gate of the thirteenth PMOS tube, the drain of the thirteenth PMOS tube, the gate of the twenty-first PMOS tube and the gate of the twenty-second PMOS tube; The drain of the ninth PMOS tube is connected to the drain of the tenth NMOS tube and the gate of the tenth NMOS tube; The source of the tenth PMOS tube is connected to the drain of the eleventh NMOS tube and the gate of the eleventh NMOS tube; The gate of the twelfth PMOS tube is connected to the drain of the twelfth PMOS tube and the source of the thirteenth PMOS tube; The drain of the thirteenth PMOS tube is connected to the drain of the fourteenth NMOS tube; The source of the fourteenth NMOS tube is connected to the drain of the fifteenth NMOS tube; The drain of the sixteenth PMOS tube is connected to the source of the seventeenth PMOS tube and the source of the eighteenth PMOS tube; The drain of the seventeenth PMOS tube is connected to the source of the twenty-third NMOS tube and the drain of the twenty-fifth NMOS tube; The gate of the eighteenth PMOS tube is connected to the power supply voltage Vref1, and the drain of the eighteenth PMOS tube is connected to the source of the twenty-fourth NMOS tube and the drain of the twenty-sixth NMOS tube; The drain of the nineteenth PMOS tube is connected to the source of the twenty-first PMOS tube; The drain of the 20th PMOS tube is connected to the source of the 22nd PMOS tube; The drain of the twenty-first PMOS tube is connected to the drain of the twenty-third NMOS tube; The drain of the twenty-second PMOS tube is connected to the drain of the twenty-fourth NMOS tube; The source of the first PMOS tube, the source of the sixth PMOS tube, the source of the seventh PMOS tube, the source of the twelfth PMOS tube, the source of the sixteenth PMOS tube, the source of the nineteenth PMOS tube and the source of the twentieth PMOS tube are all connected to the power supply VDD; The source stages of the fourth NMOS tube, the fifth NMOS tube, the eleventh NMOS tube, the fifteenth NMOS tube, the twenty-fifth NMOS tube, and the twenty-sixth NMOS tube are all connected to the ground.

3. A low-dropout linear regulator based on damping coefficient control according to claim 2, characterized in that: The second-stage amplifier circuit includes a twenty-seventh PMOS tube, a twenty-eighth NMOS tube, a twenty-ninth NMOS tube, a thirtieth NMOS tube, a thirty-first NMOS tube, a thirty-second PMOS tube and a thirty-third PMOS tube, wherein: The drain and gate of the twenty-seventh PMOS tube are connected to the drain of the third NMOS tube in the first amplifier circuit, and the drain of the twenty-seventh PMOS tube is connected to the drain of the twenty-eighth NMOS tube, the drain of the twenty-ninth NMOS tube, the gate of the twenty-ninth NMOS tube, and the gate of the thirty-first NMOS tube; The gate of the twenty-eighth NMOS tube is connected to the gate of the thirtieth NMOS tube and the drain of the twenty-second PMOS tube in the first-stage amplifier circuit; The drain of the 30th PMOS tube is connected to the drain of the 32nd PMOS tube, the gate of the 32nd PMOS tube and the gate of the 33rd PMOS tube; The drain of the thirty-first NMOS tube is connected to the drain of the thirty-third PMOS tube; The source of the twenty-eighth NMOS tube, the source of the twenty-ninth NMOS tube, the source of the thirtieth NMOS tube, and the source of the thirty-first NMOS tube are connected to the ground; The source stage of the twenty-seventh PMOS tube, the source stage of the thirty-second PMOS tube and the source stage of the thirty-third PMOS tube are connected to the power supply VDD.

4. A low-dropout linear regulator based on damping coefficient control according to claim 3, characterized in that: The power stage circuit comprises: a thirty-fourth PMOS tube, a first resistor, a second resistor, a first capacitor and a second capacitor; The source of the thirty-fourth PMOS tube is connected to the power supply VDD, the gate of the thirty-fourth PMOS tube is connected to the drain of the thirty-first NMOS tube, and the drain of the thirty-fourth PMOS tube is connected to one end of the first capacitor, one end of the first resistor, and one end of the second capacitor; The other end of the first capacitor is connected to the drain of the twenty-sixth NMOS transistor in the first amplifier circuit; The first resistor and the second resistor are connected in series, the second capacitor is connected in parallel with the first resistor, and the other end of the second resistor is connected to the ground; The other end of the second capacitor is connected to the drain of the seventeenth NMOS tube in the first amplifier circuit.

5. A low-dropout linear regulator based on damping coefficient control according to claim 4, characterized in that: The damping coefficient control circuit includes a 35th PMOS tube, a 36th PMOS tube, a 37th NMOS tube, a 38th NMOS tube, a 39th NMOS tube, a 40th NMOS tube, a 41st NMOS tube, a 42nd PMOS tube, a 43rd PMOS tube, a 44th PMOS tube, a 45th PMOS tube and a third capacitor, wherein: The gate of the thirty-fifth PMOS tube is connected to the gate of the thirty-sixth PMOS tube, the drain of the thirty-sixth PMOS tube, the drain of the thirty-seventh NMOS tube, and the gate of the forty-fifth PMOS tube, and the drain of the thirty-fifth PMOS tube is connected to the drain of the thirty-ninth NMOS tube, the gate of the thirty-ninth NMOS tube, and the gate of the fortieth NMOS tube; The source of the thirty-seventh NMOS tube is connected to the drain of the forty-first NMOS tube and the source of the thirty-eighth NMOS tube; the gate of the thirty-seventh NMOS tube is connected to one end of the third capacitor, the drain of the forty-fourth NMOS tube and the drain of the forty-fifth PMOS tube; The gate of the thirty-eighth NMOS tube is connected to the power supply voltage Vref2, the drain of the thirty-eighth NMOS tube is connected to the drain of the forty-second PMOS tube, and the gate of the forty-second PMOS tube is connected to the gate of the forty-third PMOS tube; The drain of the 40th NMOS tube is connected to the drain of the 43rd PMOS tube; The gate of the forty-first NMOS tube is connected to the drain of the first PMOS tube in the first amplifier circuit; The gate of the 44th PMOS tube is connected to the other end of the third capacitor and the drain of the 31st NMOS tube in the second amplifier circuit; The source stage of the thirty-fifth PMOS tube, the source stage of the thirty-sixth PMOS tube, the source stage of the forty-second PMOS tube, the source stage of the forty-third PMOS tube and the source stage of the forty-fifth PMOS tube are connected to the power supply VDD; The source stage of the thirty-ninth NMOS tube, the source stage of the fortieth NMOS tube, the source stage of the forty-first NMOS tube, and the source stage of the forty-fourth PMOS tube are connected to the ground.

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