Communication method, SPI host, SPI slave and SPI communication system

Abstract

The invention discloses a communication method, an SPI host, an SPI slave and an SPI communication system. The communication method is applied to an SPI host, the SPI host is connected with an SPI slave through a communication interface, and the communication method comprises the steps that data frames in a preset number of first registers of the SPI slave are sequentially read, and first check codes calculated by the SPI slave based on the data frames in the preset number of first registers are read; calculating a second check code based on the data frames in the preset number of first registers; and judging whether the data frame read by the SPI host is correct or not based on the first check code and the second check code. Through the above mode, the communication method does not need to frequently calculate the check code, so that the calculation time of the check code can be reduced, and the communication rate and efficiency are improved.

Description

Technical Field

[0001] The present application relates to the field of communication transmission technology, and in particular to a communication method, an SPI host, an SPI slave and an SPI communication system. Background Art

[0002] The existing standard Serial Peripheral Interface (SPI) communication usually has no verification function, which is prone to communication errors in an environment with more interference, and the communication reliability is not high. The conventional cyclic redundancy check used for SPI communication is mostly a single frame check, that is, a cyclic redundancy check (CRC) code is added frame by frame to the control command frame, address frame and data frame of SPI communication, and a CRC code calculation and verification comparison are performed for each 8-bit or 16-bit single frame. In this way, the number of CRC code verifications is too many, resulting in a significant reduction in communication efficiency and a limited communication rate; therefore, a high-efficiency SPI communication method is urgently needed. Summary of the invention

[0003] The present application proposes a communication method, an SPI host, an SPI slave and an SPI communication system, aiming to solve the above-mentioned problems.

[0004] In order to solve the above technical problems, a technical solution adopted in the present application is: providing a communication method, which is applied to an SPI host, and the SPI host is connected to an SPI slave through a communication interface. The communication method applied to the SPI host includes: sequentially reading data frames in a preset number of first registers of the SPI slave, and reading a first check code calculated by the SPI slave based on the data frames in the preset number of first registers; calculating a second check code based on the data frames in the preset number of first registers; and judging whether the data frame read by the SPI host is correct based on the first check code and the second check code.

[0005] The step of calculating the second check code based on the data frames in the preset number of first registers includes: obtaining a calculation rule for the SPI slave to calculate the first check code; and calculating the second check code based on the data frames in the preset number of first registers using the calculation rule.

[0006] Among them, the step of calculating the second check code based on the data frames in the preset number of first registers using the calculation rules includes: merging the data frames in the preset number of first registers according to the order or reading order specified by the calculation rules to form a total data frame; inputting each bit of data of the total data frame into the operation circuit at the same time, and performing parallel calculation using the calculation rules to obtain the second check code of the total data frame.

[0007] The step of judging whether the data frame read by the SPI host is correct based on the first check code and the second check code includes: in response to the second check code being the same as the first check code, judging that the data frame read by the SPI host is correct; in response to the second check code being different from the first check code, judging that an error occurs in the data frame read by the SPI host.

[0008] The communication method applied to the SPI host further includes: in response to the number of errors in the data frame read by the SPI host being greater than or equal to a preset number threshold, an alarm operation is performed to prompt a communication abnormality.

[0009] To solve the above technical problems, another technical solution adopted in the present application is: providing a communication method, which is applied to an SPI slave, and the SPI slave is connected to an SPI host through a communication interface. The communication method applied to the SPI slave includes: receiving data frames written by the SPI host into a preset number of second registers, and receiving a first check code calculated by the SPI host based on the data frames in the preset number of second registers; calculating a second check code based on the data frames written into the preset number of second registers; and judging whether the data frame received by the SPI slave is correct based on the first check code and the second check code.

[0010] The step of calculating the second check code based on the data frames written in the preset number of second registers includes: obtaining the calculation rule of the SPI host to calculate the first check code; and calculating the second check code based on the data frames in the preset number of second registers using the calculation rule.

[0011] Among them, the step of calculating the second check code based on the data frames in the preset number of second registers using the calculation rules includes: merging the data frames in the preset number of second registers according to the order or writing order specified by the calculation rules to form a total data frame; inputting each bit of data of the total data frame into the operation circuit at the same time, and performing parallel calculation using the calculation rules to obtain the second check code of the total data frame.

[0012] Among them, the step of judging whether the data frame received by the SPI slave is correct based on the first check code and the second check code includes: in response to the second check code being the same as the first check code, judging that the data frame received by the SPI slave is correct; in response to the second check code being different from the first check code, judging that an error occurs in the data frame received by the SPI slave.

[0013] The communication method applied to the SPI slave also includes: in response to a correct data frame received by the SPI slave, updating the data of the SPI slave; in response to an error in the data frame received by the SPI slave, maintaining the data of the SPI slave unchanged.

[0014] To solve the above technical problems, another technical solution adopted in the present application is: providing an SPI host, the SPI host including a communication interface and a controller, the communication interface is connected to the SPI slave and is used to send data to the SPI slave; the controller is used to execute any one of the above communication methods applied to the SPI host.

[0015] To solve the above technical problems, another technical solution adopted in the present application is: to provide an SPI slave, which includes a communication interface and a controller, the communication interface is connected to the SPI host and is used to send data to the SPI host; the controller is used to execute any one of the above communication methods applied to the SPI slave.

[0016] To solve the above technical problems, another technical solution adopted in the present application is: to provide an SPI communication system, which includes an SPI master and multiple SPI slaves; wherein each SPI slave is communicatively connected to the SPI master.

[0017] The beneficial effect of the present application is that, different from the prior art, the communication method of the present application is applied to the SPI host, and the communication method includes: sequentially reading the data frames in the first register of the preset number of SPI slaves, and reading the first check code calculated by the SPI slave based on the data frames in the first register of the preset number; calculating the second check code based on the data frames in the first register of the preset number; judging whether the data frame read by the SPI host is correct based on the first check code and the second check code. In the above manner, the communication method of the present application does not need to frequently calculate the check code, thereby reducing the calculation time of the check code, thereby improving the communication rate and efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and are used together with the specification to illustrate the technical solution of the present application.

[0019] Figure 1 This is the timing diagram of the SPI communication system communication clock SCLK and chip select CS (same as SS);

[0020] Figure 2 This is a schematic diagram of the SPI communication frame format;

[0021] Figure 3 This is a schematic diagram of the SPI communication process;

[0022] Figure 4 It is a flowchart of the first embodiment of the communication method of the present application;

[0023] Figure 5 yes Figure 4A flow chart of an embodiment of step S102;

[0024] Figure 6 yes Figure 5 A flow chart of an embodiment of step S202;

[0025] Figure 7 yes Figure 4 A schematic diagram of a flow chart of an embodiment of step S103;

[0026] Figure 8 It is a flowchart of the second embodiment of the communication method of the present application;

[0027] Fig. 9 yes Figure 8 A schematic diagram of a flow chart of an embodiment of step S502;

[0028] Fig.10 yes Fig. 9 A flow chart of an embodiment of step S602;

[0029] Fig.11 yes Figure 8 A flow chart of an embodiment of step S503;

[0030] Fig.12 It is a flowchart of the third embodiment of the communication method of the present application;

[0031] Fig.13 It is a structural diagram of an embodiment of the SPI host of the present application;

[0032] Fig.14 It is a structural diagram of an embodiment of the SPI slave of the present application;

[0033] Fig.15 It is a structural diagram of an embodiment of the SPI communication system of the present application. DETAILED DESCRIPTION

[0034] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0036] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0037] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0038] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0039] Before introducing the communication method of the present application, it is necessary to first introduce the existing SPI communication system and SPI communication. In the existing SPI communication system, the interface of the SPI communication system allows data to be sent and received simultaneously on the master output slave input connection line (MOSI) and the master input slave output connection line (MISO). In the SPI communication process, clock polarity (ClockPolarity, CPOL) and clock phase (ClockPhase, CPHA) are the main parameters that define the clock format used by SPI. CPOL has no significant impact on the transmission protocol of the SPI communication system. If CPOL = 0, it means that the idle state of the serial synchronous clock is low level; if CPOL = 1, it means that the idle state of the serial synchronous clock is high potential. CPHA is used to select one of two different transmission protocols for data transmission. If CPHA = 0, the data is sampled at the first transition edge (rising or falling) of the serial synchronous clock; if CPHA = 1, the data is sampled at the second transition edge (rising or falling) of the serial synchronous clock. Among them, the clock phase and polarity of the SPI master and SPI slave in the SPI communication system should be consistent.

[0040] See also Figure 1 , Figure 1 This is the timing diagram of the SPI communication system communication clock (Serial Clock, SCLK) and chip select CS (same as SS) (Chip Select or Slave Select). Figure 1 As shown, Figure 1The SPI communication in uses mode 0, which means CPOL=0, CPHA=0.

[0041] See also Figure 2 , Figure 2 This is a schematic diagram of the SPI communication frame format. Figure 2 As shown, in the existing SPI communication system, a single communication frame of SPI communication is usually 16 bits of data, and one transmission includes two types of frames, namely a control address frame and a data frame.

[0042] The format of the control address frame is: 1bit R / W+4bit Busrt Size+10bit Addr+1bit Dummy; R / W represents the control command bit, 0 represents a read command, 1 represents a write command, if Busrt Size is 1, it represents a single access, if Busrt Size is another value, it represents the busrt size, with a maximum of 15 busrt addresses, and Busrt Size cannot be 0; Addr represents the relative address given in the register manual of the SPI slave; Dummy represents invalid data.

[0043] When reading and writing data, a data frame contains 16 bits of data. When reading data, the SPI host only pays attention to the received data and does not need to pay attention to the sent data; when writing data, the SPI host only pays attention to the sent data, and the received data is 0.

[0044] See also Figure 3 , Figure 3 This is a schematic diagram of the SPI communication process. Figure 3 As shown, in the SPI communication system, one communication includes one control address frame and several data frames.

[0045] However, in the existing standard SPI communication, there is usually no verification function, communication errors are prone to occur in an environment with more interference, and the communication reliability is not high; therefore, in order to improve the reliability of SPI communication, conventional CRC codes are used in the prior art to perform data verification on SPI.

[0046] Among them, the specific calculation method of CRC code is as follows:

[0047] After the sender sends the K-bit data code, an r-bit supervision code for verification is generated according to certain rules and attached to the original data. The information code is n=k+r bits. Therefore, this code is also called (n, k) code. The receiver verifies according to the rules agreed upon by both parties to determine whether the data is wrong. This rule is the generating polynomial. The K-bit data code is represented by M(x). Select a suitable CRC generating polynomial G(x). The highest power of G(x) is r. Shift M(x) left by r bits, M(x)*x rPerform non-borrow division (i.e. XOR operation) on G(x), and the remainder is the CRC check code, that is:

[0048]

[0049] Among them, the K-bit data code is represented by M(x), G(x) represents the CRC generating polynomial; R(x) represents the CRC code. The sender generates the CRC code based on the above principle and attaches it to the end of the data and sends it out. The data received by the receiver is also divided by G(x). If the remainder is 0, it is considered that the data transmission is correct, otherwise it is treated as an error. x is represented as a variable, which can be each bit of data in the K-bit data code.

[0050] In the SPI communication of the above-mentioned SPI communication system, the CRC code is applied to perform communication verification, which is to calculate the 16-bit cyclic redundancy check code for the 16-bit single-frame data (including the control address frame or the data frame, etc.) in the communication process, and the calculated 16-bit CRC check code is directly appended to the original single-frame data to form a single-frame data of 32-bit data. Therefore, in the above-mentioned SPI communication, the data width of the single-frame data is also changed from 16 bits to 32 bits. Therefore, when using this method for SPI communication, it is necessary to add CRC codes to the control command frame, address frame and data frame of the SPI communication frame by frame, so it is necessary to calculate and check each single-frame data during the communication process. The number of times of checking the CRC code is too many, resulting in a significant reduction in communication efficiency and a limited communication rate; therefore, a highly efficient SPI communication method is now urgently needed.

[0051] Therefore, in order to solve the above problems, this application first proposes a communication method, see Figure 4 , Figure 4 1 is a flow chart of the first embodiment of the communication method of the present application. In this embodiment, the communication method is applied to the SPI host, and the SPI host is connected to the SPI slave through a communication interface. Figure 4 As shown, the communication method applied to the SPI host of this embodiment specifically includes steps S101 to S104:

[0052] Step S101: sequentially reading data frames in a preset number of first registers of the SPI slave, and reading a first check code calculated by the SPI slave based on the data frames in the preset number of first registers.

[0053] In this embodiment, when the SPI host communicates with the SPI slave, in response to the user command being a read command, the SPI host can parse the read command, obtain the address of the first register in the SPI slave corresponding to the read command, and sequentially read the data frames in the first register of the SPI slave in a preset number based on the address. The read command includes the addresses of multiple registers and corresponding read instructions. In this embodiment, the preset number can be two or more.

[0054] After the SPI host reads the data frames in the preset number of first registers of the SPI slave, at this time, the SPI host can also read the first check code calculated in the SPI slave based on the data frames in the preset number of first registers. In this embodiment, when the SPI host reads the data frames in the preset number of first registers of the SPI slave, the SPI slave can also calculate the first check code based on the data frames in the preset number of first registers during this process, and store the first check code in the corresponding register. When the SPI host reads the data frames in the preset number of first registers of the SPI slave, the first check code in the register can be read.

[0055] Step S102: Calculating a second check code based on a preset number of data frames in the first register.

[0056] After reading the data frames in the preset number of first registers of the SPI slave, the SPI host can calculate the second check code in the SPI host using the data frames in the preset number of first registers.

[0057] The method for the SPI host to calculate the second check code and the SPI slave to calculate the first check code can refer to the specific calculation method of the CRC code described above, but it should be noted that the method for the SPI host to calculate the second check code and the SPI slave to calculate the first check code needs to be consistent.

[0058] Step S103: determining whether the uplink data received by the SPI host is correct based on the first check code and the second check code.

[0059] After the SPI host calculates the second check code based on the data frames in the preset number of first registers, it can then compare the second check code with the first check code obtained by reading from the SPI slave. If they are consistent, it can be determined that the data frames in the preset number of first registers read by the SPI host are correct. If they are different, it can be determined that the data frames in the preset number of first registers read by the SPI host are correct, but an error has occurred.

[0060] Different from the prior art, the communication method of the present application is applied to the SPI host, and the communication method includes: sequentially reading the data frames in the first register of the preset number of SPI slaves, and reading the first check code calculated by the SPI slave based on the data frames in the first register of the preset number; calculating the second check code based on the data frames in the first register of the preset number; judging whether the data frame read by the SPI host is correct based on the first check code and the second check code. In the above manner, the communication method of the present application does not need to frequently calculate the check code, thereby reducing the calculation time of the check code, thereby improving the communication rate and efficiency.

[0061] Optionally, the method for calculating the second check code based on the data frames in the preset number of first registers is as follows: Figure 5 See Figure 5 , Figure 5 yes Figure 4 Schematic diagram of the process of step S102 in an embodiment. In this embodiment, Figure 5 As shown, this embodiment can be Figure 5 The method shown implements step S102, and the specific implementation steps also include steps S201 to S202:

[0062] Step S201: obtaining a calculation rule for the SPI slave to calculate a first check code.

[0063] As described above, the way the SPI host calculates the second check code and the way the SPI slave calculates the first check code need to be consistent. Therefore, before calculating the second check code, the SPI host needs to obtain the calculation rule of the SPI slave calculating the first check code from the SPI slave. In this embodiment, the calculation rule can be the generator polynomial G(x) for generating CRC described above.

[0064] Step S202: Calculate a second check code based on a preset number of data frames in the first register using a calculation rule.

[0065] At this time, after obtaining the calculation rule, the SPI host can use the calculation rule to calculate the second check code based on a preset number of data frames in the first register.

[0066] Optionally, the method for calculating the second check code based on a preset number of data frames in the first register using a calculation rule is as follows: Figure 6 See Figure 6 , Figure 6 yes Figure 5 Schematic diagram of the process of step S202 in an embodiment. In this embodiment, Figure 6 As shown, this embodiment can be Figure 6 The method shown implements step S202, and the specific implementation steps also include steps S301 to S302:

[0067] Step S301 : merging a preset number of data frames in the first register according to an order specified by a calculation rule or a reading order to form a total data frame.

[0068] In this embodiment, after the SPI host reads the data frames in the preset number of first registers of the SPI slave and obtains the corresponding calculation rules, when calculating the second check code based on the calculation rules, the data frames in the preset number of first registers can be merged according to the reading order to form a total data frame.

[0069] In this embodiment, the data frames in the preset number of first registers can be merged according to the reading order; in other embodiments, if the calculation rule of the SPI slave is set with a corresponding merging order, the data frames in the preset number of first registers can be merged based on the merging order of the calculation rule.

[0070] For example, in this embodiment, each register stores a data frame. When the preset number is 4, the SPI host reads 4 data frames. If each data frame is 16 bits, after merging the 4 data frames, the total data frame obtained is 64 bits. Among them, the shift calculation is used in the process of merging data frames. The shift calculation refers to the binary shift operation, which mainly includes two operations of left shift and right shift. For example, if two 16-bit data frames are merged, one of the data frames can be shifted left or right by 16 bits and then added to the other data frame, so that the total merged data frame can be obtained.

[0071] Step S302: input each bit of data of the total data frame into the operation circuit at the same time, and perform parallel calculation using the calculation rule to obtain the second check code of the total data frame.

[0072] When the SPI host obtains the total data frame of the data frames in the preset number of first registers, each bit of data of the total data frame can be simultaneously input into the operation circuit, and the calculation rule of obtaining the first check code of the SPI slave machine is used for parallel calculation to obtain the second check code of the total data frame.

[0073] Exemplarily, the SPI host reads data from the SPI slave's registers whose addresses are 0x50, 0x40, 0x42, and 0x52, respectively, in sequence, and each register stores a data frame. At this time, the control address frames of the 0x50, 0x40, 0x42, and 0x52 registers can be ignored, and only the data frames of the 0x50, 0x40, 0x42, and 0x52 registers are obtained. The data frames of the 0x50, 0x40, 0x42, and 0x52 registers are merged into a total data frame through shift calculation, and each bit of data of the total data frame is simultaneously input into the operation circuit, and the calculation rules of the SPI slave for calculating the first check code are used for parallel calculation to obtain the second check code of the total data frame.

[0074] In the above embodiment, the data frame corresponding to the address 0x50 is placed at 1-16 bits of the total data frame, the data frame corresponding to the address 0x40 is placed at 17-32 bits of the total data frame, the data frame corresponding to the address 0x42 is placed at 33-48 bits of the total data frame, and the data frame corresponding to the address 0x52 is placed at 49-64 bits of the total data frame.

[0075] Optionally, a method for judging whether a data frame read by the SPI host is correct based on the first check code and the second check code is as follows: Figure 7 See Figure 7 , Figure 7 yes Figure 4 Schematic diagram of the flow chart of step S103 in an embodiment. In this embodiment, this embodiment can be performed as follows Figure 7 The method shown implements step S103, and the specific implementation steps also include steps S401 to S402:

[0076] Step S401: In response to the second check code being the same as the first check code, it is determined that the data frame read by the SPI host is correct.

[0077] If the second check code calculated by the SPI host and the SPI slave using the same calculation rule is the same as the first check code, it means that there is no problem in the communication transmission between the SPI host and the SPI slave, that is, it is determined that the data frames in the preset number of first registers read by the SPI host are correct.

[0078] Step S402: In response to the second check code being different from the first check code, it is determined that an error occurs in the data frame read by the SPI host.

[0079] If the second check code and the first check code calculated by the SPI host and the SPI slave using the same calculation rule are different, it means that there is a problem in the communication transmission between the SPI host and the SPI slave, that is, it is determined that the data frames in the preset number of first registers read by the SPI host are wrong.

[0080] Optionally, based on Figure 7The communication method applied to the SPI host of this embodiment also includes the following steps:

[0081] In response to the number of errors in the data frame read by the SPI host being greater than or equal to a preset number threshold, an alarm operation is performed to prompt a communication abnormality.

[0082] In this embodiment, if the second check code and the first check code calculated by the SPI host and the SPI slave using the same calculation rule are different, it means that an error occurs in the data frames in the preset number of first registers read by the SPI host. At this time, the number of errors in the error count counter in the SPI host is increased by one. If the number of errors in the error count counter is greater than or equal to the preset number threshold, it means that the communication between the SPI host and the SPI slave is abnormal. At this time, an alarm operation can be performed to prompt the user that the communication between the SPI host and the SPI slave is abnormal.

[0083] Optionally, the present application further proposes a communication method, see Figure 8 , Figure 8 1 is a flow chart of the second embodiment of the communication method of the present application. In this embodiment, the communication method is applied to a SPI slave, and the SPI slave is connected to the SPI master via a communication interface. Figure 8 As shown, the communication method applied to the SPI slave of this embodiment specifically includes steps S501 to S503:

[0084] Step S501: receiving data frames written into a preset number of second registers by the SPI host, and receiving a first check code calculated by the SPI host based on the data frames in the preset number of second registers.

[0085] In this embodiment, when the SPI slave communicates with the SPI master, in response to the user command being a write command, the SPI master can parse the write command, obtain the address of the second register in the SPI slave corresponding to the write command, and write data frames to the preset number of second registers of the SPI slave based on the address; at this time, the SPI slave receives the data frames written by the SPI master to the preset number of second registers. Wherein, the write command includes the addresses of multiple registers and corresponding write instructions. In this embodiment, the preset number can be two or more.

[0086] After the SPI slave receives the data frames written by the SPI master into the preset number of second registers, at this time, the SPI slave can also receive the first check code calculated by the SPI master based on the data frames in the preset number of second registers. In this embodiment, when the SPI slave receives the data frames written by the SPI master into the preset number of second registers, the SPI master can also calculate the first check code based on the data frames written into the preset number of second registers during this process, and send the first check code to the register corresponding to the SPI slave.

[0087] Step S502: Calculate a second check code based on a preset number of data frames written into the second register.

[0088] After receiving the data frames written by the SPI host into the preset number of second registers, the SPI slave can use the data frames in the preset number of second registers to calculate the second check code in the SPI slave. When calculating the second check code, the data frames in the preset number of second registers can be merged according to the writing order of the SPI host; in other embodiments, if the calculation rule of the SPI host is set with a corresponding merging order, the data frames in the preset number of second registers can be merged based on the merging order of the calculation rule.

[0089] The way in which the SPI slave calculates the second check code and the SPI master calculates the first check code can also refer to the specific calculation method of the CRC code described above, but it should be noted that the way in which the SPI slave calculates the second check code and the SPI master calculates the first check code needs to be consistent.

[0090] Step S503: determining whether the data frame received by the SPI slave is correct based on the first check code and the second check code.

[0091] After the SPI slave calculates the second check code based on the data frames in the preset number of second registers, it can then compare the second check code with the first check code sent from the SPI host to the SPI slave. If they are consistent, it can be determined that the data frames in the preset number of second registers received by the SPI slave are correct. If they are different, it can be determined that errors occur in the data frames in the preset number of second registers received by the SPI slave.

[0092] Optionally, based on Figure 8 In an embodiment, a method for calculating a second check code based on a preset number of data frames written in a second register is as follows: Fig. 9 See Fig. 9 , Fig. 9 yes Figure 8 Schematic diagram of the process of step S502 in an embodiment. In this embodiment, Fig. 9 As shown, this embodiment can be Fig. 9The method shown implements step S502, and the specific implementation steps also include steps S601 to S602:

[0093] Step S601: Obtain the calculation rule of the SPI host for calculating the first check code.

[0094] As mentioned above, the way the SPI slave calculates the second check code and the way the SPI master calculates the first check code need to be consistent. Therefore, before calculating the second check code, the SPI slave needs to obtain the calculation rule of the SPI master for calculating the first check code from the SPI master. In this embodiment, the calculation rule can be the generator polynomial G(x) for generating CRC mentioned above.

[0095] Step S602: Calculate a second check code based on a preset number of data frames in a second register using a calculation rule.

[0096] At this time, after obtaining the calculation rule, the SPI slave can use the calculation rule to calculate the second check code based on the data frames in the preset number of second registers.

[0097] Optionally, the method for calculating the second check code based on the data frames in the preset number of second registers using the calculation rule is as follows: Fig.10 See Fig.10 , Fig.10 yes Fig. 9 Schematic diagram of the process of step S602 in an embodiment. In this embodiment, Fig.10 As shown, this embodiment can be Fig.10 The method shown implements step S602, and the specific implementation steps also include steps S701 to S702:

[0098] Step S701 : merging a preset number of data frames in the second registers according to an order specified by a calculation rule or a writing order to form a total data frame.

[0099] In this embodiment, after the SPI slave receives the data frames written by the SPI master into a preset number of second registers and obtains the corresponding calculation rules, when calculating the second check code based on the calculation rules, the data frames in the preset number of second registers can be merged according to the writing order to form a total data frame.

[0100] In this embodiment, the data frames in a preset number of second registers can be merged according to the writing order; in other embodiments, if the calculation rule of the SPI host is set with a corresponding merging order, the data frames in the preset number of second registers can be merged based on the merging order of the calculation rule.

[0101] The merging process is the same as the process of merging a preset number of data frames in the first register described above, and will not be described in detail here.

[0102] Step S702: input each bit of data of the total data frame into the operation circuit at the same time, and perform parallel calculation using the calculation rule to obtain a second check code of the total data frame.

[0103] After obtaining the total data frame of the data frames in the preset number of second registers, the SPI slave can simultaneously input each bit of data of the total data frame into the operation circuit, and use the calculation rules for obtaining the first check code calculated by the SPI host in the previous text to perform parallel calculations to obtain the second check code of the total data frame.

[0104] In this embodiment, the SPI slave can be set as a field programmable gate array, which has the characteristics of parallel calculation. Therefore, in this embodiment, when calculating the second check code, the parallel calculation characteristics of the field programmable gate array can be used to adjust the calculation method of the CRC code in the previous text, abandoning the time-consuming serial shift CRC calculation method and using the parallel CRC calculation method instead. This can increase the communication rate between the SPI slave and the SPI host.

[0105] Exemplarily, the SPI host writes data to the SPI slave's registers whose addresses are 0x58, 0x48, 0x4A, and 0x5A respectively in sequence. After receiving the above data, the SPI slave can ignore the control address frames of the 0x58, 0x48, 0x4A, and 0x5A registers, and only obtain the data frames of the 0x58, 0x48, 0x4A, and 0x5A registers, and merge the data frames of the 0x58, 0x48, 0x4A, and 0x5A registers into a total data frame, and input each bit of data of the total data frame into the operation circuit at the same time, and use the calculation rules of the SPI host to calculate the first check code for parallel calculation to obtain the second check code of the total data frame.

[0106] In the above embodiment, when merging to form a total data frame, the merging can be performed according to the write order of the SPI host. The data frame corresponding to the 0x58 address can be placed at 1-16 bits of the total data frame, the data frame corresponding to the 0x48 address can be placed at 17-32 bits of the total data frame, the data frame corresponding to the 0x4A address can be placed at 33-48 bits of the total data frame, and the data frame corresponding to the 0x5A address can be placed at 49-64 bits of the total data frame.

[0107] Optionally, based on Figure 8 In an embodiment, a method for determining whether a data frame received by an SPI slave is correct based on a first check code and a second check code is as follows: Fig.11 See Fig.11 , Fig.11 yes Figure 8 Schematic diagram of the flow chart of step S503 in an embodiment. In this embodiment, this embodiment can be performed as follows Fig.11The method shown implements step S503, and the specific implementation steps also include steps S801 to S802:

[0108] Step S801: In response to the second check code being the same as the first check code, it is determined that the data frame received by the SPI slave is correct.

[0109] If the first check code and the second check code calculated by the SPI host and the SPI slave using the same calculation rule are the same, it means that there is no problem in the communication transmission between the SPI host and the SPI slave, that is, it is determined that the data frames in the preset number of second registers received by the SPI slave are correct.

[0110] Step S802: In response to the second check code being different from the first check code, it is determined that an error occurs in the data frame received by the SPI slave.

[0111] If the first check code and the second check code calculated by the SPI host and the SPI slave using the same calculation rule are different, it means that there is a problem in the communication transmission between the SPI host and the SPI slave, that is, it is determined that there are errors in the data frames in the preset number of second registers received by the SPI slave.

[0112] Optionally, based on Figure 8 For an example, see Fig.12 , Fig.12 1 is a flow chart of the third embodiment of the communication method of the present application. Fig.12 As shown, in Figure 8 Based on the embodiment, the communication method applied to the SPI slave of this embodiment further specifically includes steps S901 to S902:

[0113] Step S901: in response to the data frame received by the SPI slave being correct, the data of the SPI slave is updated.

[0114] If the first check code and the second check code calculated by the SPI master and the SPI slave using the same calculation rule are the same, it means that the data frames in the preset number of second registers received by the SPI slave are correct; at this time, the data of the SPI slave can be updated based on the data frames in the preset number of second registers.

[0115] Step S902: In response to an error in the data frame received by the SPI slave, the data of the SPI slave is maintained unchanged.

[0116] If the second check code calculated by the SPI master and the SPI slave using the same calculation rule is different from the first check code, it means that an error occurs in the data frame in the preset number of second registers of the SPI slave; at this time, the SPI slave does not update its own data and maintains the data of the SPI slave unchanged.

[0117] Optionally, the present application further proposes an SPI host, see Fig.13 , Fig.13 Schematic diagram of the structure of an embodiment of the SPI host of the present application. Fig.13 As shown, the SPI host 100 of this embodiment includes a communication interface 120 and a controller 110. The communication interface 120 is connected to the SPI slave and is used to send data to the SPI slave. The controller 110 is used to execute the communication method applied to the SPI host 100 in any of the above embodiments.

[0118] The controller 110 may be configured as a CPU (Central Processing Unit). The controller 110 may be an integrated circuit chip having signal processing capabilities. The controller may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0119] Optionally, the present application further proposes an SPI slave, see Fig.13 , Fig.13 1 is a schematic diagram of the structure of an embodiment of the SPI slave of the present application. Fig.13 As shown, the SPI slave 200 of this embodiment includes a communication interface 220 and a controller 210. The communication interface 220 is connected to the SPI host and is used to send data to the SPI host; the controller 210 is used to execute the communication method applied to the SPI slave 200 in any of the above embodiments.

[0120] The controller 220 may be configured as a CPU (Central Processing Unit). The controller 220 may be an integrated circuit chip having signal processing capabilities. The controller may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0121] Optionally, the present application further proposes an SPI communication system, see Fig.14 , Fig.14 1 is a schematic diagram of the structure of an embodiment of the SPI communication system of the present application. Fig.14 As shown, the SPI communication system 300 of this embodiment includes one SPI master 100 and a plurality of SPI slaves 200 ; wherein each SPI slave 200 is communicatively connected to the SPI master 100 .

[0122] In this embodiment, the SPI host 100 can be set as a Zynq chip, and the SPI slave 200 can be set as an IOFPGA or a SAF FPGA.

[0123] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A communication method, characterized in that: Applied to an SPI host, the SPI host is connected to an SPI slave through a communication interface, and the communication method includes: Sequentially read the data frames in a preset number of first registers of the SPI slave, and read the first check code calculated by the SPI slave based on the data frames in the preset number of first registers; Calculating a second check code based on the data frames in the preset number of first registers; Whether the data frame read by the SPI host is correct is determined based on the first check code and the second check code.

2. The communication method according to claim 1, characterized in that: The step of calculating the second check code based on the data frames in the preset number of first registers comprises: Obtaining a calculation rule for the SPI slave to calculate the first check code; The second check code is calculated based on the data frames in the preset number of first registers using the calculation rule.

3. The communication method according to claim 2, characterized in that: The step of calculating the second check code based on the preset number of data frames in the first register by using the calculation rule comprises: Merging the data frames in the preset number of first registers according to the order specified by the calculation rule or the reading order to form a total data frame; Each bit of data of the total data frame is simultaneously input into the operation circuit, and parallel calculation is performed using the calculation rule to obtain the second check code of the total data frame.

4. The communication method according to claim 1, characterized in that: The step of judging whether the data frame read by the SPI host is correct based on the first check code and the second check code comprises: In response to the second verification code being the same as the first verification code, determining that the data frame read by the SPI host is correct; In response to the second check code being different from the first check code, it is determined that an error occurs in the data frame read by the SPI host.

5. The communication method according to claim 4, characterized in that: Also includes: In response to the number of errors in the data frame read by the SPI host being greater than or equal to a preset number threshold, an alarm operation is performed to prompt communication abnormality.

6. A communication method, characterized in that: Applied to an SPI slave, the SPI slave is connected to an SPI host via a communication interface, and the communication method includes: receiving data frames written by the SPI host into a preset number of second registers, and receiving a first check code calculated by the SPI host based on the data frames in the preset number of second registers; Calculate a second check code based on the data frames written in the preset number of second registers; Whether the data frame received by the SPI slave is correct is determined based on the first check code and the second check code.

7. The communication method according to claim 6, characterized in that: The step of calculating the second check code based on the data frames written in the preset number of second registers comprises: Obtaining a calculation rule for the SPI host to calculate the first check code; The second check code is calculated based on the data frames written in the preset number of second registers using the calculation rule.

8. The communication method according to claim 7, characterized in that: The step of calculating the second check code based on the preset number of data frames written in the second register by using the calculation rule comprises: Merging the data frames in the preset number of second registers according to the order specified by the calculation rule or the writing order to form a total data frame; Each bit of data of the total data frame is simultaneously input into the operation circuit, and parallel calculation is performed using the calculation rule to obtain the second check code of the total data frame.

9. The communication method according to claim 6, characterized in that: The step of judging whether the data frame received by the SPI slave is correct based on the first check code and the second check code comprises: In response to the second check code being the same as the first check code, determining that the data frame received by the SPI slave is correct; In response to the second check code being different from the first check code, it is determined that an error occurs in the data frame received by the SPI slave.

10. The communication method according to claim 9, characterized in that: Also includes: In response to the data frame received by the SPI slave being correct, updating the data of the SPI slave; In response to an error in the data frame received by the SPI slave, the data of the SPI slave is maintained unchanged.

11. An SPI host, characterized in that: The SPI host includes a communication interface and a controller, wherein the communication interface is connected to the SPI slave and is used to send data to the SPI slave; the controller is used to execute the communication method described in any one of claims 1-5.

12. An SPI slave, characterized in that: The SPI slave includes a communication interface and a controller, wherein the communication interface is connected to the SPI host and is used to send data to the SPI host; the controller is used to execute the communication method described in any one of claims 6-10.

13. An SPI communication system, characterized in that: It comprises an SPI master as claimed in claim 11 and a plurality of SPI slaves as claimed in claim 12; wherein each of the SPI slaves is communicatively connected to the SPI master.

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