An SPI slave controller and its working method

Abstract

This invention discloses an SPI slave controller and its operating method. The SPI slave controller includes an SPI interface, an SPI transmit shift register, an SPI receive shift register, and a system bus interface. The SPI slave controller is integrated into a chip and also includes a core control module, a transmit asynchronous FIFO, a first DMA controller, a receive asynchronous FIFO, a second DMA controller, and a register module. The technical solution provided by this invention adopts a dual asynchronous FIFO (First Input First Output) combined with a dual DMA (Data Memory Access) controller architecture, which greatly improves the communication frequency in the process. It breaks the fixed multiple relationship that must be met between the system clock and the serial communication clock in traditional SPI design, allowing higher communication rates to be supported at lower system clock frequencies, thereby improving the overall data transmission efficiency and system throughput.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits and communication interface technology, and in particular to an SPI slave controller and its operating method. Background Technology

[0002] Serial Peripheral Interface (SPI) is a synchronous, serial communication bus protocol widely used for short-range communication between microcontrollers, sensors, memory, and various peripheral chips. With the rapid development of the Internet of Things (IoT), automotive electronics, industrial control, and high-end consumer electronics, modern System-on-Chips (SoCs) place unprecedented demands on the performance of their on-chip interconnect buses. Specifically, the application scenarios of the SPI interface have expanded from simple sensor data reading and configuration register writing to areas requiring high-speed, real-time, and large-volume data transmission, such as high-resolution image sensors, high-speed digital-to-analog converters, high-capacity serial Flash memory, and control and data interaction for Gigabit Ethernet PHYs (Physical External Signal Interface chips). These applications urgently require the SPI interface to operate stably at higher communication rates to provide greater sustained throughput.

[0003] However, in traditional SPI slave interface designs, the system clock frequency (f_sys) must be at least twice the communication clock frequency (f_sck) (i.e., f_sys ≥ 2 × f_sck) to ensure that data loss or overwriting does not occur during cross-clock domain data synchronization. This frequency constraint severely restricts applications operating at high communication clock frequencies and forces on-chip systems to increase their clock frequency, thereby increasing power consumption and design complexity. Therefore, there is an urgent need in the field for a high-performance SPI slave controller design that can overcome the frequency bottleneck. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides an SPI slave controller and its operating method.

[0005] Therefore, according to a first aspect of the present invention, an SPI slave controller is provided, including an SPI interface, an SPI transmit shift register, an SPI receive shift register and a system bus interface, wherein the SPI slave controller is integrated on a system-on-a-chip and further includes a core control module, a transmit asynchronous FIFO, a first DMA controller, a receive asynchronous FIFO, a second DMA controller and a register module;

[0006] The core control module is connected to the SPI interface, the SPI transmit shift register, the SPI receive shift register, the transmit asynchronous FIFO, the receive asynchronous FIFO, the register module, the first DMA controller, and the second DMA controller. It is used to acquire the clock signal and chip select signal output by the host through the SPI interface; to read configuration parameters stored in the register module, including communication mode flags configured by the on-chip system; to dynamically generate enable signals and control logic suitable for different communication modes based on the configuration parameters, thereby controlling the SPI transmit shift register or the SPI receive shift register to shift and load data; and to monitor the status flags generated by the transmit asynchronous FIFO and the receive asynchronous FIFO in the system clock domain, and send transmission enable and start commands to the first DMA controller or the second DMA controller according to the status flags.

[0007] The register module is connected to the system bus interface and the core control module, and is used to receive configuration read and write requests initiated by the system on-chip through the system bus interface, update internal configuration parameters, and provide real-time configuration parameters to the core control module.

[0008] The first DMA controller is connected to the core control module, the system bus interface, and the transmit asynchronous FIFO, and is used to read data to be transmitted from the memory of the on-chip system and write it into the transmit asynchronous FIFO under the control of the core control module.

[0009] The asynchronous FIFO is connected to the first DMA controller, the SPI transmit shift register, and the core control module. It is used to receive data written from the first DMA controller in the system clock domain and to allow the SPI transmit shift register to read the data to be transmitted in the communication clock domain.

[0010] The SPI transmit shift register is connected to the SPI interface, the transmit asynchronous FIFO, and the core control module. It is used to read data in the transmit asynchronous FIFO in parallel. Under the communication clock domain, it is controlled by the core control module and loads the read data into the SPI interface according to the configured communication mode.

[0011] The SPI receive shift register is connected to the SPI interface, the receive asynchronous FIFO, and the core control module. It is used to be controlled by the core control module under the communication clock domain to sample serial data from the SPI interface and write it into the receive asynchronous FIFO in parallel.

[0012] The asynchronous FIFO is connected to the SPI receive shift register, the second DMA controller, and the core control module. It is used to receive data written from the SPI receive shift register in the communication clock domain and to provide data to the second DMA controller in the system clock domain.

[0013] The second DMA controller is connected to the receive asynchronous FIFO, the core control module, and the system bus interface, and is used to read data from the receive asynchronous FIFO under the control of the core control module and write it to the on-chip system memory through the system bus interface.

[0014] According to a second aspect of the present invention, a method for operating an SPI slave controller based on the first aspect is provided, the method comprising:

[0015] Step 101: The core control module reads the configuration parameters stored in the register module, dynamically generates enable signals and control logic suitable for different communication modes based on the configuration parameters, and monitors the "non-full" status flag generated by the asynchronous FIFO under the system clock domain.

[0016] Step 102: At each rising edge of the system clock, the first DMA controller monitors the "not full" status flag of the transmit asynchronous FIFO sent by the core control module. When the "not full" status flag is detected to be valid, it initiates a read operation request to the on-chip system memory to the system bus interface and latches one byte of data to be transmitted from the data bus.

[0017] Step 103: On the next rising edge of the system clock, the first DMA controller writes the latched data to be transmitted into the transmit asynchronous FIFO, triggering the transmit asynchronous FIFO to update its local write pointer;

[0018] Step 104: The asynchronous FIFO converts the read pointer under the communication clock SCK domain into Gray code and synchronizes it to the system clock domain. Under the system clock domain, by comparing the synchronized read pointer with the local write pointer of the system clock domain, a "non-full" status flag is continuously generated and the "non-full" status flag is provided to the core control module.

[0019] Step 105: Under the control of the core control module, the SPI transmit shift register reads parallel data from the transmit asynchronous FIFO, performs serial shifting according to the data line configuration corresponding to the current communication mode, and outputs it to the data line in the SPI interface.

[0020] According to a third aspect of the present invention, a method for operating an SPI slave controller based on the first aspect is provided, the method comprising:

[0021] Step 201: The core control module reads the configuration parameters stored in the register module, dynamically generates enable signals and control logic suitable for different communication modes based on the configuration parameters, and monitors the "non-empty" status flag generated by the receiving asynchronous FIFO in the system clock domain.

[0022] Step 202: Under the control of the core control module, the SPI receive shift register samples serial data from the data line of the SPI interface according to the currently configured communication mode, and shifts the data into the SPI receive shift register one by one. The assembled parallel data is written into the receive asynchronous FIFO, and at the same time, the receive asynchronous FIFO is triggered to update the write pointer of the communication clock SCK field.

[0023] Step 203: The receiving asynchronous FIFO converts the write pointer under the communication clock SCK domain into Gray code and synchronizes it to the system clock domain. In the system clock domain, by comparing the synchronized write pointer with the local read pointer of the system clock domain, a "non-empty" status flag is continuously generated, and the "non-empty" status flag is provided to the core control module.

[0024] Step 204: At each rising edge of the system clock, the second DMA controller monitors the "not empty" status flag of the receive asynchronous FIFO sent by the core control module. When the "not empty" status flag is detected to be valid, step 205 is executed.

[0025] Step 205: The second DMA controller reads data from the receive asynchronous FIFO and writes the read data into the on-chip system memory through the system bus interface on the next rising edge of the system clock, while triggering the receive asynchronous FIFO to update the local read pointer of the system clock domain.

[0026] According to a fourth aspect of the present invention, a chip is provided that includes the SPI slave controller described above, the chip communicating with a master via the SPI slave controller.

[0027] The technical solution provided by this invention employs a dual asynchronous FIFO (First Input First Output) architecture combined with a dual DMA (Data Memory Access) controller, which significantly improves the communication frequency in the process. This breaks the fixed multiple relationship (usually ≥2 times) that must be met between the system clock (sys_clk) and the serial communication clock (sck) in traditional SPI designs, allowing for higher communication rates at lower system clock frequencies. This improves overall data transmission efficiency and on-chip system throughput. Furthermore, through the coordinated design of configurable register modules and core control modules, it achieves compatibility and dynamic switching between single-wire, dual-wire, and four-wire SPI communication modes on a single controller hardware, thereby significantly enhancing the flexibility and compatibility of the interface while increasing the upper limit of the communication rate. Attached Figure Description

[0028] To illustrate this more clearly, the embodiments of the present invention or the prior art will be briefly described below with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of an existing SPI interface device;

[0030] Figure 2 This is a schematic diagram of the communication structure of an SPI slave controller provided in Embodiment 1 of the present invention;

[0031] Figure 3 This is a block diagram of an SPI slave controller structure provided in Embodiment 1 of the present invention;

[0032] Figure 4 This is a schematic flowchart of a data transmission method for an SPI slave controller provided in Embodiment 2 of the present invention;

[0033] Figure 5 This is a schematic flowchart of a data receiving method for an SPI slave controller provided in Embodiment 2 of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0035] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of devices and methods consistent with some aspects of the invention as detailed in the appended claims.

[0036] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings. Example 1

[0037] In existing technologies, such as Figure 1 The diagram shows a traditional SPI interface device. When a traditional SPI interface device operates in slave mode and receives data, it shifts the serial data into a shift register under the SCK clock domain, assembles it into parallel bytes, and stores it in a buffer. The SPI interface needs to synchronize the data in the buffer to the system clock (sys_clk) domain. This synchronization process consumes at least two system clock cycles. To prevent it from being overwritten by new data, the buffer must be locked, preventing any write operations. This results in strict performance constraints on data transmission: the system clock frequency (f_sys_clk) must be at least twice the SPI communication clock frequency (f_sck) (i.e., f_sys_clk ≥ 2 × f_sck). For example, for a four-wire SPI interface operating at a 50 MHz communication clock frequency, the on-chip system frequency must reach 100 MHz or higher, which significantly increases the on-chip system power consumption and design complexity. When sending data, the data stream faces a similar problem. After writing data to the buffer, it must wait for the data to be synchronized to the SCK clock domain before serial shifting and output can begin, resulting in idle waiting and reduced bus utilization.

[0038] Meanwhile, in existing technologies, single-wire mode prioritizes low cost and low power consumption, and its slower data rate (N=8) allows for the use of simplified data paths and shallow buffers. In contrast, four-wire mode prioritizes extreme throughput, and its extremely high data rate (N=2) requires extremely high system clock frequencies (f_sys ≥ 2 * f_sck) and wider and deeper buffers. Moreover, the core data path components of the two modes differ greatly and are difficult to reuse efficiently. Single-wire mode uses a simple 1-bit shift register and fixed unidirectional pins MOSI and MISO, resulting in simple control logic. Four-wire mode, on the other hand, requires complex multi-bit bidirectional shift registers, with all data lines being bidirectional. This necessitates complex tri-state gate control, direction switching logic, and timing control. This part of the logic is completely unusable in single-wire mode, but integrating it together increases the chip and device area and static power consumption. Therefore, to support different SPI extension modes such as single-wire (standard full-duplex), two-wire (half-duplex), and four-wire (half-duplex), it is usually necessary to design separate hardware controllers or data paths for each mode. In traditional architectures, if a unified design is forced, the hardware must be built to the high standard of four-wire mode, resulting in huge waste of area and power consumption when used in single-wire mode.

[0039] Based on this, the present application provides an SPI slave controller. The SPI slave controller provided in this application adopts a dual asynchronous FIFO (First Input First Output) combined with a dual DMA (Direct Memory Access) controller architecture, which greatly improves the communication frequency in the process.

[0040] like Figure 2 The diagram shown is a schematic of the SPI slave controller communication structure of this application. The SPI interface of the SPI slave controller includes the following signal lines:

[0041] SS is the slave device enable signal line, controlled by the SPI master. When SS is low, communication is active.

[0042] SCK is the clock signal line, generated by the SPI master. Communication can be performed when SS is low and SCK has a clock signal.

[0043] MOSI is the master output and slave input data line;

[0044] MISO is the master input and slave output data line;

[0045] IO2 and IO3 are data lines in the four-wire communication mode.

[0046] In this application, the SPI slave controller is integrated into the SoC chip. The SoC chip acts as a slave and communicates with the master through the SPI interface. The main clock of the SoC chip is sys_clk, and the communication clock between the SPI interface and the master is SCK.

[0047] The SPI slave controller provided in this application supports the following three communication modes:

[0048] Mode 1: Normal communication mode, using 4 lines: SS, SCK, MOSI and MISO. In normal operation mode, MOSI is used as the master output and slave input data line, and MISO is used as the master input and slave output data line. It can work in full-duplex mode.

[0049] Mode 2: Two-wire communication mode, using 4 lines: SS, SCK, MOSI and MISO. When the slave device receives data, both MOSI and MISO are used as input data lines. When the slave device sends data, both MOSI and MISO are used as output data lines. This mode operates in half-duplex mode.

[0050] Mode 3: Four-wire communication mode, using 6 lines: SS, SCK, MOSI, MISO, IO2, and IO3. When the slave device receives data, MOSI, MISO, IO2, and IO3 are all used as input data lines of the slave device; when the slave device sends data, MOSI, MISO, IO2, and IO3 are all used as output data lines of the slave device. At this time, it works in half-duplex mode.

[0051] The SPI slave controller provided in this application will be described in detail below.

[0052] like Figure 3 As shown, this embodiment of the invention provides an SPI slave controller, which is integrated into a system-on-a-chip (SoC) to realize data transmission between the SoC and the host interface. The SPI slave controller includes an SPI interface, a core control module, a register module, a first DMA controller, a transmit asynchronous FIFO, an SPI transmit shift register, an SPI receive shift register, a receive asynchronous FIFO, a second DMA controller, and a system bus interface.

[0053] The SPI interface connects to the SPI transmit shift register, the SPI receive shift register, and the core control module. It is used to connect to an external host and includes the chip select signal line SS, the clock signal line SCK, and the data lines MOSI, MISO, IO2, and IO3.

[0054] The core control module, connected to the SPI interface, SPI transmit shift register, SPI receive shift register, transmit asynchronous FIFO, receive asynchronous FIFO, register module, first DMA controller, and second DMA controller, is used to acquire the clock signal SCK and chip select signal SS output by the host through the SPI interface; to read the configuration parameters stored in the register module, including the communication mode flag configured by the on-chip system, and to dynamically generate internal enable signals and control logic suitable for different communication modes based on the configuration parameters, so as to control the SPI transmit shift register or SPI receive shift register to shift and load data; and to monitor the status flags generated by the transmit asynchronous FIFO and receive asynchronous FIFO under the system clock domain, and send transmission enable and start commands to the first DMA controller or second DMA controller according to the status flags.

[0055] The core control module dynamically generates enable signals and control logic suitable for different communication modes based on the communication mode flag to achieve communication mode compatibility;

[0056] The core control module is specifically used to obtain the current communication mode flag, generate an enable signal corresponding to the obtained communication mode, and control the SPI transmit shift register and SPI receive shift register to perform data shifting and loading based on the clock signal SCK when the chip select signal is valid.

[0057] Specifically, the core control module includes a protocol state machine, which is used to execute the corresponding protocol sequence according to the communication mode flag and generate corresponding control signals to dynamically configure the bit width of the SPI transmit shift register and the SPI receive shift register and control the direction of the data lines.

[0058] For example, in dual-line receive mode, the core control module controls the SPI receive shift register to simultaneously sample data from both the MOSI and MISO data lines and combine them into a single data unit.

[0059] The configuration parameters also include the transmission data length configured by the on-chip system. The core control module is also used to determine the data transmission completion status based on the configured transmission data length and to set the data transmission completion flag stored in the status register in the register module.

[0060] The core control module is also connected to the system bus interface to receive control signals sent by the on-chip system through the system bus interface, and to reset the data transmission flag stored in the status register in the register module according to the control signals.

[0061] The register module connects to the system bus interface and the core control module. It is used to receive configuration read and write requests initiated by the on-chip system through the system bus interface, update internal configuration parameters, and provide real-time configuration parameters to the core control module.

[0062] The first DMA controller is connected to the core control module, the system bus interface, and the transmit asynchronous FIFO. Under the control of the core control module, it reads the data to be transmitted from the memory of the on-chip system and writes it into the transmit asynchronous FIFO.

[0063] Specifically, the first DMA controller is connected to the on-chip system memory at one end through the system bus interface, and at the other end is connected to the write port of the asynchronous FIFO (located in the system clock domain).

[0064] The asynchronous FIFO is connected to the first DMA controller, the SPI transmit shift register, and the core control module. It is used to receive data written by the first DMA controller as data to be transmitted in the system clock domain, and to provide the SPI transmit shift register with the data to be transmitted in the communication clock domain.

[0065] Specifically, the asynchronous FIFO is a hardware storage module for cross-clock domain data transmission. It can be formed by a set of discrete registers (such as 8 bytes) to create a circular buffer, without the need for built-in dual-port RAM.

[0066] The asynchronous FIFO includes a write port and a read port. The write port is connected to the first DMA controller in the system clock domain, and the read port is connected to the SPI transmit shift register in the communication clock domain. This connection enables reliable data transmission and rate adaptation from the system domain to the communication domain.

[0067] The asynchronous FIFO also includes a first read / write pointer controller and a first status flag generation unit;

[0068] Furthermore, under the system clock sys_clk domain, the asynchronous FIFO transmits the read pointer (rd_ptr_sck) under the communication clock SCK domain through the first read / write pointer controller, which synchronizes it to the system clock sys_clk domain via Gray code. The first status flag generation unit compares the synchronized read pointer with the local write pointer (wr_ptr_sys) and generates a "not full" status flag. This "not full" status flag is obtained by the core control module and used to control the first DMA controller.

[0069] In this embodiment, under the communication clock SCK domain, the asynchronous FIFO does not need to generate a "non-empty" status flag. It only needs to ensure that the average data write rate of the system clock sys_clk domain is higher than the data read rate of the communication clock SCK domain.

[0070] The SPI transmit shift register is connected to the SPI interface, the transmit asynchronous FIFO, and the core control module. It is used to read data in the transmit asynchronous FIFO in parallel under the control of the core control module in the communication clock domain, and load the read data into the SPI interface according to the configured communication mode.

[0071] The SPI transmit shift register includes a parallel loading end and a serial output end. The parallel loading end is connected to the read port of the transmit asynchronous FIFO, and the serial output end is connected to the MISO and other data lines of the SPI interface.

[0072] Specifically, whenever a new byte needs to be sent (e.g., at the start of transmission or the completion of the previous byte transmission), the SPI transmit shift register loads a complete byte of data from the memory cell pointed to by the read pointer under the SCK field of the transmit asynchronous FIFO at the effective edge of the communication clock SCK. Under the control of the enable signal output by the core control module, the loaded data is shifted out one by one to the data line of the SPI interface. When a byte (8 bits) of data has been shifted out, the transmit asynchronous FIFO is triggered to increment its read pointer to prepare for loading the next byte.

[0073] The SPI receive shift register is connected to the SPI interface, the receive asynchronous FIFO, and the core control module. It is used to sample serial data from the SPI interface and write it into the receive asynchronous FIFO in parallel under the control of the core control module in the communication clock domain.

[0074] The SPI receive shift register includes a serial input terminal and a parallel output terminal. The serial input terminal is connected to the MOSI and other data lines of the SPI interface, and the parallel output terminal is connected to the write port of the receive asynchronous FIFO.

[0075] Specifically, whenever new data needs to be received (e.g., the start of transmission or the completion of the previous byte reception), the SPI receive shift register samples serial data from the data line of the SPI interface and shifts it into the SPI receive register at the effective edge of the communication clock SCK. After a complete byte (8 bits) of data has been shifted in, under the control of the enable signal output by the core control module, the byte of data is written into the memory cell pointed to by the write pointer of the SCK field of the receive asynchronous FIFO. After the data writing operation is completed, the receive asynchronous FIFO is triggered to increment its write pointer to prepare for storing the next received byte of data.

[0076] The asynchronous FIFO is connected to the SPI receive shift register, the second DMA controller, and the core control module. It is used to receive data written from the SPI receive shift register in the communication clock domain and to allow the second DMA controller to read the data to be stored in the system clock domain.

[0077] Specifically, the asynchronous FIFO is a hardware storage module for cross-clock domain data transmission. It can be composed of a set of discrete registers (such as 8 bytes) forming a circular buffer and does not require built-in dual-port RAM.

[0078] The asynchronous FIFO for receiving includes a write port and a read port. The write port is connected to the SPI receive shift register in the communication clock domain, and the read port is connected to the second DMA controller in the system clock domain. This connection enables the transfer and buffering of received data from the communication clock domain to the system clock domain.

[0079] The asynchronous FIFO also includes a second read / write pointer controller and a second status flag generation unit;

[0080] Furthermore, under the system clock sys_clk domain, the receive asynchronous FIFO synchronizes the write pointer (wr_ptr_sck) under the communication clock SCK domain to the system clock sys_clk domain via Gray code through the second read / write pointer controller. The synchronized write pointer is compared with the local read pointer (rd_ptr_sys) by the second status flag generation unit and a "non-empty" status flag is generated. This "non-empty" status flag is obtained by the core control module and used to control the second DMA controller.

[0081] Under the communication clock SCK domain, the asynchronous FIFO does not need to generate a "not full" status flag;

[0082] The second DMA controller is connected to the receive asynchronous FIFO, the core control module, and the system bus interface. It is used to read data from the receive asynchronous FIFO under the control of the core control module and write it to the on-chip system memory through the system bus interface.

[0083] Specifically, one end of the second DMA controller is connected to the read port of the asynchronous FIFO (located in the system clock domain), and the other end is connected to the on-chip system memory through the system bus interface;

[0084] The system bus interface is connected to the first DMA controller, the second DMA controller, and the register module. It is used to respond to read and write requests from the first DMA controller and the second DMA controller, initiate read and write operations on the on-chip system memory, and respond to read and write requests from the on-chip system to the configuration parameters stored in the register module.

[0085] The system bus interface is also connected to the core control module to respond to requests from the on-chip system to send control signals to the core control module.

[0086] In this embodiment, the SPI transmit shift register and the SPI receive shift register are specifically multi-bit shift registers; in single-wire communication mode, the shift register uses 1 bit each time, in two-wire communication mode, the shift register uses 2 bits each time, and in four-wire communication mode, the shift register uses 4 bits each time.

[0087] In this embodiment, the sending asynchronous FIFO and receiving asynchronous FIFO can support four-wire communication mode transmission. When used in single-wire communication mode, it only has a larger buffer "margin" and does not cause performance loss. The increased hardware area is much lower than the area of ​​the integrated communication mode in traditional design. This is because the asynchronous FIFO has depth and width storage areas.

[0088] In this embodiment, the first DMA controller and the second DMA controller are specifically high-performance DMA controllers with sufficient bandwidth to meet the data transmission requirements of the four-wire communication mode. In the single-wire mode, they operate at a lower utilization rate. High-speed data transmission is achieved through the DMA controller without the need for central processing unit intervention, effectively reducing the CPU load of the on-chip system.

[0089] The SPI slave controller provided by the above scheme is equipped with independent transmit asynchronous FIFO and receive asynchronous FIFO. Each asynchronous FIFO has two independent ports. One port is located in the communication clock domain and is directly connected to the SPI shift register. The other port is located in the system clock domain and is connected to the DMA controller module. Data transmission between the two ports is achieved through a dedicated pointer controller and status flag generation unit. There is no need to "freeze" the entire buffer for signal synchronization, thus decoupling the operation of the two clock domains.

[0090] This invention utilizes a special asynchronous FIFO to remove the constraint of the fixed frequency ratio of sys_clk and sck, and leverages a high-performance built-in DMA to ensure smooth data flow across clock domains. The parallel pipeline architecture of dual DMA controllers and dual asynchronous FIFOs enables overlapping operations of data transfer and serial communication, reducing CPU intervention and improving overall data transmission efficiency and on-chip system throughput. Furthermore, through the aforementioned configurable core control module, flexible shift register design, and unified asynchronous FIFO buffering mechanism, this invention successfully integrates the three SPI communication modes that originally required separate design into a single controller. Users only need to configure registers via software to switch modes, achieving a balance between high performance and high flexibility, and solving the problem of incompatibility caused by separate design of communication modes in existing technologies. Example 2

[0091] Embodiment 2 of the present invention provides a method for operating an SPI slave controller, the method including a data transmission method and a data reception method;

[0092] like Figure 4 The diagram shows the data transmission method for the SPI slave controller, which specifically includes the following steps:

[0093] Step 101: The core control module reads the configuration parameters stored in the register module, dynamically generates enable signals and control logic suitable for different communication modes based on the configuration parameters, and monitors the "non-full" status flag generated by the asynchronous FIFO under the system clock domain.

[0094] In this embodiment, the "not full" status flag is generated by the status flag generation unit that sends the asynchronous FIFO.

[0095] Step 102: At each rising edge of the system clock, the first DMA controller monitors the "not full" status flag of the transmit asynchronous FIFO sent by the core control module. When the "not full" status flag is detected to be valid, step 103 is executed.

[0096] In this embodiment, an initialization process is included before step 101, which specifically includes:

[0097] The SoC's CPU accesses the register module via the system bus to configure the SPI operating mode and set the clock to match the external master device;

[0098] Step 103: The first DMA controller initiates a read operation request to the on-chip system memory through the system bus interface and latches one byte of data to be sent from the data bus;

[0099] In this embodiment, the first DMA controller preloads the data to be sent into the asynchronous FIFO before the external host initiates data transmission, thereby achieving high-speed transmission;

[0100] One feasible approach is for the first DMA controller to perform one 8-bit data read / write operation per system clock cycle sys_clk.

[0101] Step 104: On the next rising edge of the system clock, the first DMA controller writes the latched data to be sent into the transmit asynchronous FIFO, triggering the transmit asynchronous FIFO to update the local write pointer;

[0102] Step 105: Send the asynchronous FIFO to convert the read pointer under the communication clock SCK domain into Gray code and synchronize it to the system clock domain. Under the system clock domain, by comparing the synchronized read pointer with the local write pointer of the system clock domain, continuously generate the "non-full" status flag and provide the "non-full" status flag to the core control module.

[0103] In this embodiment, the first read / write pointer controller of the asynchronous FIFO converts the read pointer in the communication clock SCK domain into Gray code and synchronizes it to the system clock domain.

[0104] In this embodiment, the first state flag generation unit of the asynchronous FIFO continuously generates a "non-full" state flag by comparing the synchronized read pointer with the local write pointer of the system clock domain.

[0105] Specifically, the first state flag generation unit compares the synchronized read pointer with the local write pointer in the system clock domain as follows: The first state flag generation unit converts the Gray code of the synchronized read pointer into binary code and compares it with the local write pointer in the system clock domain. If the most significant bit is not opposite and the remaining bits are equal, it is determined that the asynchronous FIFO is not full and a "non-full" state flag is generated.

[0106] In the communication clock SCK domain, the transmit asynchronous FIFO does not perform an "empty" state check because the master needs to prepare data before communicating. Typically, a GPIO interrupt handshake is used to confirm the start of communication. When the SPI transmit shift register needs to load new data, it directly reads the data from the memory cell currently pointed to by the transmit asynchronous FIFO read pointer.

[0107] Step 106: Under the control of the core control module, the SPI transmit shift register reads parallel data from the transmit asynchronous FIFO, performs serial shifting according to the data line configuration corresponding to the current communication mode, and outputs the data to the data lines in the SPI interface.

[0108] In this embodiment, the internal buffer data is shifted once for every bit shifted out of the SPI transmit shift register;

[0109] When the external host pulls the chip select low and starts providing the communication clock SCK, the core control module controls the SPI transmit shift register to shift data.

[0110] In this embodiment, after the SPI transmit shift register completes the shifting out of one byte (8 bits), at the next valid edge of the SCK clock, the transmit asynchronous FIFO updates the read pointer in the communication clock SCK domain. At the same time, the SPI transmit shift register automatically reads the next byte from the position newly pointed to by the read pointer, preparing for the subsequent shifting out operation.

[0111] Specifically, updating the read pointer involves incrementing the value of the read pointer rd_ptr_sck by 1; this update operation does not "freeze" the asynchronous FIFO, and write operations in the system clock domain can continue.

[0112] The read / write pointer controller of the asynchronous FIFO will resynchronize the updated SCK field read pointer to the system clock field for the next round of state comparison and flag generation, thereby forming a continuous data stream.

[0113] like Figure 5 The diagram shows a data receiving method for an SPI slave controller, which includes the following steps:

[0114] Step 201: The core control module reads the configuration parameters stored in the register module, dynamically generates enable signals and control logic suitable for different communication modes based on the configuration parameters, and monitors the "non-empty" status flag generated by the asynchronous FIFO under the system clock domain.

[0115] In this embodiment, the "not empty" status flag is generated by the status flag generation unit that sends the asynchronous FIFO.

[0116] Step 202: Under the control of the core control module, the SPI receive shift register samples serial data from the data line of the SPI interface according to the currently configured communication mode, and shifts the data into the SPI receive shift register one by one. The assembled parallel data is written into the receive asynchronous FIFO, and at the same time, the write pointer of the communication clock SCK field of the receive asynchronous FIFO is triggered to update.

[0117] In this embodiment, the SPI receive shift register samples instructions or data sent by the host from the data line under the SCK clock domain;

[0118] In this embodiment, writing the assembled parallel data into the receive asynchronous FIFO specifically means writing the assembled parallel data into the storage unit of the receive asynchronous FIFO located in the communication clock SCK domain;

[0119] In this embodiment, when the SPI receive shift register is full of one byte of data, the data is written to the write pointer position of the receive asynchronous FIFO in the communication clock domain, and the read / write pointer controller in the receive asynchronous FIFO is triggered to increment the value of the write pointer wr_ptr_sck by 1.

[0120] For example, in two-wire mode, the SPI receive shift register samples one bit from both MOSI and MISO simultaneously in each SCK cycle, quickly assembling it into a byte. After a data unit (such as a byte) is full, the data is written to the receive asynchronous FIFO.

[0121] Step 203: The asynchronous FIFO receives the write pointer in the communication clock SCK domain and converts it into Gray code, and synchronizes it to the system clock domain. In the system clock domain, the status flag generation unit of the asynchronous FIFO continuously generates a "non-empty" status flag by comparing the synchronized write pointer with the local read pointer in the system clock domain, and provides the "non-empty" status flag to the core control module.

[0122] In this embodiment, the second read / write pointer controller that receives the asynchronous FIFO converts the write pointer in the communication clock SCK domain into Gray code and synchronizes it to the system clock domain.

[0123] In this embodiment, the second state flag generation unit that receives the asynchronous FIFO continuously generates a "non-empty" state flag by comparing the synchronized write pointer with the local read pointer of the system clock domain.

[0124] Specifically, the second state flag generation unit compares the synchronized write pointer with the local read pointer in the system clock domain as follows: The second state flag generation unit converts the Gray code of the synchronized write pointer into binary code and compares it with the local read pointer in the system clock domain. If the data bits of the read and write pointers are not equal, it determines that the receive asynchronous FIFO is not empty and generates a "non-empty" state flag.

[0125] In the communication clock SCK domain, the receive asynchronous FIFO does not perform a "full" state judgment. As long as the SPI receive shift register completes the assembly of a data unit, it can be written to the receive asynchronous FIFO (provided that the physical buffer is not full, but since the data shift rate of the system clock domain is sufficient, it is usually not full). The read and write pointer controller of the receive asynchronous FIFO will continuously manage the updated system clock domain read pointer (used for the next round of state comparison) and SCK domain write pointer (used for the next round of synchronization), thereby forming a continuous data receiving stream.

[0126] Step 204: At each rising edge of the system clock, the second DMA controller monitors the "not empty" status flag of the receive asynchronous FIFO sent by the core control module. When the "not empty" status flag is detected to be valid, step 205 is executed.

[0127] Step 205: The second DMA controller reads data from the memory cell of the receive asynchronous FIFO located in the system clock domain, and writes the read data into the on-chip system memory through the system bus interface on the next rising edge of the system clock, while triggering the receive asynchronous FIFO to update the local read pointer of the system clock domain;

[0128] In this embodiment, both the transmit asynchronous FIFO and the receive asynchronous FIFO can be formed into a circular buffer using a set of discrete registers (e.g., 8 bytes). The transmit asynchronous FIFO synchronizes the read pointer of the SCK domain with the system clock domain using Gray code synchronization, compares it with the local write pointer to generate a "not full" flag, which is then read by the core control module to trigger the first DMA controller. Similarly, the receive asynchronous FIFO synchronizes the write pointer of the SCK domain with the system clock domain using Gray code synchronization, compares it with the local read pointer to generate a "not empty" flag, which is then read by the core control module to trigger the second DMA controller. In the SCK clock domain, neither the transmit nor receive asynchronous FIFO performs a complete full / empty check; only simple pointer incrementing and read / write operations are performed. This design is key to the architecture's ability to break the limitations of traditional clock frequency ratios. A sufficient condition for its stable operation is that the average data processing rate on the system side is higher than the average data transmission rate on the communication side.

[0129] In this embodiment, the second DMA controller operates at the system clock rate sys_clk, independently and in real-time moving data from the receive asynchronous FIFO to the on-chip system memory. Even if the external SCK frequency is extremely high (e.g., more than 8 times sys_clk), as long as the sustained throughput of the on-chip system clock domain (sys_clk domain) is greater than the sustained throughput of the communication clock domain (SCK domain), the data in the receive buffer will not overflow. This allows the SPI interface provided in this application to reliably receive and process serial data streams with frequencies several times higher than its own system clock, provided that the sustained throughput of the system clock domain (sys_clk domain) is met.

[0130] Through the above steps, the received data is safely and efficiently transferred from the communication clock domain to the system clock domain, and automatically stored in the on-chip system memory by the second DMA controller. The whole process does not require frequent CPU intervention and avoids the frequency limitations caused by cross-clock domain synchronization in traditional designs.

[0131] The following specific examples illustrate the data processing speed effect of using the SPI slave controller of this application;

[0132] To ensure continuous and uninterrupted data transmission (i.e., no data overflow or underflow in the asynchronous FIFO), the inequality relationship must be satisfied: the sustainable throughput of sys_clk data processing R_sys must be greater than the SCK communication data rate R_sck, i.e., R_sys > R_sck. Here, R_sys represents the sustainable throughput of the system-side data path, and its theoretical maximum value is determined by the operating frequency and efficiency of the built-in DMA controller. In this embodiment, R_sys = system clock frequency (f_sys) × 1 byte / cycle; R_sck represents the effective data rate on the SCK communication line, and its value is R_sck = communication clock frequency (f_sck) / N, where N is the number of communication clock cycles required to transmit one byte of data.

[0133] Taking the standard single-data-line mode SPI as an example, each byte of data transmission requires 8 SCK cycles. Based on the above formula, the core constraint condition for clock frequency in this invention can be derived as: f_sys > f_sck / 8. Based on this condition, it can be seen that traditional SPI interfaces, due to their cross-clock domain synchronization mechanism limitations, typically require the system clock frequency to be at least twice the communication clock frequency, i.e., f_sys ≥ 2 × f_sck. Under the same system clock frequency f_sys, the upper limit of the communication clock frequency supported by the SPI interface provided by this invention is f_sck_max_inv < (8 × f_sys). Therefore, under the same conditions, the improvement factor P in communication clock frequency support capability compared to traditional interfaces can be quantitatively calculated as: P = f_sck_max_inv / f_sck_max_trad ≈ (8 × f_sys) / (f_sys / 2) = 16, i.e., a performance improvement of up to 16 times.

[0134] Taking dual SPI (dual SPI) mode as an example, each byte of data transmission requires 4 SCK cycles. Based on the above formula, the core constraint condition for clock frequency in this invention can be derived as: f_sys > (f_sck / 4). Based on this condition, it can be known that under the same system clock frequency f_sys, the upper limit of the communication clock frequency supported by the SPI interface provided by this invention is f_sck_max_inv < (4 × f_sys). Therefore, the improvement factor P in communication clock frequency support capability compared to traditional interfaces can be quantitatively calculated as: P = f_sck_max_inv / f_sck_max_trad ≈ (4 × f_sys) / (f_sys / 2) = 8, that is, a performance improvement of up to 8 times.

[0135] Taking the quad SPI (quad SPI) mode as an example, i.e., double data rate mode, it requires 2 SCK cycles to transmit 1 byte. According to the above formula, the core constraint condition of the present invention on the clock frequency relationship can be derived as: f_sys > (f_sck / 2). Based on this condition, it can be seen that under the same system clock frequency f_sys, the upper limit of the communication clock frequency supported by the SPI interface provided by the present invention is f_sck_max_inv < (2 × f_sys). Therefore, the improvement factor P of the present invention in communication clock frequency support capability compared with the traditional interface can be quantitatively calculated as: P = f_sck_max_inv / f_sck_max_trad ≈ (2 × f_sys) / (f_sys / 2) = 4, that is, the performance improvement is as high as 4 times.

[0136] This embodiment, through the collaborative design of "independent dual DMA controller" and "independent dual asynchronous FIFO", shifts the performance bottleneck from a fixed clock frequency ratio to a flexible and optimizable sustainable throughput matching relationship. According to the calculation data in the above example, the communication clock frequency and corresponding effective data transmission rate supported by the present invention under the same system clock frequency can reach up to 16 times that of the traditional design, achieving a performance breakthrough of orders of magnitude.

[0137] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0138] This invention also provides a chip that includes the SPI slave controller described in the above embodiments, and the chip communicates with the master through the SPI slave controller.

[0139] In this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or order; the term "multiple" refers to two or more unless otherwise explicitly defined. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship. The terms "install," "connect," "link," "fix," etc., should be interpreted broadly. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; "link" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0140] In the description of this invention, it should be understood that the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0141] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, equivalent variations made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. An SPI slave controller, comprising an SPI interface, an SPI transmit shift register, an SPI receive shift register, and a system bus interface, wherein the SPI slave controller is integrated into a system-on-a-chip, characterized in that, It also includes a core control module, a transmit asynchronous FIFO, a first DMA controller, a receive asynchronous FIFO, a second DMA controller, and a register module; The core control module is connected to the SPI interface, the SPI transmit shift register, the SPI receive shift register, the transmit asynchronous FIFO, the receive asynchronous FIFO, the register module, the first DMA controller, and the second DMA controller. It is used to acquire the clock signal and chip select signal output by the host through the SPI interface; to read the configuration parameters stored in the register module, and dynamically generate enable signals and control logic suitable for different communication modes based on the configuration parameters, so as to control the SPI transmit shift register or the SPI receive shift register to shift and load data; and to monitor the status flags generated by the transmit asynchronous FIFO and the receive asynchronous FIFO in the system clock domain, and send transmission enable and start commands to the first DMA controller or the second DMA controller according to the status flags. The register module is connected to the system bus interface and the core control module, and is used to receive configuration read and write requests initiated by the system on-chip through the system bus interface, update internal configuration parameters, and provide real-time configuration parameters to the core control module. The first DMA controller is connected to the core control module, the system bus interface, and the transmit asynchronous FIFO, and is used to read data to be transmitted from the memory of the on-chip system and write it into the transmit asynchronous FIFO under the control of the core control module. The asynchronous FIFO is connected to the first DMA controller, the SPI transmit shift register, and the core control module. It is used to receive data written from the first DMA controller in the system clock domain and to allow the SPI transmit shift register to read data in the communication clock domain. The SPI transmit shift register is connected to the SPI interface, the transmit asynchronous FIFO, and the core control module. It is used to read data in the transmit asynchronous FIFO in parallel. Under the communication clock domain, it is controlled by the core control module and loads the read data into the SPI interface according to the configured communication mode. The SPI receive shift register is connected to the SPI interface, the receive asynchronous FIFO, and the core control module. It is used to be controlled by the core control module under the communication clock domain to sample serial data from the SPI interface and write it into the receive asynchronous FIFO in parallel. The asynchronous FIFO is connected to the SPI receive shift register, the second DMA controller, and the core control module. It is used to receive data written from the SPI receive shift register in the communication clock domain and to provide data to the second DMA controller in the system clock domain. The second DMA controller is connected to the receive asynchronous FIFO, the core control module, and the system bus interface, and is used to read data from the receive asynchronous FIFO under the control of the core control module, and write it to the on-chip system memory through the system bus interface.

2. The SPI slave controller according to claim 1, characterized in that, The SPI interface is connected to the SPI transmit shift register, the SPI receive shift register, and the core control module, and is used to connect to an external host. The SPI interface includes a chip select signal line, a clock signal line, and a data signal line; The system bus interface is connected to the first DMA controller, the second DMA controller, and the register module, and is used to respond to read and write requests from the first DMA controller and the second DMA controller, initiate read and write operations on the on-chip system memory, and respond to read and write requests from the on-chip system for configuration parameters stored in the register module.

3. The SPI slave controller according to claim 1, characterized in that, The configuration parameters include a communication mode flag configured by the system-on-chip. The core control module is specifically used to obtain the current communication mode flag stored in the register module, generate an enable signal corresponding to the obtained communication mode, and control the SPI transmit shift register and the SPI receive shift register to shift and load data based on the clock signal when the chip select signal is valid.

4. The SPI slave controller according to claim 1, characterized in that, The asynchronous FIFO includes a write port and a read port. The write port is connected to the first DMA controller in the system clock domain, and the read port is connected to the SPI transmit shift register in the communication clock domain. The asynchronous FIFO includes a write port and a read port. The write port is connected to the SPI receive shift register under the communication clock domain, and the read port is connected to the second DMA controller under the system clock domain.

5. The SPI slave controller according to claim 1, characterized in that, The asynchronous FIFO for transmission also includes a first read / write pointer controller and a first status flag generation unit; The first read / write pointer controller is used to synchronize the read pointer in the communication clock domain to the system clock domain via Gray code in the system clock domain; The first status flag generation unit is used to compare the synchronized read pointer with the local write pointer and generate a "not full" status flag. The status flag is obtained by the core control module and used to control the first DMA controller.

6. The SPI slave controller according to claim 1, characterized in that, The asynchronous FIFO for receiving also includes a second read / write pointer controller and a second status flag generation unit; The second read / write pointer controller is used to synchronize the write pointer in the communication clock domain to the system clock domain via Gray code in the system clock domain; The second status flag generation unit is used to compare the synchronized write pointer with the local read pointer and generate a "not empty" status flag. The status flag is obtained by the core control module and used to control the second DMA controller.

7. The SPI slave controller according to claim 1, characterized in that, The system clock frequency of the SPI slave controller is greater than the ratio of the communication clock frequency to the number of serial clock cycles required to transmit one byte of data.

8. A method for operating an SPI slave controller based on any one of claims 1 to 7, characterized in that, The method includes: Step 101: The core control module reads the configuration parameters stored in the register module, dynamically generates enable signals and control logic suitable for different communication modes based on the configuration parameters, and monitors the "non-full" status flag generated by the asynchronous FIFO under the system clock domain. Step 102: At each rising edge of the system clock, the first DMA controller monitors the "not full" status flag of the transmit asynchronous FIFO sent by the core control module. When the "not full" status flag is detected to be valid, it initiates a read operation request to the on-chip system memory to the system bus interface and latches one byte of data to be transmitted from the data bus. Step 103: On the next rising edge of the system clock, the first DMA controller writes the latched data to be transmitted into the transmit asynchronous FIFO, triggering the transmit asynchronous FIFO to update its local write pointer; Step 104: The asynchronous FIFO converts the read pointer in the communication clock domain into Gray code and synchronizes it to the system clock domain. In the system clock domain, by comparing the synchronized read pointer with the local write pointer in the system clock domain, a "non-full" status flag is continuously generated and the "non-full" status flag is provided to the core control module. Step 105: Under the control of the core control module, the SPI transmit shift register reads parallel data from the transmit asynchronous FIFO, performs serial shifting according to the data line configuration corresponding to the current communication mode, and outputs the data to the data line in the SPI interface.

9. A method for operating an SPI slave controller based on any one of claims 1 to 7, characterized in that, The method includes: Step 201: The core control module reads the configuration parameters stored in the register module, dynamically generates enable signals and control logic suitable for different communication modes based on the configuration parameters, and monitors the "not empty" status flag generated by the asynchronous FIFO under the system clock domain. Step 202: Under the control of the core control module, the SPI receive shift register samples serial data from the data line of the SPI interface according to the currently configured communication mode, and shifts the data into the SPI receive shift register one by one. The assembled parallel data is written into the receive asynchronous FIFO, and at the same time, the receive asynchronous FIFO is triggered to update the write pointer of the communication clock field. Step 203: The receiving asynchronous FIFO converts the write pointer under the communication clock domain into Gray code and synchronizes it to the system clock domain. In the system clock domain, by comparing the synchronized write pointer with the local read pointer of the system clock domain, a "not empty" status flag is continuously generated and the "not empty" status flag is provided to the core control module. Step 204: At each rising edge of the system clock, the second DMA controller monitors the "not empty" status flag of the receive asynchronous FIFO sent by the core control module. When the "not empty" status flag is detected to be valid, step 205 is executed. Step 205: The second DMA controller reads data from the receive asynchronous FIFO and writes the read data into the on-chip system memory through the system bus interface on the next rising edge of the system clock, while triggering the receive asynchronous FIFO to update the local read pointer of the system clock domain.

10. A chip, characterized in that, The chip includes an SPI slave controller as described in any one of claims 1 to 7, and the chip communicates with the master through the SPI slave controller.

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