Gain cell memory device and method of operating same

Abstract

A gain cell memory device is provided that includes a write transistor on a substrate; a read transistor on the substrate; a capacitor having a first electrode electrically connected to the first source / drain region of the write transistor and the gate electrode of the read transistor, a node dielectric, and a second electrode; and a peripheral circuit configured to electrically bias the source region of the read transistor at a normal source bias voltage when the gain cell memory device is not in a read operation, and electrically biasing a source region of the read transistor with a current-enhanced source bias voltage that increases a turn-on current of the read transistor when the gain cell memory device is in a read operation. The embodiment of the invention also provides a method for operating the gain cell memory device.

Description

Technical Field

[0001] Embodiments of the present application relate to gain unit memory devices and methods of operating the same. Background Art

[0002] A gain unit memory device is a memory device in which the presence or absence of charge on a signal node can be sensed using signal amplification of at least one sensing transistor (i.e., at least one read transistor). Specifically, the signal node is electrically connected to the gate electrode of the read transistor. For example, a three-transistor-one-capacitor (3T1C) gain unit memory device uses a write transistor, a pair of read transistors, and a capacitor. A key performance parameter of a gain unit memory device is the effective retention time, i.e., the maximum duration that allows reliable decoding of the charge stored at the signal node. The longer the effective retention time, the less frequent the refresh operation of the gain unit memory device. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a gain unit memory device is provided, comprising: a write transistor located on a substrate; a read transistor located on the substrate; a capacitor having a first electrode, a node dielectric, and a second electrode, wherein the first electrode is electrically connected to a first source / drain region of the write transistor and a gate electrode of the read transistor; and a peripheral circuit configured to electrically bias the source region of the read transistor with a normal source bias voltage when the gain unit memory device is not in a read operation, and to electrically bias the source region of the read transistor with a current enhancement source bias voltage that increases a conduction current of the read transistor when the gain unit memory device is in a read operation.

[0004] According to another aspect of an embodiment of the present application, a gain unit memory device is provided, comprising: a write transistor, located on a substrate; a read transistor, located on the substrate; a capacitor, having a first electrode, a node dielectric, and a second electrode, the first electrode comprising a signal node electrically connected to a first source / drain region of the write transistor and electrically connected to a gate electrode of the read transistor, wherein the capacitor is located in a dielectric material layer overlying the write transistor and the read transistor; a metal interconnect structure, located in the dielectric material layer, providing electrical connections to the first electrode, the second source / drain region of the write transistor, and the source region of the read transistor; a read bit line, configured to electrically bias the drain region of the read transistor; a source bias line, electrically connected to the source region of the read transistor; and a peripheral circuit, configured to electrically bias the source region of the read transistor with a normal source bias voltage when the gain unit memory device is not in a read operation, and to electrically bias the source region of the read transistor with a current enhancement source bias voltage that increases the on-current of the read transistor when the gain unit memory device is in a read operation.

[0005] According to another aspect of an embodiment of the present application, a method for operating a gain unit memory device is provided, the method comprising: providing a gain unit memory device, the gain unit memory device comprising a write transistor located on a substrate, a read transistor located on the substrate, a capacitor, a read bit line and a source line, the capacitor having a first electrode, a node dielectric and a second electrode, the first electrode comprising a first source / drain region electrically connected to the write transistor and a signal node electrically connected to a gate electrode of the read transistor, the read bit line being configured to electrically bias the drain region of the read transistor, and the source bias line being connected to the source region of the read transistor; performing a write operation to encode a data bit in the signal node by applying a write-read bit line bias voltage to the second source / drain region of the write transistor and by turning on the write transistor when the source bias line is electrically biased with the first source bias voltage; and performing a read operation by precharging the read bit line with a precharge bias voltage, by applying a second source bias voltage different from the first source bias voltage to the source bias line, and by sensing the voltage at the drain region of the read transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] It is noted that in any virtual vertical section view, elements may be arbitrarily placed within or outside the vertical plane of the view, and there may not be a specific physical vertical plane that can display all of the elements shown in the virtual vertical section view.

[0008] Figure 1A It is a virtual vertical cross-sectional view of an exemplary structure for forming a three-transistor-one-capacitor (3T1C) gain unit memory device after forming a field effect transistor, a contact-level dielectric material layer, a device contact through-hole structure, a first metal line-level dielectric material layer and a first metal line structure according to an embodiment of the present disclosure. Figure 1B yes Figure 1A A top view of an exemplary structure of FIG.

[0009] Figure 1C It is a virtual vertical cross-sectional view of an exemplary structure for forming a two-transistor-one-capacitor (2T1C) gain unit memory device after forming a field effect transistor, a contact-level dielectric material layer, a device contact through-hole structure, a first metal line-level dielectric material layer and a first metal line structure according to an embodiment of the present disclosure. Figure 1D yes Figure 1C A top view of an exemplary structure of FIG.

[0010] Figure 2A is a virtual vertical cross-sectional view of an exemplary structure for forming a three-transistor-one-capacitor (3T1C) gain cell memory device after forming a second line and via level structure, a via level dielectric layer, and a bottom connecting via structure according to an embodiment of the present disclosure. Figure 2B yes Figure 2A A top view of an exemplary structure of FIG.

[0011] Figure 2C is a virtual vertical cross-sectional view of an exemplary structure for forming a two-transistor-one-capacitor (2T1C) gain cell memory device after forming a second line and via level structure, a via level dielectric layer, and a bottom connecting via structure according to an embodiment of the present disclosure. Figure 2D yes Figure 2C A top view of an exemplary structure of FIG.

[0012] Figure 3A is a virtual vertical cross-sectional view of an exemplary structure for forming a three-transistor-one-capacitor (3T1C) gain cell memory device after forming a capacitor according to an embodiment of the present disclosure. Figure 3B yes Figure 3A A top view of an exemplary structure of FIG.

[0013] Figure 3C is a virtual vertical cross-sectional view of an exemplary structure for forming a two-transistor one-capacitor (2T1C) gain cell memory device after forming a capacitor according to an embodiment of the present disclosure. Figure 3D yes Figure 3C A top view of an exemplary structure of FIG.

[0014] Figure 4A is a virtual vertical cross-sectional view of an exemplary structure for forming a three-transistor-one-capacitor (3T1C) gain cell memory device after forming an upper level dielectric material layer and an upper level metal interconnect structure according to an embodiment of the present disclosure. Figure 4B yes Figure 4A A top view of an exemplary structure of FIG.

[0015] Figure 4C is a virtual vertical cross-sectional view of an exemplary structure for forming a two-transistor-one-capacitor (2T1C) gain cell memory device after forming an upper level dielectric material layer and an upper level metal interconnect structure according to an embodiment of the present disclosure. Figure 4D yes Figure 4C A top view of an exemplary structure of FIG.

[0016] Figure 5A-5H is a circuit schematic diagram of various configurations of a three-transistor-one-capacitor (3T1C) gain cell memory device according to various embodiments of the present disclosure.

[0017] Figure 5I-5Lis a circuit schematic diagram of various configurations of a two-transistor-one-capacitor (2T1C) gain cell memory device according to various embodiments of the present disclosure.

[0018] Figure 6A-6H are waveform diagrams illustrating the operation of various configurations of a three transistor one capacitor (3T1C) gain cell memory device according to various embodiments of the present disclosure.

[0019] Figure 6I-6L are waveform diagrams illustrating the operation of various configurations of a two-transistor-one-capacitor (2T1C) gain cell memory device according to various embodiments of the present disclosure.

[0020] Figure 7 is a waveform diagram of a bit line voltage as a function of time of a measurement operation and as a function of a stored value of a data bit according to an embodiment of the present disclosure.

[0021] Figure 8 is a graph showing the dependence of the read bit line voltage difference as a function of the time of the measurement operation.

[0022] Fig. 9 is a graph showing the dependence of the drain-to-source current on the source bias voltage when the drain and gate electrodes are biased to turn on the second read transistor according to an embodiment of the present disclosure.

[0023] Fig.10 is a graph comparing the read bit line voltage difference over time for two different source bias voltages.

[0024] Fig.11 is a first flow chart illustrating a sequence of processing steps for operating a gain cell memory device of the present disclosure.

[0025] Fig.12 is a second flow chart illustrating a sequence of processing steps for operating the gain cell memory device of the present disclosure. DETAILED DESCRIPTION

[0026] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0027] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0028] The present invention relates to a gain unit memory device that provides an enhanced read margin and extends the effective charge retention time. Specifically, the enhanced conduction state of the read transistor can be used to perform a sensing operation, wherein the source region of the read transistor can be electrically biased at a voltage that increases the drain current amplitude. The resistive load on the read bit line can be reduced, thereby adjusting the output voltage at the read bit line to distinguish the edge charge state of the signal node at the end of the effective charge retention time. Therefore, the sensitivity of the read transistor can be enhanced only during the read operation to provide low power operation and efficient sensing operation. The gain unit memory device of various embodiments of the present disclosure can extend the effective charge retention time without increasing the size of the gain unit memory device or significantly increasing the power consumption. The gain unit memory device of various embodiments of the present disclosure can reduce the data refresh rate and can reduce power consumption. Various aspects of the present disclosure are now described with reference to the accompanying drawings.

[0029] refer to Figure 1A and Figure 1B , shows an exemplary structure for forming a three-transistor-one-capacitor (3T1C) gain unit memory device after forming field effect transistors (write transistor (WT), first read transistor (RT1), second read transistor (RT2)), contact-level dielectric material layer 601, device contact through-hole structure 612, first metal line-level dielectric material layer 610 and first metal line structure 618. Figure 1B is a top view showing an exemplary arrangement of elements. Figure 1A is a virtual vertical cross-sectional view in which the elements are arbitrarily rearranged into or out of the viewing plane. Thus, although each pair of elements in direct contact with each other may be located in a corresponding local vertical plane parallel to the first horizontal direction hd1, Figure 1A Not all elements in a can lie in the same vertical plane. Therefore, Figure 1A The view may be a combined view of a plurality of vertical cross-sectional views taken on a plurality of vertical planes parallel to the first vertical direction hd1 and laterally offset from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. Figure 1A is a virtual vertical cross-section.

[0030] The exemplary structure includes a substrate 9, which may be a semiconductor substrate, such as a commercially available silicon wafer. A shallow trench isolation structure 720 including a dielectric material such as silicon oxide may be formed on the upper portion of the substrate 9. Suitable doped semiconductor wells, such as a p-type well and an n-type well, may be formed in each region, which may be laterally surrounded by a portion of the shallow trench isolation structure 720. For example, the substrate 9 may have a doping of a first conductivity type, and a doped well 10 having a doping of a second conductivity type may be formed by doping the upper portion of the substrate 9 with a dopant of the second conductivity type. If the first conductivity type is a p-type, the second conductivity type is an n-type, and vice versa.

[0031] Field effect transistors may be formed on the top surface of substrate 9. For example, each field effect transistor may include a source region 732 and a drain region 738, or a pair of source / drain regions 730. "Source / drain region" refers to a region that can be used as a source region or a drain region depending on electrical bias. Semiconductor channel 735 includes a surface portion of substrate 9 extending between each pair of source region 732 and drain region 738 or between a pair of source / drain regions 730.

[0032] Each field effect transistor includes a respective gate structure 750. Each gate structure 750 may include a gate dielectric 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source side metal semiconductor alloy region 742 may be formed on each source region 732, and a drain side metal semiconductor alloy region 748 may be formed on each drain region 738. The metal semiconductor alloy region formed on the source / drain region 730 is referred to herein as a source / drain metal semiconductor alloy region. The field effect transistor may be formed in any configuration known in the art. For example, the field effect transistor may include a planar field effect transistor, a fin field effect transistor, a full ring gate (GAA) field effect transistor, and / or any other type of field effect transistor.

[0033] A contact-level dielectric material layer 601 may be formed above the field effect transistors (WT, RT1, RT2). A device contact via structure 612 may be formed through the contact-level dielectric material layer 601 and contact or provide electrical connection with various components of the semiconductor device on the substrate 9 (e.g., gate electrodes 754, source regions 732, drain regions 738, and source / drain regions 730 of various field effect transistors (WT, RT1, RT2)). A first metal line-level dielectric material layer 610 may be formed above the contact-level dielectric material layer 601. A first metal line structure 618 may be formed in the first metal line-level dielectric material layer 610. Each of the contact-level dielectric material layer 601 and the first metal line-level dielectric material layer 610 may include an interlayer dielectric (ILD) material, such as undoped silicate glass, doped silicate glass, and / or porous or non-porous organic silicate glass. Each of the device contact via structure 612 and the first metal line structure 618 may include at least one conductive material, which may be a combination of a metal liner layer (such as a metal nitride or a metal carbide) and a metal filler material. Each metal liner layer may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal liners and metal filler materials are also within the intended scope of the present disclosure.

[0034] Each of the source / drain region 730 of the write transistor WT, the source region 732 of the second read transistor RT2, the drain region 738 of the first read transistor RT1, the common source / drain region 730 (including a single heavily doped semiconductor region) of the first read transistor RT1 and the second read transistor RT2, and each gate electrode 754 of the write transistor WT, the first read transistor RT1, and the first read transistor RTD2 may be electrically connected to a corresponding device contact through-hole structure 612 and / or may be contacted by a corresponding device contact structure 612. It should be noted that Figure 1A Not shown is the device contact via structure 612 electrically connected to the source region 732 of the second read transistor RT2 .

[0035] According to one aspect of the present disclosure, a subset of the device contact via structures 612 and the first metal line structures 618 within the region of the gain unit memory device electrically connects the first source / drain region 730 of the write transistor WT and the gate electrode 754 of the second read transistor RT2. In one embodiment, the first metal line structure 618 may include a connecting metal line CML extending laterally between the write transistor WT and the second read transistor RT2 and contacting a top surface of the first device contact via structure 612 electrically connected to and overlying the first source / drain region 730 of the write transistor WT, and contacting a top surface of the second device contact via structure 612 electrically connected to and overlying the gate electrode 754 of the second read transistor RT2.

[0036] The illustrated region of the exemplary structure corresponds to the region of the gain unit memory device. It should be understood that the illustrated structure can be repeated to form a two-dimensional array to provide a two-dimensional array of gain unit memory devices. In addition, additional transistors for providing peripheral circuits for the two-dimensional array of gain unit memory devices can be formed on the substrate. Such additional transistors can be configured to provide various control voltages and bias voltages, such as a write word line bias voltage for electrically biasing the gate electrode 754 of the corresponding row of the write transistor WT, a write bit line bias voltage for electrically biasing the second source / drain region 730 of each column of the write transistor WT, a read word line bias voltage for electrically biasing the gate electrode 754 of each row of the first read transistor RT1, a read bit line bias voltage for electrically biasing the drain region 738 of the first read transistor RT1 of each column, and a source bias voltage for electrically biasing the source region 732 of the second read transistor RT2 of each column.

[0037] refer to Figure 1C and Figure 1D , in reference Figure 1A and Figure 1B After the processing steps are described, an exemplary structure for forming a two transistor one capacitor (2T1C) gain cell memory device is shown. Figure 1C and Figure 1D The exemplary structure shown in FIG. 1 may be formed by forming only a single read transistor RT instead of a combination of the first read transistor RT1 and the second read transistor RT2. Figure 1A and Figure 1B The exemplary structure of the three-transistor-one-capacitor (3T1C) gain unit memory device shown in FIG. Figure 1A and Figure 1B The first read transistor RT1 in the Figure 1A and Figure 1B The second read transistor RT2 in the embodiment is relabeled as the read transistor RT to provide Figure 1C and Figure 1DThe exemplary structure shown in .

[0038] refer to Figure 2A and Figure 2B , after forming a second line and via level dielectric material layer 620, a first metal via structure 622, a second metal line structure 628, a via level dielectric layer 630A and a bottom electrode contact via structure 22, an exemplary structure for forming a three transistor one capacitor (3T1C) gain cell memory device is shown. Figure 2B is a top view showing an exemplary arrangement of components. Figure 2A All elements in can be in the same vertical plane, so Figure 2A The view may be a combined view of a plurality of vertical cross-sectional views taken on a plurality of vertical planes that are parallel to the first horizontal direction hd1 and laterally offset from each other along the second horizontal direction hd2. Figure 2A is a virtual vertical cross-section.

[0039] The first metal via structure 622 may be formed at the lower portion of the second line and via level dielectric material layer 620. The second metal line structure 628 may be formed at the upper portion of the second line and via level dielectric material layer 620. The bottom electrode contact via structure 22 may be formed through the via level dielectric layer 630A. Each of the second line and via level dielectric material layer 620 and the via level dielectric layer 630A may include an interlayer dielectric (ILD) material, such as undoped silicate glass, doped silicate glass, and / or porous or non-porous organosilicate glass. Each of the first metal via structure 622, the second metal line structure 628, and the bottom electrode contact via structure 22 may include at least one conductive material, which may be a combination of a metal liner layer (such as a metal nitride or a metal carbide) and a metal filling material. Each metal liner layer may include TiN, TaN, WN, TiC, TaC and WC, and each metal filling material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof and / or combinations thereof. Other suitable metal liners and metal filling materials are also within the intended scope of the present disclosure.

[0040] The set of all metal interconnect structures located below the horizontal plane including the top surface of the via-level dielectric layer 630A is referred to herein as the first metal interconnect structure (612, 618, 622, 628, 22). In one embodiment, the first metal interconnect structure (612, 618, 622, 628, 22) may include a write word line WWL, which is a metal line used as a word line of the write transistor WT. In one embodiment, the first metal interconnect structure (612, 618, 622, 628, 22) may include a read word line RWL, which is a metal line used as a word line of the first read transistor RT1. In one embodiment, the read word line RWL may include a subset of the second metal line structure 628. Each read word line RWL may be electrically connected to the gate electrode 754 within a corresponding row of the first read transistor RT1.

[0041] In one embodiment, a subset of the first metal interconnect structures (612, 618, 622, 628, 22) may include a source bias line SBL. Each source bias line SBL may be connected to a conductive path (in a manner similar to that in FIG. 1 ) embodied as a corresponding subset of the first metal interconnect structures (612, 618, 622, 628, 22) (e.g., a corresponding subset of the device contact via structure 612, the first metal line structure 618, and the first metal via structure 622). Figure 2B The source region 732 (indicated as a dotted line in FIG. 1 ) is electrically connected to the second read transistor RT2 of the corresponding column or the second read transistor RT1 of the corresponding row.

[0042] Although the present disclosure is described using an embodiment in which the write word line WWL, the read word line RWL, and the source bias line SBL are implemented as respective subsets of the first metal interconnect structure (612, 618, 622, 628, 22), each of the write word line WWL, the read word line RWL, and the source bias voltage line SBL may be formed over a subsequently formed capacitor and thus may be formed over a capacitor. Such variations are expressly contemplated herein.

[0043] The bottom electrode contact via structures 22 are subsequently used to provide electrical contact to the first electrode (ie, the bottom electrode) of the respective capacitor. Thus, each bottom electrode contact via structure 22 may be formed in a region where a capacitor is subsequently to be formed.

[0044] Reference Figure 2C and Figure 2D , in reference Figure 2A and Figure 2B After the processing steps are described, an exemplary structure for forming a two transistor one capacitor (2T1C) gain cell memory device is shown. Figure 2C and Figure 2DThe exemplary structure shown in FIG. 1 can be formed from a structure for forming a first read transistor RT1 and a second read transistor RT2 by forming only a single read transistor RT1 instead of a combination of the first read transistor RT1 and the second read transistor RT2. Figure 2A and Figure 2B The exemplary structure of the three-transistor-one-capacitor (3T1C) gain unit memory device shown in FIG. Figure 2A and Figure 2B The first read transistor RT1 in the Figure 2A and Figure 2B The second read transistor RT2 in the embodiment is relabeled as the read transistor RT to provide Figure 2C and Figure 2D The exemplary structure shown in .

[0045] Reference Figure 3A and Figure 3B , shows an exemplary structure for forming a three transistor one capacitor (3T1C) gain cell memory device after forming a capacitor array 30. Thus, a capacitor 30 is formed in each region of the gain cell memory device. Figure 3B is a top view showing an exemplary arrangement of components. Figure 3A All elements in can be in the same vertical plane, so Figure 3A The view may be a combined view of a plurality of vertical cross-sectional views taken on a plurality of vertical planes that are parallel to the first horizontal direction hd1 and laterally offset from each other along the second horizontal direction hd2. Figure 3A is a virtual vertical cross-section.

[0046] A set of material layers may be deposited on the top surface of the via-level dielectric layer 630A. The set of material layers may include, from bottom to top, a bottom electrode material layer, a node dielectric material layer, and a top electrode material layer. Each of the bottom electrode material layer and the top electrode material layer may include and / or may be substantially composed of a metal, a conductive metal compound, and / or a conductive metal oxide.

[0047] Exemplary metals that can be used for the bottom electrode material layer and / or the top electrode material layer include refractory metals (such as tungsten, molybdenum, tantalum and rhenium), and metals with an electronegativity greater than that of molybdenum (such as gold (Au) with an electronegativity of 2.54, tungsten (W) with an electronegativity of 2.36, platinum (Pt) with an electronegativity of 2.28, iridium (Ir) with an electronegativity of 2.20, and osmium (Os) with an electronegativity of 2.20). Exemplary conductive metal compounds that can be used for the bottom electrode material layer and / or the top electrode material layer include tungsten nitride, titanium nitride, tantalum nitride and molybdenum nitride. Exemplary conductive metal oxides that can be used for the bottom electrode material layer and / or the top electrode material layer include, for example, indium tin oxide, fluorine-doped tin oxide, zinc oxide, tungsten oxide (WO3), etc.

[0048] Each of the bottom electrode material layer and the top electrode material layer can be deposited by physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The thickness of each of the bottom electrode material layer and the top electrode material layer can be in the range of 5nm to 40nm, such as 10nm to 25nm, but smaller or larger thicknesses can also be used.

[0049] The node dielectric material layer may include any node dielectric material known in the art. Exemplary dielectric materials that can be used for the node dielectric material include silicon nitride, aluminum oxide, and transition metal oxides having a dielectric constant greater than 10 and / or greater than 20 and / or greater than 30. In one embodiment, the node dielectric material layer may include and / or may be substantially composed of a dielectric material that can provide a dielectric constant greater than 30. Such dielectric materials include perovskite oxide materials, hafnium-based oxides, zirconium-based oxides, and titanium-based oxides. Perovskite oxide materials include barium titanate (BaTiO3), strontium titanate (SrTiO3), lead zirconate titanate (PZT), barium strontium titanate (BST), lead titanate (PbTiO3), and the like. The dielectric constant of the perovskite oxide material in the crystalline phase may be in the range of 30 to 1000. Hafnium-based oxides include hafnium dioxide (HfO2), hafnium oxynitride, and hafnium silicate (HfSiO4), and may have a dielectric constant in the range of 30 to 40 in the crystalline state. Zirconium-based oxides include zirconium dioxide (ZrO2), zirconium oxynitride, and zirconium silicate (ZrSiO4), and may have a dielectric constant in a crystalline state ranging from 30 to 35. Titanium-based oxides include titanium dioxide (TiO2) or titanium oxynitride, and may have a dielectric constant in a range of 80 to 150.

[0050] The node dielectric material layer may be deposited by atomic layer deposition, physical vapor deposition, or chemical vapor deposition. The node dielectric material layer may have a thickness in the range of 2 nm to 10 nm, such as 3 nm to 8 nm, although lesser or greater thicknesses may also be used.

[0051] A photoresist layer (not shown) may be applied over the stack of the bottom electrode material layer, the node dielectric material layer, and the top electrode material layer, and may be photolithographically patterned into a two-dimensional array of photoresist material portions that cover corresponding areas on corresponding bottom electrode contact via structures 22. Typically, in a plan view, the area of ​​each photoresist material portion within the two-dimensional array of photoresist material portions may be in the range of 40% to 90% of the area of ​​each gain unit memory device. For example, the layer stack including the bottom electrode material layer, the node dielectric material layer, and the top electrode material layer may be patterned into a two-dimensional array of capacitors 30 by performing an anisotropic etching process that etches the layer stack using the photoresist material portions as an etching mask.

[0052] Each capacitor 30 includes a first electrode 32 (also referred to as a bottom electrode), a node dielectric 35 (a patterned portion of a node dielectric material layer), and a second electrode 38 (also referred to as a top electrode). The first electrode 32 includes a patterned portion of a bottom electrode material layer. The node dielectric 35 includes a patterned portion of a node dielectric material layer. The second electrode 38 includes a patterned portion of a top electrode material layer.

[0053] Reference Figure 3C and Figure 3D , shows that in reference Figure 3A and Figure 3B The described processing steps are then used to form an exemplary structure of a two transistor one capacitor (2T1C) gain cell memory device. Figure 3C and Figure 3D The exemplary structure shown in FIG. 1 can be formed from a structure for forming a first read transistor RT1 and a second read transistor RT2 by forming only a single read transistor RT1 instead of a combination of the first read transistor RT1 and the second read transistor RT2. Figure 3A and Figure 3B The exemplary structure of the three-transistor-one-capacitor (3T1C) gain unit memory device shown in FIG. Figure 3A and Figure 3B The first read transistor RT1 in the Figure 3A and Figure 3B The second read transistor RT2 in the embodiment is relabeled as the read transistor RT to provide Figure 3C and Figure 3D The exemplary structure shown in .

[0054] Reference Figure 4A and Figure 4B , showing an exemplary structure for forming a three transistor one capacitor (3T1C) gain cell memory device after forming additional dielectric material layers and additional metal interconnect structures. Figure 4B is a top view showing an exemplary arrangement of components. Figure 4A All elements in can be in the same vertical plane, so Figure 4A The view may be a combined view of a plurality of vertical cross-sectional views taken on a plurality of vertical planes that are parallel to the first horizontal direction hd1 and laterally offset from each other along the second horizontal direction hd2. Figure 4A is a virtual vertical cross-section.

[0055] The additional dielectric material layer may include a capacitor-level dielectric layer 630B, a fourth line and via-level dielectric material layer 640, a fifth line and via-level dielectric material segment 650, a sixth line and via-level dielectric material layer 660, and an additional dielectric material layer (not shown). The group of dielectric material layers formed above the via-level dielectric layer 630A is referred to herein as a second dielectric material (630B, 640, 650, 660). A group of all dielectric materials (excluding the node dielectric 35) between the second line and via-level dielectric material layer 620 and the fourth line and via-level dielectric material layer 640 constitutes a third line and via-level dielectric material layer 630. Therefore, the third line and via-level dielectric material layer 630 may include a via-level dielectric layer 630A and a capacitor-level dielectric layer 630B.

[0056] The additional metal interconnect structure is referred to herein as a second metal interconnect structure (28, 632, 638, 642, 648, 658, 662, 668). The second metal interconnect structure (28, 632, 638, 642, 648, 658, 662, 668) may be formed in the second dielectric material layer (630B, 640, 650, 660). The second metal interconnect structure (28, 632, 638, 642, 648, 658, 662, 668) may include a top electrode contact via structure 28 formed in contact with a top surface of a corresponding top electrode 38 and through the capacitor-level dielectric layer 630B, a second metal via structure 632 formed in a lower portion of the third line and via-level dielectric material layer 630, a third metal line structure 638 formed in an upper portion of the third line and via-level dielectric material layer 630, and a third metal line structure 638 formed in a lower portion of the fourth line and via-level dielectric material layer 640. A via structure 642, a fourth metal line structure 648 formed in the upper portion of the fourth line and via-level dielectric material layer 640, a fourth metal via structure (not shown) formed in the lower portion of the fifth line and via-level dielectric material layer 650, a fifth metal line structure 658 formed in the upper portion of the fifth line and via-level dielectric material layer 650, a fifth metal via structure 662 formed in the lower portion of the sixth line and via-level dielectric material layer 660, a sixth metal line structure 668 formed in the upper portion of the sixth line and via-level dielectric material layer 660, and the like.

[0057] The second metal interconnect structure (28, 632, 638, 642, 648, 658, 662, 668) may include a write bit line WBL and a read bit line RBL. Each write bit line WB may be electrically connected to the second source / drain region 730 of the write transistor WT column through a corresponding subset of the second metal interconnect structure (28, 633, 638, 643, 648, 658, 662, and 668) and a corresponding subset of the first metal interconnect structure (612, 618, 622, 628, and 22). Each read bit line RBL may be electrically connected to the drain region 738 of the first read transistor RT1 column through a corresponding subset of the second metal interconnect structure (28, 632, 638, 642, 648, 658, 662, 668) and a corresponding subset of the first metal interconnect structure (612, 618, 622, 628, 22). A set of second metal interconnect structures ( 28 , 632 , 638 , 642 , 648 , 658 , 662 , 668 ) are schematically represented as dashed lines, which serve as components of a conductive path between the read bit line RBL and the drain region 738 of the first read transistor RT1 , and are located between the third metal line structure 638 and the fifth metal line structure 658 .

[0058] In one embodiment, each top electrode 38 may be electrically connected to electrical ground through a corresponding subset of second metal interconnect structures (28, 632, 638, 642, 648, 658, 662, 668) that includes a corresponding top electrode contact via structure 28. A subset of second metal interconnect structures (28, 632, 638, 642, 648, 658, 662, 668) includes an electrically grounded interconnect structure EG.

[0059] Reference Figure 4C and Figure 4D , shows that in reference Figure 4A and Figure 4B The described processing steps are then used to form an exemplary structure of a two transistor one capacitor (2T1C) gain cell memory device. Figure 4C and Figure 4D The exemplary structure shown in FIG. 1 can be formed from a structure for forming a first read transistor RT1 and a second read transistor RT2 by forming only a single read transistor RT1 instead of a combination of the first read transistor RT1 and the second read transistor RT2. Figure 4A and Figure 4B The exemplary structure of the three-transistor-one-capacitor (3T1C) gain unit memory device shown in FIG. Figure 4A and Figure 4B The first read transistor RT1 in the Figure 4A and Figure 4B The second read transistor RT2 in the embodiment is relabeled as the read transistor RT to provide Figure 4C and Figure 4DThe exemplary structure shown in .

[0060] Figure 5A-5H 1 is a circuit diagram of various configurations of a three-transistor-one-capacitor (3T1C) gain unit memory device MD according to various embodiments of the present disclosure. Typically, each of the write transistor WT, the first read transistor RT1, and the second read transistor RT2 in the gain unit memory device MD may include a p-type field effect transistor (PFET) or an n-type field effect transistor (NFET). Figure 5A-5H The various configurations shown in correspond to eight combinations, wherein each of the write transistor WT, the first read transistor RT1, and the second read transistor RT2 in the gain unit memory device MD may include a PFET or an NFET. Table 1 below provides combinations of various types of field effect transistors in eight configurations corresponding to the eight combinations.

[0061] Table 1: Types of field effect transistors in various configurations of 3T1C gain cell memory devices of various embodiments.

[0062]

[0063] Generally, the embodiment gain unit memory device of the present disclosure may include a series connection of a write transistor WT, a first read transistor RT1, and a second read transistor RT2, wherein a common source / drain region is shared between the first read transistor RT1 and the second read transistor RT2. A signal node SN is formed by electrically connecting the first source / drain region of the write transistor WT to the gate electrode of the second read transistor RT2 and the first electrode of the capacitor (such as the bottom electrode 32). The second electrode of the capacitor may be electrically grounded. The second source / drain region of the write transistor WT may be electrically connected to the write bit line WBL. The gate of the write transistor WT may be electrically connected to the write word line WWL. The drain region of the first read transistor RT1 may be electrically connected to the read bit line RBL. The gate of the first read transistor RT1 may be electrically connected to the read word line. The source region of the second read transistor RT2 may be electrically connected to the source bias line SBL. The gain unit memory device MD may include a peripheral circuit PC configured to electrically bias each of the write word line WWL, the write bit line WBL, the read bit line RBL, the read word line RWL, and the source bias line SBL.

[0064] Figure 5I-5L1 is a circuit diagram of various configurations of a two-transistor-one-capacitor (2T1C) gain unit memory device MD according to various embodiments of the present disclosure. By removing the first read transistor RT1, by removing the write bit line WBL, and by connecting the read bit line RBL directly to the drain region of the read transistor RT (which corresponds to the second read transistor RT2 of the three-transistor-one-capacitor (3T1C) gain unit memory device), the reference Figure 5A-5H Various types of three-transistor-one-capacitor (3T1C) gain unit memory devices MD are derived from the various types of two-transistor-one-capacitor (2T1C) gain unit memory devices MD described.

[0065] The operation of the two-transistor-one-capacitor (2T1C) gain unit memory device MD may be the same as the three-transistor-one-capacitor (3T1C) gain unit memory device MD, except that the drain voltage of the read transistor RT (i.e., the voltage of the drain region of the read transistor RT) is directly controlled by the read bit line RBL that is electrically short-circuited with the drain region of the read transistor RT. In other words, the voltage of the drain region of the second read transistor RT2 in the above 3T1C gain unit memory element MD is controlled by the read bit line RBL that is electrically short-circuited with the drain region of the read transistor RT. FIG. 5I to FIG. 5L The 2T1C gain cell shown is replicated during operation of memory element MD.

[0066] In some embodiments, the source bias line (SBL) voltage range is optimized to enhance memory operation flexibility. Specifically, for a configuration using an n-type field effect transistor (NFET) as the second read transistor RT2, the SBL voltage can be adjusted to 0V±ΔV. Conversely, for a configuration using a p-type field effect transistor (PFET) for RT2, the SBL voltage can be set to Vdd±ΔV. This adjustment allows maximizing the voltage difference (ΔV) between the read bit line (RBL) states "0" and "1" within a given read access time, thereby enhancing the distinguishability between stored data states.

[0067] Figure 5I-5L The various configurations shown in correspond to four combinations, where each of the write transistor WT and the read transistor RT in the gain unit memory device MD may include a PFET or an NFET. Table 2 below provides combinations of various types of field effect transistors in four configurations corresponding to the four combinations.

[0068] Table 2: Types of field effect transistors in various configurations of 2T1C gain cell memory devices of various embodiments.

[0069]

[0070] Figure 6A-6H2 are waveform diagrams of the operation of various configurations of a three-transistor-one-capacitor (3T1C) gain unit memory device MD according to various embodiments of the present disclosure.

[0071] In the operational dynamics of a gain cell memory device, the read bit line (RBL) exhibits a critical behavior that distinguishes the data state being read. Specifically, during a read operation, with the read word line (RWL) activated, the RBL is designed to discharge from the supply voltage Vdd to 0V to achieve a read "1" state, indicating the presence of a high data state. Conversely, for a read "0" state, the RBL remains at the supply voltage Vdd, indicating no discharge and, therefore, a low data state. This distinction in RBL voltage levels during a read operation forms the basis for accurately sensing and distinguishing between "1" and "0" data bits stored in the memory device.

[0072] For each gain unit memory device MD including a write transistor WT and a series connection of a first read transistor RT1 and a second read transistor RT2, a read bit line RBL may be connected to a drain region 738 of the first read transistor RT1 and a source bias line SBL may be connected to a source region 732 of the second read transistor RT2. Each gain unit memory device MD includes a signal node SN at which a first electrode 32 of a capacitor 30 may be electrically connected to a first source / drain region 730 of the write transistor WT and a gate electrode 754 of the second read transistor RT2.

[0073] A write operation can be performed to encode a data bit in the signal node SN by applying a write read bit line bias voltage to the second source / drain region 730 of the write transistor WT and by turning on the write transistor WT when the source bias line SBL is electrically biased with a first source bias voltage (referred to herein as a normal source bias voltage).

[0074] Table 3 below provides Figure 5A-5H The various embodiment configurations shown in Figure 6A-6H The relationship between various operation voltages of the write word line WWL and the write bit line WBL during the write operation and the various embodiment configurations described in the . The write bit line "1" voltage refers to the bias voltage at the write bit line WBL when writing "1" at the signal node, and the write bit line "0" voltage refers to the bias voltage at the write bit line WBL when writing "0" at the signal node.

[0075] Table 3: Operating voltages of the write word line WWL and write bit line WBL for various configurations of the gain cell memory device of various embodiments.

[0076]

[0077] The read operation can be performed in the following manner: precharging the read bit line RBL with a precharge bias voltage, applying a second source bias voltage (referred to herein as a current enhancement source bias voltage Vsb) different from the first source bias voltage (i.e., the normal source bias voltage) to the source bias voltage line SBL, and turning on the first read transistor RT1. Figure 6A-6H The voltage responses of the read bit line RBL under an ideal read "1" condition (ie, an ideal condition for reading a stored data bit "1") and an ideal read "0" condition are shown, respectively.

[0078] In order to sense the data stored at the signal node SN, the magnitude of the difference between the precharge bias voltage and the second source bias voltage (e.g., the current enhancement source bias voltage Vsb) is greater than the magnitude of the difference between the precharge bias signal and the first source bias signal (e.g., the normal source bias voltage). In one embodiment, the first of the precharge bias voltage and the first source bias voltage (e.g., the normal source bias voltage) is the circuit power supply voltage Vdd, and the second of the precharge bias voltage and the first source bias voltage (e.g., the normal source bias voltage) is the electrical ground voltage. In an embodiment in which an n-type field effect transistor is used for the second read transistor RT2, the precharge bias voltage may be the circuit power supply voltage Vdd, and the first source bias voltage may be the ground voltage. In an embodiment in which a p-type field effect transistor is used for the second read transistor RT2, the precharge bias voltage may be the electrical ground voltage, and the first source bias voltage may be the circuit power supply voltage Vdd.

[0079] In one embodiment, a second source bias voltage (e.g., current enhancement source bias voltage Vsb) is applied to the first source bias voltage line SBL by applying a current enhancement source bias voltage pulse; the first read transistor RT1 is turned on by applying a gate voltage pulse to the gate electrode 754 of the first read transistor RT1; and the current enhancement source bias voltage pulse has the same duration as the gate voltage pulse. In one embodiment, the gain unit memory device MD includes a sense amplifier electrically connected to the read bit line RBL and a data latch electrically coupled to the output of the sense amplifier; and the first read transistor RT1 is turned on by applying a gate voltage pulse to the gate electrode 754 of the first read transistor RT1. The output of the sense amplifier can be captured at a time point when the gate voltage pulse is turned off using the data latch.

[0080] Table 4 below provides Figure 5A-5H The various configurations shown in Figure 6A-6H The relationships between the various configurations described in and the various operating voltages of the read word line RWL, the read bit line RBL, and the source bias line SBL during a read operation.

[0081] Table 4: Operating voltages of the read word line RWL, read bit line RBL, and source bias line SBL during read operations of various configurations of the 3T1C gain cell memory device of various embodiments.

[0082]

[0083] Figure 6A-6L 2 are waveform diagrams illustrating the operation of various configurations of a two-transistor-one-capacitor (2T1C) gain unit memory device MD according to various embodiments of the present disclosure.

[0084] For each gain unit memory device MD including a write transistor WT and a read transistor RT, a read bit line RBL may be connected to a drain region 738 in the read transistor RT, and a source bias line SBL may be connected to a source region 732 of the read transistor RT. Each gain unit memory device MD includes a signal node SN at which a first electrode 32 of a capacitor 30 may be electrically connected to a first source / drain region 730 of the write transistor WT and a gate electrode 754 of the read transistor RT.

[0085] A write operation can be performed by applying a write read bit line bias voltage to the second source / drain region 730 of the write transistor WT and turning on the write transistor WT while the source bias line SBL is electrically biased at a first source bias voltage (referred to herein as a normal source bias voltage) to encode a data bit in the signal node SN.

[0086] Table 5 below provides Figure 5I-5L The various embodiment configurations shown in Figure 6I-6L The relationship between various operation voltages of the write word line WWL and the write bit line WBL during the write operation and the various embodiment configurations described in the . The write bit line "1" voltage refers to the bias voltage at the write bit line WBL when writing "1" at the signal node, and the write bit line "0" voltage refers to the bias voltage at the write bit line WBL when writing "0" at the signal node.

[0087] Table 5: Operating voltages of the write word line WWL and write bit line WBL for various configurations of the gain cell memory device of various embodiments.

[0088]

[0089] The read operation can be performed in the following manner: precharging the read bit line RBL with a precharge bias voltage, applying a second source bias voltage (referred to herein as a current enhancement source bias voltage Vsb) different from the first source bias voltage (i.e., the normal source bias voltage) to the source bias voltage line SBL, and disconnecting the precharge bias voltage and electrically floating the read bit line RBL. Figure 6I-6LThe voltage responses of the read bit line RBL under an ideal read "1" condition (ie, an ideal condition for reading a stored data bit "1") and an ideal read "0" condition are shown, respectively.

[0090] Additionally, in a two-transistor-one-capacitor (2T1C) gain-unit memory device configuration, the read operation can be alternately triggered by switching the SBL voltage. Fig.5I In the corresponding configuration, both RBL and SBL can be precharged to Vdd. During the read operation, SBL is switched from Vdd to 0V. This operation causes RBL to discharge to 0V when reading the "1" state, or remain at Vdd when reading the "0" state. By fine-tuning the SBL level (0V±ΔV) during the read operation, the discharge time of RBL can be optimized, thereby maximizing the voltage difference between the RBL states "0" and "1", improving the efficiency and accuracy of the read operation. Figure 5J , Figure 5K and Figure 5L Each of the two transistor one capacitor (2T1C) gain cell memory device configurations shown in FIG. 1 performs the same type of modification for the read operation.

[0091] In order to sense the data stored at the signal node SN, the magnitude of the difference between the precharge bias voltage and the second source bias voltage (e.g., the current enhancement source bias voltage Vsb) is greater than the magnitude of the difference between the precharge bias signal and the first source bias signal (e.g., the normal source bias voltage). In one embodiment, the first of the precharge bias voltage and the first source bias voltage (e.g., the normal source bias voltage) is the circuit power supply voltage Vdd, and the second of the precharge bias voltage and the first source bias voltage (e.g., the normal source bias voltage). In an embodiment in which an n-type field effect transistor is used for the read transistor RT, the precharge bias voltage may be the circuit power supply voltage Vdd, and the first source bias voltage may be an electrical ground voltage. In an embodiment in which a p-type field effect transistor is used for the read transistor RT, the precharge bias voltage may be an electrical ground voltage, and the first source bias voltage may be the circuit power supply voltage Vdd.

[0092] In one embodiment, a second source bias voltage (e.g., current enhancement source bias voltage Vsb) is applied to the first source bias voltage line SBL by applying a current enhancement source bias voltage pulse; and the current enhancement source bias pulse has a duration that is the same as the duration of the step of electrically floating the read bit line RBL. In one embodiment, the gain unit memory device MD includes a sense amplifier electrically connected to the read bit line RBL and a data latch electrically coupled to the output of the sense amplifier. The data latch can be used to capture the output of the sense amplifier at a point in time when the read operation is terminated. The termination of the read operation coincides with the time when the electrically floating state of the read bit line RBL is terminated.

[0093] Table 6 below provides Figure 5I-5L The various configurations shown in Figure 6I-6L The relationships between the various configurations described in and the various operating voltages of the read word line RWL, the read bit line RBL, and the source bias line SBL during a read operation.

[0094] Table 6: Operating voltages of the read word line RWL, read bit line RBL, and source bias line SBL during a read operation for various configurations of the 2T1C gain cell memory device of various embodiments.

[0095]

[0096] Common Reference Figure 1A-Figure 4B and Figure 5A-5H , the gain unit memory device MD of various embodiments may include: a write transistor WT located on a substrate 9; a series connection of a first read transistor RT1 and a second read transistor RT2 located on the substrate 9; a capacitor 30 having a first electrode 32, a node dielectric 35, and a second electrode 38, wherein the first electrode 32 is electrically connected to a first source / drain region 730 of the write transistor WT and a gate electrode 754 of the second read transistor RT2; and a peripheral circuit PC, which is configured to electrically bias the source region 732 of the second read transistor RT2 with a normal source bias voltage when the first read transistor RT1 is turned off, and to electrically bias the source region 732 of the second read transistor RT2 to a current enhancement source bias voltage Vsb when the first read transistor RT1 is turned on during a read operation, and the current enhancement source bias voltage Vsb increases the on-current of the second read transistor RT2.

[0097] The gain unit memory device MD may include a read bit line RBL electrically connected to a drain region 738 of a first read transistor RT1. The peripheral circuit PC is configured to apply a precharge bias voltage to the read bit line RBL before turning on the second read transistor RT2 during a read operation before turning on the first read transistor RT1. In one embodiment, the first of the precharge bias voltage and the normal source bias voltage is a circuit power supply voltage Vdd; the second of the precharge bias voltage and the normal source bias voltage is a ground voltage. In one embodiment, the current enhancement source bias voltage Vsb is equal to the sum of (1+α) times the normal source bias voltage plus -α times the precharge bias voltage, where the value of α is in the range of 0.01 to 0.30, for example, 0.03 to 0.15. The circuit power supply voltage Vdd may be in the range of 1.0V to 20V, for example, 2V to 10V, but lower and higher voltages may also be used.

[0098] In one embodiment, the peripheral circuit PC is configured to apply a read gate pulse to the gate electrode 754 of the first read transistor RT1 for a first duration Dt during a read operation.

[0099] Common Reference Figure 1A-Figure 6L According to various embodiments of the present disclosure, a gain unit memory device is provided, which includes: a write transistor WT located on a substrate 9; a read transistor (RT2 or RT) located on the substrate 9; a capacitor 30 having a first electrode 32, a node dielectric 35, and a second electrode 38, wherein the first electrode 32 is electrically connected to a first source / drain region 730 of the write transistor WT and a gate electrode 754 of the read transistor (RT2 or RT); and a peripheral circuit PC, which is configured to electrically bias the source region 732 of the read transistor (RT2 or RT) with a normal source bias voltage when the gain unit memory device is not in a read operation, and to electrically bias the source region 732 of the second read transistor (RT 2 or RT) to a current enhancement source bias voltage that increases the on-current of the second read transistor (RT 2 or RT) when the gain unit memory device is in a read operation.

[0100] Reference Figure 7 , a waveform diagram of the bit line voltage as a function of the time of the measurement operation and as a function of the stored value of the data bit according to an embodiment of the present disclosure. Figure 6A-6L As shown, four measurements can be made using a sequence of four read operations. Figure 7 Indicated in Fig. 6A , Figure 6B , Fig. 6E , Fig. 6F , Fig.6I and Figure 6K The voltages varying with time during a read operation at the read bit line RBL of the configurations shown are configurations in which the second read transistor RT2 is an NFET. The precharge voltage (i.e., the circuit power supply voltage Vdd) changes to 0V with different time constants according to the current flowing between the common source / drain region of the two read transistors (RT1, RT2) and the source region of the second read transistor RT2. The larger the amount of charge stored at the signal node SN, the higher the current through the second read transistor RT2, and the faster the voltage at the read bit line RBL drops.

[0101] Typically, the amount of charge stored in the signal node SN when programming "1" decreases over time, so it becomes more difficult to sense the state of "1" in a timely manner. Similarly, due to the accumulation of stray charges, such as leakage current in the signal node, the state of no charge in the signal node SN when programming "0" may deteriorate over time. This drift in the amount of charge stored in the signal node SN is reflected in the change in the voltage at the read bit line RBL over time. The four different time points at which the read operation is initiated are marked as T0, T1, T2, and T3. The initial time point T0 corresponds to the first time point at which the read operation is initiated, and can be offset in time from the termination of the programming operation of the semiconductor circuit including the gain unit memory device by less than 10 clock cycles, such as 1-4 clock cycles. The first time point T1 is offset in time from the initial time point T0 by about 25% of the half-life, which is the time required for the stored charge amount to decay from the full charge level to 50% of the full charge level. The second time point T2 is offset in time from the initial time point T0 by about 50% of the half-life. The third time point T3 is deviated in time from the initial time point T0 by about 75% of the half-life.

[0102] for Figure 6C , Fig.6D , Figure 6G , Figure 6H , Figure 6J and Figure 6L In the configuration shown, the precharge voltage is 0 V, and the waveform of the time-dependent voltage at the read bit line RBL can have an inverted configuration. Specifically, if the stored data bit at the signal node SN is "0", the precharge voltage of 0 V is converted to the circuit power supply voltage Vdd, and if the stored data bit at the signal node SN is "1", it is maintained at 0 V and gradually drifts upward.

[0103] The voltage at the read bit line RBL may be sensed after the duration of the read operation (i.e., the first duration Dt). After the first duration Dt of four read operations for sensing the "1" state and sensing the "0" state, each voltage level at the read bit line RBL sensed by the sense amplifier is Figure 7 The star mark in the figure indicates that the voltage difference between the sensing voltage of the "0" state (ie, SN=0) and the sensing voltage of the "1" state (ie, SN="1") of the read operation is referred to herein as the read bit line voltage difference DV_RBL. Figure 7 Four read bit line voltage differences DV_RBL corresponding to four different time points of starting a read operation are shown in FIG. The magnitude of the read bit line voltage difference DV_RBL decreases over time. Figure 8The time dependency of the magnitude of the read bit line voltage difference DV_RBL is shown in . As the magnitude of the read bit line voltage difference DV_RBL decreases over time, it becomes increasingly difficult to distinguish between the "1" and "0" states in time.

[0104] Fig. 9 is a graph showing the dependence of the drain-to-source current on the source bias voltage when the drain and gate electrodes 754 are biased to turn on the second read transistor RT2. Fig. 9 1 shows the transistor characteristics of the second read transistor RT2 when the second read transistor RT2 is an NFET. In an embodiment where a 0V bias voltage is applied to the source bias voltage line SBL, the gate-source bias voltage that determines the current between the drain region and the source region of the second read transistor RT2 is the same as the voltage V_g at the gate electrode of the second read transistor RT2, which is determined by the amount of charge present at the signal node. The IV curve under this condition is represented by the dotted curve marked as "Ids at Vsb = 0".

[0105] According to one aspect of the present disclosure, applying a current enhancement source bias voltage Vsb less than 0V to the source bias line SBL has the effect of increasing the source-gate bias voltage from V_g to V_g+|Vsb|. In this case, the IV curve is represented by the solid line labeled "Ids at Vsb<0". Therefore, applying a current enhancement source bias voltage Vsb to the source bias line SBL has the effect of increasing the gate-source bias voltage by |Vsb|.

[0106] In one embodiment, the magnitude of the current enhancement source bias voltage Vsb can be determined to maximize the difference in drain-to-source current Ids at two threshold voltages. The first threshold voltage is the minimum voltage at the signal node SN for unambiguously sensing the "0" state, and the second threshold voltage is the maximum voltage at the signal node SN for unambiguously sensing the "1" state. The first threshold voltage can be expressed as Vdd / 2-g / 2, and the second threshold voltage can be expressed as Vdd / 2+g / 2. The difference between the first threshold voltage and the second threshold voltage is g, referred to herein as the sensing margin gate voltage. The sensing margin gate voltage g can be in the range of 5% to 30% of the circuit power supply voltage Vdd, for example 10% to 20%.

[0107] exist Fig. 9In the example shown, under the condition of Vsb = 0V, the difference between the drain-to-source current Ids at the two threshold voltages is represented by DI_0. Under the condition of Vsb < 0V, the difference between the drain-to-source current Ids at the two threshold voltages is represented by DI_1. According to one aspect of the present disclosure, the value of the current enhancement source bias voltage Vsb can be selected so that DI_1 (i.e., the difference between the drain-to-source current Ids at the two threshold voltages under the condition of Vsb < 0V) is maximized.

[0108] Reference Fig.10 , shows the effect of using the current enhancement source bias voltage Vsb of various embodiments. As described above, during each read operation, the current enhancement source bias voltage Vsb can be applied as a negative voltage of the second read transistor RT2 including an NFET, or as a voltage higher than the circuit power supply voltage Vdd of the second read transistor RT2 as a PFET. By using the reference Fig. 9 The method described selects the value of the current enhancement source bias voltage Vsb, compared with the read operation using 0V or the circuit power supply voltage Vdd as the bias voltage of the source bias line SBL, referring to Figure 7 and Figure 8 The discussed read bit line voltage difference DV_RBL can be increased. Therefore, the circuits of various embodiments provide a wider sensing window for the read operation.

[0109] Common Reference Figure 6A-6L and Fig. 9 , the first duration Dt and the current enhancement source bias voltage Vsb can be selected so that the voltage at the read bit line RBL at the time point when the first duration Dt ends is between the target range. Under the condition that the gate electrode 754 of the second read transistor RT2 is at an intermediate voltage, the target range is selected to be between the first voltage and the second voltage. The intermediate voltage is equal to the sum of 0.5 times the precharge bias voltage and 0.5 times the normal source bias voltage (such as Vdd / 2). The first voltage is equal to the sum of 0.4 times the precharge bias voltage and 0.6 times the normal source bias voltage, and the second voltage is equal to the sum of 0.6 times the precharge bias voltage and 0.4 times the normal source bias voltage. In other words, when the gate voltage of the second read transistor is 0.5 times the circuit power supply voltage Vdd, the selected values ​​of the first duration Dt and the current enhancement source bias voltage Vsb make the output voltage at the read bit line RBL in the range of 0.4 times to 0.6 times the circuit power supply voltage Vdd.

[0110] In one embodiment, the current enhancement source bias voltage Vsb is applied with a current enhancement source bias pulse having the same duration as the read gate pulse. In one embodiment, the peripheral circuit PC includes a sense amplifier electrically connected to the read bit line RBL; and the peripheral circuit PC includes a data latch configured to store the output of the sense amplifier at a time point when the read gate pulse is turned off.

[0111] Common Reference Figure 1A-Figure 5H , Figure 6A-6H and Figure 7-10 , a gain unit memory device MD is provided, which includes: a write transistor WT located on a substrate 9; a series connection of a first read transistor RT1 and a second read transistor RT2 located on the substrate 9; a capacitor 30 having a first electrode 32, a node dielectric 35 and a second electrode 38, and formed in a dielectric material layer (610, 610, 620, 630, 640, 650, 660) covering the write transistor WT and the series connection; a metal interconnect structure formed in the dielectric material layer (610, 610, 620, 630, 640, 650, 660) providing a first source / drain region 32, a node dielectric 35 and a second electrode 38 connected to the first electrode 32, the write transistor WT and the series connection; 730 is electrically connected to the gate electrode 754 of the second read transistor RT2; a read bit line RBL, which is electrically connected to the drain region 738 of the first read transistor RT1; a source bias line SBL, which is electrically connected to the source region 732 of the second read transistor RT2; and a peripheral circuit PC, which is configured to electrically bias the source region 732 of the second read transistor RT2 with a normal source bias voltage when the first read transistor RT1 is turned off during a read operation, and to electrically bias the second read transistor RT2 with a current enhancement source bias voltage Vsb when the first read transistor RT1 is turned on, and the current enhancement source bias voltage Vsb increases the on-current of the second read transistor RT2.

[0112] In one embodiment, the peripheral circuit PC is configured to apply a precharge bias voltage to the read bit line RBL before turning on the second read transistor RT2 during a read operation before turning on the first read transistor RT1; the first of the precharge bias voltage and the normal source bias voltage is the circuit power supply voltage Vdd; the second of the precharge bias voltage and the normal source bias voltage is the ground voltage. In one embodiment, the current enhancement source bias voltage Vsb is equal to the sum of (1+α) times the normal source bias voltage plus -α times the precharge bias voltage, where the value of α is in the range of 0.01 to 0.30.

[0113] In one embodiment, the second read transistor RT2 includes an n-type field effect transistor; the normal source bias voltage is 0V; and the current enhancement source bias voltage Vsb is a negative voltage. In one embodiment, the second read transistor RT2 includes a p-type field effect transistor; the normal source bias voltage is a positive circuit power supply voltage Vdd; and the current enhancement source bias voltage Vsb is a positive voltage higher than the positive circuit power supply voltage Vdd.

[0114] In one embodiment, the write transistor WT comprises a p-type field effect transistor; and the gate electrode 754 of the write transistor WT is electrically biased at the positive circuit supply voltage Vdd, except during a write operation, during which the write transistor WT is electrically biased at 0 V. In one embodiment, the write transistor WT comprises an n-type field effect transistor; and the gate electrode 754 of the write transistor WT is electrically biased at 0 V, except during a write operation, during which the gate electrode 754 of the write transistor WT is electrically biased to the positive circuit supply voltage Vdd.

[0115] In one embodiment, the substrate 9 includes a semiconductor substrate; the write transistor WT, the second read transistor RT2 and the first read transistor RT1 include field effect transistors located on the top surface of the semiconductor substrate; the capacitor 30 includes a metal insulator metal capacitor formed in a dielectric material layer (610, 610, 620, 630, 640, 650, 660) covering the field effect transistor; the gain unit memory device MD includes a set of metal interconnect structures that provide electrical contact with the first electrode 32, the first source / drain region 730 of the write transistor WT and the gate electrode 754 of the second read transistor RT2, and are formed in the dielectric material layer (610, 610, 620, 630, 640, 650, 660).

[0116] Common Reference Figure 1A-Figure 6L According to various embodiments of the present disclosure, a gain unit memory device is provided, which includes: a write transistor WT located on a substrate 9; a read transistor (RT2 or RT) located on the substrate 9; a capacitor 30 having a first electrode 32, a node dielectric 35, and a second electrode 38, wherein the first electrode 32 is electrically connected to a first source / drain region 730 of the write transistor WT and a gate electrode 754 of the read transistor (RT2 or RT); and a peripheral circuit PC, which is configured to electrically bias the source region 732 of the read transistor (RT2 or RT) with a normal source bias voltage when the gain unit memory device is not in a read operation, and to electrically bias the source region 732 of the read transistor (RT2 or RT) to a current enhancement source bias voltage that increases the on-current of the second read transistor (RT 2 or RT) when the gain unit memory device is in a read operation.

[0117] In one embodiment, the gain unit memory device includes a read bit line RBL configured to electrically bias the drain region 738 of the read transistor (RT2 or RT) during an initial step of a read operation. In one embodiment, the peripheral circuit PC is configured to apply a precharge bias voltage to the read bit line RBL before turning on the additional read transistor RT1. In one embodiment, the first of the precharge bias voltage and the normal source bias voltage is a circuit power supply voltage; the second of the precharge bias voltage and the normal source bias voltage is a ground voltage. In one embodiment, the current enhancement source bias voltage is equal to the sum of (1+α) times the normal source bias voltage plus -α times the precharge bias voltage, where the value of α is in the range of 0.01 to 0.30.

[0118] In one embodiment, the gain unit memory device includes an additional read transistor RT1, which is connected in series to the drain region 738 of the read transistor (RT2 or RT). The drain region 738 of the additional read transistor RT1 is electrically shorted to the read bit line RBL. In one embodiment, the peripheral circuit PC is configured to apply a read gate pulse to the gate electrode 754 of the additional read transistor RT1 for a first duration during a read operation. In one embodiment, the first duration and the current enhancement source bias voltage are selected so that under the condition that the gate electrode 754 of the read transistor (RT2 or RT) is at a voltage equal to 0.5 times the precharge bias voltage and 0.5 times the normal source bias voltage, at the time point when the first duration ends, the voltage at the read bit line RBL is between the first voltage and the second voltage; the first voltage is equal to the sum of 0.4 times the precharge bias voltage and 0.6 times the normal source bias voltage; the second voltage is equal to the sum of 0.6 times the precharge bias voltage and 0.4 times the normal source bias voltage. In one embodiment, the current enhancement source bias voltage is applied in a current enhancement source bias pulse having the same duration as the read gate pulse.

[0119] In one embodiment, the read bit line RBL is electrically shorted to the drain region 738 of the read transistor (RT2 or RT). In one embodiment, the peripheral circuit PC is configured to: maintain the read bit line RBL in a high impedance state when the gain unit memory device is not in a read operation; apply a precharge bias voltage to the read bit line RBL during a precharge step of the read operation; and measure the voltage at the read bit line RBL after a first duration after the precharge step.

[0120] According to another aspect of the present invention, a gain unit memory device is provided, which includes: a write transistor WT located on a substrate 9; a read transistor (RT2 or RT) located on the substrate 9; a capacitor 30 having a first electrode 32, a node dielectric 35, and a second electrode 38, the first electrode 32 including a signal node electrically connected to a first source / drain region 730 of the write transistor WT and a gate electrode 754 of the read transistor (RT2 or RT), wherein the capacitor 30 is embedded in a dielectric material layer covering the write transistor WT and the read transistor; a metal interconnect structure (612, 618, 622, 628, 22, 28, 632, 638, 642, 648, 658, 662, 668) located in the dielectric material layer (601, 610, 620, 630, 640, 650 , 660), and providing electrical connections to the first electrode 32, the second source / drain region 730 of the write transistor WT and the source region 732 of the read transistor (RT2 or RT); a read bit line RBL, configured to electrically bias the drain region 738 of the read transistor (RT2 or RT); a source bias line SBL, which is electrically connected to the source region 732 of the read transistor (RT2 or RT); and a peripheral circuit PC, which is configured to electrically bias the source region 732 of the read transistor (RT2 or RT) with a normal source bias voltage when the gain unit memory device is not in a read operation, and to electrically bias the source region 732 of the read transistor (RT2 or RT) with a current enhancement source bias voltage that increases the on-current of the second read transistor (RT2 or RT) when the gain unit memory device is in a read operation.

[0121] In one embodiment, the peripheral circuit PC is configured to apply a precharge bias voltage to the read bit line RBL during an initial step of a read operation; the first of the precharge bias voltage and the normal source bias voltage is a circuit power supply voltage; the second of the precharge bias voltage and the normal source bias voltage is a ground voltage. In one embodiment, the current enhancement source bias voltage is equal to the sum of (1+α) times the normal source bias voltage plus -α times the precharge bias voltage, where the value of α is in the range of 0.01 to 0.30. In one embodiment, the peripheral circuit PC includes a sense amplifier electrically connected to the read bit line RBL; and the peripheral circuit PC includes a data latch configured to store the output of the sense amplifier at a point in time when the read operation is terminated.

[0122] Fig.11 is a flow chart illustrating a sequence of processing steps for operating a gain cell memory device MD of various embodiments.

[0123] Refer to step 1110 and Figure 1A-Figure 5L, a gain unit memory device MD is provided. The gain unit memory device MD includes a write transistor WT located on a substrate 9, a read transistor (RT or RT2) located on the substrate 9, a capacitor 30 having a first electrode 32, a node dielectric 35, and a second electrode 38, a read bit line RBL, and a source bias line SBL, the first electrode 32 including a signal node electrically connected to a first source / drain region 730 of the write transistor WT and a gate electrode 754 of the read transistor (RT or RT2), the read bit line RBL is configured to electrically bias the drain region 738 of the read transistor (RT or RT2), which may be by being electrically shorted to the drain region 738, or by an additional read transistor RT1, and a source bias line SBL, which is connected to the source region 732 of the second read transistor RT2.

[0124] Refer to step 1120 and Figure 6A-6L , a write operation can be performed, which encodes the data bit in the signal node SN by applying a write read bit line bias voltage to the second source / drain region 730 of the write transistor WT and turning on the write transistor WT while the source bias line SBL is electrically biased with a first source bias voltage (e.g., a normal source bias voltage).

[0125] Refer to step 1130 and Figure 6A-6L , Figure 7 , Figure 8 , Fig. 9 and Fig.10 , a read operation can be performed by precharging the read bit line RBL with a precharge bias voltage, by applying a second source bias voltage (e.g., a current enhancement source bias voltage Vsb) different from the first source bias voltage (e.g., a normal source bias voltage) to the source bias line SBL, and by sensing the voltage at the drain region 738 of the read transistor (RT or RT2).

[0126] Fig.12 is a flow chart illustrating a sequence of processing steps for operating a gain cell memory device MD of various embodiments.

[0127] Refer to step 1210 and Figure 1A-Figure 5H, providing a gain unit memory device MD. The gain unit memory device MD includes a write transistor WT located on a substrate 9, a series connection of a first read transistor RT1 and a second read transistor RT2 located on the substrate 9, a capacitor 30 having a first electrode 32, a node dielectric 35, and a second electrode 38, a read bit line RBL connected to a drain region 738 of the first read transistor RT1, and a source bias line SBL connected to a source region 732 of the second read transistor RT2, wherein the gain unit memory device MD includes a signal node SN at which the first electrode 32 is electrically connected to a first source / drain region 730 of the write transistor WT and the second read transistor RT2 has a gate 754.

[0128] Refer to step 1220 and Figure 6A-6H , a write operation can be performed, which encodes the data bit in the signal node SN by applying a write read bit line bias voltage to the second source / drain region 730 of the write transistor WT and turning on the write transistor WT while the source bias line SBL is electrically biased with a first source bias voltage (e.g., a normal source bias voltage).

[0129] Refer to step 1230 and Figure 6A-6H , Figure 7 , Figure 8 , Fig. 9 and Fig.10 , a read operation can be performed in the following manner: precharging the read bit line RBL with a precharge bias voltage, applying a second source bias voltage (e.g., a current enhancement source bias voltage Vsb) different from the first source bias voltage (e.g., a normal source bias voltage) to the source bias voltage line SBL, and turning on the first read transistor RT1.

[0130] Various embodiments of the present disclosure may provide a gain unit memory device that provides a wider sensing margin, i.e., a wider range of valid voltages that may exist in a signal node SN, and a method of operating, for example, a gain unit memory device. The wider sensing margin extends the duration that the gain unit memory device stores data bits, thereby reducing the frequency at which the data bits of the gain unit memory device need to be refreshed. By extending the duration that the gain unit memory device maintains valid data, the gain unit memory device can reduce the data refresh frequency, thereby reducing the power consumption of the gain unit memory.

[0131] In some embodiments, a gain unit memory device includes: a write transistor located on a substrate; a read transistor located on the substrate; a capacitor having a first electrode, a node dielectric, and a second electrode, wherein the first electrode is electrically connected to a first source / drain region of the write transistor and a gate electrode of the read transistor; and a peripheral circuit configured to electrically bias the source region of the read transistor with a normal source bias voltage when the gain unit memory device is not in a read operation, and to electrically bias the source region of the read transistor with a current enhancement source bias voltage that increases a conduction current of the read transistor when the gain unit memory device is in a read operation.

[0132] In the above gain cell memory device, further comprising a read bit line configured to electrically bias the drain region of the read transistor during an initial step of a read operation.

[0133] In the above-described gain cell memory device, the peripheral circuit is configured to apply a precharge bias voltage to the read bit line before turning on the additional read transistor.

[0134] In the above-mentioned gain unit memory device, a first one of the precharge bias voltage and the normal source bias voltage is a circuit power supply voltage; and a second one of the precharge bias voltage and the normal source bias voltage is a ground voltage.

[0135] In the above-mentioned gain cell memory device, the current enhancement source bias voltage is equal to the sum of (1+α) times the normal source bias voltage plus -α times the precharge bias voltage, where the value of α is in the range of 0.01 to 0.30.

[0136] In the above gain unit memory device, an additional read transistor is further included that is connected to the drain region of the read transistor in a series connection, wherein the drain region of the additional read transistor is electrically shorted to the read bit line.

[0137] In the above-described gain cell memory device, the peripheral circuit is configured to apply a read gate pulse of a first duration to a gate electrode of the additional read transistor during a read operation.

[0138] In the above-mentioned gain unit memory device, a first duration and a current enhancement source bias voltage are selected so that, under the condition that the gate electrode of the read transistor is at a voltage equal to the sum of 0.5 times the precharge bias voltage and 0.5 times the normal source bias voltage, the voltage at the read bit line at the time point when the first duration ends is between the first voltage and the second voltage; the first voltage is equal to the sum of 0.4 times the precharge bias voltage and 0.6 times the normal source bias voltage; and the second voltage is equal to the sum of 0.6 times the precharge bias voltage and 0.4 times the normal source bias voltage.

[0139] In the above-described gain cell memory device, the current enhancement source bias voltage is applied as a current enhancement source bias voltage pulse having the same duration as the read gate pulse.

[0140] In the above-described gain cell memory device, the read bit line is electrically shorted to the drain region of the read transistor.

[0141] In the above-mentioned gain unit memory device, the peripheral circuit is configured to: maintain the read bit line in a high impedance state when the gain unit memory device is not in a read operation; apply a precharge bias voltage to the read bit line during a precharge step of the read operation; and measure the voltage at the read bit line after a first duration after the precharge step.

[0142] In some embodiments, a gain unit memory device includes: a write transistor located on a substrate; a read transistor located on the substrate; a capacitor having a first electrode, a node dielectric, and a second electrode, the first electrode including a signal node electrically connected to a first source / drain region of the write transistor and electrically connected to a gate electrode of the read transistor, wherein the capacitor is located in a dielectric material layer overlying the write transistor and the read transistor; a metal interconnect structure located in the dielectric material layer and providing electrical connections to the first electrode, the second source / drain region of the write transistor, and the source region of the read transistor; a read bit line configured to electrically bias the drain region of the read transistor; a source bias line electrically connected to the source region of the read transistor; and a peripheral circuit configured to electrically bias the source region of the read transistor with a normal source bias voltage when the gain unit memory device is not in a read operation, and to electrically bias the source region of the read transistor with a current enhancement source bias voltage that increases the on-current of the read transistor when the gain unit memory device is in a read operation.

[0143] In the above-mentioned gain unit memory device, the peripheral circuit is configured to apply a precharge bias voltage to the read bit line during an initial step of a read operation; the first of the precharge bias voltage and the normal source bias voltage is a circuit power supply voltage; and the second of the precharge bias voltage and the normal source bias voltage is a ground voltage.

[0144] In the above gain unit memory device, the current enhancement source bias voltage is equal to the sum of (1+α) times the normal source bias voltage plus -α times the precharge bias voltage, where the value of α is in the range of 0.01 to 0.30.

[0145] In the above-mentioned gain unit memory device, the peripheral circuit includes a sense amplifier electrically connected to the read bit line; and the peripheral circuit includes a data latch configured to store an output of the sense amplifier at a time point when the read operation is terminated.

[0146] In some embodiments, a method of operating a gain unit memory device includes: providing a gain unit memory device, the gain unit memory device including a write transistor located on a substrate, a read transistor located on the substrate, a capacitor, a read bit line and a source line, the capacitor having a first electrode, a node dielectric and a second electrode, the first electrode including a first source / drain region electrically connected to the write transistor and a signal node electrically connected to a gate electrode of the read transistor, the read bit line being configured to electrically bias the drain region of the read transistor, and the source bias line being connected to the source region of the read transistor; performing a write operation to encode a data bit in the signal node by applying a write-read bit line bias voltage to the second source / drain region of the write transistor and by turning on the write transistor when the source bias line is electrically biased with the first source bias voltage; and performing a read operation by precharging the read bit line with a precharge bias voltage, by applying a second source bias voltage different from the first source bias voltage to the source bias line, and by sensing a voltage at the drain region of the read transistor.

[0147] In the above-described gain cell memory device, the magnitude of the difference between the precharge bias voltage and the second source bias voltage is greater than the magnitude of the difference between the precharge bias voltage and the first source bias voltage.

[0148] In the above-mentioned gain unit memory device, a first one of the precharge bias voltage and the first source bias voltage is a circuit power supply voltage; and a second one of the precharge bias voltage and the first source bias voltage is a ground voltage.

[0149] In the above-mentioned gain unit memory device, the gain unit memory device includes an additional read transistor, which is configured to switch the electrical connection between the read bit line and the drain region of the read transistor; the second source bias voltage is applied to the first source bias line by applying a current enhancement source bias voltage pulse; the additional read transistor is turned on by applying a gate voltage pulse to the gate electrode of the additional read transistor; and the current enhancement source bias voltage pulse has the same duration as the gate voltage pulse.

[0150] In the above-mentioned gain unit memory device, the gain unit memory device includes a sense amplifier electrically connected to the read bit line and a data latch electrically coupled to the output of the sense amplifier; and the method also includes using the data latch to capture the output of the sense amplifier at a point in time when the read operation is terminated.

[0151] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Each embodiment described using the term "comprising" is also inherently disclosed, unless otherwise explicitly disclosed herein, in certain embodiments, the term "comprising" can be replaced with the term "consisting essentially of..." or "consisting of...". Whenever two or more elements are listed in the same paragraph in different paragraphs as an alternative, in some embodiments, a Markush group including two or more element lists can also be implicitly disclosed. Whenever the auxiliary verb "may" is used in the present disclosure to describe the formation of an element or the execution of a processing step, embodiments in which such elements or such processing steps are not performed are also explicitly considered, provided that the resulting device or apparatus can provide equivalent results. Therefore, the auxiliary verb "may" applied to the formation of an element or the execution of a processing step should also be interpreted as "may" or "may, or may not", as long as the formation of such an element or processing step is omitted to provide the same result or equivalent result, and the equivalent result includes slightly better results and slightly worse results. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A gain unit memory device, comprising: a write transistor, located on the substrate; a read transistor located on the substrate; a capacitor having a first electrode, a node dielectric, and a second electrode, wherein the first electrode is electrically connected to the first source / drain region of the write transistor and the gate electrode of the read transistor; as well as The peripheral circuit is configured to electrically bias the source region of the read transistor with a normal source bias voltage when the gain unit memory device is not in a read operation, and to electrically bias the source region of the read transistor with a current enhancement source bias voltage that increases a conduction current of the read transistor when the gain unit memory device is in a read operation. 2 . The gain cell memory device of claim 1 , further comprising a read bit line configured to electrically bias a drain region of the read transistor during an initial step of the read operation.

3. The gain unit memory device according to claim 2, wherein: The peripheral circuit is configured to apply a precharge bias voltage to the read bit line before turning on the additional read transistor.

4. The gain cell memory device of claim 3, wherein: A first one of the precharge bias voltage and the normal source bias voltage is a circuit power supply voltage; and A second one of the precharge bias voltage and the normal source bias voltage is a ground voltage.

5. The gain unit memory device of claim 4, wherein: The current enhancement source bias voltage is equal to the sum of (1+α) times the normal source bias voltage plus -α times the precharge bias voltage, where the value of α is in the range of 0.01 to 0.

30.

6. The gain cell memory device of claim 2, further comprising an additional read transistor connected in series to a drain region of the read transistor, wherein A drain region of the additional read transistor is electrically shorted to the read bit line.

7. A gain unit memory device, comprising: a write transistor, located on the substrate; a read transistor located on the substrate; a capacitor having a first electrode, a node dielectric, and a second electrode, the first electrode including a signal node electrically connected to a first source / drain region of the write transistor and electrically connected to a gate electrode of the read transistor, wherein the capacitor is located within a dielectric material layer overlying the write transistor and the read transistor; a metal interconnect structure within the dielectric material layer providing electrical connection to the first electrode, the second source / drain region of the write transistor, and the source region of the read transistor; a read bit line configured to electrically bias a drain region of the read transistor; a source bias line electrically connected to the source region of the read transistor; and The peripheral circuit is configured to electrically bias the source region of the read transistor with a normal source bias voltage when the gain unit memory device is not in a read operation, and to electrically bias the source region of the read transistor with a current enhancement source bias voltage that increases a conduction current of the read transistor when the gain unit memory device is in the read operation.

8. The gain cell memory device of claim 7, wherein: The peripheral circuit includes a sense amplifier electrically connected to the read bit line; as well as The peripheral circuit includes a data latch configured to store an output of the sense amplifier at a point in time when the read operation is terminated.

9. A method of operating a gain cell memory device, the method comprising: A gain unit memory device is provided, the gain unit memory device including a write transistor located on a substrate, a read transistor located on the substrate, a capacitor having a first electrode, a node dielectric, and a second electrode, the first electrode including a signal node electrically connected to a first source / drain region of the write transistor and electrically connected to a gate electrode of the read transistor, the read bit line being configured to electrically bias a drain region of the read transistor, and the source bias line being connected to a source region of the read transistor; performing a write operation to encode a data bit in a signal node by applying a write read bit line bias voltage to a second source / drain region of the write transistor and by turning on the write transistor when the source bias line is electrically biased at a first source bias voltage; as well as A read operation is performed by precharging the read bit line with a precharge bias voltage, by applying a second source bias voltage different from the first source bias voltage to the source bias line, and by sensing a voltage at a drain region of the read transistor.

10. The method according to claim 9, wherein: The magnitude of the difference between the precharge bias voltage and the second source bias voltage is greater than the magnitude of the difference between the precharge bias voltage and the first source bias voltage.

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