SiC groove terminal structure manufacturing method

Abstract

The invention discloses a manufacturing method of a SiC groove terminal structure, and belongs to the technical field of semiconductor manufacturing. Comprising the following steps: forming a plurality of P + regions in an N-epitaxial layer to divide the N-epitaxial layer into a terminal region and a plurality of cellular regions, forming a first Pwell region in the terminal region, and respectively forming a JFET injection region, a second Pwell region and an N + region in the cellular regions; defining a gradual change groove terminal ring in the terminal area and defining a grid electrode groove pattern on the cellular area through photoresist; forming a plurality of terminal region grooves of which the depths are gradually increased in the direction of the cellular region in the terminal region through the pattern, and forming a grid electrode groove in the cellular region; and forming side walls on the terminal region trench and the gate trench, and forming a P-type protection region at the bottom. And removing the side wall and the hard mask layer, and further forming a grid electrode, a source electrode and a drain electrode. According to the method, a mask plate required by the process is not added, a single groove and deep pplus scheme is compatible, and the problem of electric field concentration of a deep pplus transition region during reverse voltage withstanding is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a SiC trench terminal structure. Background Art

[0002] In the design of SiC trench MOSFET, the design of the terminal is very critical. Although the research on the planar MOS terminal structure is relatively mature, in trench MOSFET, due to the need to strengthen the protection of the gate oxide at the bottom of the gate trench, a deep source trench is often used in combination with conventional pplus injection or deep pplus injection to protect the gate oxide and improve the robustness of the cell. However, after the transition zone is formed by deep pplus injection, if the field limiting ring terminal is formed by pplus high-energy injection, it will put forward extremely high requirements on the injection mask. High-energy injection means that a thicker and harder mask is required, which also leads to the CD of the mask being unable to achieve the size required by the conventional field limiting ring, and the performance of the field limiting ring will also be lost. In order to reduce the dependence on the high-energy injection mask and improve the performance of the terminal, the industry usually uses JTE terminals, but the disadvantages of JTE terminals are also significant, such as small process window, high sensitivity to injection, and large influence by interface charge. In order to improve the JTE injection window, dual-zone JTE can be introduced, but this will also increase the mask cost and the process steps. Summary of the invention

[0003] On one hand, the present invention is intended to provide a method for manufacturing a SiC trench terminal structure to solve the deficiencies in the prior art. The technical problem to be solved by the present invention is achieved through the following technical solutions, including: Providing an N+ substrate, and forming an N- epitaxial layer on the N+ substrate; Forming a plurality of P+ regions in the N-epitaxial layer by high-energy ion implantation to divide the N-epitaxial layer into a terminal region and a plurality of cell regions, forming a first Pwell region in the terminal region, and forming a JFET implantation region, a second Pwell region and an N+ region in the cell region respectively; A hard mask layer is formed on the N-epitaxial layer, and a gradient trench terminal ring is defined in the terminal area and a gate trench pattern is defined in the cell area by photoresist; the gradient trench terminal ring has a plurality of terminal area trench patterns with a trench width gradually increasing toward the cell area.

[0004] Further etching the hard mask layer through the above-mentioned terminal region trench pattern and gate trench pattern, and forming a plurality of terminal region trenches with gradually increasing depths in the terminal region toward the cell region, and forming a gate trench in the cell region; Forming sidewalls on the terminal region trench and the gate trench, and using the sidewalls as masks to form P-type protection zones at the bottom of the terminal region trench and the gate trench by ion implantation; After completing the implantation of the P-type protection area, removing the sidewalls and the hard mask layer in the terminal area trench and the cell area gate trench; Finally, polysilicon is filled in the terminal region trench and the gate trench to form a gate, and an interlayer dielectric isolation layer and a source metal are formed thereon, and a drain is formed on the back side of the N+ substrate.

[0005] Furthermore, the N-epitaxial layer is 4H-SiC with a thickness of 10 μm and a concentration of 1×10 16 cm -3 ; The N+ substrate is an N-type 4H-SiC substrate with a thickness of 180μm.

[0006] Furthermore, the P+ region is formed by Al ion implantation, with a maximum implantation energy of 1.8 MeV and a junction depth of 2 μm.

[0007] Furthermore, the first Pwell region and the second Pwell region are formed by Al ion implantation, the implantation energy is 500 KeV, and the junction depth is 0.7 μm.

[0008] Furthermore, the JFET injection region is implanted with N ions, the injection energy is 600 KeV, and the injection junction depth is 0.9 μm; the N+ region is implanted with N ions, the injection energy is 70 KeV, and the junction depth is 0.3 μm.

[0009] Furthermore, the aspect ratio of the trench in the terminal region is 1:1.

[0010] Furthermore, the P-type protection zone is implanted with Al ions, and the implanted Al ions have a dosage of 1×10 13 cm -3 , the injection energy is 50~70keV.

[0011] Compared with the related art, the technical solution of the present application has at least the following advantages: The SiC trench terminal structure manufacturing method provided by the present invention does not increase the mask required for the process, is compatible with the single trench + deep pplus solution, does not increase the additional injection process, is compatible with the conventional solution, and solves the problem of electric field concentration in the deep pplus transition zone during reverse withstand voltage. In addition, it also effectively shortens the terminal length. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of forming a terminal region and a cell region in an N-epitaxial layer; Figure 2A schematic diagram of a gradient trench terminal ring and a gate trench pattern defined by a hard mask layer; Figure 3 It is a schematic diagram of forming a gradient trench terminal ring and a gate trench by etching; Figure 4 is a schematic diagram of forming a side wall in a trench; Figure 5 It is a schematic diagram of forming a P protection zone at the bottom of the trench; Figure 6 is a schematic diagram of removing the sidewall and hard mask layer; Figure 7 It is a schematic diagram of forming gate oxide, polysilicon gate, interlayer dielectric isolation layer and source and drain metal electrodes. DETAILED DESCRIPTION

[0013] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail in conjunction with the embodiments and drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0014] The following is combined with Figure 1-7 The method for manufacturing the SiC trench terminal structure of the present application is described in detail. An N+ substrate 1 is provided, and an N-epitaxial layer 2 is formed on the N+ substrate 1; the N-epitaxial layer 2 is 4H-SiC, with a thickness of 10 μm and a concentration of 1×10 16 cm -3 ; N+ substrate 1 is an N-type 4H-SiC substrate with a thickness of 180μm.

[0015] In the N-epitaxial layer 2, multiple P+ regions 4 are formed by high-energy ion implantation to divide the N-epitaxial layer 2 into a terminal region and multiple cell regions, and a first Pwell region 3 is formed in the terminal region, and a JFET implantation region 5, a second Pwell region 6 and an N+ region 7 are formed in the cell region respectively; the P+ region 4 is formed by Al ion implantation, with a maximum implantation energy of 1.8 MeV and a junction depth of 2 μm. The JFET implantation region 5 is implanted with N ions, with an implantation energy of 600 KeV and an implantation junction depth of 0.9 μm. The first Pwell region 3 and the second Pwell region 6 are formed by Al ion implantation, with an implantation energy of 500 KeV and a junction depth of 0.7 μm. The N+ region 7 is implanted with N ions, with an implantation energy of about 70 KeV and a junction depth of about 0.3 μm.

[0016] A hard mask layer 9 is formed on the N-epitaxial layer 2, and a gradient trench terminal ring is defined in the terminal area and a gate trench pattern is defined in the cell area through a photoresist 10; the gradient trench terminal ring has multiple terminal area trench patterns with a trench width gradually increasing toward the cell area. The material of the hard mask layer 9 is SiO 2 .

[0017] The hard mask layer 9 is further etched through the above-mentioned terminal area groove pattern and gate groove pattern, and multiple terminal area grooves with gradually increasing depths in the direction of the cell area are formed in the terminal area, and gate grooves are formed in the cell area; the aspect ratio of the above-mentioned terminal area grooves is 1:1. For example, the depth of the gate groove in the active area is 0.8μm, and the etching process needs to open a width of 0.8μm on the hard mask. In this way, the terminal area scheme is designed, and a window is opened on the hard mask of the terminal area, the window is 2μm, and the corresponding etched groove depth is also 2μm. From right to left, the window width decreases successively, and the decreasing step is 0.1μm. The width of the last window is 0.8μm. There are 13 windows in total, which corresponds to 13 grooves with decreasing depths, and the spacing between each groove is 2μm.

[0018] A sidewall 11 is formed on the terminal area trench and the gate trench. For the conventional single trench solution, the bottom of the gate trench needs to be protected by injecting P-type to protect the gate oxide at the bottom of the trench. The P protection area injection used here needs to first protect the trench sidewall to prevent the P protection area injection from affecting the concentration of Pwell. The trench sidewall protection uses the hard mask used for etching the trench and then deposits a sidewall. By etching the sidewall, a sidewall with a width of about 0.2um is obtained.

[0019] The sidewall 11 is used as a mask to form a P-type protection zone 12 at the bottom of the terminal region trench and the gate trench by ion implantation. The P protection zone 12 is implanted with Al ions, and the implanted Al ion dosage is 1×10 13 cm -3 The injection energy is 50~70keV. The P protection zones formed above have different functions. The P protection zones in the cell area are mainly used to reduce the bottom gate oxide electric field strength and improve reliability; while the P protection zones in the terminal area become part of the terminal design of the terminal voltage divider.

[0020] After the P-type protection zone 12 is implanted, the sidewalls 11 and the hard mask layer 9 in the terminal zone trench and the cell zone gate trench are removed; finally, a gate oxide 16 and a gate 15 are formed by filling polysilicon in the terminal zone trench and the gate trench, and an interlayer dielectric isolation layer 14 and a source metal 13 are formed thereon, and a drain 8 is formed on the back of the N+ substrate.

[0021] The present invention optimizes the existing single-groove deepened P+ implanted SiC MOSFET terminal design, and provides a terminal structure that can reduce the electric field strength of the deep P+ transition zone at the edge of the terminal, reduce the terminal length, and does not require the addition of additional masks and additional process steps. The structure adopts a gradient groove depth design, the groove depth close to the transition zone is deeper, and the groove away from the transition zone decreases in depth. Since the conventional means of protecting the gate oxide at the bottom of the groove is to implant the P protection zone, after the gradient groove is formed in the terminal zone, the P protection zone is also implanted at the bottom of the trench in the terminal zone to form a P protection zone. The P protection zone implantation here can generate a depletion zone expansion when subjected to reverse bias, which plays a role in withstanding the voltage drop.

[0022] It should be noted that the above detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present application belongs.

[0023] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0025] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0026] For ease of description, spatially relative terms, such as "above", "above", "on the upper surface of", "above", etc., may be used herein to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" may include both "above" and "below". The device may also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatially relative descriptions used herein are interpreted accordingly.

[0027] In the above detailed description, reference is made to the accompanying drawings, which form a part of this document. In the accompanying drawings, similar symbols typically identify similar components unless the context indicates otherwise. The illustrated embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be used, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein.

[0028] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a SiC trench termination structure, characterized in that: The steps include: Providing an N+ substrate (1), and forming an N- epitaxial layer (2) on the N+ substrate (1); Forming a plurality of P+ regions (4) in the N-epitaxial layer (2) by high-energy ion implantation to divide the N-epitaxial layer (2) into a terminal region and a plurality of cell regions, forming a first Pwell region (3) in the terminal region, and forming a JFET implantation region (5), a second Pwell region (6) and an N+ region (7) in the cell region; Forming a hard mask layer (9) on the N-epitaxial layer (2), and defining a gradient trench terminal ring in the terminal region and a gate trench pattern in the cell region by means of a photoresist (10); The gradient groove terminal ring has a plurality of terminal region groove patterns with a groove width gradually increasing toward the cell region; The hard mask layer (9) is further etched through the terminal region groove pattern and the gate groove pattern, and a plurality of terminal region grooves whose depth gradually increases in the direction of the cell region are formed in the terminal region, and a gate groove is formed in the cell region; Forming sidewalls (11) on the terminal region trench and the gate trench, and using the sidewalls (11) as masks to form P-type protection areas (12) at the bottom of the terminal region trench and the gate trench by ion implantation; After the implantation of the P-type protection area (12) is completed, the sidewalls (11) and the hard mask layer (9) in the terminal area trench and the cell area gate trench are removed; Finally, a gate oxide (16) is formed in the terminal region trench and the gate trench and filled with polysilicon to form a gate (15), and an interlayer dielectric isolation layer (14) and a source metal (13) are formed thereon, and a drain (8) is formed on the back side of the N+ substrate (1).

2. The method for manufacturing a SiC trench termination structure according to claim 1, wherein: The N-epitaxial layer (2) is 4H-SiC with a thickness of 10 μm and a concentration of 1×10 16 cm -3 The N+ substrate (1) is an N-type 4H-SiC substrate with a thickness of 180 μm.

3. The method for manufacturing a SiC trench termination structure according to claim 1, wherein: The P+ region (4) is formed by Al ion implantation, with a maximum implantation energy of 1.8 MeV and a junction depth of 2 μm.

4. The method for manufacturing a SiC trench termination structure according to claim 1, wherein: The first Pwell region (3) and the second Pwell region (6) are formed by Al ion implantation, with an implantation energy of 500 KeV and a junction depth of 0.7 μm.

5. The method for manufacturing a SiC trench termination structure according to claim 1, wherein: The JFET injection region (5) is implanted with N ions, the injection energy is 600 KeV, and the injection junction depth is 0.9 μm; the N+ region (7) is implanted with N ions, the injection energy is 70 KeV, and the injection junction depth is 0.3 μm.

6. The method for manufacturing a SiC trench termination structure according to claim 1, wherein: The depth-to-width ratio of the termination region trench is 1:

1.

7. The method for manufacturing a SiC trench termination structure according to claim 1, wherein: The P-type protection zone (12) is implanted with Al ions, and the implanted Al ions have a dosage of 1×10 13 cm -3 , the injection energy is 50~70keV.

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