Formation method of semiconductor structure

Abstract

A semiconductor structure forming method comprises the steps that a substrate is provided, the substrate comprises adjacent device regions, channel protruding parts and gate structures stretching across the channel protruding parts of the adjacent device regions are formed on the substrate of the device regions, and the gate structures cover part of the tops and part of the side walls of the channel protruding parts; source and drain doping layers are formed in the channel lug bosses on the two sides of the gate structure, a dielectric layer is formed on the substrate exposed out of the gate structure, and the dielectric layer covers the source and drain doping layers and the side wall of the gate structure; and taking the side walls of the dielectric layers at the two sides of the gate structures as stop positions, and removing the gate structures at the junction positions of the adjacent device regions. The side walls of the dielectric layer at the two sides of the gate structure can play a role in etching stop, so that the dielectric layer can play a role in protecting the source-drain doping layer at the two sides of the gate structure, the probability of damage to the source-drain doping layer caused by the process of removing the gate structure is reduced, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor transistors are moving towards higher component density and higher integration, and semiconductor process nodes are continuously decreasing in accordance with Moore's Law. Transistors, as the most basic semiconductor transistors, are currently being widely used. Therefore, with the increase in component density and integration of semiconductor transistors, in order to adapt to the reduction of process nodes, the channel length of transistors must be continuously shortened.

[0003] In order to better adapt to the requirement of proportional reduction of transistor size, semiconductor processes have gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors. Among them, gate-all-around transistors include vertical gate-all-around transistors and horizontal gate-all-around transistors. In a gate-all-around transistor, the gate surrounds the area where the channel is located from all sides. Compared with planar transistors, the gate of a gate-all-around transistor has a stronger control ability over the channel and can better suppress the short channel effect.

[0004] Currently, the performance of gate-all-around (GAA) transistors still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to further improve the performance of the semiconductor structure.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising an adjacent device area, a channel protrusion formed on the substrate of the device area, and a gate structure spanning the channel protrusion adjacent to the device area, the gate structure covering a portion of the top and a portion of the sidewalls of the channel protrusion, a source-drain doped layer formed in the channel protrusions on both sides of the gate structure, a dielectric layer formed on the substrate exposed by the gate structure, the dielectric layer covering the source-drain doped layer and the sidewalls of the gate structure; using the sidewalls of the dielectric layer on both sides of the gate structure as stop positions, removing the gate structure at the junction of the adjacent device areas.

[0007] Optionally, the gate structure at the boundary between adjacent device regions is removed by an etching process, and the etching process has an etching selectivity ratio between the gate structure and the dielectric layer.

[0008] Optionally, the dielectric layer includes a sidewall layer; and an etching selectivity ratio between the gate structure and the sidewall layer is greater than 3:1.

[0009] Optionally, the dielectric layer includes an interlayer dielectric layer; and an etching selectivity ratio between the gate structure and the interlayer dielectric layer is greater than 3:1.

[0010] Optionally, the dielectric layer includes a sidewall layer covering the sidewall of the gate structure, and an interlayer dielectric layer covering the sidewall of the sidewall layer; the sidewall of the sidewall layer in contact with the gate structure is used as an etching stop position to remove the gate structure at the junction of adjacent device areas.

[0011] Optionally, the spacer layer includes a gate spacer covering a sidewall of the gate structure, and an etch stop layer covering a sidewall of the gate spacer.

[0012] Optionally, the process of removing the gate structure at the boundary position of adjacent device regions includes a plasma dry etching process.

[0013] Optionally, the plasma used in the plasma dry etching process includes one or both of inductively coupled plasma and microwave electron cyclotron resonance plasma.

[0014] Optionally, the process parameters of the plasma dry etching process include: the process gas includes one or more of CH2F2, O2, NF3, Ar, N2, Cl2 and HBr; the bias power range is 0W to 3000W; the source power range is 100W to 5000W; the chamber pressure range is 1mT to 100mT; and the process temperature range is -20°C to 150°C.

[0015] Optionally, the process parameters of the plasma dry etching process include: the gas flow range of CH2F2 is 10sccm to 100sccm; the gas flow range of O2 is 10sccm to 50sccm; the gas flow range of NF3 is 10sccm to 500sccm; the gas flow range of Ar is 50sccm to 1000sccm; the gas flow range of N2 is 50sccm to 300sccm; the gas flow range of Cl2 is 50sccm to 800sccm; the gas flow range of HBr is 100sccm to 900sccm.

[0016] Optionally, the step of removing the gate structure at the junction of adjacent device areas by using the side walls of the dielectric layer on both sides of the gate structure as stop positions includes: forming a mask layer with a mask opening on top of the dielectric layer and the gate structure, the mask layer covering the dielectric layer and the gate structure, and the mask opening being located above the gate structure at the junction of adjacent device areas; using the mask layer as a mask, performing patterning on the gate structure exposed by the mask opening to remove the gate structure at the junction of adjacent device areas.

[0017] Optionally, the material of the dielectric layer includes one or more of silicon nitride, silicon oxide and silicon oxynitride.

[0018] Optionally, the channel protrusion is a channel stack structure suspended on the substrate, and the channel stack structure includes one or more channel layers spaced apart in the longitudinal direction; or, a fin protrudes from the top of the substrate, and a portion of the height of the fin close to one side of the top of the fin serves as the channel protrusion.

[0019] Optionally, along the extension direction of the gate structure, the distance between the source and drain doping layers of adjacent device regions is less than 10 nanometers.

[0020] Optionally, the process of forming the source-drain doping layer includes an epitaxial process.

[0021] Optionally, the side wall of the dielectric layer is used as a stopping position, and in the step of removing the gate structure at the boundary position of the adjacent device area, an opening surrounded by the dielectric layer and the substrate is formed; the method for forming the semiconductor structure also includes: forming a partition structure in the opening, and the partition structure covers the side wall of the gate structure.

[0022] Optionally, the process of forming the partition structure in the opening includes an atomic layer deposition process.

[0023] Optionally, the step of forming a partition structure in the opening includes: forming a partition material layer on the top of the gate structure, on the top of the dielectric layer, and in the opening; taking the top of the dielectric layer as a stopping position, flattening the partition material layer above the top of the dielectric layer, and the remaining partition material layer located in the opening serves as the partition structure.

[0024] Optionally, the gate structure includes a gate dielectric layer conformally covering a portion of the top and a portion of the sidewalls of the channel protrusion, and a gate electrode layer covering the gate dielectric layer; the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0026] An embodiment of the present invention provides a method for forming a semiconductor structure, providing a substrate, the substrate comprising an adjacent device region, a channel protrusion formed on the substrate of the device region, and a gate structure spanning the channel protrusion of the adjacent device region, the gate structure covering a portion of the top and a portion of the sidewall of the channel protrusion, a source-drain doping layer formed in the channel protrusion on both sides of the gate structure, a dielectric layer formed on the substrate exposed by the gate structure, the dielectric layer covering the source-drain doping layer and the sidewall of the gate structure, and removing the gate structure at the junction of the adjacent device region with the dielectric layer sidewalls on both sides of the gate structure as the stop position. Since the dielectric layer sidewalls on both sides of the gate structure are used as the stop position, in the process of removing the gate structure at the junction of the adjacent device region, the dielectric layer sidewalls on both sides of the gate structure can play the role of etching stop, so that the dielectric layer can protect the source-drain doping layer on both sides of the gate structure, reducing the probability of the process of removing the gate structure causing damage to the source-drain doping layer, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figures 1 to 8 is a structural schematic diagram corresponding to a method for forming a semiconductor structure;

[0028] Figures 9 to 14 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0029] The performance of the current semiconductor structure needs to be improved. The reasons why the performance needs to be improved are analyzed in combination with a structural schematic diagram corresponding to a method for forming a semiconductor structure.

[0030] Figures 1 to 8 is a structural schematic diagram corresponding to a method for forming a semiconductor structure, wherein: Figure 1 It is a top view. Figure 2 yes Figure 1 Cross-sectional view along BB direction, Figure 3 yes Figure 1 Cross-sectional view along AA direction, Figure 4 It is a top view. Figure 5 yes Figure 4 Cross-sectional view along BB direction, Figure 6 yes Figure 4 Cross-sectional view along the AA direction.

[0031] refer to Figures 1 to 3 , providing a substrate 11, the substrate 11 including an adjacent device area 10A, a channel protrusion 14 and a gate structure 16 spanning the channel protrusion 14 adjacent to the device area 10A are formed on the substrate 11 of the device area 10A, the gate structure 16 covers a portion of the top and a portion of the sidewall of the channel protrusion 14, source-drain doped layers 15 are formed in the channel protrusions 14 on both sides of the gate structure 16, a dielectric layer 17 is formed on the substrate 11 exposed by the gate structure 16, and the dielectric layer 17 covers the source-drain doped layers 15 and the sidewalls of the gate structure 16.

[0032] refer to Figures 4 to 6 A patterned mask layer 26 is formed on the top of the dielectric layer 17 and the gate structure 16 , and the patterned mask layer 26 exposes the gate structure 16 and the dielectric layer 17 at the boundary position of the adjacent device region 10A.

[0033] refer to Figures 7 and 8 , using the mask layer 26 as a mask, the gate structure 16 and the dielectric layer 17 at the boundary between the adjacent device regions 10A are removed.

[0034] Research has found that as the process of semiconductor structure is further reduced, the distance between adjacent device areas 10A is getting closer, which means that the distance between the source and drain doping layers 15 between adjacent device areas 10A is getting smaller and smaller. Accordingly, in the process of removing the gate structure 16 and the dielectric layer 17 at the junction of adjacent device areas 10A, the etching process can easily cause the source and drain doping layers 15 at the junction of adjacent device areas 10A to be damaged, thereby affecting the performance of the semiconductor structure.

[0035] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including an adjacent device area, a channel protrusion formed on the substrate of the device area, and a gate structure spanning the channel protrusion adjacent to the device area, the gate structure covering a portion of the top and a portion of the side wall of the channel protrusion, a source-drain doped layer formed in the channel protrusions on both sides of the gate structure, a dielectric layer formed on the substrate exposed by the gate structure, the dielectric layer covering the source-drain doped layer and the side wall of the gate structure; using the side walls of the dielectric layer on both sides of the gate structure as stop positions, removing the gate structure at the junction of the adjacent device areas.

[0036] An embodiment of the present invention provides a method for forming a semiconductor structure, providing a substrate, the substrate comprising an adjacent device region, a channel protrusion formed on the substrate of the device region, and a gate structure spanning the channel protrusion of the adjacent device region, the gate structure covering a portion of the top and a portion of the sidewall of the channel protrusion, a source-drain doping layer formed in the channel protrusion on both sides of the gate structure, a dielectric layer formed on the substrate exposed by the gate structure, the dielectric layer covering the source-drain doping layer and the sidewall of the gate structure, and removing the gate structure at the junction of the adjacent device region with the dielectric layer sidewalls on both sides of the gate structure as the stop position. Since the dielectric layer sidewalls on both sides of the gate structure are used as the stop position, in the process of removing the gate structure at the junction of the adjacent device region, the dielectric layer sidewalls on both sides of the gate structure can play the role of etching stop, so that the dielectric layer can protect the source-drain doping layer on both sides of the gate structure, reducing the probability of the process of removing the gate structure causing damage to the source-drain doping layer, thereby improving the performance of the semiconductor structure.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figures 9 to 14 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0039] refer to Figures 9 and 10 ,in, Fig. 9 It is a top view. Fig.10 yes Fig. 9A cross-sectional view along the AA direction provides a substrate 102, wherein the substrate 102 includes an adjacent device area 100A, a channel protrusion 104 and a gate structure 105 spanning the channel protrusion 104 adjacent to the device area 100A are formed on the substrate 102 of the device area 100A, the gate structure 105 covers a portion of the top and a portion of the sidewall of the channel protrusion 104, source-drain doped layers 120 are formed in the channel protrusions 104 on both sides of the gate structure 105, a dielectric layer 110 is formed on the substrate 102 exposed by the gate structure 105, and the dielectric layer 110 covers the source-drain doped layers 120 and the sidewalls of the gate structure 105.

[0040] The substrate 102 is used to provide a process platform for forming a gate-all-around (GAA) transistor.

[0041] In this embodiment, the base 102 is a three-dimensional base 102 , and the base 102 includes a substrate 100 and a protruding portion 101 protruding from the substrate 100 .

[0042] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0043] The protrusion 101 exposes a portion of the substrate 100 , thereby providing a process basis for subsequently forming an isolation layer.

[0044] In this embodiment, the material of the protrusion 101 is the same as that of the substrate 100, and the material of the protrusion 101 is silicon. In other embodiments, the material of the protrusion may also be a semiconductor material suitable for forming a fin, such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the protrusion may also be different from that of the substrate.

[0045] The device region 100A is a region where the gate structure 105 and the source-drain doping layer 120 are formed.

[0046] Specifically, the channel protrusion 104 is used to provide a conductive channel for the transistor.

[0047] In this embodiment, the channel protrusion 104 is a channel structure layer suspended on the substrate 102 , and the channel structure layer includes one or more channel layers 103 spaced apart in the longitudinal direction.

[0048] In this embodiment, the channel structure layer includes a plurality of spaced channel layers 103, and the stacking direction of the plurality of stacked channel layers 103 is perpendicular to the surface of the substrate 100. In this embodiment, the number of the channel layers 103 is two. In other embodiments, the number of the channel layers may not be limited to two.

[0049] In this embodiment, the material of the channel structure layer is the same as that of the protrusion 101 , and the material of the channel structure layer is Si.

[0050] In other embodiments, a fin portion protrudes from the top of the substrate, and a portion of the height of the fin portion near one side of the top of the fin portion serves as the channel protrusion.

[0051] The gate structure 105 is used to control the opening and closing of the conductive channel when the device is working.

[0052] Specifically, the gate structure 105 is a metal gate structure.

[0053] In this embodiment, the gate structure 105 includes a gate dielectric layer (not shown) conformally covering a portion of the top and a portion of the sidewall of the channel protrusion 104 , and a gate electrode layer (not shown) covering the gate dielectric layer.

[0054] As an example, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0055] Specifically, the gate dielectric layer includes a gate oxide layer that conformally covers a portion of the top, a portion of the sidewall, and a portion of the bottom of the channel layer 103, and a high-k gate dielectric layer that conformally covers the gate oxide layer. The material of the high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide.

[0056] It should be noted that the gate dielectric layer also conformally covers a portion of the top of the isolation layer.

[0057] The gate electrode layer is used for subsequent electrical connection with an external structure. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may also include only the work function layer.

[0058] The source-drain doped layer 120 is used to provide a source region and a drain region for the semiconductor structure.

[0059] In this embodiment, the source-drain doped layer 120 is located in the channel protrusion 104 on both sides of the gate structure 105 .

[0060] Among them, when the fully enclosed gate transistor is a P-type MOS transistor, the material of the stress layer is Si or SiGe, and the doped ions in the source and drain doping layer 120 are P-type ions; when the fully enclosed gate transistor is an N-type MOS transistor, the material of the stress layer is Si or SiC, and the doped ions in the source and drain doping layer 120 are N-type ions.

[0061] It should be noted that, along the extension direction of the gate structure 105, the distance between the source-drain doping layers 120 of the adjacent device regions 100A should not be too large. If the distance between the source-drain doping layers 120 of the adjacent device regions 100A is too large, it is easy to cause the area occupied by the substrate 102 to be too large, which is not conducive to the reduction of the transistor area, resulting in the overall size of the semiconductor structure not meeting the process requirements. For this reason, in this embodiment, along the extension direction of the gate structure 105, the distance between the source-drain doping layers 120 of the adjacent device regions 100A is less than 10 nanometers.

[0062] As an example, the process of forming the source-drain doping layer 120 includes an epitaxial process.

[0063] Specifically, the epitaxial process is the most commonly used growth process for forming the source-drain doped layer 120, and has the characteristics of good growth quality. Forming the source-drain doped layer 120 through the epitaxial process reduces the probability of generating voids in the source-drain doped layer 120, thereby affecting the performance of the semiconductor structure.

[0064] It should be noted that the dielectric layer 110 is used to electrically isolate the adjacent device regions 100A, and also provides a process basis for subsequently removing the gate structure 105 at the boundary between the adjacent device regions 100A.

[0065] It should also be noted that in the subsequent process of removing the gate structure 105 at the junction of the adjacent device area 100A, the side walls of the dielectric layer 110 on both sides of the gate structure 105 can act as an etching stop, so that the dielectric layer 110 can protect the source and drain doped layers 120 on both sides of the gate structure 105, reducing the probability of damage to the source and drain doped layers 120 caused by the process of removing the gate structure 105, thereby improving the performance of the semiconductor structure.

[0066] In this embodiment, the dielectric layer 110 includes a spacer layer 109 covering the sidewalls of the gate structure 105 , and an interlayer dielectric layer 108 covering the sidewalls of the spacer layer 109 .

[0067] Specifically, the spacer layer 109 protects the sidewalls of the gate structure 105 , and is also used to define the formation position of the source / drain doped layer 120 during the process of forming the source / drain doped layer 120 .

[0068] It should be noted that in the subsequent process of removing the gate structure 105 at the boundary position of the adjacent device region 100A, the side wall of the spacer layer 109 in contact with the gate structure 105 is used as the etching stop position.

[0069] As an example, the spacer layer 109 includes a gate spacer 106 covering a sidewall of the gate structure 105 , and an etch stop layer 107 covering a sidewall of the gate spacer 106 .

[0070] In the subsequent process of removing the gate structure 105 at the boundary position of the adjacent device region 100A, the gate spacer 106 protects the sidewall of the gate structure 105 in the device region 100A.

[0071] In this embodiment, the gate spacer 106 is a single-layer structure, and the material of the gate spacer 106 is silicon nitride.

[0072] In the subsequent process of removing the gate structure 105 at the boundary between the adjacent device regions 100A, the etch stop layer 107 can function as an etch stop.

[0073] In this embodiment, the material of the etch stop layer 107 includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0074] It should be noted that the interlayer dielectric layer 108 is used to electrically isolate the adjacent device area 100A. At the same time, in the subsequent process of removing the gate structure 105 at the junction of the adjacent device area 100A, the source-drain doped layer 120 is covered by the interlayer dielectric layer 108, so that the interlayer dielectric layer 108 protects the source-drain doped layer 120, reducing the probability of damage to the source-drain doped layer 120.

[0075] As an example, the material of the interlayer dielectric layer 108 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0076] Silicon nitride, silicon oxide and silicon oxynitride are all dielectric materials, which can electrically isolate the adjacent device area 100A. At the same time, in the subsequent process of removing the gate structure 105 at the junction of the adjacent device area 100A, the etching selectivity between silicon nitride, silicon oxide and silicon oxynitride and the material selected for the gate structure 105 can be utilized to achieve the purpose of removing the gate structure 105 at the junction of the adjacent device area 100A, and the probability of damaging other film layers (such as the source and drain doping layer 120) can also be reduced.

[0077] refer to Figures 11 to 13 ,in, Fig.11 It is a top view. Fig.12 yes Fig.11In the cross-sectional view along the AA direction, the side walls of the dielectric layer 110 on both sides of the gate structure 105 are used as the stop position to remove the gate structure 105 at the boundary position of the adjacent device area 100A.

[0078] It should be noted that the side walls of the dielectric layer 110 on both sides of the gate structure 105 are used as the stopping position. Therefore, in the process of removing the gate structure 105 at the boundary between the adjacent device area 100A, the side walls of the dielectric layer 110 on both sides of the gate structure 105 can play a role in etching stop, so that the dielectric layer 110 can protect the source-drain doped layer 120 on both sides of the gate structure 105, reducing the probability of damage to the source-drain doped layer 120 caused by the process of removing the gate structure 105, thereby improving the performance of the semiconductor structure.

[0079] In this embodiment, the gate structure 105 at the boundary between the adjacent device regions 100A is removed by an etching process, and the etching process has an etching selectivity ratio between the gate structure 105 and the dielectric layer 110 .

[0080] In the etching process, the gate structure 105 and the dielectric layer 110 have an etching selectivity ratio, and the etching selectivity between the gate structure 105 and the dielectric layer 110 can be utilized to achieve the purpose of removing the gate structure 105 at the junction of the adjacent device area 100A, so that the dielectric layer 110 can protect the source-drain doped layer 120, and at the same time, it can also reduce the probability of causing damage to other film layers (such as the source-drain doped layer 120).

[0081] It should be noted that, in the process of removing the gate structure 105 at the boundary position of the adjacent device area 100A, the etching selectivity ratio between the gate structure 105 and the sidewall layer 109 should not be too small. If the etching selectivity ratio between the gate structure 105 and the sidewall layer 109 is too small, it is easy to cause the etching rate of the gate structure 105 to be close to the etching rate of the sidewall layer 109. Accordingly, in the process of removing the gate structure 105 at the boundary position of the adjacent device area 100A, the probability of the sidewall layer 109 being etched and removed is increased, thereby increasing the probability of the source-drain doped layer 120 being damaged. For this reason, in the present embodiment, in the process of removing the gate structure 105 at the boundary position of the adjacent device area 100A, the etching selectivity ratio between the gate structure 105 and the sidewall layer 109 is greater than 3:1.

[0082] It should also be noted that, in the process of removing the gate structure 105 at the boundary position of the adjacent device area 100A, the etching selectivity ratio between the gate structure 105 and the interlayer dielectric layer 108 should not be too small. If the etching selectivity ratio between the gate structure 105 and the interlayer dielectric layer 108 is too small, it is easy to cause the etching rate of the gate structure 105 to be close to the etching rate of the interlayer dielectric layer 108. Accordingly, in the process of removing the gate structure 105 at the boundary position of the adjacent device area 100A, the probability of the interlayer dielectric layer 108 being etched and removed is increased, so that the protection effect of the interlayer dielectric layer 108 on the source-drain doped layer 120 is reduced, thereby increasing the probability of the source-drain doped layer 120 being damaged. For this reason, in the present embodiment, in the process of removing the gate structure 105 at the boundary position of the adjacent device area 100A, the etching selectivity ratio between the gate structure 105 and the interlayer dielectric layer 108 is greater than 3:1.

[0083] As an example, the side wall of the spacer layer 109 in contact with the gate structure 105 is used as an etching stop position to remove the gate structure 105 at the boundary position of the adjacent device region 100A.

[0084] It should be noted that, by taking the side wall of the sidewall layer 109 in contact with the gate structure 105 as the etching stop position, the gate structure 105 at the boundary between the adjacent device area 100A is removed, so that the sidewall layer 109 can protect the interlayer dielectric layer 108, thereby reducing the probability of the interlayer dielectric layer 108 being consumed by the etching process, and enabling the interlayer dielectric layer 108 to electrically isolate the adjacent device area 100A. At the same time, the interlayer dielectric layer 108 can also protect the source-drain doping layer 120.

[0085] In this embodiment, the process of removing the gate structure 105 at the boundary between the adjacent device regions 100A includes a plasma dry etching process.

[0086] The plasma dry etching process includes ion physical bombardment sputtering and chemical reaction corrosion. In the plasma dry etching process, the etching controllability is relatively high. The plasma can be used to produce physical and chemical reactions with the gate structure 105 at the junction of the adjacent device area 100A, thereby achieving the purpose of completely removing the gate structure 105 at the junction of the adjacent device area 100A. At the same time, it can also reduce the probability of causing damage to other film layers in the device area 100A.

[0087] As an example, the plasma used in the plasma dry etching process includes one or both of inductively coupled plasma (ICP) and microwave electron cyclotron resonance plasma (ECR).

[0088] In the process of microwave electron cyclotron resonance plasma etching, the plasma is connected to the inductor coil, which provides a bias voltage, thereby providing energy to the plasma, so as to achieve the purpose of vertically acting on the gate structure 105 at the junction of adjacent device areas 100A, and remove the gate structure 105 at the junction of adjacent device areas 100A.

[0089] In the process of using microwave electron cyclotron resonance plasma, free electrons gain energy when they make spiral motion in the magnetic field, thereby increasing electron collisions to produce high-density plasma. The plasma has the characteristics of anisotropic etching and has high image transmission accuracy. It can achieve the effect of completely removing the gate structure 105 at the junction of adjacent device areas 100A. At the same time, it can also reduce the probability of causing damage to other film layers in the device area 100A.

[0090] In this embodiment, the process parameters of the plasma dry etching process include: the process gas includes one or more of CH2F2, O2, NF3, Ar, N2, Cl2 and HBr; the bias power range is 0W to 3000W; the source power range is 100W to 5000W; the chamber pressure range is 1mT to 100mT; the process temperature range is -20℃ to 150℃.

[0091] It should be noted that fluorine, chlorine and bromine are the main etching gases, Ar and N2 are carrier gases, and O2 is the protective gas.

[0092] It should be noted that during the plasma dry etching process, the bias power range should not be too large. If the bias power is too large, the probability of the substrate surface being damaged will increase. For this reason, in this embodiment, during the plasma dry etching process, the bias power is 0W to 3000W.

[0093] It should also be noted that during the plasma dry etching process, the source power range should not be too large or too small. If the source power is too large, the probability of the substrate surface being damaged is likely to increase; if the source power is too small, the plasma energy is likely to be too small, thereby causing the plasma to etch the gate structure 105 at the junction of the adjacent device area 100A at a slower rate, thereby reducing the process efficiency. For this reason, in this embodiment, during the plasma dry etching process, the source power range is 100W to 5000W.

[0094] Specifically, during the plasma dry etching process, the chamber pressure range should not be too large or too small. If the chamber pressure is too large, etching termination may occur easily; if the chamber pressure is too small, the etching morphology cannot be maintained. For this reason, in this embodiment, during the plasma dry etching process, the chamber pressure range is 1 mT to 100 Mt.

[0095] It should be noted that during the plasma dry etching process, the process temperature range should not be too large or too small. If the process temperature is too high, the etching morphology cannot be maintained; if the process temperature is too low, etching termination may occur. For this reason, in this embodiment, during the plasma dry etching process, the process temperature range is -20°C to 150°C.

[0096] As an example, the process parameters of the plasma dry etching process include: the gas flow range of CH2F2 is 10sccm to 100sccm; the gas flow range of O2 is 10sccm to 50sccm; the gas flow range of NF3 is 10sccm to 500sccm; the gas flow range of Ar is 50sccm to 1000sccm; the gas flow range of N2 is 50sccm to 300sccm; the gas flow range of Cl2 is 50sccm to 800sccm; the gas flow range of HBr is 100sccm to 900sccm.

[0097] In this embodiment, the step of removing the gate structure 105 at the boundary position of the adjacent device region 100A with the sidewalls of the dielectric layer 110 on both sides of the gate structure 105 as the stop position includes: Fig.12 As shown, a mask layer 130 having a mask opening 132 is formed on the top of the dielectric layer 110 and the gate structure 105, the mask layer 130 covers the dielectric layer 110 and the gate structure 105, and the mask opening 132 is located above the gate structure 105 at the junction of the adjacent device region 100A; Fig.13 As shown, the mask layer 130 is used as a mask to perform a patterning process on the gate structure 105 exposed by the mask opening 132 , and the gate structure 105 at the boundary position between the adjacent device regions 100A is removed.

[0098] The mask layer 130 is used as an etching mask for removing the gate structure 105 at the boundary position between the adjacent device regions 100A.

[0099] In this embodiment, the material of the mask layer 130 includes photoresist.

[0100] The mask layer 130 covers the dielectric layer 110 so that the mask layer 130 protects the dielectric layer 110 . In the process of removing the gate structure 105 at the junction of the adjacent device area 100A, the probability of the dielectric layer 110 being etched away can be reduced, so that the dielectric layer 110 can protect the source-drain doped layer 120 .

[0101] As an example, the mask opening 132 is located above the gate structure 105 at the junction of the adjacent device area 100A. Since there is an etching selectivity ratio between the dielectric layer 110 and the gate dielectric layer 110, the size of the mask opening 132 can be increased, which means that the process window for removing the gate structure 105 at the junction of the adjacent device area 100A is increased, thereby reducing the difficulty of the etching process.

[0102] In this embodiment, the sidewall of the dielectric layer 110 is used as a stop position, and in the step of removing the gate structure 105 at the boundary position adjacent to the device region 100A, an opening 150 surrounded by the dielectric layer 110 and the substrate 102 is formed.

[0103] The opening 150 provides a space for a partition structure to be formed subsequently, so that the partition structure to be formed subsequently can electrically isolate the gate structure 105 of the adjacent device region 100A.

[0104] It should be noted that, after removing the gate structure 105 at the boundary position between the adjacent device regions 100A, the method for forming the semiconductor structure further includes: removing the mask layer 130 .

[0105] The mask layer 130 is removed to expose the top surfaces of the gate structure 105 and the dielectric layer 110 , thereby providing a process basis for the subsequent formation of a partition structure.

[0106] In this embodiment, the process of removing the mask layer 130 includes a wet etching process or an ashing process.

[0107] refer to Fig.14 , a partition structure 180 is formed in the opening 150 , and the partition structure 180 covers the sidewall of the gate structure 105 .

[0108] The partition structure 180 is used to electrically isolate the gate structures 105 of the adjacent device regions 100A, thereby reducing the probability of the gate structures 105 of the adjacent device regions 100A being short-circuited with each other.

[0109] In this embodiment, the step of forming a partition structure 180 in the opening 150 includes: forming a partition material layer (not shown) on the top of the gate structure 105, on the top of the dielectric layer 110, and in the opening 150; taking the top of the dielectric layer 110 as a stopping position, flattening the partition material layer above the top of the dielectric layer 110, and the remaining partition material layer located in the opening 150 serves as the partition structure 180.

[0110] The partition material layer is used as a material layer for forming the partition structure 180 .

[0111] In this embodiment, the process of planarizing the partition material layer above the top of the dielectric layer 110 includes a chemical mechanical polishing process.

[0112] In this embodiment, the material of the partition structure 180 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0113] Silicon nitride, silicon oxide and silicon oxynitride are all dielectric layers that have an insulating function and can electrically isolate the gate structure 105 of the adjacent device region 100A.

[0114] In this embodiment, the process of forming the partition structure 180 in the opening 150 includes an atomic layer deposition process.

[0115] The atomic layer deposition process has the characteristic of consistency in film layer deposition thickness. By forming the partition structure 180 using the atomic layer deposition process, the thickness of the partition structure 180 between adjacent device areas 100A can be made consistent, thereby providing better electrical isolation for the gate structures 105 of the adjacent device areas 100A. At the same time, forming the partition structure 180 using the atomic layer deposition process also reduces the risk of generating voids in the partition structure 180, thereby improving the insulation effect of the partition structure 180.

[0116] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an adjacent device region, a channel protrusion formed on the substrate of the device region, and a gate structure spanning the channel protrusion adjacent to the device region, the gate structure covering a portion of the top and a portion of the sidewall of the channel protrusion, source-drain doping layers formed in the channel protrusions on both sides of the gate structure, a dielectric layer formed on the substrate exposed by the gate structure, the dielectric layer covering the source-drain doping layers and the sidewalls of the gate structure; The dielectric layer sidewalls on both sides of the gate structure are used as stop positions to remove the gate structure at the boundary position of the adjacent device regions.

2. The method for forming a semiconductor structure according to claim 1, wherein: The gate structure at the boundary position of the adjacent device regions is removed by an etching process, and the etching process has an etching selectivity ratio for the gate structure and the dielectric layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The dielectric layer includes a sidewall layer; and the etching selection ratio between the gate structure and the sidewall layer is greater than 3:

1.

4. The method for forming a semiconductor structure according to claim 2, wherein: The dielectric layer includes an interlayer dielectric layer; and the etching selection ratio between the gate structure and the interlayer dielectric layer is greater than 3:

1.

5. The method for forming a semiconductor structure according to claim 1 or 2, wherein: The dielectric layer includes a sidewall layer covering the sidewall of the gate structure, and an interlayer dielectric layer covering the sidewall of the sidewall layer; The side wall of the spacer layer in contact with the gate structure is used as an etching stop position to remove the gate structure at the boundary position of the adjacent device area.

6. The method for forming a semiconductor structure according to claim 5, wherein: The spacer layer includes a gate spacer covering a sidewall of the gate structure and an etching stop layer covering a sidewall of the gate spacer.

7. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the gate structure at the boundary position of the adjacent device regions includes a plasma dry etching process.

8. The method for forming a semiconductor structure according to claim 7, wherein: The plasma used in the plasma dry etching process includes one or both of inductively coupled plasma and microwave electron cyclotron resonance plasma.

9. The method for forming a semiconductor structure according to claim 7, wherein: The process parameters of the plasma dry etching process include: the process gas includes one or more of CH2F2, O2, NF3, Ar, N2, Cl2 and HBr; the bias power range is 0W to 3000W; the source power range is 100W to 5000W; the chamber pressure range is 1mT to 100mT; the process temperature range is -20℃ to 150℃.

10. The method for forming a semiconductor structure according to claim 9, wherein: The process parameters of the plasma dry etching process include: the gas flow range of CH2F2 is 10sccm to 100sccm; the gas flow range of O2 is 10sccm to 50sccm; the gas flow range of NF3 is 10sccm to 500sccm; the gas flow range of Ar is 50sccm to 1000sccm; the gas flow range of N2 is 50sccm to 300sccm; the gas flow range of Cl2 is 50sccm to 800sccm; the gas flow range of HBr is 100sccm to 900sccm.

11. The method for forming a semiconductor structure according to claim 1, wherein: The step of removing the gate structure at the junction of adjacent device areas by using the dielectric layer sidewalls on both sides of the gate structure as stop positions includes: forming a mask layer with a mask opening on top of the dielectric layer and the gate structure, the mask layer covering the dielectric layer and the gate structure, and the mask opening being located above the gate structure at the junction of adjacent device areas; using the mask layer as a mask, performing a patterning process on the gate structure exposed by the mask opening to remove the gate structure at the junction of adjacent device areas.

12. The method for forming a semiconductor structure according to claim 1, wherein: The material of the dielectric layer includes one or more of silicon nitride, silicon oxide and silicon oxynitride.

13. The method for forming a semiconductor structure according to claim 1, wherein: The channel protrusion is a channel stack structure suspended on the substrate, and the channel stack structure includes one or more channel layers spaced apart in the longitudinal direction; or, A fin portion is protruded from the top of the substrate, and a portion of the height of the fin portion close to one side of the top of the fin portion serves as the channel protrusion portion.

14. The method for forming a semiconductor structure according to claim 1, wherein: Along the extension direction of the gate structure, the distance between the source and drain doping layers of adjacent device regions is less than 10 nanometers.

15. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the source-drain doping layer includes an epitaxial process.

16. The method for forming a semiconductor structure according to claim 1, wherein: The side wall of the dielectric layer is used as a stop position, and in the step of removing the gate structure at the boundary position adjacent to the device region, an opening surrounded by the dielectric layer and the substrate is formed; The method for forming a semiconductor structure further includes: forming a partition structure in the opening, wherein the partition structure covers a side wall of the gate structure.

17. The method for forming a semiconductor structure according to claim 16, wherein: The process of forming the partition structure in the opening includes an atomic layer deposition process.

18. The method for forming a semiconductor structure according to claim 16, wherein: The step of forming a partition structure in the opening includes: forming a partition material layer on the top of the gate structure, on the top of the dielectric layer, and in the opening; taking the top of the dielectric layer as a stop position, flattening the partition material layer above the top of the dielectric layer, and the remaining partition material layer located in the opening serves as the partition structure.

19. The method for forming a semiconductor structure according to claim 1, wherein: The gate structure comprises a gate dielectric layer conformally covering a portion of the top and a portion of the sidewall of the channel protrusion, and a gate electrode layer covering the gate dielectric layer; The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

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