Wafer testing device and testing method

Abstract

The invention provides a wafer testing device and method, and the device comprises a probe card table which comprises a probe card and a functional circuit, and the probe card is provided with a first-class bonding point and a second-class bonding point; the first-class bonding points and the second-class bonding points are electrically connected with chip pins of the wafer to be tested through probes; the two types of bonding points respectively correspond to different functional circuits; and the test console is in communication connection with the probe card table, is used for selecting a matched second-class bonding point according to the type of the wafer to be tested to be electrically connected with a chip pin of the wafer to be tested, and is also used for testing the wafer to be tested through the probe card table to obtain a test result. The probe card is provided with the first type of bonding points and the second type of bonding points, and the second type of bonding points can be flexibly selected according to the model of the to-be-tested wafer, so that the to-be-tested wafer is connected to different functional circuits, different functional tests are realized, the probe card table can be compatible with the to-be-tested wafers of different models, and the test efficiency is improved. The problem that existing ATE test equipment is poor in compatibility is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer testing, and in particular to a wafer testing device and a testing method. Background Art

[0002] In order to ensure the functional effectiveness of semiconductor devices, wafer chips are usually tested by ATE (Automatic Test Equipment) before device packaging.

[0003] ATE testing is to connect the probes on the ATE test equipment to the pins of the wafer chip to achieve electrical connection, and then apply stimulation to the wafer chip through the test program burned on the ATE test equipment, measure the response output of the wafer chip, and compare the measured response output with the expected result to determine whether the wafer chip meets the specification requirements. Common test items include DC parameter test, AC parameter test and functional test, etc. For example, for image sensor wafer chips, test items also include optoelectronic performance test.

[0004] However, the probe cards used in existing ATE test equipment are developed and designed according to the pin design of the wafer chip to be tested, and are not compatible with different types of wafer chips, resulting in high test development costs. In addition, the existing ATE test platform is a parallel port test, while some types of wafer chips are in serial communication mode, such as LVDS (Low-VoltageDifferentialSignaling) interface. Therefore, the existing parallel port test method cannot test wafer chips in serial communication mode, which limits ATE testing. Summary of the invention

[0005] The object of the present invention is to provide a wafer testing device and a testing method to solve the problem of poor compatibility of existing ATE testing equipment.

[0006] In order to solve the above technical problems, the present invention provides a wafer testing device, comprising: A probe card station comprises a probe card and a functional circuit, wherein the probe card is provided with a plurality of first-class bonding points and a plurality of second-class bonding points; the first-class bonding points and the second-class bonding points are used to electrically connect with chip pins of a wafer to be tested through probes; the second-class bonding points correspond to different functional circuits respectively; A test console is communicatively connected to the probe card station, and is used to select matching the second type of bonding points according to the model of the wafer to be tested to electrically connect with the chip pins of the wafer to be tested, and is also used to test the wafer to be tested through the probe card station to obtain test results.

[0007] Optionally, in the wafer testing device, the one type of bonding points are connected one-to-one with at least some chip pins of two types of wafers to be tested.

[0008] Optionally, in the wafer testing device, the second type of bonding points of the chip pins of different models of wafers to be tested are not completely the same.

[0009] Optionally, in the wafer testing device, the functional circuit includes a serial input interface circuit, a parallel input interface circuit, an output interface circuit, a flash memory circuit, a cache circuit, a read-only storage circuit, a functional algorithm circuit, and a temperature sensor circuit.

[0010] Optionally, in the wafer testing device, the first type of bonding points and the second type of bonding points are arranged in the form of bump implants or solder vias.

[0011] In order to solve the above technical problems, the present invention further provides a wafer testing method, which is applied to the wafer testing device as described in any one of the above items, and the wafer testing method comprises: Get the model of the wafer to be tested; According to the model of the wafer to be tested, select the matching second-class bonding point; Placing the wafer to be tested on the probe card stage and electrically connecting the first type of bonding points and the selected second type of bonding points through probes; The test console issues test instructions to test the wafer to be tested to obtain test results.

[0012] Optionally, in the wafer testing method, the wafer testing method further includes: Power on and initialize the probe card station and test console; Confirm whether the communication between the probe card station and the test console is normal; Confirm whether the communication between the wafer to be tested and the test console is normal.

[0013] Optionally, in the wafer testing method, the method of selecting matching second-type bonding points according to the model of the wafer to be tested includes: According to the model of the wafer to be tested, confirm whether the input mode is serial input or parallel input, and select the corresponding type II bonding point according to the input mode; According to the model of the wafer to be tested, confirm the test items and select the corresponding Class II bonding points according to the test items.

[0014] Optionally, in the wafer testing method, the test console issues a test instruction to test the wafer to be tested to obtain a test result, which includes: Configure the wafer to be tested; Perform functional test on the wafer to be tested; The test console analyzes and processes the received data to obtain the test results; Store test results.

[0015] Optionally, in the wafer testing method, the method of configuring the wafer to be tested includes: Configure the chip registers of the wafer to be tested; The chips of the wafer to be tested are configured to be collected, stitched and / or cached in parallel or in series.

[0016] The wafer testing device and testing method provided by the present invention include: a probe card station, including a probe card and a functional circuit, wherein the probe card is provided with a plurality of first-class bonding points and a plurality of second-class bonding points; the first-class bonding points and the second-class bonding points are used to electrically connect with the chip pins of the wafer to be tested through probes; the second-class bonding points correspond to different functional circuits respectively; a test control console is communicatively connected with the probe card station, and is used to select matching second-class bonding points according to the model of the wafer to be tested to electrically connect with the chip pins of the wafer to be tested, and is also used to test the wafer to be tested through the probe card station to obtain test results. By setting the first-class bonding points and the second-class bonding points on the probe card, wherein the second-class bonding points can be flexibly selected according to the model of the wafer to be tested, the wafer to be tested can be connected to different functional circuits, and different functional tests can be realized, so that the probe card station can be compatible with different models of wafers to be tested, thereby solving the problem of poor compatibility of existing ATE test equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of the structure of a wafer testing device provided in this embodiment; Figure 2 A schematic diagram of the corresponding relationship between the two types of bonding points and the functional circuits provided in this embodiment; Figure 3 A flowchart of a wafer testing method provided in this embodiment; Figure 4 A flowchart of a wafer testing process provided for this embodiment; The descriptions of the reference numerals are as follows: 100-probe card; 101-basic probe card area; 102-auxiliary probe card area; a-type I bonding point; b-type II bonding point; b1-first type II bonding point; b2-second type II bonding point; b3-third type II bonding point; b4-fourth type II bonding point; b5-fifth type II bonding point; b6-sixth type II bonding point; b7-seventh type II bonding point; b8-eighth type II bonding point; 200-test console. DETAILED DESCRIPTION

[0018] The wafer testing device and the testing method proposed in the present invention are further described in detail below in combination with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often part of the actual structure. In particular, the emphasis of each accompanying drawing is different, and sometimes different proportions are used.

[0019] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0020] This embodiment provides a wafer testing device, such as Figure 1 As shown, including: A probe card station includes a probe card 100 and a functional circuit, wherein the probe card 100 is provided with a plurality of first-class bonding points a and a plurality of second-class bonding points b; the first-class bonding points a and the second-class bonding points b are used to electrically connect with chip pins of a wafer to be tested through probes; the second-class bonding points correspond to different functional circuits respectively; The test console 200 is communicatively connected to the probe card station, and is used to select the matching second type bonding point b to electrically connect with the chip pins of the wafer to be tested according to the model of the wafer to be tested, and is also used to test the wafer to be tested through the probe card station to obtain test results.

[0021] The wafer testing device provided in this embodiment sets a type I bonding point a and a type II bonding point b on the probe card 100, wherein the type II bonding point b can be flexibly selected according to the model of the wafer to be tested, so that the wafer to be tested can be connected to different functional circuits to implement different functional tests, so that the probe card station 100 can be compatible with different models of wafers to be tested, thereby solving the problem of poor compatibility of existing ATE testing equipment.

[0022] Specifically, in actual applications, the probe card 100 can be divided into a basic probe card area 101 and an auxiliary probe card area 102 according to the chip pin functions of various different models of wafers to be tested. The basic probe card area 101 is provided with multiple type I bonding points a, and the auxiliary probe card area 102 is provided with multiple type II bonding points b.

[0023] Of course, considering that chip pins of wafers of different models are arranged differently, a second type of bonding point b may exist among a plurality of first type of bonding points a, that is, an auxiliary probe card area 102 may exist in the basic probe card area 101 .

[0024] Furthermore, in this embodiment, the type of bonding points a are connected to at least some chip pins of two types of wafers to be tested in a one-to-one correspondence.

[0025] Specifically, in this embodiment, a type of bonding point a usually corresponds to chip pins at fixed positions in various types of wafers. For example, in wafers of different models, there are chip pins at coordinate positions (x1, y1) and (x2, y2). Then, the probe card 100 can be provided with a type of bonding point a corresponding to (x1, y1) and (x2, y2), respectively, so as to bond with the chip pins at that position, thereby being compatible with a variety of different types of wafers.

[0026] Furthermore, in this embodiment, the two types of bonding points b correspond to different functional circuits respectively; the two types of bonding points b connected to the chip pins of different models of wafers to be tested are not completely the same.

[0027] Specifically, in this embodiment, the second type of bonding point b is for the difference of chip pins of different types of wafers. For example, in a certain type of wafer, a chip pin for power supply is set at the coordinate position (x3, y3), and the probe card 100 can set a second type of bonding point b corresponding to (x3, y3) to facilitate bonding with the chip pin at this position to realize power supply to the chip. If there is no chip pin at the coordinate position (x3, y3) in other types of wafers, the second type of bonding point b at this position can be omitted during testing.

[0028] In practical applications, the functional circuits include, but are not limited to, serial input interface circuits, parallel input interface circuits, output interface circuits, flash memory circuits, cache circuits, read-only storage circuits, functional algorithm circuits, and temperature sensor circuits. For example, for an image sensor wafer, its functional algorithm circuit may be an ISP (Image Signal Processing) image algorithm circuit.

[0029] Specifically, different second-type bonding points b are connected to different functional circuits, so that the required second-type bonding points b can be flexibly selected according to the model of the wafer to be tested and the test requirements. Figure 2As shown, the first type-II bonding point b1 is connected to the serial input interface circuit, the second type-II bonding point b2 is connected to the parallel input interface circuit, the third type-II bonding point b3 is connected to the output interface circuit, the fourth type-II bonding point b4 is connected to the flash memory circuit, the fifth type-II bonding point b5 is connected to the cache circuit, the sixth type-II bonding point b6 is connected to the read-only storage circuit, the seventh type-II bonding point b7 is connected to the functional algorithm circuit, and the eighth type-II bonding point b8 is connected to the temperature sensing circuit.

[0030] By setting a serial input interface circuit and a parallel input interface circuit, the corresponding input interface circuit can be selected according to the data communication method of the wafer to be tested, so that the wafer with serial input method can be tested; at the same time, by setting different functional circuits, the testing requirements of various types of wafers can be met, broadening the application scenarios of the wafer testing device.

[0031] Of course, in practical applications, other functional circuits can be set and connected to the functional circuits through other second-class bonding points b. Preferably, considering the differences in chip pin positions of different types of wafers, the same second-class bonding point b can be switched to connect to different functional circuits, thereby achieving corresponding connections between chip pins and functional circuits.

[0032] In this embodiment, the first type of bonding point a and the second type of bonding point b are disposed on the probe card 100 in the form of bump implants or solder vias. In this way, a reliable bonding connection can be established between the probe and the functional circuit.

[0033] Also, in this embodiment, the test console 200 is implemented in the form of FPGA (field programmable gate array). Of course, in other embodiments, it can also be implemented in the form of SoC (system on chip) or MCU (microprocessor), etc., and this application does not limit this.

[0034] This embodiment also provides a wafer testing method, which is applied to the wafer testing device as described above. Figure 3 As shown, the wafer testing method includes: S1, obtaining the model of the wafer to be tested; S2, selecting matching second-class bonding points according to the model of the wafer to be tested; S3, placing the wafer to be tested on the probe card stage, and electrically connecting the first type of bonding points and the selected second type of bonding points through probes; S4, the test console issues a test instruction to test the wafer to be tested to obtain the test result.

[0035] The wafer testing method provided in this embodiment flexibly selects matching Class II bonding points according to the model of the wafer to be tested, so that the wafer to be tested can be connected to different functional circuits to achieve different functional tests, and the probe card station can be compatible with different models of wafers to be tested, thereby solving the problem of poor compatibility of existing ATE testing equipment.

[0036] In actual applications, before starting the test, it is usually necessary to power on and initialize the wafer test device to confirm that the wafer test device can operate normally. Specifically, first, the probe card station and the test console 200 are powered on and initialized; then, it is confirmed whether the communication between the probe card station and the test console 200 is normal; finally, it is confirmed whether the communication between the wafer to be tested and the test console 200 is normal.

[0037] Furthermore, in this embodiment, in step S1, the model of the wafer to be tested is obtained.

[0038] In practical applications, the model of the wafer to be tested can be obtained by manual reading and manually entered into the test console 200; of course, the corresponding relationship between the models of all wafers to be tested and the wafer ID number can also be burned into the read-only memory of the test console 200 in advance, and then, the corresponding model can be obtained by reading the ID number of the wafer to be tested. This application does not limit the method of obtaining the model of the wafer to be tested, and the specific implementation method is well known to those skilled in the art.

[0039] Furthermore, in this embodiment, in step S2, the method of selecting matching second-type bonding points according to the model of the wafer to be tested includes: S21, according to the model of the wafer to be tested, confirming that the input mode is serial input or parallel input, and selecting the corresponding second type of bonding points according to the input mode.

[0040] Specifically, if it is a serial input, select the second type of bonding point b connected to the serial input interface circuit to be connected to the wafer to be tested, or select the second type of bonding point b corresponding to the interface position of the wafer to be tested, and switch the functional circuit connected to the second type of bonding point b to the serial input interface circuit; similarly, if it is a parallel input, select the second type of bonding point b connected to the parallel input interface circuit to be connected to the wafer to be tested, or select the second type of bonding point b corresponding to the interface position of the wafer to be tested, and switch the functional circuit connected to the second type of bonding point b to the parallel input interface circuit.

[0041] S22, confirming the test items according to the model of the wafer to be tested, and selecting the corresponding second-type bonding points according to the test items.

[0042] Specifically, it is necessary to select the second type of bonding points b corresponding to the output interface circuit, the functional algorithm circuit, and the related data storage circuit to be connected to the wafer to be tested; or according to the chip functions corresponding to each chip pin of the wafer to be tested, select the second type of bonding points b corresponding to the chip pin position, and according to the chip function of the chip pin, switch the corresponding second type of bonding points b to connect to the corresponding functional circuit.

[0043] Furthermore, in this embodiment, in step S3, the wafer to be tested is placed on a probe card stage, and is electrically connected to the first type of bonding points and the selected second type of bonding points through probes.

[0044] In this way, the chip pins of the wafer to be tested are electrically connected to the corresponding bonding points, thereby realizing a circuit communication connection between the wafer to be tested and the test console.

[0045] Further, in this embodiment, in step S4, the test console issues a test instruction to test the wafer to be tested to obtain a test result, which includes: S41, configuring a wafer to be tested.

[0046] Specifically, in this embodiment, it is necessary to configure the chip registers of the wafer to be tested, and configure the chips of the wafer to be tested for collection, splicing and / or caching in parallel or serial, that is, configure the chip registers of the wafer to be tested for serial or parallel collection, splicing and / or caching.

[0047] S42, performing a functional test on the wafer to be tested.

[0048] Specifically, the functional test can be implemented by calling the corresponding functional circuit through the test program burned by the test console. The specific testing method is well known to those skilled in the art and will not be described in detail in this application.

[0049] S43, the test console analyzes and processes the received data to obtain the test results.

[0050] In actual applications, it is necessary to determine whether the wafer chip currently being tested is normal based on the received data. If it is normal, the data parameters under each configuration are tested to obtain the test results. If the wafer chip is determined to be abnormal, it is necessary to repeat step S41, update the configuration parameters, reconfigure the wafer, and then test again.

[0051] S44, storing the test results.

[0052] Specifically, the test results can be written into the chip register of the wafer to be tested, or stored in a specified directory of the test console, or even stored in a cloud database, and this application does not impose any restrictions on this.

[0053] After the test of the current wafer to be tested is completed, the wafer is replaced and the above steps are repeated for testing.

[0054] Below, taking the image sensor wafer as an example, combined with Figure 4 , illustrating the implementation process of the wafer testing method provided in this embodiment: First, the probe card station and the test console are powered on and initialized; then, confirm in turn whether the communication between the probe card station and the test console is normal, and whether the communication between the image sensor wafer to be tested and the test console is normal; if there is an abnormality in the communication between the probe card station and the test console, re-power on and initialize the probe card station and the test console; if there is an abnormality in the communication between the image sensor wafer to be tested and the test console, re-confirm whether the communication between the probe card station and the test console is normal; if the abnormality still exists after re-confirmation, an alarm is prompted and manual processing is performed.

[0055] Next, the model of the image sensor wafer to be tested is obtained, so that matching second-class bonding points and test procedures can be selected according to the model of the image sensor wafer to be tested, including whether the communication mode is parallel or serial, test items to be executed, etc.

[0056] Afterwards, the image sensor wafer to be tested is configured, and the image sensor wafer to be tested is tested under the configuration parameters, such as ISP algorithm processing; if the image sensor wafer to be tested is abnormal under the current configuration parameters, the configuration parameters are updated, the image sensor wafer to be tested is reconfigured and the test is re-performed; if the image sensor wafer to be tested is normal under the current configuration, various functional tests are performed under the configuration parameters to obtain test data.

[0057] Finally, the test console analyzes the image data to analyze and process the test data to obtain the final test results; the test results are stored for later confirmation by personnel.

[0058] Of course, in practical applications, the wafers to be tested are not limited to image sensor wafers, but can also be other types of wafers, and this application does not impose any restrictions on this.

[0059] The wafer testing method provided in this embodiment flexibly selects matching Class II bonding points according to the model of the wafer to be tested, so that the wafer to be tested can be connected to different functional circuits to achieve different functional tests, so that the probe card station can be compatible with different models of wafers to be tested, reducing the development cost of the probe card station. The wafer testing method provided in this embodiment can test wafers with serial input mode by selecting serial input interface circuits and parallel input interface circuits according to the communication mode of the wafer to be tested; at the same time, through different functional circuits, it can meet the testing requirements of various types of wafers, broadening the application scenarios of wafer testing. The wafer testing method provided in this embodiment, the entire testing process, including parameter configuration, bonding point selection, data analysis and processing, and test result generation, is fully automated, reducing labor costs, improving testing efficiency, and having high test accuracy.

[0060] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0061] The wafer testing device and testing method provided in this embodiment include: a probe card station, including a probe card and a functional circuit, wherein the probe card is provided with a plurality of first-class bonding points and a plurality of second-class bonding points; the first-class bonding points and the second-class bonding points are used to electrically connect with the chip pins of the wafer to be tested through probes; the second-class bonding points correspond to different functional circuits respectively; a test control console is communicatively connected with the probe card station, and is used to select matching second-class bonding points according to the model of the wafer to be tested to electrically connect with the chip pins of the wafer to be tested, and is also used to test the wafer to be tested through the probe card station to obtain test results. By setting the first-class bonding points and the second-class bonding points on the probe card, wherein the second-class bonding points can be flexibly selected according to the model of the wafer to be tested, the wafer to be tested can be connected to different functional circuits to achieve different functional tests, so that the probe card station can be compatible with different models of wafers to be tested, solving the problem of poor compatibility of existing ATE test equipment.

[0062] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A wafer testing device, characterized in that: include: A probe card station comprises a probe card and a functional circuit, wherein the probe card is provided with a plurality of first-class bonding points and a plurality of second-class bonding points; the first-class bonding points and the second-class bonding points are used to electrically connect with chip pins of a wafer to be tested through probes; the second-class bonding points correspond to different functional circuits respectively; A test console is communicatively connected to the probe card station, and is used to select matching the second type of bonding points according to the model of the wafer to be tested to electrically connect with the chip pins of the wafer to be tested, and is also used to test the wafer to be tested through the probe card station to obtain test results.

2. The wafer testing device according to claim 1, characterized in that: The one type of bonding points are connected to at least some chip pins of two types of wafers to be tested in a one-to-one correspondence.

3. The wafer testing device according to claim 1, characterized in that: The second-class bonding points of the chip pins of different types of wafers to be tested are not exactly the same.

4. The wafer testing device according to claim 1, characterized in that: The functional circuit includes a serial input interface circuit, a parallel input interface circuit, an output interface circuit, a flash memory circuit, a cache circuit, a read-only storage circuit, a functional algorithm circuit, and a temperature sensor circuit.

5. The wafer testing device according to claim 1, characterized in that: The first type of bonding points and the second type of bonding points are arranged in the form of bump implants or solder point vias.

6. A wafer testing method, applied to the wafer testing device according to any one of claims 1 to 5, characterized in that: The wafer testing method comprises: Get the model of the wafer to be tested; According to the model of the wafer to be tested, select the matching second-class bonding point; Placing the wafer to be tested on the probe card stage and electrically connecting the first type of bonding points and the selected second type of bonding points through probes; The test console issues test instructions to test the wafer to be tested to obtain test results.

7. The wafer testing method according to claim 6, characterized in that: Before starting the test, the wafer testing method further includes: Power on and initialize the probe card station and test console; Confirm whether the communication between the probe card station and the test console is normal; Confirm whether the communication between the wafer to be tested and the test console is normal.

8. The wafer testing method according to claim 6, characterized in that: The method for selecting matching second-type bonding points according to the model of the wafer to be tested includes: According to the model of the wafer to be tested, confirm whether the input mode is serial input or parallel input, and select the corresponding type II bonding point according to the input mode; According to the model of the wafer to be tested, confirm the test items and select the corresponding Class II bonding points according to the test items.

9. The wafer testing method according to claim 6, characterized in that: The method in which the test console issues a test instruction to test the wafer to be tested to obtain a test result includes: Configure the wafer to be tested; Perform functional test on the wafer to be tested; The test console analyzes and processes the received data to obtain the test results; Store test results.

10. The wafer testing method according to claim 9, characterized in that: The method for configuring a wafer to be tested comprises: Configure the chip registers of the wafer to be tested; The chips of the wafer to be tested are configured to be collected, stitched and / or cached in parallel or in series.

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