Memory management method and device

Abstract

The invention provides a memory management method and device, which can reduce the occupancy rate of a physical memory and improve the data throughput of the memory by combining the same physical memory pages, thereby improving the memory bandwidth, improving the utilization rate of a computing unit and improving the data processing performance. And the method is suitable for most high-throughput hardware, does not depend on specific hardware, and is high in generalization capability. The method comprises the following steps: firstly, acquiring input data, storing the input data in a memory, and mapping a plurality of virtual memory pages to a plurality of physical memory pages storing the input data; then, at least two virtual memory pages in the multiple virtual memory pages are mapped to a first physical memory page, that is, the at least two virtual memory pages are mapped and shot to the same physical memory page, and the data, indicated by the at least two virtual memory pages, stored in the memory are the same; and when the at least two virtual memory pages are called, indicating to read data in the first physical memory page.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a memory management method and device. Background Art

[0002] Most of the power consumption of heterogeneous chips is used for data communication. The computing bandwidth of the accelerator is much larger than the memory bandwidth, so all high-throughput accelerator hardware will encounter a problem: the memory bandwidth restricts the performance improvement of data processing.

[0003] For example, sparse matrix operations are very common in neural networks. A large number of quantization and ReLU activation functions will result in a large number of zeros in the data. At the same time, the hardware computing unit will fill the matrix for performance reasons, so the resulting matrix is ​​very large. When using neural networks for reasoning, it will occupy a very large memory bandwidth. Therefore, how to reduce memory bandwidth pressure, increase computing unit utilization, and improve data processing performance is an urgent problem to be solved. Summary of the invention

[0004] The present application provides a memory management method and device, which can reduce the occupancy rate of physical memory and improve the data throughput of memory by merging the same physical memory pages, thereby increasing memory bandwidth, increasing the utilization rate of computing units, and improving data processing performance; and is suitable for most high-throughput hardware, does not depend on specific hardware, and has strong generalization capabilities.

[0005] In view of this, in a first aspect, the present application provides a memory management method, the method comprising: first, obtaining input data, the input data being stored in a memory, the address of the memory indicating multiple physical memory pages, usually, when the electronic device is running, it reads data by calling a virtual memory page, and a mapping relationship between a virtual memory page and a physical memory page can be pre-set, that is, a mapping relationship between the multiple virtual memory pages mentioned in the present application and multiple physical memory pages, such as mapping multiple virtual memory pages to the multiple physical memory pages, each virtual memory page being mapped to at least one physical memory page, and the multiple virtual memory pages being used to read the input data stored in the memory when called; then, mapping at least two of the multiple virtual memory pages to a first physical memory page, that is, mapping at least two virtual memory pages to the same physical memory page, the data stored in the memory indicated by the at least two virtual memory pages being the same, and when the at least two virtual memory pages are called, they indicate reading data in the same first physical memory page.

[0006] The implementation methods of the present application can be applied to high-throughput processors. By mapping virtual memory pages representing the same or similar content to the same physical memory page, physical memory pages occupied by virtual memory pages with the same content can be released, reducing the occupancy rate of physical memory pages, thereby increasing available memory and improving memory bandwidth.

[0007] In a possible implementation, the aforementioned method further includes: if any one of the at least two virtual memory pages mapped to the first physical memory page is called, then data is read from the first physical memory page. Therefore, when any one of the virtual memory pages mapped to the same physical memory page is called, the data stored in the common physical memory page can be read, thereby realizing data reading when multiple virtual memory pages are mapped to the same physical memory page.

[0008] In a possible implementation, before mapping at least two of the multiple virtual memory pages to the first physical memory page, the method may further include: correcting the data mapped by multiple first virtual memory pages in the multiple virtual memory pages to the same value through an approximation algorithm, that is, correcting the values ​​mapped to the memory by different virtual pages to the same value using an approximation algorithm, and the approximation algorithm is an algorithm for calculating approximate values, such as can be used to calculate the approximate value of data stored in a physical memory page.

[0009] Therefore, in the implementation manner of the present application, an approximate algorithm can be used to increase the same data in the input data, that is, to increase virtual memory pages indicating the same data, so that when subsequent memory merging is performed, more virtual memory pages can be merged to further reduce memory usage.

[0010] In a possible implementation, the aforementioned method of correcting the data mapped by multiple first virtual memory pages in multiple virtual pages to the same value through an approximate algorithm may also include: calculating the same value of the data mapped by multiple first virtual memory pages through an approximate algorithm; and then verifying the same value, such as running an application that needs to use the same value or running a calculation that needs to use the same value; if the verification passes, the data mapped by multiple first virtual memory pages are corrected to the same value.

[0011] Therefore, after performing the approximate operation, the approximate result can also be verified, thereby ensuring that the application or process that needs to call the approximate result can run normally, thereby improving the operating reliability of the device.

[0012] In a possible implementation, the aforementioned method may further include: if the verification of the same value fails, adjusting the approximation algorithm, and recalculating the same value of the data mapped by multiple first virtual memory pages through the adjusted approximation algorithm; or, if the verification of the same value fails, rolling back the data corresponding to the first virtual memory page that fails the verification, and stopping calculating the same value.

[0013] In the implementation manner of the present application, if the verification fails, the approximate algorithm can be adjusted to recalculate the same value, or the data can be rolled back, thereby avoiding the unavailability of the saved data and further improving the operational reliability of the device.

[0014] In a possible implementation, the aforementioned identical value includes a value included in the input data or data in one of the first virtual memory pages mapping the memory. In the implementation of the present application, the identical value may be one of the values ​​in the input data or the value of one of the memory pages, thereby increasing the probability of data availability.

[0015] In a possible implementation, the aforementioned method may further include: releasing the physical memory corresponding to at least one second physical memory page, wherein the at least one second physical memory page is a physical memory page that is not mapped by the virtual memory page after at least two virtual memory pages are mapped to the first physical memory page. Therefore, after mapping multiple virtual memory pages to the same physical memory page, the free physical memory page can be released, thereby reducing memory usage and improving memory data throughput.

[0016] In a possible implementation, the aforementioned method may further include: setting the first physical memory page to a read-only state, wherein when the state of the first physical memory page is a read-only state, the data in the first physical memory page is not allowed to be modified. In the implementation of the present application, a physical memory page mapped by multiple virtual memory pages may be set to a read-only state, thereby avoiding the situation where the data mapped by multiple virtual memory pages becomes unavailable when the data of the physical memory page is modified.

[0017] In a possible implementation, the aforementioned method may further include: when the data mapped by the second virtual memory page in multiple virtual memory pages mapped to the same physical memory page is modified, the data read in the memory corresponding to the first physical memory page is copied to the memory corresponding to the third physical memory page, and the second virtual memory page is a virtual memory page mapped to the first physical memory page; then the data in the memory corresponding to the third physical memory page is modified, and the second virtual memory page is mapped to the third physical memory page. It can be understood that when the data corresponding to a virtual memory page needs to be modified, the data to be modified is copied to other physical memory pages, and then the data in the other physical memory pages is rewritten, and the virtual memory page is mapped to the modified physical memory page.

[0018] In an implementation manner of the present application, when data in a physical memory page set to read-only status needs to be modified, such as when a process calls a virtual memory page and performs a modification operation, the data can be modified by copying, thereby avoiding the modification of data in a physical memory page that maps multiple virtual memory pages, which would cause the data mapped by the multiple virtual memory pages to be unavailable.

[0019] In a possible implementation, the aforementioned input data includes a sparse matrix of a neural network, and the sparse matrix includes a matrix corresponding to parameters in the neural network.

[0020] In a second aspect, the present application provides a memory management device, the device comprising:

[0021] An acquisition module is used to acquire input data, where the input data is stored in a memory, where the address of the memory indicates a plurality of physical memory pages, and where there is a mapping relationship between the plurality of physical memory pages and a plurality of virtual memory pages. For example, a plurality of virtual memory pages can be mapped to a plurality of physical memory pages, and the plurality of virtual memory pages are used to read the input data when they are called;

[0022] A memory management module is used to map at least two virtual memory pages among multiple virtual memory pages to a first physical memory page, the data stored in the memory indicated by the at least two virtual memory pages are the same, and when the at least two virtual memory pages are called, they indicate to read the data in the first physical memory page.

[0023] Among them, the effects achieved by the second aspect or any optional implementation of the second aspect can be found in the description of the first aspect or any optional implementation of the first aspect, and will not be repeated here.

[0024] In a possible implementation, the memory management module is further configured to read data from the first physical memory page if any one of the at least two virtual memory pages is called.

[0025] In a possible implementation, the memory management module is further used to correct the data mapped by multiple first virtual memory pages in the multiple virtual memory pages to the same value by using an approximate algorithm before mapping at least two virtual memory pages in the multiple virtual memory pages to the first physical memory page.

[0026] In a possible implementation, the memory management module is further used to: calculate the same value of data mapped by multiple first virtual memory pages through an approximate algorithm; verify the same value; if the verification passes, correct the data mapped by multiple first virtual memory pages to the same value.

[0027] In one possible implementation, the memory management module is further used to: if the verification of the same value fails, adjust the approximation algorithm, and recalculate the same value of the data mapped by multiple first virtual memory pages through the adjusted approximation algorithm; or, if the verification of the same value fails, roll back the data corresponding to the first virtual memory page that fails the verification, and stop calculating the same value.

[0028] In a possible implementation, the same value includes a value included in the input data or data in one of the first virtual memory pages mapped memory.

[0029] In a possible implementation, the memory management module is further used to: release the physical memory corresponding to at least one second physical memory page, where the at least one second physical memory page is a physical memory page that is not mapped by the virtual memory page after mapping at least two virtual memory pages to the first physical memory page.

[0030] In a possible implementation, the memory management module is further configured to set the first physical memory page to a read-only state, wherein when the state of the first physical memory page is the read-only state, data in the first physical memory page is not allowed to be modified.

[0031] In a possible implementation, the memory management module is also used to: when the data mapped by the second virtual memory page is modified, copy the data read from the memory corresponding to the first physical memory page to the memory corresponding to the third physical memory page, the second virtual memory page being the virtual memory page mapped to the first physical memory page; modify the data in the memory corresponding to the third physical memory page; and map the second virtual memory page to the third physical memory page.

[0032] In a possible implementation, the input data includes a sparse matrix of the neural network, and the sparse matrix includes a matrix corresponding to parameters in the neural network.

[0033] In a third aspect, an embodiment of the present application provides a memory management device, which has the function of implementing the memory management method of the first aspect. The function can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0034] In a fourth aspect, an embodiment of the present application provides a memory management device, comprising: a processor and a memory, wherein the processor and the memory are interconnected via a line, and the processor calls a program code in the memory to execute the processing-related functions in the memory management method shown in any one of the first aspects above. Optionally, the memory management device can be a chip.

[0035] In the fifth aspect, an embodiment of the present application provides a digital processing chip or chip, the chip includes a processing unit and a communication interface, the processing unit obtains program instructions through the communication interface, the program instructions are executed by the processing unit, and the processing unit is used to perform functions related to processing in the above-mentioned first aspect or any optional embodiment of the first aspect.

[0036] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, comprising instructions, which, when executed on a computer, enables the computer to execute the method in the above-mentioned first aspect or any optional implementation manner of the first aspect.

[0037] In the seventh aspect, an embodiment of the present application provides a computer program product comprising a computer program / instructions, which, when executed by a processor, enables the processor to execute the method in the above-mentioned first aspect or any optional implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic diagram of the structure of a system architecture provided for this application;

[0039] Figure 2 A structural diagram of another system architecture provided for this application;

[0040] Figure 3 A flowchart of a memory management method provided by this application;

[0041] Figure 4 A flowchart of another memory management method provided by this application;

[0042] Figure 5 A structural diagram of another system architecture provided for this application;

[0043] Figure 6 A flowchart of another memory management method provided by this application;

[0044] Figure 7 A flowchart of another memory management method provided by this application;

[0045] Figure 8 A schematic diagram of the structure of a memory management device provided by this application;

[0046] Fig. 9 A schematic diagram of the structure of another memory management device provided in this application. DETAILED DESCRIPTION

[0047] The following will describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0048] In common hardware architectures, heterogeneous accelerators have become mainstream. Most of the power consumption of heterogeneous chips is used for data communication. The computing bandwidth of the accelerator is much larger than the memory bandwidth, so all high-throughput accelerator hardware will encounter a problem: memory bandwidth restricts the performance improvement of data processing.

[0049] For example, it is very common to generate sparse matrices during the processing of neural networks. For example, a large amount of quantization and linear rectification function (ReLU) activation function will cause a large number of 0s in the data. At the same time, the hardware computing unit will fill the matrix for performance, and there will be a large number of 0s after filling. For example, running the residual neural network ResNet50 model on the Ascend embedded neural network processing unit (NPU) will expand the number of channels from 3 to 16, and the amount of data will become 5.3 times the original. After filling, 81.25% of the data is 0.

[0050] Generally, in neural networks, sparsifying some input data to approximate 0 has little impact on the results. For example, in the background blur scene in Google Meet, 70% sparsification can increase the model speed by 30% while maintaining the quality of the foreground mask.

[0051] In a common way, the matrix of the neural network can be sparse and compressed, and the data can be recorded in a sparse matrix format to reduce memory consumption. However, the sparse matrix format is only suitable for the calculation of matrices with a very high sparsity rate (such as more than 99%). For example, in order to reduce memory consumption, an existing solution can sparse the input data, regard every four values ​​as a group, change two values ​​to 0, and keep only two non-zero values, so that the sparsity of the entire matrix becomes 50%, and the calculation of 0 is skipped during hardware calculation, and the data size and calculation amount are reduced by half. When using a neural network for inference, fine-grained structured pruning is used first, and then additional training steps are used to fine-tune the remaining non-zero weights. However, skipping the calculation of 0 requires customized hardware implementation, and can only improve the throughput of processing sparse matrices. Its generalization ability is limited and can only be used in specific scenarios.

[0052] Obviously, reducing memory bandwidth pressure, increasing computing unit utilization, improving data processing performance, and being applicable to all high-throughput accelerator hardware without hardware dependence have become urgent issues to be solved.

[0053] Therefore, the present application provides a memory management method for improving memory data throughput, which can reduce the occupancy rate of physical memory and improve memory data throughput by merging the same physical memory pages, thereby increasing memory bandwidth, increasing computing unit utilization, and improving data processing performance; and is suitable for most high-throughput hardware, does not depend on specific hardware, and has strong generalization capabilities.

[0054] First of all, the present application relates to the memory field or the processor field. To facilitate understanding, some concepts or terms involved in the present application are explained below.

[0055] Physical address (PA): In memory, information is stored in bytes. To correctly store or retrieve information, each byte unit is given a unique memory address, called a physical address, also called an actual address or an absolute address. The physical memory page mentioned in this application means that the physical address corresponding to the memory is divided into multiple address pages, and each address page is a physical memory page.

[0056] Virtual address (VA): The address used by the application is a virtual address, which needs to be converted into an actual physical address through the address mapping method provided by the CPU. In this way, when multiple processes are running at the same time, the virtual memory space of each process can be isolated from each other, and the operating system only needs to maintain the mapping relationship between the virtual address and the physical address. The virtual memory page mentioned in this application can be understood as dividing the virtual address into multiple address pages, each address page is a virtual memory page. Usually, the virtual memory page has a mapping relationship with the physical memory page. When a process needs to read data, it can first determine the virtual memory page corresponding to the data, and determine the physical memory page that stores the data based on the mapping relationship between the virtual memory page and the physical memory page. Then, the physical address that stores the data can be determined, and the data can be read from the memory based on the physical address.

[0057] Memory management unit (MMU): responsible for the conversion of virtual addresses to physical addresses, memory protection and other functions.

[0058] Accelerator or acceleration device: A heterogeneous device with independent memory that can perform high-performance computing, that is, a device that includes multiple or multiple processors.

[0059] The method provided in the present application can be deployed in various chips or processors that can process data in memory, and can be used to implement accelerators and improve memory bandwidth.

[0060] Specifically, it can be applied to various electronic devices, such as various terminals or servers, etc., in which memory is set. The electronic device can also be called a memory management device or a memory management apparatus, etc. For example, the terminal can include but is not limited to a mobile phone, a tablet personal computer (TPC), a media player, a smart TV, a laptop computer (LC), a personal digital assistant (PDA), a personal computer (PC), a camera, a video camera, a smart watch, a wearable device (WD) or an autonomous driving vehicle, etc., and the embodiment of the present application does not limit this. The server can specifically include a distributed server, a cloud server or a centralized server, etc., and the present application does not limit this.

[0061] Typically, a device may be equipped with an operating system (OS). For example, a conventional architecture equipped with an OS may be as follows: Figure 1 shown.

[0062] like Figure 1 As shown, the device 100 can be logically divided into a hardware layer 21, an operating system (OS) 161, and an application layer 31, wherein the operating system can also be called a kernel layer.

[0063] The hardware layer 21 may include hardware resources such as a central processing unit (CPU) 101, a microcontroller unit (MCU) 103, a graphics processing unit (GPU) 111, an embedded neural network processor (NPU) 107, a sensor 114, and a positioning module 150.

[0064] The application layer 31 includes one or more applications, such as application 163. Application 163 can be any type of application, such as a social application, an e-commerce application, a browser, etc.

[0065] The operating system 161 , as software middleware between the hardware layer 21 and the application layer 31 , is a computer program that manages and controls hardware and software resources.

[0066] In one embodiment, operating system 161 includes kernel 23 , hardware abstraction layer (HAL) 25 , libraries and runtime 27 , and framework 29 .

[0067] The kernel 23 is used to provide underlying system components and services, such as power management, memory management, thread management, hardware drivers, etc.; the hardware drivers include accelerator drivers, sensor drivers, positioning module drivers, etc.

[0068] The hardware abstraction layer 25 is a package of the kernel driver, providing an interface to the framework 29 and shielding the implementation details of the lower layer. The hardware abstraction layer 25 runs in the user space, while the kernel driver runs in the kernel space.

[0069] The library and runtime 27 is also called the runtime library, which provides the required library files and execution environment for the executable program at runtime. The library and runtime 27 includes runtime (ART) 271 and library 273. The runtime 271 can convert the bytecode of the application into a virtual machine or virtual machine instance of machine code. The library 273 can provide a program library that supports the executable program at runtime, including but not limited to a browser engine (such as webkit), a script execution engine (such as a JavaScript engine) or a graphics processing engine.

[0070] The framework 27 is used to provide various basic common components and services for the application programs in the application layer 31, such as window management, location management, etc. The framework 27 may include a phone manager 291, a resource manager 293, a location manager 295, and the like.

[0071] The functions of each component of the operating system 161 described above can be implemented by a processor (such as a CPU, GPU, or NPU, etc.) executing a program stored in the memory 105. The method provided in the present application can be executed by a processor with data processing capabilities such as a CPU, GPU, or NPU in a device.

[0072] Those skilled in the art will appreciate that the device 100 may include Figure 1 Fewer or more components than shown, Figure 1 The device shown only includes components that are more relevant to the multiple implementations disclosed in the embodiments of the present application.

[0073] Based on the aforementioned Figure 1 In the structure shown, during the operation of the device, such as when starting a system application or an application installed in the device, it is necessary to start or switch based on the application data. Figure 1It can be seen that multiple application programs (referred to as "applications") can be installed on a device, and it is possible to switch between multiple applications or between multiple scenarios of an application, such as different functions or interfaces of an application. When a device switches application scenarios, including switching between multiple applications or switching between multiple scenarios within an application, the device memory involves the operation of multiple modules, including memory allocation, and memory reading and writing. Therefore, in the application startup or switching scenario, the data generated by the application needs to be processed in the memory, such as writing or reading.

[0074] In combination with the above Figure 1 The device structure shown introduces the system architecture of the method provided in this application.

[0075] See also Figure 2 , a schematic diagram of a system architecture provided in this application.

[0076] Based on the memory calling process, the system architecture provided by this application can be divided into three layers, such as Figure 2 The application layer, kernel layer, and hardware layer shown in are introduced below respectively.

[0077] The method provided in this application can be deployed in kernel state through an accelerator driver to provide a calling interface for the application layer, such as Figure 1 As shown in the collapse interface, the application can call the collapse interface (or replace it with other interface names) to implement the accelerator driver. After the accelerator driver is called, it can scan the same data page and merge the virtual memory page and the physical memory page. The hardware part can provide hardware support for the accelerator driver, and the accelerator can be implemented through the CPU, GPU or NPU processor of the hardware part.

[0078] Specifically, at the application layer, a system application, such as an AI framework or other applications, may call the collapse interface to perform memory optimization for input data.

[0079] Among them, AI framework (a software framework) can specifically include but is not limited to TensorFlow, Pytorch, Mindspore or other heterogeneous applications encoded in other ways, and support programming of accelerator devices.

[0080] Optionally, at the application layer, approximate preprocessing may be performed, that is, approximate processing may be performed on the input data, and the number of pages with the same data may be increased under the premise that the impact on the calculation result is acceptable.

[0081] In the kernel layer, after the collapse interface is called, the accelerator driver can be implemented. The accelerator driver is responsible for interacting with the accelerator device and managing the accelerator local memory. It can be implemented by the GPU or NPU. Specifically, it can scan the physical memory pages with the same data and merge the VA-PA mapping based on the scan results.

[0082] The hardware may specifically include processors such as CPU, GPU or NPU, and may also include memory or storage, etc. The memory optimization solution provided in this application may be executed by a processor with data processing capability such as CPU, GPU or NPU, thereby reducing memory usage and increasing memory bandwidth.

[0083] It can be understood that the method provided in the present application can be executed by a processor by being deployed on an accelerator.

[0084] The following is an introduction to the method flow provided by this application.

[0085] See also Figure 3 , a flow chart of a memory management method provided by the present application is as follows.

[0086] 301. Obtain input data, where the input data is stored in the memory as multiple physical memory pages.

[0087] The input data is stored in the memory, and the physical address of the memory storing the input data can be divided into multiple physical memory pages, or the address of the memory can be indicated as multiple physical memory pages, and the multiple physical memory pages have a mapping relationship with multiple virtual memories. For example, a mapping table (of course, it can also be a mapping diagram or other mapping data, etc.) can be pre-set, and the mapping table includes the mapping relationship between the virtual memory page and the physical memory page.

[0088] The input data may specifically include data generated by the application, data required for the application to run, or data input by the user, etc. For example, in one possible scenario, the input data may include a sparse matrix of a neural network, which is a matrix corresponding to the parameters in the neural network, such as a weight matrix or a structural parameter matrix, etc. Generally, the larger the scale of a neural network, the more parameters it has. Through the method provided in this application, a large number of memory pages occupied by the neural network can be optimized, thereby improving memory throughput and improving the data processing capability of the device.

[0089] In a possible implementation, after obtaining the input data, the data mapped by multiple virtual memory pages can also be corrected by an approximation algorithm. The approximation algorithm is an algorithm for calculating replaceable approximate values ​​of data. For example, multiple virtual memory pages (referred to as the first virtual memory page for ease of distinction) are corrected to the same value when mapped to the data in the memory, thereby increasing the number of virtual memory pages with the same data mapped to the memory, so that more physical memory pages can be merged or released later.

[0090] Optionally, an approximate algorithm can be used to calculate the same value of the data mapped to the memory by the multiple first virtual memory pages, and the same value can be verified. If the verification is successful, the data in the memory mapped by the multiple virtual memory pages will be corrected to the same value. Therefore, the data mapped to the memory by each virtual memory page can be corrected by an approximate algorithm, thereby increasing the number of virtual memory pages mapped with the same data, so that more physical memory pages can be merged later, thereby improving.

[0091] In addition, if the verification for the same value fails, it can be determined whether the termination condition is met, such as the type of the adjusted approximate algorithm exceeds the preset number, or the correction time exceeds the preset time. If the termination condition is met, the data mapped by the virtual memory page that has not been verified can be rolled back, and the calculation of the same value for the virtual memory page is stopped. If the termination condition is not met, the approximate algorithm can be adjusted, and the same value of the data mapped by the multiple first virtual memory pages can be recalculated by the adjusted approximate algorithm, and the verification is continued, and so on.

[0092] Optionally, the same value may include a value in the input data or data mapped to the memory by one of the first virtual memory pages, etc. Thus, the final same value is consistent with the distribution law of the input data, thereby improving the practicality of the data.

[0093] Specifically, the method of verifying the same value may include running an application program that needs to use the input data, using the application program to verify the input data, etc., so as to finally obtain corrected and usable data.

[0094] 302. Map at least two virtual memory pages among the multiple virtual memory pages to the same physical memory page.

[0095] Subsequently, each memory page can be scanned to see whether it includes a physical memory page that stores the same data, and two or more (i.e., at least two) virtual memory pages pointing to the same data can be mapped to the same physical memory page, or physical memory pages that store the same data can be merged so that two or more virtual memory pages are mapped to the same physical memory page, which is called the first physical memory page for easy distinction.

[0096] The same physical memory page can be the physical memory page originally mapped by one of the at least two virtual memories, or it can be a new physical memory page generated based on the same value obtained by the aforementioned calculation, or it can be a new physical memory page generated by copying one of the physical memory pages, etc. The specific details can be determined based on the actual application scenario, and this application does not limit this.

[0097] Therefore, after mapping two or more virtual memory pages to the same physical memory page, that is, two or more virtual memory pages only need to occupy one physical memory page. Compared with the one-to-one mapping relationship between virtual memory pages and physical memory pages, the physical memory pages mapped by multiple virtual memory pages can be reduced, thereby reducing memory usage and releasing memory for storing duplicate data, thereby improving the effective utilization of memory and improving memory data throughput.

[0098] In one possible scenario, after multiple virtual pages are mapped to the same physical memory page, if any one of the multiple virtual memory pages needs to be called, data can be read from the same physical memory page. Therefore, when any virtual memory page mapped to the same physical memory page is called, the data stored in the common physical memory page can be read, thereby realizing data reading when multiple virtual memory pages are mapped to the same physical memory page.

[0099] In a possible implementation, at least one second physical memory page can also be released, and the second physical memory page is the physical memory page that is not mapped by the virtual memory page after at least two virtual memory pages are mapped to the same physical memory page. It can be understood that after at least two virtual memory pages are mapped to the same physical memory page, one or more physical memory pages that do not have mappings can be freed up. For example, before 5 virtual memory pages are mapped to the same physical memory page, the 5 virtual memories are mapped to 5 physical memory pages, and after the 5 virtual memory pages are mapped to the same physical memory page, 4 physical memory pages are freed up and are not mapped. At this time, the 4 physical memory pages can be released, thereby reducing the memory usage, increasing the available amount of memory, and increasing the data throughput of the memory, thereby increasing the memory bandwidth.

[0100] In one possible scenario, when multiple virtual memory pages are mapped to the same physical memory page, in order to avoid the data of the physical memory page being modified, which would cause the mapped data to be unavailable when one or more of the virtual memory pages are called, the first physical memory page can be set to a read-only state, that is, only reading the data in the first physical memory page is allowed, but the data in the first physical memory page cannot be modified.

[0101] In one possible scenario, after mapping at least two virtual memory pages to the same physical memory page, if the data mapped by one of the virtual memory pages (referred to as the second virtual memory page for ease of distinction) needs to be modified, the data can be read from the memory corresponding to the first physical memory page, and the read data can be copied to the memory corresponding to the other physical memory page (referred to as the third physical memory page for ease of distinction), the data in the third physical memory page is modified, and the second virtual memory page is mapped to the third physical memory page. Therefore, when the data mapped by one of the virtual memory pages mapped to the same physical memory page needs to be modified, it can be modified by copying, so that the data mapped by other virtual memory pages will not be changed.

[0102] For example, if virtual memory page 1, virtual memory page 2, and virtual memory page 3 are all mapped to physical memory page 1, physical memory page 1 can be set to read-only state, that is, only reading is allowed but not modification, so as to avoid data modification in the physical memory page causing incorrect data mapping of multiple virtual memory pages. When the application calls the data of virtual memory page 2 and modifies it, the data of physical memory page 1 can be read and copied to physical memory page 2. At this time, virtual memory page 2 can be mapped to physical memory page 2 and modified, so that when the data mapped by virtual memory page 2 needs to be modified, the modification of the data mapped by virtual memory page 1 and virtual memory page 3 is avoided, thereby improving data security and improving system operation reliability.

[0103] The above is an introduction to the method flow provided by the present application. The following is an illustrative further introduction to the method flow provided by the present application in combination with specific application scenarios.

[0104] See also Figure 4 , a flow chart of another memory management method provided by the present application is described as follows.

[0105] 401. Select an approximate algorithm.

[0106] After the start, that is, after determining the data that needs to be memory managed, an approximation algorithm is selected.

[0107] Optionally, the approximate algorithm may include, but is not limited to, one or more of the following: a greedy algorithm, a local search, a linear programming algorithm, or a dynamic programming algorithm.

[0108] In the initial correction stage, such as the first approximation operation, one of the algorithms can be randomly selected as the approximation algorithm, or a pre-set algorithm can be selected, etc. The specific selection can be based on the actual application scenario.

[0109] 402. Approximately correct the input data at page granularity.

[0110] Generally, for some data that is sparse, will not be modified, or may not be used repeatedly, the data can be approximately corrected, that is, corrected to a usable approximate value.

[0111] Specifically, the approximate value of the data in each page can be calculated by an approximate algorithm, and the data can be corrected to the approximate value. Generally, the data of the entire page can be approximated to another page or the same value in the input data range by using an approximate algorithm according to the granularity of the virtual address page alignment.

[0112] 403. Verify the calculation result. If it passes, execute step 404. If it fails, execute step 401.

[0113] Optionally, there may be multiple ways to perform verification, such as directly performing calculations using an algorithm that requires the data after the approximate operation to verify whether the data is available in the algorithm; or substituting the data after the approximate operation into an application that needs to call this data for calculation, and determining whether the application can run normally based on the calculation results.

[0114] For example, the data after the approximate operation can be substituted into an application that needs to call this data for calculation, and the calculation result can be compared with the running result before the approximate operation. If the results are consistent or the difference is small and within the error range, it means that the approximate operation has little effect on the result, and the subsequent memory merge can continue. If the results are inconsistent or the difference is large, step 401 can be continued, that is, a new approximate algorithm can be selected for re-correction and verification until the verification passes or the approximate algorithm is exhausted.

[0115] 404. System call.

[0116] Once the approximation is performed and verified, a system call can be made to perform the subsequent steps.

[0117] The method provided in this application can be deployed in the system through an accelerator driver. After completing the approximate operation and verification, the accelerator driver can be called to perform subsequent processing steps for the memory. When making a system call, the kernel layer can be entered from the application layer, and the starting address and size can be passed in to facilitate the subsequent merging of the same data pages.

[0118] 405. Scan memory pages in parallel.

[0119] After making a system call, the data stored in the physical memory pages corresponding to each virtual memory page can be scanned through the system process. For example, the data stored in the physical memory mapped by each virtual memory page can be scanned. In addition, the memory scan can be performed in parallel, such as scanning the data stored in the physical memory pages mapped by multiple virtual memory pages at the same time.

[0120] 406. Compare the data of the memory pages.

[0121] During the process of scanning memory pages, the data differences between the memory pages can be compared.

[0122] 407. Determine whether there are identical pages. If not, continue with step 406. If yes, proceed to step 408.

[0123] After comparing the data between the memory pages, it can be determined whether there are identical pages, i.e., physical memory pages storing identical data. If there are physical memory pages storing identical data, the memory merging can be continued, i.e., step 408 is executed. If there are no physical memory pages storing identical data, step 406 can be continued, i.e., the data stored in each physical memory page is continuously compared.

[0124] 408. Merge virtual memory and physical memory mapping.

[0125] In the case of identical pages, memory merging can be performed.

[0126] For example, physical memory pages including the same data may be merged, such as adjusting the mapping relationship of multiple virtual memory pages mapped to physical memory pages storing the same data to map to the same physical memory page, thereby reducing the physical memory pages occupied by the multiple virtual memory pages when mapping.

[0127] 409. Set read-only protection.

[0128] After multiple virtual memory pages are mapped to the same physical memory page, the physical memory page can be set to a read-only state, thereby preventing the data in the physical memory page from being modified.

[0129] For example, when an application needs to modify the data corresponding to its virtual memory page, it can trigger a pagefault (a data processing instruction) to map this page to a new physical page to avoid the situation where the data of one page is modified and the data of other pages are also changed, resulting in incorrect calculation results.

[0130] 410. Release duplicate physical pages.

[0131] After mapping multiple virtual memory pages to the same physical memory page, the freed physical memory page can be released, thereby reducing memory consumption.

[0132] For example, if three virtual memory pages are mapped to the same physical memory page, the three virtual memory pages only need to occupy one physical memory page, and the two free physical memory pages can be released, thereby reducing the physical memory occupied by the virtual memory pages.

[0133] 411. Determine whether to traverse all memory pages. If not, execute step 406. If yes, terminate the operation.

[0134] After each memory merge is completed, it can be determined whether all memory pages that need to be defragmented have been traversed. If so, the memory defragmentation can be stopped. If not, the data of each memory page can be continued to be compared, that is, step 406 is continued.

[0135] In the implementation mode of the present application, the number of memory pages storing the same data can be increased by approximate operations without affecting the calculation results, thereby increasing the sparsity of data and increasing the proportion of identical data, providing a basis for further performance optimization. As a result, more memory pages can be merged during subsequent memory merging, thereby reducing memory usage, releasing more physical memory pages, and improving memory throughput.

[0136] The method provided in this application can usually be executed by a high-throughput processor, such as a GPU or an NPU. The following takes the method provided in this application as an example of an NPU to introduce a specific application scenario. The NPU mentioned below can also be replaced by a GPU or a CPU, etc., which will not be repeated below.

[0137] See also Figure 5 , which is the specific architecture when the method provided in this application is executed by NPU.

[0138] At the application layer, an approximate decision machine can usually perform approximate operations, that is, perform approximate operations on data that need to be memory optimized, and then call the collapse interface. First, the NPU driver can be started, and specifically the memory management module can be started to manage the NPU memory, thereby improving the data throughput of the NPU memory.

[0139] Specifically, the process of memory management for NPU can be divided into multiple parts, such as approximate correction of data and calling system calls to perform memory optimization, which are introduced below.

[0140] 1. Approximate correction

[0141] The process of approximating the data input to the NPU can be as follows: Figure 6 shown.

[0142] For each continuous data segment, according to the granularity of virtual address page alignment, each page is either not modified or an approximation algorithm is used to approximate the data of the entire page to another page in the input data range or a fixed value. In this embodiment, the fixed value is 0 (it can also be other values), and then it is verified whether the impact of the result is acceptable (such as running application verification or calculating the approximated value, etc.). If it is acceptable, the approximation correction is performed. If it is unacceptable, the approximation operation is rolled back.

[0143] Therefore, in the implementation manner of the present application, an approximation algorithm can be used to approximate data at the virtual page alignment granularity, thereby increasing the sparsity of the data and the proportion of data similarity without affecting the calculation results, thereby providing a basis for further performance optimization.

[0144] 2. Call system calls to perform memory optimization

[0145] For example, the process of optimizing NPU memory can be as follows: Figure 7 shown.

[0146] After attempting to approximately correct the data segment, execute it, call the collapse interface, enter the kernel state, and concurrently scan and compare to find pages with all 0s, all certain values, and data that are exactly the same as other pages. Map the page to the physical page corresponding to the first page of the pages with exactly the same data, set read-only protection and copy-on-write, and release the physical pages corresponding to other pages. That is, you can map pages with all 0s, all fixed values, and data that are the same as other virtual pages to the physical page corresponding to the first page, and release the physical pages corresponding to other pages.

[0147] Therefore, in the implementation mode of the present application, the data can be corrected through approximate operations, thereby increasing the physical memory pages of the same data in the memory, so that when performing memory management, more memory pages with the same data can be merged, thereby releasing more memory and improving the data throughput of the memory. The method provided by the present application can break through the hardware computing bandwidth with a software solution, is applicable to a large number of hardware, and has strong generalization capabilities; it is transparent to users and does not require algorithm modification; it can reduce memory consumption, reduce the cache bandwidth pressure of heterogeneous accelerators, and better return the bandwidth of the computing unit. It can also automatically divide and execute page merges in parallel, reducing the time of page merges and improving end-to-end performance.

[0148] The above describes the process of the method provided in the present application, and the following describes the structure of the device for executing the method.

[0149] See also Figure 8 , a schematic diagram of the structure of a memory management device provided in the present application, the memory management device can be used to perform the aforementioned Figure 3-Figure 7 The steps in the method shown in .

[0150] The memory management device may specifically include:

[0151] The acquisition module 801 is used to acquire input data. The input data is stored in a memory. The address of the memory indicates a plurality of physical memory pages. The plurality of physical memory pages have a mapping relationship with a plurality of virtual memory pages. The plurality of virtual memory pages are used to read the input data when they are called.

[0152] The memory management module 802 is used to map at least two virtual memory pages among multiple virtual memory pages to the first physical memory page, the at least two virtual memory pages indicate the same data stored in the memory, and when the at least two virtual memory pages are called, they indicate to read the data in the first physical memory page.

[0153] In a possible implementation, the memory management module 802 may also be configured to read data from the first physical memory page if any one of the at least two virtual memory pages is called.

[0154] In a possible implementation, the memory management module 802 is further used to correct the data mapped by multiple first virtual memory pages in the multiple virtual memory pages to the same value by using an approximate algorithm before mapping at least two virtual memory pages in the multiple virtual memory pages to the first physical memory page.

[0155] In a possible implementation, the memory management module 802 is further used to: calculate the same value of data mapped by multiple first virtual memory pages through an approximate algorithm; verify the same value; if the verification passes, correct the data mapped by multiple first virtual memory pages to the same value.

[0156] In one possible implementation, the memory management module 802 is also used to: if the verification of the same value fails, adjust the approximation algorithm, and recalculate the same value of the data mapped by multiple first virtual memory pages through the adjusted approximation algorithm; or, if the verification of the same value fails, roll back the data corresponding to the first virtual memory page that fails the verification, and stop calculating the same value.

[0157] In a possible implementation, the same value includes a value included in the input data or data in one of the first virtual memory pages mapped memory.

[0158] In a possible implementation, the memory management module 802 is further used to: release the physical memory corresponding to at least one second physical memory page, where the at least one second physical memory page is a physical memory page that is not mapped by the virtual memory page after mapping at least two virtual memory pages to the first physical memory page.

[0159] In a possible implementation, the memory management module 802 is further configured to set the first physical memory page to a read-only state, wherein when the state of the first physical memory page is the read-only state, the data in the first physical memory page is not allowed to be modified.

[0160] In a possible implementation, the memory management module 802 is also used to: when the data mapped by the second virtual memory page is modified, copy the data read from the memory corresponding to the first physical memory page to the memory corresponding to the third physical memory page, the second virtual memory page being the virtual memory page mapped to the first physical memory page; modify the data in the memory corresponding to the third physical memory page; and map the second virtual memory page to the third physical memory page.

[0161] In a possible implementation, the input data includes a sparse matrix of the neural network, and the sparse matrix includes a matrix corresponding to parameters in the neural network.

[0162] like Fig. 9 FIG. 1 is a schematic diagram of the hardware structure of a memory management device 90 provided in an embodiment of the present application. The memory management device 90 can be used to implement the aforementioned Figures 3 to 7 The steps of the method.

[0163] Fig. 9 The memory management device 90 shown may include: a processor 901 , a memory 902 , a communication interface 903 , and a bus 904 . The processor 901 , the memory 902 , and the communication interface 903 may be connected via the bus 904 .

[0164] The processor 901 is the control center for generating the memory management device 90, and may be a general-purpose central processing unit (CPU) or other general-purpose processors. The general-purpose processor may be a microprocessor or any conventional processor, such as a GPU or an NPU, and may be adaptively configured according to the actual application scenario.

[0165] As an example, the processor 901 may include one or more CPUs, and may also include other processors, such as Fig. 9 The CPU, NPU or GPU shown in .

[0166] The memory 902 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to these.

[0167] In a possible implementation, the memory 902 may exist independently of the processor 901. The memory 902 may be connected to the processor 901 via a bus 904 and used to store data, instructions, or program codes. When the processor 901 calls and executes the instructions or program codes stored in the memory 902, the method provided in the embodiment of the present application can be implemented, for example, Figures 3 to 7 The memory management method shown.

[0168] In another possible implementation, the memory 902 may also be integrated with the processor 901 .

[0169] The communication interface 903 is used for the memory management device 90 to connect with other devices through a communication network, and the communication network may be Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc. The communication interface 903 may include a receiving unit for receiving data and a sending unit for sending data.

[0170] The bus 904 may be an industry standard architecture (ISA) bus, a peripheral component interconnect (PCI) bus, or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig. 9 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0171] It should be pointed out that Fig. 9The structure shown in the figure does not constitute a limitation on the memory management device 90, except Fig. 9 In addition to the components shown, the memory management device 90 may include more or fewer components than shown, or combine certain components, or arrange the components differently.

[0172] Through the description of the above implementation methods, the technicians in the relevant field can clearly understand that the present application can be implemented by means of software plus necessary general hardware, and of course, it can also be implemented by special hardware including special integrated circuits, special CPUs, special memories, special components, etc. In general, all functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structures used to implement the same function can also be various, such as analog circuits, digital circuits or special circuits. However, for the present application, software program implementation is a better implementation method in more cases. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer floppy disk, a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc., including a number of instructions to enable a memory management device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0173] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0174] In an embodiment of the present application, a computer-readable storage medium is also provided, in which a program for training a model or performing an inference task is stored. When the program is run on a computer, the computer performs the above-mentioned Figures 3 to 7 All or part of the steps in the method described in the embodiment shown in FIG.

[0175] The present application also provides a digital processing chip. The digital processing chip integrates a circuit and one or more interfaces for implementing the above-mentioned processor or the functions of the processor. When the digital processing chip integrates a memory, the digital processing chip can complete the above-mentioned Figures 3 to 7 The method steps of any one or more embodiments in the corresponding embodiments. When the digital processing chip does not have an integrated memory, it can be connected to an external memory through a communication interface. The digital processing chip implements the method steps of any one or more embodiments in the above embodiments according to the program code stored in the external memory.

[0176] A computer program product is also provided in the embodiment of the present application, and the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server, or data center. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or a data center that includes one or more available media integrations. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk (SSD)), etc.

[0177] A person skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium, which can include: ROM, RAM, disk or CD, etc.

[0178] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described here can be implemented in a sequence other than the content illustrated or described here. The term "and / or" in the present application is only a kind of association relationship describing the associated objects, indicating that there can be three kinds of relationships, for example, A and / or B can be represented: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are an "or" relationship. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or modules is not necessarily limited to those steps or modules clearly listed, but may include other steps or modules that are not clearly listed or inherent to these processes, methods, products or devices. The naming or numbering of the steps in this application does not mean that the steps in the method flow must be executed in the time / logical sequence indicated by the naming or numbering. The named or numbered process steps can change the execution order according to the technical purpose to be achieved, as long as the same or similar technical effects can be achieved. The division of modules in this application is a logical division. There may be other division methods when it is implemented in actual applications. For example, multiple modules can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some ports, and the indirect coupling or communication connection between modules can be electrical or other similar forms, which are not limited in this application. In addition, the modules or submodules described as separate components may or may not be physically separated, may or may not be physical modules, or may be distributed in multiple circuit modules, and some or all of the modules can be selected according to actual needs to achieve the purpose of the present application solution.

Claims

1. A memory management method, characterized in that: The method comprises: Acquire input data, wherein the input data is stored in a memory, an address of the memory indicates a plurality of physical memory pages, the plurality of physical memory pages have a mapping relationship with a plurality of virtual memory pages, and the plurality of virtual memory pages are used to read the input data when being called; At least two virtual memory pages among the plurality of virtual memory pages are mapped to a first physical memory page, wherein the data indicated by the at least two virtual memory pages and stored in the memory are the same.

2. The method according to claim 1, characterized in that: The method further comprises: If any one of the at least two virtual memory pages is called, data is read from the first physical memory page.

3. The method according to claim 1 or 2, characterized in that: Before mapping at least two of the plurality of virtual memory pages to the first physical memory page, the method further includes: By using an approximate algorithm, data mapped by multiple first virtual memory pages in the multiple virtual memory pages are corrected to be the same value.

4. The method according to claim 3, characterized in that The method of correcting the data mapped by the plurality of first virtual memory pages in the plurality of virtual pages to the same value by using an approximate algorithm further comprises: Calculating the same value of the data mapped by the plurality of first virtual memory pages by using the approximate algorithm; verifying the same value; If the verification of the same value is successful, the data mapped by the plurality of first virtual memory pages are corrected to the same value.

5. The method according to claim 4, characterized in that The method further comprises: If the verification of the identical value fails, adjusting the approximate algorithm, and recalculating the identical value of the data mapped by the plurality of first virtual memory pages by using the adjusted approximate algorithm; Alternatively, if the verification of the identical value fails, the data corresponding to the first virtual memory page that fails the verification is rolled back, and the calculation of the identical value is stopped.

6. The method according to any one of claims 3 to 5, characterized in that: The same value includes a value included in the input data or one of the first virtual memory pages mapping the data in the memory.

7. The method according to any one of claims 1 to 6, characterized in that The method further comprises: The first physical memory page is set to a read-only state, wherein when the state of the first physical memory page is the read-only state, data in the first physical memory page is not allowed to be modified.

8. The method according to claim 7, characterized in that The method further comprises: When data mapped by the second virtual memory page is modified, copying data read from the memory corresponding to the first physical memory page to the memory corresponding to the third physical memory page, the second virtual memory page being a virtual memory page mapped to the first physical memory page; Modifying data in the memory corresponding to the third physical memory page; The second virtual memory page is mapped to the third physical memory page.

9. The method according to any one of claims 1 to 8, characterized in that The method further comprises: The physical memory corresponding to at least one second physical memory page is released, where the at least one second physical memory page is a physical memory page that is not mapped by the virtual memory page after the at least two virtual memory pages are mapped to the first physical memory page.

10. The method according to any one of claims 1 to 9, characterized in that The input data includes a sparse matrix of a neural network, and the sparse matrix includes a matrix corresponding to parameters in the neural network.

11. A memory management device, characterized in that: The device comprises: An acquisition module, used for acquiring input data, wherein the input data is stored in a memory, the address of the memory indicates a plurality of physical memory pages, the plurality of physical memory pages have a mapping relationship with a plurality of virtual memory pages, and the plurality of virtual memory pages are used for reading the input data when being called; A memory management module is used to map at least two virtual memory pages among the multiple virtual memory pages to a first physical memory page, the at least two virtual memory pages indicate that the data stored in the memory is the same, and when the at least two virtual memory pages are called, they indicate to read the data in the first physical memory page.

12. The device according to claim 11, characterized in that The memory management module is further configured to read data from the first physical memory page if any one of the at least two virtual memory pages is called.

13. The device according to claim 12, characterized in that The memory management module is further used to correct the data mapped by multiple first virtual memory pages in the multiple virtual memory pages to the same value by using an approximate algorithm before mapping at least two virtual memory pages in the multiple virtual memory pages to the first physical memory page.

14. The device according to claim 13, characterized in that The memory management module is further used for: Calculating the same value of the data mapped by the plurality of first virtual memory pages by using the approximate algorithm; verifying the same value; If the verification of the same value is successful, the data mapped by the plurality of first virtual memory pages are corrected to the same value.

15. The device according to claim 14, characterized in that The memory management module is further used for: If the verification of the identical value fails, adjusting the approximate algorithm, and recalculating the identical value of the data mapped by the plurality of first virtual memory pages by using the adjusted approximate algorithm; Alternatively, if the verification of the identical value fails, the data corresponding to the first virtual memory page that fails the verification is rolled back, and the calculation of the identical value is stopped.

16. The device according to any one of claims 13 to 15, characterized in that The same value includes a value included in the input data or one of the first virtual memory pages mapping the data in the memory.

17. The device according to any one of claims 12 to 16, characterized in that The memory management module is further used to set the first physical memory page to a read-only state, wherein when the state of the first physical memory page is the read-only state, the data in the first physical memory page is not allowed to be modified.

18. The device according to claim 17, characterized in that The memory management module is further used for: When data mapped by the second virtual memory page is modified, copying data read from the memory corresponding to the first physical memory page to the memory corresponding to the third physical memory page, the second virtual memory page being a virtual memory page mapped to the first physical memory page; Modifying data in the memory corresponding to the third physical memory page; The second virtual memory page is mapped to the third physical memory page.

19. The device according to any one of claims 12 to 18, characterized in that The memory management module is further used for: The physical memory corresponding to at least one second physical memory page is released, where the at least one second physical memory page is a physical memory page that is not mapped by the virtual memory page after the at least two virtual memory pages are mapped to the first physical memory page.

20. The device according to any one of claims 12 to 19, characterized in that The input data includes a sparse matrix of a neural network, and the sparse matrix includes a matrix corresponding to parameters in the neural network.

21. A memory management device, characterized in that: include: A memory storing executable program instructions; and A processor, wherein the processor is used to be coupled with the memory, read and execute instructions in the memory, and trigger the client to implement the method according to any one of claims 1 to 10.

22. A chip, characterized in that: include: A processor and a memory, wherein the processor is used to call and execute instructions stored in the memory, so that the chip implements the method according to any one of claims 1 to 10.

23. A computer-readable storage medium, characterized in that: The method comprises instructions, which, when executed on a computer, cause the computer to perform the method according to any one of claims 1 to 10.

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