Memory access method and related equipment

Abstract

The embodiment of the invention provides a memory access method and related equipment, and the method comprises the steps: obtaining a prefetch request which is a prediction request generated by a processor and an extraction request obtained by extracting a request sent to a network-on-chip by the processor; wherein the prefetching request at least comprises a memory address and control information; sending the prefetching request to a prefetching network; based on the prefetching request, reading prefetching data corresponding to the prefetching request from the memory; judging whether the memory address of the access request sent to the memory by the processor is matched with the memory address of the prefetching request or not; and if the memory address of the access request sent to the memory by the processor is matched with the memory address of the prefetching request, returning the prefetching data to the access request. The embodiment of the invention can improve the data transmission efficiency.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a memory access method and related devices. Background Art

[0002] In the design of Network-on-Chip (NOC), the efficiency of data transmission between processors (such as CPUs) and memory, especially bandwidth and latency, has always been a core challenge faced by designers. In recent years, as the progress of semiconductor manufacturing processes has slowed down, the size of chips has continued to expand as the process matures, and many chip designs are approaching the physical limits of lithography technology. This large chip design not only increases the complexity of the design, but also causes data latency issues to become more and more significant, becoming the main bottleneck for latency when the processor accesses memory.

[0003] In this context, how to reduce latency to improve data transmission efficiency has become a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a memory access method and related devices to improve data transmission efficiency.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides a memory access method, comprising:

[0007] Obtaining a prefetch request, wherein the prefetch request is a prediction request generated by a processor and / or an extraction request obtained by extracting an access request sent by the processor to a memory; wherein the prefetch request includes at least a memory address and control information;

[0008] Based on the prefetch request, reading prefetch data corresponding to the prefetch request from the memory;

[0009] determining whether a memory address of an access request sent by the processor to the memory matches the memory address of the prefetch request;

[0010] If the memory address of the access request sent by the processor to the memory matches the memory address of the pre-fetch request, the pre-fetch data is returned to the processor as feedback data of the access request.

[0011] Optionally, if the memory address of the access request sent by the processor to the memory does not match the memory address of the pre-fetch request, the pre-fetched data is discarded.

[0012] Optionally, when the prefetch request is a prediction request generated by a processor and an extraction request obtained by extracting an access request sent by the processor to the memory, after the step of obtaining the prefetch request and before the step of reading prefetch data corresponding to the prefetch request from the memory based on the prefetch request, the method further includes:

[0013] De-duplicate prefetch requests with the same memory address;

[0014] Prefetch requests after deduplication based on prefetch network transmission.

[0015] Optionally, after the step of deduplicating the prefetch requests with the same memory address and before the step of prefetching the deduplicated prefetch requests based on the network transmission, the step further includes:

[0016] Based on the preset rule, a preset tag is configured for the prefetch request entering the prefetch network.

[0017] Optionally, the memory access method is adapted to a multi-chip device, and the pre-fetch request is transmitted across chips based on a pre-fetch network across chip lines; the step of transmitting the deduplicated pre-fetch request based on the pre-fetch network includes:

[0018] The pre-fetch request is sent from a sending end of a pre-fetch network cross-chip line in one chip to a receiving end of a pre-fetch network cross-chip line in another chip;

[0019] The sending end of the pre-fetch network cross-chip line is set at a position closest to all processors in the chip where the sending end is located, and the receiving end of the pre-fetch network cross-chip line is set at a position close to the memory in the chip where the receiving end is located.

[0020] Optionally, the step of prefetching the request after deduplication based on prefetching network transmission further includes:

[0021] The pre-fetch request is cached.

[0022] Optionally, the step of caching the pre-fetch request includes:

[0023] When the cached prefetch requests overflow, the new prefetch requests are discarded or replaced;

[0024] When the pre-fetch request is not sent to the memory within a preset time, the pre-fetch request is discarded.

[0025] Optionally, the priority of the prefetch request is lower than the priority of an access request sent by the processor to the memory.

[0026] Optionally, the pre-fetch network includes a weight selector for assigning different weight values ​​to different links or nodes in the pre-fetch network.

[0027] In a second aspect, an embodiment of the present application provides a memory access device, including:

[0028] an acquisition module, configured to acquire a pre-fetch request, wherein the pre-fetch request is a prediction request generated by a processor and / or an extraction request obtained by extracting an access request sent by the processor to a memory; wherein the pre-fetch request includes at least a memory address and control information;

[0029] A prefetch request control module is used to read prefetch data corresponding to the prefetch request from the memory based on the prefetch request; determine whether the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request; wherein, if the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request, the prefetch data is returned to the access request.

[0030] Optionally, the pre-fetch request control module includes: a reading module and a judging module;

[0031] The reading module is used to read the prefetch data corresponding to the prefetch request from the memory based on the prefetch request;

[0032] The judgment module is used to judge whether the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request; wherein, if the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request, the prefetch data is returned to the access request.

[0033] Optionally, if the memory address of the access request sent by the processor to the memory does not match the memory address of the pre-fetch request, the pre-fetched data is discarded.

[0034] Optionally, also include:

[0035] A deduplication module, used for deduplicating the pre-fetch request;

[0036] The transmission module is used for transmitting the deduplicated prefetch request based on the prefetch network.

[0037] Optionally, also include:

[0038] The marking module is used to configure a preset mark for the pre-fetch request entering the pre-fetch network based on a preset rule.

[0039] In a third aspect, an embodiment of the present application provides an electronic device comprising at least one memory and at least one processor, wherein the memory stores one or more computer executable instructions, and the processor calls the one or more computer executable instructions to execute the memory access method as described in the first aspect above.

[0040] In a fourth aspect, an embodiment of the present application provides a storage medium, which stores one or more computer-executable instructions. When the one or more computer-executable instructions are executed, the memory access method described in the first aspect above is implemented.

[0041] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising one or more computer executable instructions, which, when executed, implement the memory access method as described in the first aspect above.

[0042] An embodiment of the present application provides a memory access method and related equipment, wherein the memory access method includes: obtaining a prefetch request, wherein the prefetch request is a prediction request generated by a processor, and / or an extraction request obtained by extracting an access request sent by the processor to the memory; wherein the prefetch request includes at least a memory address and control information; based on the prefetch request, reading prefetch data corresponding to the prefetch request from the memory; determining whether the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request; if the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request, returning the prefetch data to the processor as feedback data of the access request.

[0043] It can be seen that the memory access method provided in the embodiment of the present application reads the prefetch data corresponding to the prefetch request from the memory based on the prefetch request, and then when the processor issues an access request, determines whether the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request. If the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request, it means that the processor requests the prefetch data that has been read from the memory before. At this time, the prefetch data can be directly returned to the processor as feedback data of the access request without accessing the slower memory, thereby reducing latency and improving data transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0045] Figure 1 It is an optional flow chart of the memory access method provided in the embodiment of the present application;

[0046] Figure 2 It is a schematic diagram of an optional structure of a CPU accessing a memory provided in an embodiment of the present application;

[0047] Figure 3 This is a schematic diagram of an optional structure of NOC network cross-chip transmission provided in an embodiment of the present application;

[0048] Figure 4 is another optional flow chart of the memory access method provided in the embodiment of the present application;

[0049] Figure 5 It is another optional flow chart of the memory access method provided in the embodiment of the present application;

[0050] Figure 6 It is a schematic diagram of an optional structure of pre-fetch network cross-chip transmission provided in an embodiment of the present application;

[0051] Figure 7 is a schematic diagram of an optional structure of a memory access device provided in an embodiment of the present application;

[0052] Figure 8 This is another optional structural diagram of the CPU accessing the memory provided in the embodiment of the present application;

[0053] Fig. 9 It is an optional block diagram of the electronic device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0055] As described in the background technology, in the design of Network-on-Chip (NOC), the data transmission efficiency between the processor (such as CPU) and the memory, especially the bandwidth and delay, has always been the core challenge faced by designers. In recent years, as the progress of semiconductor manufacturing technology has slowed down, the size of the chip has continued to expand with the increasing maturity of the process, and many chip designs are approaching the physical limits of lithography technology. This large chip design not only increases the complexity of the design, but also causes the data delay problem to become more and more significant, becoming the main bottleneck of the delay when the processor accesses the memory. In this context, how to reduce the delay to improve the efficiency of data transmission has become a technical problem that technicians in this field urgently need to solve.

[0056] Based on this, an embodiment of the present application provides a memory access method and related equipment, wherein the memory access method includes: obtaining a prefetch request, the prefetch request is a prediction request generated by a processor, and / or an extraction request obtained by extracting an access request sent by the processor to the memory; wherein the prefetch request includes at least a memory address and control information; based on the prefetch request, reading prefetch data corresponding to the prefetch request from the memory; determining whether the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request; if the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request, returning the prefetch data to the processor as feedback data of the access request.

[0057] It can be seen that the memory access method provided in the embodiment of the present application reads the prefetch data corresponding to the prefetch request from the memory based on the prefetch request, and then when the processor issues an access request, determines whether the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request. If the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request, it means that the processor requests the prefetch data that has been read from the memory before. At this time, the prefetch data can be directly returned to the processor as feedback data of the access request without accessing the slower memory, thereby reducing latency and improving data transmission efficiency.

[0058] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0059] refer to Figure 1 , Figure 1 is an optional flow chart of the memory access method provided in the embodiment of the present application. Figure 1 As shown, the memory access method may include the following steps:

[0060] Step S100, obtaining a pre-fetch request.

[0061] Wherein, the prefetch request includes at least a memory address and control information. The memory address refers to the address of the memory that the prefetch request needs to access, which specifies the specific location where data needs to be read or written from the memory. The memory controller can implement data access operations on the memory area accessed by the prefetch request based on the memory address. The control information is used to instruct the memory controller how to perform data access operations. It may include but is not limited to operation type, data size, priority, and control flags. Wherein, the operation type is used to indicate whether the request is a read operation or a write operation. For the prefetch request in this application, the operation type is a read operation because the purpose of prefetching is to obtain data in advance for subsequent use. The data size is used to specify the amount of data to be read or written. For the prefetch request in this application, the data size is the amount of data to be read.

[0062] The pre-fetch request is a prediction request generated by a processor, and / or an extraction request obtained by extracting an access request sent by the processor to the memory. Taking the processor as a CPU (Central Processing Unit) as an example, the pre-fetch request can come from a prediction inside the CPU, or from a normal access request sent by the CPU to the memory. The following explains these two sources respectively:

[0063] Prediction within the CPU means predicting the next instruction in advance based on prediction technology when the CPU is executing the current instruction. This process can be completed by the predictor inside the CPU, which predicts the next instruction based on some algorithms and historical data.

[0064] refer to Figure 2 , Figure 2 Schematic diagram of an optional structure of a CPU accessing a memory provided in an embodiment of the present application. Figure 2 As shown, the process of CPU accessing memory can be as follows: the CPU initiates an access request, which first passes through multiple levels of cache to minimize the number of direct memory accesses, thereby improving access efficiency. Specifically, when the CPU needs to access data, it will first search the highest level of cache. If there is a miss (that is, the required data is not in this level of cache), it will continue to search the next level of cache, and so on, until the required data is found or the bottom-level storage (such as memory) is reached. Among them, a relatively small number of storage units in the upper-level cache can map a relatively large number of storage units in the lower-level cache, and a relatively small number of storage units in the last-level cache can map a relatively large number of storage units in the memory; and, the upper-level cache has a faster data access speed than the lower-level cache, but the capacity of the upper-level cache is smaller than that of the lower-level cache.

[0065] In the CPU access process, if all the multi-level caches miss, the access request will enter the NOC network (Network on Chip), and the access request will be routed to the memory access proxy module. The memory access proxy module is responsible for converting the access request into a format suitable for memory access and sending it to the memory controller. The memory controller then sends the access request further to the memory for processing. The access request that needs to go through the above access process can be called a normal access request sent by the CPU to the memory.

[0066] In some cases, if the required data is located on different chips, the NOC network is also responsible for cross-chip transmission. Figure 3 , Figure 3 Schematic diagram of an optional structure of NOC network cross-chip transmission provided by an embodiment of the present application. Figure 3 As shown, the NOC network in DIE 0 is connected to the NOC network in DIE 1 through a PHY (Physical Layer) port to achieve communication between the NOC network in DIE 0 and the NOC network in DIE 1.

[0067] In an optional implementation, the memory address of the pre-fetch request has a smaller bit width than the memory address of the access request transmitted through the NOC network, for example, the bit width of the memory address may range from 32 to 64 bits. A smaller bit width may allow the pre-fetch request to occupy less bandwidth during transmission, thereby reducing the possibility of network congestion and improving data transmission efficiency.

[0068] The priority of the pre-fetch request is lower than the priority of the access request sent by the processor to the memory. That is, when the access requests A, A, B, and C sent by the processor to the memory need to access the memory at the same time as the pre-fetch request B, the priority of the access request A sent by the processor to the memory is higher than the priority of the pre-fetch request B. The access requests A, A, B, and C sent by the processor to the memory have different memory addresses from the pre-fetch request B.

[0069] Compared with the prefetch request B, the access request A sent by the processor to the memory is issued based on the current exact demand. Therefore, when the two conflict, in order to ensure the correct execution and performance of the program, the access request A sent by the processor to the memory needs to be processed first.

[0070] Continue to refer Figure 1 , execute step S200, based on the prefetch request, read the prefetch data corresponding to the prefetch request from the memory.

[0071] Based on the prefetch request, prefetch data corresponding to the prefetch request is read from the memory, and then when the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request, the prefetch data is returned to the processor as feedback data of the access request without accessing the slower memory, thereby reducing latency and further improving data transmission efficiency.

[0072] Continue to refer Figure 1 , execute step S300 to determine whether the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request.

[0073] If (that is, the memory address of the access request sent by the processor to the memory matches the memory address of the pre-fetch request), then step S400 is executed to return the pre-fetched data to the processor as feedback data of the access request. If the memory address of the access request sent by the processor to the memory matches the memory address of the pre-fetch request, it means that the processor is requesting the pre-fetched data that has been read from the memory before. At this time, the pre-fetched data can be directly returned to the processor as feedback data of the access request without accessing the slower memory, thereby reducing latency and improving data transmission efficiency.

[0074] For further reference, Figure 4 , Figure 4 FIG. 1 is another optional flow chart of the memory access method provided in the embodiment of the present application. Figure 4 As shown, if the memory address of the access request sent by the processor to the memory does not match the memory address of the pre-fetch request, step S500 is executed to discard the pre-fetched data. Specifically, when a new pre-fetch request arrives and the cache space is insufficient to accommodate all the data that needs to be pre-fetched, some data that has been pre-fetched but not yet used by the CPU can be discarded to make room for the new pre-fetch request.

[0075] It can be seen that the memory access method provided in the embodiment of the present application reads the prefetch data corresponding to the prefetch request from the memory based on the prefetch request, and then when the processor issues an access request, determines whether the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request. If the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request, it means that the processor requests the prefetch data that has been read from the memory before. At this time, the prefetch data can be directly returned to the processor as feedback data of the access request without accessing the slower memory, thereby reducing latency and improving data transmission efficiency.

[0076] In an alternative example, refer to Figure 5FIG. 2 shows another optional flow chart of the memory access method provided in the embodiment of the present application. Figure 5 As shown, after the step of obtaining the prefetch request and before the step of reading the prefetch data corresponding to the prefetch request from the memory based on the prefetch request, the method may further include:

[0077] Step S101, deduplication of prefetch requests with the same memory address.

[0078] Since the prefetch request is a prediction request generated from a processor and / or an extraction request obtained by extracting an access request sent by the processor to the memory, when the prefetch request is a prediction request generated from a processor and an extraction request obtained by extracting an access request sent by the processor to the memory, prefetch requests with the same memory address may arrive one after another in a short period of time, so it is necessary to deduplicate the prefetch requests with the same memory address, for example, the prefetch request that arrives first can be retained, and the prefetch request that arrives later can be discarded.

[0079] Step S102, pre-fetching the deduplicated pre-fetching request based on the pre-fetching network transmission.

[0080] Since the prefetch request entering the prefetch network belongs to the prefetch function, it is to obtain the data that may be needed in the future in advance to reduce the delay in actual access. At the same time, since there is a certain uncertainty in the prefetch process (such as whether the data will be actually used, network conditions, etc.), a certain degree of prefetch packet loss is allowed.

[0081] In addition, to optimize the delay of the pre-fetch network, the routing of the pre-fetch network can be simplified, and the transmission delay of data packets in the network can be reduced by reducing the complexity and level of routing. For example, a more direct routing path can be adopted, or the number of routing nodes can be reduced.

[0082] Furthermore, selectors can also be used, for example, "one-to-many" and "many-to-one" selectors can be used to optimize data transmission to reduce branching and merging of data during transmission, thereby reducing latency. Among them, a "one-to-many" selector means that a data source (or called a sender, source node) can transmit data to multiple data receiving ends (or called target nodes, terminals) at the same time. A "many-to-one" selector means that multiple data sources can transmit data to one data receiving end at the same time.

[0083] In an optional implementation, the step of prefetching the prefetch request after deduplication based on the prefetch network transmission may also include: caching the prefetch request. The embodiment of the present application caches the prefetch request, and when the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request, the prefetch data can be directly returned to the processor as feedback data of the access request without accessing the slower memory, thereby reducing latency and improving data transmission efficiency.

[0084] In a specific implementation, the step of caching the prefetch request may include: when the cached prefetch request overflows, discarding or replacing the new prefetch request; when the prefetch request is not sent to the memory within a preset time, discarding the prefetch request. That is to say, when a new prefetch request arrives, if the cache is full, these additional prefetch requests can be processed in the following two ways. One is to discard new prefetch requests that exceed the cache capacity. One is to use a certain replacement algorithm (such as LRU, LFU, etc.) to replace the prefetch requests already in the cache. In some cases, the prefetch request may not be sent to the memory within the expected time, causing the prefetch request to become outdated or invalid. To avoid system resources being occupied by invalid requests, if the prefetch request fails to be successfully sent to the memory within the preset time, it can be discarded.

[0085] The memory access method is adapted to a multi-chip device. In an optional implementation, the pre-fetch request is transmitted across chips based on a pre-fetch network cross-chip line; the step of transmitting the deduplicated pre-fetch request based on the pre-fetch network may include: the pre-fetch request is sent from a sending end of a pre-fetch network cross-chip line in one chip to a receiving end of a pre-fetch network cross-chip line in another chip. Specifically, refer to Figure 6 , Figure 6 is a schematic diagram of an optional structure of pre-fetch network cross-chip transmission provided in an embodiment of the present application. Figure 6 As shown, the pre-fetch request is sent from the transmitter of the pre-fetch network cross-chip line in DIE 0 to the receiver of the pre-fetch network cross-chip line in DIE 1, and is sent from the transmitter of the pre-fetch network cross-chip line in DIE 1 to the receiver of the pre-fetch network cross-chip line in DIE 0. The transmitter and the receiver in DIE 0 and DIE 1 can both be PHY (Physical Layer, physical layer) ports.

[0086] In a specific implementation, the transmitting end of the pre-fetch network cross-chip line is set at a position closest to all processors in the chip where the transmitting end is located, and the receiving end of the pre-fetch network cross-chip line is set at a position close to the memory in the chip where the receiving end is located. Setting the transmitting end at a position closest to the processor can shorten the physical distance between the processor and the pre-fetch network, thereby reducing the delay of data transmission. Setting the receiving end at a position close to the memory can reduce the memory access time because data can be transferred from the pre-fetch network to the memory faster.

[0087] Furthermore, to ensure data transmission efficiency and resource utilization, the number of cross-chip lines of the prefetch network may be set to match the scale of the prefetch network, because too many cross-chip lines may lead to resource waste and increased complexity, while too few cross-chip lines may limit the efficiency and speed of data transmission.

[0088] In order to optimize the balance of the prefetch network, in an optional implementation, after the step of deduplicating the prefetch requests with the same memory address and before the step of transmitting the deduplicated prefetch requests based on the prefetch network, it may also include: configuring a preset mark for the prefetch requests entering the prefetch network based on preset rules. In a specific implementation, the prefetch request may be configured with a mark 0 or a mark 1, wherein the allocation of the mark may be random or in a uniformly distributed manner (such as alternating allocation of 0 and 1). When a node in the prefetch network has multiple prefetch requests from different sources that need to be sent to the same exit (that is, when a "many-to-one" selector is used), these labeled requests will first be cached in the input buffer of the "many-to-one" selector, and the prefetch requests will be sent in order at the exit. For example, a prefetch request marked with 0 can be sent first, then a prefetch request marked with 1, and then a prefetch request marked with 0 can be sent again, and so on. By cyclically selecting prefetch requests with different labels to send, the bandwidth can be probabilistically evenly distributed, effectively avoiding the problem that a certain source or some sources occupy a large amount of bandwidth for a long time, resulting in other sources not being able to obtain sufficient bandwidth.

[0089] In another optional implementation, a weight selector can be configured for the pre-fetch network, and the weight selector is used to assign different weight values ​​to different links or nodes in the pre-fetch network. For example, a specific weight value can be assigned to each node in the pre-fetch network. This weight value can reflect the processing power, storage resources or other relevant performance indicators of the node. When a pre-fetch request enters the network, the weight selector will decide which node the pre-fetch request should be routed to based on these weight values ​​to maximize the performance and efficiency of the network. In a specific implementation, if a node has a performance bottleneck or overload, the weight value of the node can also be dynamically adjusted to reduce the number of pre-fetch requests sent to the node, thereby alleviating the pressure on the pre-fetch network.

[0090] It can be seen that the memory access method provided in the embodiment of the present application reads the prefetch data corresponding to the prefetch request from the memory based on the prefetch request, and then when the processor issues an access request, determines whether the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request. If the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request, it means that the processor requests the prefetch data that has been read from the memory before. At this time, the prefetch data can be directly returned to the processor as feedback data of the access request without accessing the slower memory, thereby reducing latency and improving data transmission efficiency.

[0091] The following is an introduction to the memory access device provided in the embodiment of the present application. The memory access device described below can be considered as a software function module or hardware function module required to implement the memory access method provided in the embodiment of the present application. The content of the memory access device described below can be referenced to the content of the method described above.

[0092] In an optional implementation, Figure 7 An optional structural diagram of a memory access device provided in an embodiment of the present application is exemplarily shown, wherein the memory access device is used to implement the memory access method provided in an embodiment of the present application, such as Figure 7 As shown, the memory access device may include:

[0093] An acquisition module 1 is used to acquire a pre-fetch request, wherein the pre-fetch request is a prediction request generated by a processor and / or an extraction request obtained by extracting an access request sent by the processor to a memory; wherein the pre-fetch request includes at least a memory address and control information;

[0094] A prefetch request control module 5 is used to read prefetch data corresponding to the prefetch request from the memory based on the prefetch request; determine whether the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request; wherein, if the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request, the prefetch data is returned to the access request.

[0095] Optionally, the pre-fetch request control module 5 includes: a reading module 51 and a judging module 52;

[0096] The reading module 51 is used for reading prefetch data corresponding to the prefetch request from the memory based on the prefetch request;

[0097] The judgment module 52 is used to judge whether the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request; wherein, if the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request, the prefetch data is returned to the access request.

[0098] Optionally, if the memory address of the access request sent by the processor to the memory does not match the memory address of the pre-fetch request, the pre-fetched data is discarded.

[0099] Optionally, also include:

[0100] A deduplication module 2, used for deduplicating the pre-fetch request;

[0101] The transmission module 4 is used for transmitting the deduplicated pre-fetch request based on the pre-fetch network.

[0102] Optionally, also include:

[0103] The marking module 3 is used to configure a preset mark for the pre-fetch request entering the pre-fetch network based on a preset rule.

[0104] Optionally, the pre-fetch request is transmitted across chips based on a pre-fetch network across chip lines; the transmission module 4 is used to transmit the deduplicated pre-fetch request based on the pre-fetch network, including:

[0105] The pre-fetch request is sent from a sending end of a pre-fetch network cross-chip line in one chip to a receiving end of a pre-fetch network cross-chip line in another chip;

[0106] The sending end of the pre-fetch network cross-chip line is set at a position closest to all processors in the chip where the sending end is located, and the receiving end of the pre-fetch network cross-chip line is set at a position close to the memory in the chip where the receiving end is located.

[0107] Optionally, the deduplication module 2 is used to transmit the deduplicated prefetch request based on the prefetch network, and further includes:

[0108] The pre-fetch request is cached.

[0109] Optionally, caching the pre-fetch request includes:

[0110] When the cached prefetch requests overflow, the new prefetch requests are discarded or replaced;

[0111] When the pre-fetch request is not sent to the memory within a preset time, the pre-fetch request is discarded.

[0112] Optionally, the priority of the prefetch request is lower than the priority of an access request sent by the processor to the memory.

[0113] Optionally, the pre-fetch network includes a weight selector for assigning different weight values ​​to different links or nodes in the pre-fetch network.

[0114] In an optional implementation, refer to Figure 8 , Figure 8 Schematic diagram of another optional structure of CPU accessing memory provided in the embodiment of the present application. Figure 8 As shown, the acquisition module first acquires the prediction request generated by the predictor inside the CPU, and the extraction request is obtained by extracting the access request sent by the processor to the memory, and then the deduplication module deduplicates the prefetch request with the same memory address, and then the deduplication prefetch request is transmitted based on the prefetch network, and finally the prefetch request control module reads the prefetch data corresponding to the prefetch request from the memory based on the prefetch request. Then, when the access request sent by the processor is sent to the memory controller through the NOC network and the memory access agent module, it is determined whether the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request. If the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request, it means that the processor requests the prefetch data that has been read from the memory before. At this time, the prefetch data can be directly returned to the processor as the feedback data of the access request without accessing the slower memory, thereby reducing the delay and improving the data transmission efficiency.

[0115] In an optional implementation, if the memory address of the access request sent by the processor to the memory does not match the memory address of the pre-fetch request, the pre-fetched data is discarded.

[0116] In an optional implementation, the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request, but the prefetch data corresponding to the prefetch request has not been read yet. In this case, the prefetch data can be returned to the processor as feedback data of the access request after waiting for the prefetch data to be read, without accessing the slower memory.

[0117] In an optional implementation, the pre-fetched data may not be cached. If, when the pre-fetched data corresponding to the pre-fetch request is read, there is no access request matching the pre-fetch request, the pre-fetched data may be directly discarded.

[0118] In an optional implementation, before the pre-fetch request after deduplication is transmitted based on the pre-fetch network, the marking module can also configure a preset mark for the pre-fetch request entering the pre-fetch network based on a preset rule, and the preset mark is used to indicate the node information of the pre-fetch network to which the pre-fetch request is sent. By indicating the node information in the pre-fetch network to which the pre-fetch request should be sent, the pre-fetch request can be managed and scheduled more effectively, ensuring the load balancing and efficient operation of the pre-fetch network.

[0119] In an optional implementation, when the memory access agent module returns feedback data to the processor, it can determine the busy level of the memory state according to the busyness of the memory, and configure the busy level into the feedback data, so that the predictor in the CPU and the extraction module (not shown in the figure) that extracts the access request sent by the CPU to the memory can limit or stop the generation of the pre-fetch request according to the busy level of the memory state fed back by the memory access agent module. For example, when the busy level of the memory state is greater than or equal to the preset busy level, the generation of the pre-fetch request is stopped.

[0120] It should be noted that the memory access method provided in the embodiment of the present application is particularly suitable for situations where there is an objective delay in processor memory access, where the delay time is usually between 50 nanoseconds and 200 nanoseconds.

[0121] It can be seen that the memory access method provided in the embodiment of the present application reads the prefetch data corresponding to the prefetch request from the memory based on the prefetch request, and then when the processor issues an access request, determines whether the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request. If the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request, it means that the processor requests the prefetch data that has been read from the memory before. At this time, the prefetch data can be directly returned to the processor as feedback data of the access request without accessing the slower memory, thereby reducing latency and improving data transmission efficiency.

[0122] An embodiment of the present application also provides an electronic device, which may include at least one memory and at least one processor, wherein the memory stores one or more computer executable instructions, and the processor calls the one or more computer executable instructions to execute the memory access method as described above.

[0123] As an optional implementation, refer to Fig. 9 , Fig. 9 is an optional block diagram of an electronic device provided in an embodiment of the present application. Fig. 9As shown, the electronic device may include: at least one processor 10 , at least one communication interface 20 , at least one memory 30 and at least one communication bus 40 .

[0124] In the embodiment of the present application, the number of the processor 10 , the communication interface 20 , the memory 30 and the communication bus 40 is at least one, and the processor 10 , the communication interface 20 , and the memory 30 communicate with each other through the communication bus 40 .

[0125] Optionally, the processor 10 may be a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an NPU (Neural-network Processing Unit), an FPGA (Field Programmable Gate Array), a TPU (Tensor Processing Unit), an AI chip, an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement an embodiment of the present application.

[0126] Optionally, the communication interface 20 may be an interface of a communication module for performing network communication.

[0127] The memory 30 may include a high-speed RAM memory, and may also include a non-volatile memory, such as at least one disk memory. The memory 30 stores one or more computer executable instructions, and the processor 10 calls the one or more computer executable instructions to execute the memory access method described above.

[0128] An embodiment of the present application also provides a storage medium, which stores one or more computer-executable instructions. When the one or more computer-executable instructions are executed, the memory access method described above is implemented.

[0129] An embodiment of the present application also provides a computer program product, which may include one or more computer executable instructions. When the one or more computer executable instructions are executed, the memory access method described above is implemented.

[0130] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0131] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A memory access method, characterized in that: include: Obtaining a prefetch request, wherein the prefetch request is a prediction request generated by a processor and / or an extraction request obtained by extracting an access request sent by the processor to a memory; wherein the prefetch request includes at least a memory address and control information; Based on the prefetch request, reading prefetch data corresponding to the prefetch request from the memory; determining whether a memory address of an access request sent by the processor to the memory matches the memory address of the prefetch request; If the memory address of the access request sent by the processor to the memory matches the memory address of the pre-fetch request, the pre-fetch data is returned to the processor as feedback data of the access request.

2. The memory access method according to claim 1, characterized in that: If the memory address of the access request sent by the processor to the memory does not match the memory address of the pre-fetch request, the pre-fetched data is discarded.

3. The memory access method according to claim 1, characterized in that: When the prefetch request is a prediction request generated by a processor and an extraction request obtained by extracting an access request sent by the processor to the memory, after the step of obtaining the prefetch request and before the step of reading prefetch data corresponding to the prefetch request from the memory based on the prefetch request, the method further includes: De-duplicate prefetch requests with the same memory address; Prefetch requests after deduplication based on prefetch network transmission.

4. The memory access method according to claim 3, characterized in that: After the step of deduplicating the prefetch requests with the same memory address and before the step of prefetching the deduplicated prefetch requests based on the network transmission, the method further includes: Based on the preset rule, a preset tag is configured for the prefetch request entering the prefetch network.

5. The memory access method according to claim 3, characterized in that: The memory access method is adapted to a multi-chip device, and the pre-fetch request is transmitted across chips based on a pre-fetch network across chip lines; The step of prefetching the request after prefetching the deduplication of the network transmission includes: The pre-fetch request is sent from a sending end of a pre-fetch network cross-chip line in one chip to a receiving end of a pre-fetch network cross-chip line in another chip; The sending end of the pre-fetch network cross-chip line is set at a position closest to all processors in the chip where the sending end is located, and the receiving end of the pre-fetch network cross-chip line is set at a position close to the memory in the chip where the receiving end is located.

6. The memory access method according to claim 3, characterized in that: The step of pre-fetching the pre-fetched request after the network transmission is deduplicated also includes: The pre-fetch request is cached.

7. The memory access method according to claim 6, characterized in that: The step of caching the pre-fetch request comprises: When the cached prefetch requests overflow, the new prefetch requests are discarded or replaced; When the pre-fetch request is not sent to the memory within a preset time, the pre-fetch request is discarded.

8. The memory access method according to claim 1, characterized in that: The pre-fetch request has a lower priority than an access request sent by the processor to the memory.

9. The memory access method according to claim 3, characterized in that: The pre-fetch network includes a weight selector for assigning different weight values ​​to different links or nodes in the pre-fetch network.

10. A memory access device, characterized in that: include: an acquisition module, configured to acquire a pre-fetch request, wherein the pre-fetch request is a prediction request generated by a processor and / or an extraction request obtained by extracting an access request sent by the processor to a memory; wherein the pre-fetch request includes at least a memory address and control information; A prefetch request control module is used to read prefetch data corresponding to the prefetch request from the memory based on the prefetch request; determine whether the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request; wherein, if the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request, the prefetch data is returned to the access request.

11. The memory access device according to claim 10, characterized in that: The pre-fetch request control module includes: a reading module and a judging module; The reading module is used to read the prefetch data corresponding to the prefetch request from the memory based on the prefetch request; The judgment module is used to judge whether the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request; wherein, if the memory address of the access request sent by the processor to the memory matches the memory address of the prefetch request, the prefetch data is returned to the access request.

12. The memory access device according to claim 11, characterized in that: If the memory address of the access request sent by the processor to the memory does not match the memory address of the pre-fetch request, the pre-fetched data is discarded.

13. The memory access device according to claim 10, characterized in that: Also includes: A deduplication module, used for deduplicating the pre-fetch request; The transmission module is used for transmitting the deduplicated prefetch request based on the prefetch network.

14. The memory access device according to claim 10, characterized in that: Also includes: The marking module is used to configure a preset mark for the pre-fetch request entering the pre-fetch network based on a preset rule.

15. An electronic device, characterized in that: The method comprises at least one memory and at least one processor, wherein the memory stores one or more computer executable instructions, and the processor calls the one or more computer executable instructions to execute the memory access method according to any one of claims 1 to 9.

16. A storage medium, characterized in that: The storage medium stores one or more computer executable instructions, and when the one or more computer executable instructions are executed, the memory access method according to any one of claims 1 to 9 is implemented.

17. A computer program product, characterized in that The method comprises one or more computer executable instructions, and when the one or more computer executable instructions are executed, the memory access method according to any one of claims 1 to 9 is implemented.

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