I2C interface and interface chip

Abstract

The invention discloses an I2C interface and an interface chip. The I2C interface comprises a push-pull output module and a data interface, the push-pull output module is used for responding to a first configuration signal and controlling an on-chip data signal of the target chip to be output to the off-chip from the data interface, and the first configuration signal is used for representing that the I2C interface is configured to be a push-pull mode in an I3C mode. According to the I2C interface, the push-pull output module responds to the first configuration signal, the on-chip data signal of the target chip is controlled to be output to the off-chip from the data interface based on the push-pull mode in the I3C mode, so that the I2C interface can be compatible with the push-pull mode in the I3C mode, the communication rate is greatly improved, the application scene of the I2C interface is expanded, and the adaptability is wider.

Description

Technical Field

[0001] The present application relates to the technical field of communication interfaces, and in particular to an I2C interface and an interface chip. Background Art

[0002] The Inter-Integrated Circuit (IIC) interface, also known as the I2C interface, is a half-duplex, bidirectional two-wire serial communication interface, mainly used to connect microcontrollers and other peripheral devices, such as sensors, memories, displays, etc.

[0003] Based on the I2C protocol, I2C communication only needs two signal lines to complete information exchange, so the wiring is simple and the cost is low. However, the I2C communication rate in the related technology is slow. Even if it works in high-speed mode, its maximum transmission rate is only 3.4Mbps, which greatly limits the application scenarios of the I2C interface. Summary of the invention

[0004] In view of the above problems, the present application provides an I2C interface and an interface chip to solve the above technical problems.

[0005] In a first aspect, the present application provides an I2C interface, which includes a push-pull output module and a data interface; the push-pull output module is used to control the on-chip data signal of the target chip to be output from the data interface to the outside of the chip in response to a first configuration signal; wherein the first configuration signal is used to characterize that the I2C interface is configured as a push-pull mode under the I3C mode.

[0006] In a possible implementation of the present application, the push-pull output module includes a first switch unit and a push-pull control unit, the first end of the first switch unit is connected to the power output end, the second end of the first switch unit is connected to the data interface and the open-drain output module of the I2C interface, and the control end of the first switch unit is connected to the push-pull control unit; the push-pull control unit is used to output an inverted data signal of the on-chip data signal to the first switch unit in response to a first configuration signal; the first switch unit is used to cooperate with the open-drain output module to generate an interface output signal in response to the inverted data signal and output it to the data interface; wherein the interface output signal is inverted to the inverted data signal.

[0007] In a possible implementation of the present application, the push-pull control unit includes a push-pull mode configuration subunit, a signal output subunit and a first OR gate; the push-pull mode configuration subunit is used to invert the first configuration signal to obtain a first inverted signal and output it to the first OR gate; wherein the first inverted signal is a low-level signal; the signal output subunit is used to invert the on-chip data signal to obtain an inverted data signal and output it to the first OR gate; the first OR gate is used to perform an "OR" operation on the first inverted signal and the inverted data signal, and output the inverted data signal to the first switch unit.

[0008] In a possible implementation of the present application, the push-pull mode configuration subunit includes a first AND gate and a first NOT gate, and the first configuration signal includes an output configuration signal, a first enable signal and a push-pull enable signal, which are respectively configured as valid levels; the first AND gate is used to perform an "AND" operation on the output configuration signal, the first enable signal and the push-pull enable signal to generate a push-pull drive signal; wherein, the output configuration signal configured as a valid level is used to characterize that the SDA data line of the I2C interface is in output mode; the first enable signal configured as a valid level is used to characterize that the I2C interface works in I3C mode; the push-pull enable signal configured as a valid level is used to characterize that the I2C interface working in I3C mode is configured as a push-pull mode; the first NOT gate is used to invert the push-pull drive signal to obtain a first inverted signal.

[0009] In a possible implementation of the present application, the I2C interface also includes an open-drain output module connected to the data interface; the open-drain output module is used to control the on-chip data signal to be output from the data interface to the outside of the chip in response to a second configuration signal or a third configuration signal; wherein the second configuration signal is used to characterize the open-drain mode of the I2C interface operating in the I3C mode; and the third configuration signal is used to characterize the open-drain mode of the I2C interface operating in the I2C mode.

[0010] In a possible implementation of the present application, the open-drain output module includes a second switch unit and an open-drain control unit, the first end of the second switch unit is connected to the data interface, the data interface is also connected to a pull-up resistor, the second end of the second switch unit is connected to the ground end, and the control end of the second switch unit is connected to the open-drain control unit; the open-drain control unit is used to output an inverted data signal of the on-chip data signal to the second switch unit in response to the second configuration signal or the third configuration signal; the second switch unit is used to generate an interface output signal in response to the inverted data signal and output it to the data interface; wherein the interface output signal is inverted to the inverted data signal.

[0011] In a possible implementation of the present application, the open-drain control unit includes a first open-drain configuration subunit, a second open-drain configuration subunit, a second OR gate, a signal output subunit and a second AND gate; the first open-drain configuration subunit is used to generate a second drive signal according to a second configuration signal and output it to the second OR gate when the I2C interface works in an open-drain mode under the I3C mode, and to output an inverted signal of the second drive signal to the second OR gate when the I2C interface works in an open-drain mode under the I2C mode; wherein the second drive signal is a high-level signal; the second open-drain configuration subunit is used to generate a second drive signal according to a third configuration signal when the I2C interface works in an open-drain mode under the I2C mode The third drive signal is output to the second OR gate, and when the I2C interface works in the open-drain mode under the I3C mode, the inverted signal of the third drive signal is output to the second OR gate; wherein the third drive signal is a high-level signal; the second OR gate is used to perform an "OR" operation on the second drive signal and the inverted signal of the third drive signal, or the third drive signal and the inverted signal of the second drive signal, and output the first valid signal to the second AND gate; the signal output subunit is used to invert the on-chip data signal, obtain the inverted data signal and output it to the second AND gate; the second AND gate is used to perform an "AND" operation on the first valid signal and the inverted data signal, and output the inverted data signal to the second switch unit.

[0012] In a possible implementation of the present application, the first open-drain configuration subunit includes a third AND gate, a fourth AND gate, a third OR gate and a fifth AND gate; the second configuration signal includes an open-drain enable signal, an output configuration signal and a first enable signal, which are respectively configured as valid levels, and a push-pull enable signal configured as an invalid level; wherein the open-drain enable signal configured as a valid level is used to indicate that the I2C interface is configured in open-drain mode, the output configuration signal configured as a valid level is used to indicate that the SDA data line of the I2C interface is in output mode, and the first enable signal configured as a valid level Used to characterize that the I2C interface works in I3C mode; the third AND gate is used to perform an "AND" operation on the inverted signal of the open-drain enable signal and the push-pull enable signal to generate a first signal output to the third OR gate; the fourth AND gate is used to perform an "AND" operation on the inverted signal of the open-drain enable signal and the push-pull enable signal to generate a second signal output to the third OR gate; the third OR gate is used to perform an "OR" operation on the first signal and the second signal to generate a third signal output to the fifth AND gate; the fifth AND gate is used to perform an "AND" operation on the third signal, the output configuration signal and the first enable signal to generate a second drive signal.

[0013] In a possible implementation of the present application, the second open-drain configuration subunit includes a sixth AND gate, and the third configuration signal includes an output configuration signal and an open-drain enable signal, which are respectively configured as valid levels, and a first enable signal configured as an invalid level; wherein the output configuration signal configured as a valid level is used to characterize that the SDA data line of the I2C interface is in output mode, the first enable signal configured as an invalid level is used to characterize that the I2C interface works in I2C mode, and the open-drain enable signal configured as a valid level is used to characterize that the I2C interface working in I2C mode is configured as an open-drain mode; the sixth AND gate is used to perform an "AND" operation on the output configuration signal, the inverted signal of the first enable signal, and the open-drain enable signal to generate a third drive signal.

[0014] In a second aspect, the present application further provides an interface chip, comprising a chip body and an I2C interface provided on the chip body as in any possible implementation of the first aspect.

[0015] From the above content, it can be concluded that the present application has the following beneficial effects:

[0016] The I2C interface provided by the present application responds to the first configuration signal through a push-pull output module to control the on-chip data signal of the target chip to be output from the data interface to the outside of the chip based on the push-pull mode in the I3C mode, so that the I2C interface of the present application can be compatible with the push-pull mode in the I3C mode, thereby greatly improving the communication rate, expanding the application scenarios of the I2C interface, and having a wider adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 It is a wiring diagram for realizing I2C communication in the related technology;

[0019] Figure 2 This is a schematic diagram of the structure of the I2C interface provided in the embodiment of the present application;

[0020] Figure 3 It is a structural schematic diagram of a push-pull output module provided in an embodiment of the present application;

[0021] Figure 4 is a structural schematic diagram of a first switch unit provided in an embodiment of the present application;

[0022] Figure 5is a schematic diagram of a push-pull control unit provided in an embodiment of the present application;

[0023] Figure 6 It is a structural schematic diagram of a push-pull mode configuration subunit provided in an embodiment of the present application;

[0024] Figure 7 is another structural diagram of the I2C interface provided in the embodiment of the present application;

[0025] Figure 8 It is a structural schematic diagram of an open-drain output module provided in an embodiment of the present application;

[0026] Fig. 9 is a structural schematic diagram of a second switch unit provided in an embodiment of the present application;

[0027] Fig.10 is a structural schematic diagram of an open-drain control unit provided in an embodiment of the present application;

[0028] Fig.11 is another structural schematic diagram of an open-drain control unit provided in an embodiment of the present application;

[0029] Fig.12 It is another structural schematic diagram of the open-drain control unit provided in the embodiment of the present application;

[0030] Fig.13 This is another structural diagram of the I2C interface provided in the embodiment of the present application. DETAILED DESCRIPTION

[0031] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0032] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0033] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0034] Moreover, the terms "comprises", "comprising" or any other variation thereof are intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of more restrictions, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the element.

[0035] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0036] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0037] The first pole / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first pole / first end and the second pole / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first pole / first end of the transistor is the drain, and the second pole / second end is the source.

[0038] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual existing components, but represent the junction points of related couplings in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0039] Before introducing the I2C interface and interface chip of the present application, the relevant background information of the embodiments of the present application is first introduced.

[0040] The I2C bus is a master-slave bus structure. Each device on the bus has a specific device address to distinguish other devices on the same I2C bus. Devices connected to the I2C bus can be used as either master devices or slave devices; and I2C communication is always initiated by the master device, and the slave device passively receives the response.

[0041] like Figure 1 As shown, device 1 and device 2 are respectively equipped with an I2C interface, which uses a two-wire structure to transmit data, including a serial data line (Serial Data, SDA) and a serial clock line (Serial Clock, SCL), where the SDA line is used for bidirectional data transmission and the SCL line is used for the clock signal of synchronous data transmission. Such a simple line connection method makes it very easy to interconnect devices and the communication cost is also low.

[0042] However, the data transmission rate of traditional I2C communication is low. The data transmission rate in standard mode is only 0.1Mbps, and the data transmission rate in fast mode is only 0.4Mbps. Even in high-speed mode, the maximum data transmission rate can only reach 3.4Mbps, which makes the I2C interface unsuitable for application scenarios with higher communication rate requirements.

[0043] Based on this, an embodiment of the present application provides an I2C interface and an interface chip, which can not only realize traditional I2C communication, but also be compatible with I3C communication, thereby greatly improving the communication rate and expanding the application scenarios of the I2C interface.

[0044] The I2C interface and interface chip provided by this application are described in detail below.

[0045] First, the embodiment of the present application provides an I2C interface, such as Figure 2 As shown, the I2C interface 10 may include a push-pull output module 100 and a data interface 200. The push-pull output module 100 may be used to control the on-chip data signal of the target chip 20 to be output from the data interface 200 to the outside of the chip in response to a first configuration signal; wherein the first configuration signal may be used to characterize that the I2C interface is configured as a push-pull mode under the I3C mode.

[0046] The I2C interface 10 is connected to the target chip 20, and can transmit on-chip data to off-chip, or transmit off-chip data to on-chip. The signal flow direction can be determined according to the actual application scenario. In some embodiments, the I2C interface 10 can also be integrated into the target chip 20 to realize signal transmission.

[0047] In the embodiment of the present application, the target chip 20 can be any existing controller such as a microcontroller unit (MCU), a single-chip microcomputer, etc. The first configuration signal can be a signal generated by the target chip 20 or other control units in the device; for example, the target chip 20 can generate a first configuration signal and output it to the push-pull output module 100 by configuring a general-purpose input / output port (GPIO); or the target chip 20 can also generate a first configuration signal and output it to the push-pull output module 100 by configuring a register through software. The first configuration signal can drive the push-pull output module 100 to work, so that the I2C interface 10 works in the push-pull mode under the I3C mode.

[0048] Specifically, after receiving the first configuration signal, the push-pull output module 100 can start signal transmission in response to the first configuration signal, and control the on-chip data signal from the target chip 20 to be output by the data interface 200 based on the push-pull mode in the I3C mode. That is, the I2C interface 10 in the embodiment of the present application can be compatible with the I3C interface to implement the push-pull mode in the I3C mode; it can be understood that the transmission rate of I3C communication is much higher than that of I2C communication, and therefore, the data transmission rate of the I2C interface 10 can be improved.

[0049] The I2C interface 10 provided in the embodiment of the present application responds to the first configuration signal through the push-pull output module 100 to control the on-chip data signal of the target chip 20 to be output from the data interface 200 to the outside of the chip based on the push-pull mode in the I3C mode, so that the I2C interface 10 can be compatible with the push-pull mode in the I3C mode, thereby greatly improving the communication rate, expanding the application scenarios of the I2C interface 10, and having a wider adaptability.

[0050] Next, continue to Figure 2 The modules shown and the specific implementation methods that may be used in practical applications are described in detail.

[0051] like Figure 3As shown, in some embodiments of the present application, the push-pull output module 100 may include a first switch unit 110 and a push-pull control unit 120, the first end of the first switch unit 110 may be connected to the power output end, the second end of the first switch unit 110 may be connected to the data interface 200, and the control end of the first switch unit 110 may be connected to the push-pull control unit 120; the push-pull control unit 120 may be used to output an inverted data signal of the on-chip data signal to the first switch unit 110 in response to a first configuration signal; the first switch unit 110 may be connected to the open-drain output module 300 of the I2C interface 10, and is used to cooperate with the open-drain output module 300 to generate an interface output signal in response to the inverted data signal and output it to the data interface 200; wherein the interface output signal is inverted to the inverted data signal.

[0052] It can be understood that the I2C interface 10 can also be configured with an open-drain output module 300, and the open-drain output module 300 can also be connected to the data interface 200 to implement the open-drain mode in the I2C mode.

[0053] In the embodiment of the present application, the push-pull control unit 120 can be connected to the target chip 20, access the on-chip data signal, and when receiving the first configuration signal, output the inverted data signal to the control end of the first switch unit 110 in response to the first configuration signal; it can be understood that the inverted data signal is the inverted signal of the on-chip data signal. The first switch unit 110 can then invert the inverted data signal again, generate an interface output signal and output it to the data interface 200. It can be understood that the interface output signal at this time is a signal in phase with the on-chip data signal, thereby realizing the output of the on-chip data signal to the outside of the chip.

[0054] In the embodiment of the present application, the first switch unit 110 can be implemented by a switching transistor, including but not limited to a metal-oxide-semiconductor field-effect transistor (MOSFET / MOS), a triode, a parallel triode or a MOS tube, etc. The specific method can be determined according to the actual application scenario and is not limited here.

[0055] like Figure 4 As shown, as an example, the first switch unit 110 includes a P-type MOS tube, the gate of which is connected to the push-pull control unit 120 and connected to the inverted data signal; the source is connected to the power output end and connected to the voltage signal vddpp output by the power output end; the drain is connected to the data interface 200, and the output interface outputs the signal to the data interface 200.

[0056] According to the characteristics of the P-type MOS tube, when the inverted data signal is at a low level "0", the P-type MOS tube is turned on. Since its source is connected to the voltage signal vddpp, the interface output signal generated to the data interface 200 is at a high level "1", thereby realizing the inversion of the interface output signal and the inverted data signal. Since the inverted data signal is opposite in phase to the on-chip data signal, the interface output signal is in phase with the on-chip data signal, thereby realizing the output of the on-chip data signal to the outside of the chip.

[0057] Since the on-resistance Rds(on) between the drain (Drain) and the source (Source) when the P-type MOS tube is turned on is much smaller than the resistance of the pull-up resistor (not shown in the figure) used for open-drain output at the data interface 200, the use of the P-type MOS tube as a pull-up greatly improves the signal transmission rate compared to the I2C mode.

[0058] When the inverted data signal is at a high level "1", the P-type MOS tube is turned off, and the open-drain output module 300 can be controlled to function, generating a low level "0" interface output signal to be output to the data interface 200, thereby realizing the transmission of the data signal within the chip.

[0059] like Figure 5 As shown, in some embodiments of the present application, the push-pull control unit 120 may include a push-pull mode configuration subunit 1201, a signal output subunit 1202 and a first OR gate OR1; the push-pull mode configuration subunit 1201 can be used to invert the first configuration signal to obtain a first inverted signal to output to the first OR gate OR1; wherein the first inverted signal is a low-level signal "0"; the signal output subunit 1202 can be used to invert the on-chip data signal to obtain an inverted data signal to output to the first OR gate OR1; the first OR gate OR1 can be used to perform an "OR" operation on the first inverted signal and the inverted data signal, and output the inverted data signal to the first switch unit 110.

[0060] In the embodiment of the present application, the push-pull mode configuration subunit 1201 can be connected to the target chip 20 or other control units, receive the first configuration signal, and then invert the first configuration signal to obtain a first inverted signal output to the first OR gate OR1.

[0061] The signal output subunit 1202 can be connected to the target chip 20, access the on-chip data signal, and invert the on-chip data signal to obtain an inverted data signal and output it to the first OR gate OR1; in the embodiment of the present application, the signal output subunit 1202 can be any existing inverter or logical NOT circuit, which can be determined according to the actual application scenario and is not limited here.

[0062] The first OR gate OR1 performs an "OR" operation on the connected first inverted signal and the inverted data signal. Since the inverted data signal needs to be output to the first switch unit 110, according to the working principle of the OR gate, when one of the two input signals is a low level "0", the output signal of the OR gate depends on the other input signal; therefore, the first inverted signal in the embodiment of the present application is a low level signal "0", and correspondingly, the first configuration signal is a high level signal "1", thereby ensuring that the inverted data signal that is inverted with the on-chip data signal is output to the first switch unit 110, and after another inversion processing by the first switch unit 110, an interface output signal that is in phase with the on-chip data signal is generated and output from the data interface 200, thereby realizing the transmission of the on-chip data signal to the outside of the chip.

[0063] like Figure 6 As shown, in some embodiments of the present application, the push-pull mode configuration subunit 1201 may include a first AND gate AND1 and a first NOT gate NOT1, and the first configuration signal may include an output configuration signal sda_set, a first enable signal i3c_en and a push-pull enable signal pp_output_en, which are respectively configured as valid levels; the first AND gate AND1 can be used to perform an "AND" operation on the output configuration signal sda_set, the first enable signal i3c_en and the push-pull enable signal pp_output_en to generate a push-pull drive signal; wherein, the output configuration signal sda_set configured as a valid level can be used to characterize that the SDA data line of the I2C interface 10 is in output mode; the first enable signal i3c_en configured as a valid level is used to characterize that the I2C interface 10 works in I3C mode; the push-pull enable signal pp_output_en configured as a valid level can be used to characterize that the I2C interface 10 working in I3C mode is configured as a push-pull mode; the first NOT gate NOT1 can be used to invert the push-pull drive signal to obtain a first inverted signal.

[0064] In an embodiment of the present application, the output configuration signal sda_set, the first enable signal i3c_en and the push-pull enable signal pp_output_en can all be configured as valid levels, which can be a high level "1" or a low level "0", which can be determined based on the actual application scenario and is not limited here.

[0065] As an example, when the effective level is a high level "1", the output configuration signal sda_set, the first enable signal i3c_en and the push-pull enable signal pp_output_en are input into the first AND gate AND1, and then the "AND" operation is performed by the first AND gate AND1 to obtain a push-pull drive signal of the same high level "1" which is output to the first NOT gate NOT1; then the push-pull drive signal is inverted by the first NOT gate NOT1 to generate a first inverted signal of a low level "0" which is output to the first OR gate OR1, so that the output of the first OR gate OR1 can completely depend on the inverted data signal, thereby ensuring that the on-chip data signal can be quickly and accurately output to the outside of the chip in the push-pull mode.

[0066] like Figure 7 As shown, in some embodiments of the present application, the I2C interface 10 may further include an open-drain output module 300 connected to the data interface 200; the open-drain output module 300 may be used to control the on-chip data signal to be output from the data interface to the outside of the chip in response to a second configuration signal or a third configuration signal; wherein the second configuration signal may be used to characterize the open-drain mode of the I2C interface 10 operating in the I3C mode; and the third configuration signal may be used to characterize the open-drain mode of the I2C interface 10 operating in the I2C mode.

[0067] In the embodiment of the present application, the second configuration signal and the third configuration signal can be signals generated by the target chip 20 or other control units in the device; for example, the target chip 20 can generate the second configuration signal or the third configuration signal by configuring the GPIO and output it to the open-drain output module 300; or the target chip 20 can also generate the second configuration signal or the third configuration signal by configuring the register by software and output it to the open-drain output module 300. Among them, the second configuration signal can drive the open-drain output module 300 to work, so that the I2C interface 10 works in the open-drain mode under the I3C mode; the third configuration signal can drive the open-drain output module 300 to work, so that the I2C interface 10 works in the open-drain mode under the I2C mode, that is, to realize the open-drain transmission function of the traditional I2C interface.

[0068] Specifically, after receiving the second configuration signal, the open-drain output module 300 may start signal transmission in response to the second configuration signal, and control the on-chip data signal from the target chip 20 to be output by the data interface 200 based on the open-drain mode in the I3C mode. Alternatively, after receiving the third configuration signal, the open-drain output module 300 may start signal transmission in response to the third configuration signal, and control the on-chip data signal from the target chip 20 to be output by the data interface 200 based on the open-drain mode in the I2C mode.

[0069] That is to say, the I2C interface 10 in the embodiment of the present application can be compatible with the I3C interface. In addition to the open-drain mode in the traditional I2C mode, it can also realize three signal transmission modes, namely the push-pull mode and the open-drain mode in the I3C mode, which greatly expands the application scenarios of the I2C interface 10 and makes it more adaptable.

[0070] like Figure 8 As shown, in some embodiments of the present application, the open-drain output module 300 may include a second switch unit 310 and an open-drain control unit 320, the first end of the second switch unit 310 may be connected to the data interface 200, the data interface 200 may also be connected to a pull-up resistor (not shown in the figure), the second end of the second switch unit 310 may be connected to the ground terminal GND, and the control end of the second switch unit 310 may be connected to the open-drain control unit 320; the open-drain control unit 320 may be used to output an inverted data signal of the on-chip data signal to the second switch unit 310 in response to the second configuration signal or the third configuration signal; the second switch unit 310 may be used to generate an interface output signal in response to the inverted data signal and output it to the data interface 200; wherein the interface output signal is inverted to the inverted data signal.

[0071] In the embodiment of the present application, the open-drain control unit 320 can be connected to the target chip 20, access the on-chip data signal, and when receiving the second configuration signal or the third configuration signal, it outputs the inverted data signal to the control end of the second switch unit 310 in response to the received configuration signal; it can be understood that the inverted data signal is the inverted signal of the on-chip data signal. The second switch unit 310 can then invert the inverted data signal again, generate an interface output signal and output it to the data interface 200. It can be understood that the interface output signal at this time is a signal in phase with the on-chip data signal, thereby realizing the output of the on-chip data signal to the outside of the chip.

[0072] In the embodiment of the present application, the second switch unit 310 can also be implemented by a switching transistor, including but not limited to a MOS tube, a triode, a parallel triode or a MOS tube, etc. The specific method can be determined according to the actual application scenario and is not limited here.

[0073] like Fig. 9 As shown, as an example, the second switch unit 310 includes an N-type MOS tube, the gate of which is connected to the open-drain control unit 320 and receives the inverted data signal; the drain is connected to the data interface 200, and the output interface outputs the signal to the data interface 200; and the source is connected to the ground terminal GND.

[0074] According to the characteristics of the N-type MOS tube, when the inverted data signal is a high level "1", the N-type MOS tube is turned on. Since its source is connected to the ground terminal GND, the potential of the data interface 200 is pulled down to the ground, and the interface output signal generated to the data interface 200 is a low level "0"; when the inverted data signal is a low level "0", the N-type MOS tube is turned off. Since the data interface 200 is connected to a pull-up resistor (not shown in the figure), the pull-up resistor can pull up the potential of the data interface 200, and the interface output signal generated to the data interface 200 is a high level "1" at this time; since the inverted data signal is opposite in phase to the on-chip data signal, the interface output signal is in phase with the on-chip data signal, thereby realizing the output of the on-chip data signal to the outside of the chip.

[0075] like Fig.10 As shown, in some embodiments of the present application, the open-drain control unit 320 may include a first open-drain configuration subunit 3201, a second open-drain configuration subunit 3202, a second OR gate OR2, a signal output subunit and a second AND gate AND2; the first open-drain configuration subunit 3201 can be used to generate a second drive signal according to a second configuration signal and output it to the second OR gate OR2 when the I2C interface 10 operates in the open-drain mode under the I3C mode, and to output an inverted signal of the second drive signal to the second OR gate OR2 when the I2C interface 10 operates in the open-drain mode under the I2C mode; wherein the second drive signal is a high-level signal; the second open-drain configuration subunit 3202 can be used to generate a second drive signal according to a third configuration signal when the I2C interface 10 operates in the open-drain mode under the I3C mode, and to output an inverted signal of the second drive signal to the second OR gate OR2 when the I2C interface 10 operates in the open-drain mode under the I2C mode; wherein the second drive signal is a high-level signal; the second open-drain configuration subunit 3202 can be used to generate a second drive signal according to a third configuration signal when the I2C interface 10 operates in the open-drain mode under the I2C mode The set signal generates a third drive signal and outputs it to the second OR gate OR2, and when the I2C interface 10 works in the open-drain mode under the I3C mode, the inverted signal of the third drive signal is output to the second OR gate OR2; wherein the third drive signal is a high level signal; the second OR gate OR2 can be used to perform an "OR" operation on the second drive signal and the inverted signal of the third drive signal, or the third drive signal and the inverted signal of the second drive signal, and output the first valid signal to the second AND gate AND2; the signal output subunit can be used to invert the on-chip data signal, obtain the inverted data signal and output it to the second AND gate AND2; the second AND gate AND2 can be used to perform an "AND" operation on the first valid signal and the inverted data signal, and output the inverted data signal to the second switch unit 310.

[0076] Reference Fig.10 In the embodiment of the present application, the signal output subunit of the open-drain control unit 320 can reuse the signal output subunit 1202 in the push-pull control unit 120 to simplify the circuit structure.

[0077] It is understandable that in some other embodiments, the signal output subunit of the open-drain control unit 320 may also be another independent unit module different from the signal output subunit 1202, for example Fig.11 The first signal output subunit 3203 shown in the figure can also be connected to the target chip 20, access the on-chip data signal, and invert the on-chip data signal to obtain an inverted data signal output to the second AND gate AND2; in the embodiment of the present application, the first signal output subunit 3203 can also be any existing inverter or logical NOT circuit, which can be determined according to the actual application scenario and is not limited here.

[0078] The first open-drain configuration subunit 3201 can be connected to the target chip 20 or other control units, access the second configuration signal, and when the I2C interface 10 works in the open-drain mode under the I3C mode, generate a second drive signal according to the second configuration signal and output it to the second OR gate OR2; the second open-drain configuration subunit 3202 can also be connected to the target chip 20 or other control units, and when the I2C interface 10 works in the open-drain mode under the I3C mode, it can output the inverted signal of the third drive signal to the second OR gate OR2; since the third drive signal is a high level "1", its inverted signal is a low level "0", and the second drive signal is a high level "1" , so that the first valid signal output by the second OR gate OR2 is a high level "1"; according to the working principle of the AND gate, when one of its two input signals is a high level "1", its output signal depends on the other input signal, that is, the output of the second AND gate AND2 depends on the inverted data signal, thereby ensuring that the inverted data signal that is inverted with the on-chip data signal is output to the second switch unit 310, and after another inversion processing by the second switch unit 310, an interface output signal that is in phase with the on-chip data signal is generated and output from the data interface 200, thereby realizing the transmission of the on-chip data signal to the outside of the chip when the I2C interface 10 works in the open-drain mode under the I3C mode.

[0079] When the I2C interface 10 works in the open-drain mode under the I2C mode, the second open-drain configuration subunit 3202 can generate a third drive signal according to the connected third configuration signal and output it to the second OR gate OR2; the first open-drain configuration subunit 3201 can output the inverted signal of the second drive signal to the second OR gate OR2; since the second drive signal is a high level "1", its inverted signal is a low level "0", and the third drive signal is a high level "1", so that the first valid signal output by the second OR gate OR2 is still a high level "1"; similarly, at this time, the output of the second AND gate AND2 depends on the inverted data signal, ensuring that the inverted data signal that is inverted with the on-chip data signal is output to the second switch unit 310, and after the second switch unit 310 is inverted again, an interface output signal with the same phase as the on-chip data signal is generated and output from the data interface 200, so that the I2C interface 10 can transmit the on-chip data signal to the outside of the chip when working in the open-drain mode under the I2C mode.

[0080] like Fig.12 As shown, in some embodiments of the present application, the first open-drain configuration subunit 3201 may include a third AND gate AND3, a fourth AND gate AND4, a third OR gate OR3 and a fifth AND gate AND5; the second configuration signal may include an open-drain enable signal od_mode_en, an output configuration signal sda_set and a first enable signal i3c_en, which are respectively configured as valid levels, and a push-pull enable signal pp_output_en, which is configured as an invalid level; wherein the open-drain enable signal od_mode_en configured as a valid level can be used to characterize that the I2C interface 10 is configured in open-drain mode, the output configuration signal sda_set configured as a valid level can be used to characterize that the SDA data line of the I2C interface 10 is in output mode, and the first enable signal i3c_en configured as a valid level can be used to characterize that the I2C interface 10 is configured in open-drain mode. Characterizes that the I2C interface 10 works in I3C mode; the third AND gate AND3 can be used to perform an "AND" operation on the open-drain enable signal od_mode_en and the inverted signal pp_output_enb of the push-pull enable signal to generate a first signal output to the third OR gate OR3; the fourth AND gate AND4 can be used to perform an "AND" operation on the inverted signal od_mode_enb of the open-drain enable signal and the push-pull enable signal pp_output_en to generate a second signal output to the third OR gate OR3; the third OR gate OR3 can be used to perform an "OR" operation on the first signal and the second signal to generate a third signal output to the fifth AND gate AND5; the fifth AND gate AND5 can be used to perform an "AND" operation on the third signal, the output configuration signal sda_set and the first enable signal i3c_en to generate a second drive signal.

[0081] In an embodiment of the present application, the third AND gate AND3, the fourth AND gate AND4 and the fifth AND gate AND5 can be connected to the target chip 20 or other control units to access the second configuration signal; when the I2C interface 10 operates in the open drain mode under the I3C mode, the second configuration signal may include an open drain enable signal od_mode_en configured as a valid level, an output configuration signal sda_set configured as a valid level, a first enable signal i3c_en configured as a valid level, and a push-pull enable signal pp_output_en configured as an invalid level.

[0082] For example, if the high level "1" is the effective level for each signal, the push-pull enable signal pp_output_en is the low level "0", and its inverted signal pp_output_enb is the high level "1". Therefore, the open-drain enable signal od_mode_en of the high level "1" and the inverted signal pp_output_enb of the push-pull enable signal of the high level "1" are ANDed by the third AND gate AND3, and the first signal of the high level "1" is output to the third OR gate OR3; and the inverted signal od_mode_en of the open-drain enable signal of the low level "0" is output to the third OR gate OR3. After the fourth AND gate AND4 performs an “AND” operation on enb and the push-pull enable signal pp_output_en of the low level “0”, a second signal of the low level “0” is output to the third OR gate OR3; the third OR gate OR3 performs an “OR” operation on the first signal of the high level “1” and the second signal of the low level “0” to generate a third signal of the high level “1” and output it to the fifth AND gate AND5. Since the output configuration signal sda_set and the first enable signal i3c_en are also the high level “1”, the fifth AND gate AND5 outputs the second drive signal of the high level “1” to the second OR gate OR2.

[0083] When the I2C interface 10 works in the open-drain mode of the I2C mode, since the first enable signal i3c_en is low level “0”, the fifth AND gate AND5 outputs low level “0”, ie, the inverted signal of the second drive signal to the second OR gate OR2 .

[0084] When the I2C interface 10 works in the push-pull mode of the I3C mode, the open-drain enable signal od_mode_en of the low level "0" and the inverted signal pp_output_enb of the push-pull enable signal of the low level "0" are "ANDed" by the third AND gate AND3, and the first signal of the low level "0" is output to the third OR gate OR3; and the inverted signal od_mode_enb of the open-drain enable signal of the high level "1" and the push-pull enable signal pp_output_en of the high level "1" are "ANDed" by the fourth AND gate AND4, and the second signal of the high level "1" is output to the third OR gate OR3; the third OR gate OR3 performs an "OR" operation on the second signal of the high level "1" and the first signal of the low level "0", and generates a high level "1". The third signal is output to the fifth AND gate AND5. Since the output configuration signal sda_set and the first enable signal i3c_en are also high level "1", the fifth AND gate AND5 outputs a second drive signal of high level "1" to the second OR gate OR2, ensuring that the second OR gate OR2 outputs a first valid signal of high level "1" to the second AND gate AND2; since the other input signal of the second AND gate AND2 is an inverted data signal, when the inverted data signal is high level "1" and the first switch unit 110 is turned off, the second switch unit 310 can be turned on based on the inverted data signal of high level "1", thereby pulling down the potential of the data interface 200 to form an interface output signal of low level "0", ensuring that the interface output signal is in phase with the on-chip data signal.

[0085] Please continue reading Fig.12 In some embodiments of the present application, the second open-drain configuration subunit 3202 may include a sixth AND gate AND6, and the third configuration signal may include an output configuration signal sda_set and an open-drain enable signal od_mode_en, which are respectively configured as valid levels, and a first enable signal i3c_en, which is configured as an invalid level; wherein the output configuration signal sda_set, which is configured as a valid level, can be used to characterize that the SDA data line of the I2C interface 10 is in output mode, the first enable signal i3c_en, which is configured as an invalid level, can be used to characterize that the I2C interface 10 works in I2C mode, and the open-drain enable signal od_mode_en, which is configured as a valid level, can be used to characterize that the I2C interface 10 working in I2C mode is configured as an open-drain mode; the sixth AND gate AND6 can be used to perform an "AND" operation on the output configuration signal sda_set, the inverted signal i3c_enb of the first enable signal, and the open-drain enable signal od_mode_en to generate a third drive signal.

[0086] In an embodiment of the present application, the sixth AND gate AND6 can be connected to the target chip 20 or other control unit to access the third configuration signal; when the I2C interface 10 operates in an open-drain mode under the I2C mode, the third configuration signal may include an open-drain enable signal od_mode_en configured as a valid level, an output configuration signal sda_set configured as a valid level, and a first enable signal i3c_en configured as an invalid level.

[0087] For example, if the high level "1" is a valid level for each signal, the open-drain enable signal od_mode_en of the high level "1", the output configuration signal sda_set of the high level "1" and the inverted signal i3c_enb of the first enable signal of the high level "1" are ANDed by the sixth AND gate AND6, and the third drive signal of the high level "1" is output to the second OR gate OR2.

[0088] When the I2C interface 10 operates in the open-drain mode under the I3C mode, since the first enable signal i3c_en is at a low level "1", the reverse signal i3c_enb is at a low level "0", so that the sixth AND gate AND6 outputs a low level "0", that is, an inverted signal of the third drive signal to the second OR gate OR2.

[0089] like Fig.13 As shown, the signal output subunit 1202 may include a second NOT gate NOT2, through which the on-chip data signal data_out is inverted to form an inverted data signal output. It can be understood that the I2C interface 10 in the embodiment of the present application can not only output the on-chip data signal data_out from the data interface 200 to the outside of the chip, but also access the signal from the data interface 200, transmit the signal from the outside of the chip to the inside of the chip, so that the target chip 20 accesses the data_in signal; specifically, after the off-chip data signal is accessed by the data interface 200, it can be processed by the Schmitt trigger 1, the interference signal filter and the Schmitt trigger 2 to form the data_in signal and transmit it to the target chip 20.

[0090] The I2C interface 10 in the embodiment of the present application can realize I2C communication or I3C communication by configuring different configuration signals. On the basis of the traditional I2C interface, the push-pull mode and open-drain mode in the I3C mode are added, the signal transmission rate is improved, the application scope is expanded, and the adaptability is wider.

[0091] Based on the above embodiments, the present application also provides an interface chip, which may include a chip body and a Figures 2 to 13 Corresponding to the I2C interface in any embodiment.

[0092] The interface chip may be an integrated circuit (IC), or microcircuit, microchip, or chip. The chip may be, but is not limited to, a system on chip (SOC) or a system in package (SIP) chip.

[0093] Since the interface chip is provided with the I2C interface of the above embodiment, it has all the beneficial effects of the I2C interface of any of the above embodiments, which will not be described in detail here.

[0094] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as a preferred embodiment as above, it is not intended to limit the present application. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An I2C interface, characterized in that: Including push-pull output module and data interface; The push-pull output module is used to control the on-chip data signal of the target chip to be output from the data interface to the outside of the chip in response to a first configuration signal; wherein the first configuration signal is used to indicate that the I2C interface is configured as a push-pull mode under the I3C mode.

2. The I2C interface according to claim 1, characterized in that: The push-pull output module includes a first switch unit and a push-pull control unit, wherein the first end of the first switch unit is connected to the power output end, the second end of the first switch unit is connected to the data interface and the open-drain output module of the I2C interface, and the control end of the first switch unit is connected to the push-pull control unit; The push-pull control unit is configured to output an inverted data signal of the on-chip data signal to the first switch unit in response to the first configuration signal; The first switch unit is used to cooperate with the open-drain output module to generate an interface output signal in response to the inverted data signal and output it to the data interface; wherein the interface output signal is inverted with the inverted data signal.

3. The I2C interface according to claim 2, characterized in that: The push-pull control unit includes a push-pull mode configuration subunit, a signal output subunit and a first OR gate; The push-pull mode configuration subunit is used to invert the first configuration signal to obtain a first inverted signal and output it to the first OR gate; wherein the first inverted signal is a low level signal; The signal output subunit is used to invert the on-chip data signal to obtain the inverted data signal and output it to the first OR gate; The first OR gate is used to perform an OR operation on the first inverted signal and the inverted data signal, and output the inverted data signal to the first switch unit.

4. The I2C interface according to claim 3, characterized in that: The push-pull mode configuration subunit includes a first AND gate and a first NOT gate, and the first configuration signal includes an output configuration signal, a first enable signal, and a push-pull enable signal, which are respectively configured as valid levels; wherein the output configuration signal configured as a valid level is used to indicate that the SDA data line of the I2C interface is in output mode, the first enable signal configured as a valid level is used to indicate that the I2C interface works in the I3C mode, and the push-pull enable signal configured as a valid level is used to indicate that the I2C interface working in the I3C mode is configured as a push-pull mode; The first AND gate is used to perform an AND operation on the output configuration signal, the first enable signal and the push-pull enable signal to generate a push-pull drive signal; The first NOT gate is used to invert the push-pull driving signal to obtain the first inverted signal.

5. The I2C interface according to claim 1, characterized in that: The I2C interface also includes an open-drain output module connected to the data interface; The open-drain output module is used to control the on-chip data signal to be output from the data interface to the outside of the chip in response to a second configuration signal or a third configuration signal; wherein the second configuration signal is used to characterize the open-drain mode of the I2C interface working in the I3C mode; and the third configuration signal is used to characterize the open-drain mode of the I2C interface working in the I2C mode.

6. The I2C interface according to claim 5, characterized in that: The open-drain output module includes a second switch unit and an open-drain control unit, wherein a first end of the second switch unit is connected to the data interface, the data interface is further connected to a pull-up resistor, a second end of the second switch unit is connected to a ground end, and a control end of the second switch unit is connected to the open-drain control unit; The open-drain control unit is configured to output an inverted data signal of the on-chip data signal to the second switch unit in response to the second configuration signal or the third configuration signal; The second switch unit is used to generate an interface output signal in response to the inverted data signal and output it to the data interface; wherein the interface output signal is inverted with the inverted data signal.

7. The I2C interface according to claim 6, characterized in that: The open drain control unit comprises a first open drain configuration subunit, a second open drain configuration subunit, a second OR gate, a signal output subunit and a second AND gate; The first open-drain configuration subunit is used to generate a second drive signal according to the second configuration signal and output it to the second OR gate when the I2C interface works in the open-drain mode in the I3C mode, and to output an inverted signal of the second drive signal to the second OR gate when the I2C interface works in the open-drain mode in the I2C mode; wherein the second drive signal is a high level signal; The second open-drain configuration subunit is used to generate a third drive signal according to the third configuration signal and output it to the second OR gate when the I2C interface works in the open-drain mode in the I2C mode, and to output an inverted signal of the third drive signal to the second OR gate when the I2C interface works in the open-drain mode in the I3C mode; wherein the third drive signal is a high level signal; The second OR gate is used to perform an OR operation on the second drive signal and the inverted signal of the third drive signal, or the third drive signal and the inverted signal of the second drive signal, and output a first valid signal to the second AND gate; The signal output subunit is used to invert the on-chip data signal to obtain the inverted data signal and output it to the second AND gate; The second AND gate is used to perform an AND operation on the first valid signal and the inverted data signal, and output the inverted data signal to the second switch unit.

8. The I2C interface according to claim 7, characterized in that: The first open-drain configuration subunit includes a third AND gate, a fourth AND gate, a third OR gate and a fifth AND gate; the second configuration signal includes an open-drain enable signal, an output configuration signal and a first enable signal, which are respectively configured as valid levels, and a push-pull enable signal configured as an invalid level; wherein the open-drain enable signal configured as a valid level is used to indicate that the I2C interface is configured as an open-drain mode, the output configuration signal configured as a valid level is used to indicate that the SDA data line of the I2C interface is in output mode, and the first enable signal configured as a valid level is used to indicate that the I2C interface works in I3C mode; The third AND gate is used to perform an AND operation on the open-drain enable signal and the inverted signal of the push-pull enable signal to generate a first signal and output it to the third OR gate; The fourth AND gate is used to perform an AND operation on the inverted signal of the open-drain enable signal and the push-pull enable signal to generate a second signal and output it to the third OR gate; The third OR gate is used to perform an OR operation on the first signal and the second signal to generate a third signal and output it to the fifth AND gate; The fifth AND gate is used to perform an AND operation on the third signal, the output configuration signal and the first enable signal to generate the second drive signal.

9. The I2C interface according to claim 7, characterized in that: The second open-drain configuration subunit includes a sixth AND gate, and the third configuration signal includes an output configuration signal and an open-drain enable signal respectively configured as valid levels, and a first enable signal configured as an invalid level; wherein the output configuration signal configured as a valid level is used to indicate that the SDA data line of the I2C interface is in output mode, the first enable signal configured as an invalid level is used to indicate that the I2C interface works in I2C mode, and the open-drain enable signal configured as a valid level is used to indicate that the I2C interface working in I2C mode is configured as an open-drain mode; The sixth AND gate is used to perform an AND operation on the output configuration signal, the inverted signal of the first enable signal, and the open-drain enable signal to generate the third drive signal.

10. An interface chip, characterized in that: It comprises a chip body and an I2C interface as claimed in any one of claims 1 to 9 arranged on the chip body.

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