Multi-channel modularized ultrasonic front-end system based on FPGA (Field Programmable Gate Array)

Abstract

The invention relates to a multi-channel modularized ultrasonic front-end system based on an FPGA (Field Programmable Gate Array), belongs to the field of ultrasonic equipment, and solves the problems of slow delay parameter calculation and low delay precision of the existing system. The system comprises an FPGA main control module, a high-voltage driving circuit, an ultrasonic probe and a receiving and conditioning circuit, wherein the FPGA main control module comprises a transmitting module and a receiving module; the transmitting module generates a control signal based on the delay parameter, triggers the high-voltage driving circuit to generate a high-voltage pulse, and excites the ultrasonic probe to transmit a wave beam; the ultrasonic probe converts the reflected wave beam into an electric signal, sends the electric signal as an echo signal to a receiving conditioning circuit for processing, and transmits the echo signal to a receiving module to form a focusing signal; the receiving module comprises a delay signal calculation module and a focusing signal calculation module, and the delay signal calculation module converts the processed echo signal into a delay signal by adopting a mode of combining coarse delay and fine delay based on a radix-4-CORDIC algorithm; the latter adopts a radix-4-CORDIC algorithm to calculate a focusing signal based on the delay signal. The ultrasonic imaging front-end system is high in speed and precision.

Description

Technical Field

[0001] The present invention relates to the field of ultrasonic imaging equipment, and in particular to a multi-channel modular ultrasonic front-end system based on FPGA. Background Art

[0002] Medical ultrasound is widely used in clinical diagnosis due to its safety, non-destructiveness and ease of use. Since its front-end circuit and display are integrated, and most of the front-end circuits use discrete analog components, there are defects such as severe image flicker, few grayscale levels, poor imaging quality, and bulky size, which is not conducive to portability. With the rapid development of microelectronics technology, there are more and more types of integrated chips, and ultrasonic circuits are developing from analog to digital, and the overall equipment is gradually becoming smaller and more portable.

[0003] The current digital medical ultrasound imaging equipment has made some improvements in terms of size and portability. For example, the utility model patent with the patent number "CN213189711U" discloses a portable ultrasound imaging front-end system, including an ultrasound probe module, an array element selection module, a transceiver isolation module, an ultrasound echo receiving module, and a main control module electrically connected in sequence, as well as a high-voltage pulse generation module electrically connected to the array element selection module and the main control module, and a power supply control module electrically connected to each of the above modules. The above technical solution reduces the scale of the ultrasound imaging front-end system to a certain extent and improves the portability of the ultrasound imaging equipment by building the front-end circuit in a highly integrated manner.

[0004] However, the above system still has certain limitations, such as: the calculation speed of delay parameters is slow, the delay accuracy is not high, thus affecting the subsequent imaging effect, and the power supplies of various components interfere with each other. Summary of the invention

[0005] In view of the above analysis, an embodiment of the present invention aims to provide a multi-channel modular ultrasound front-end system based on FPGA to solve the problem that the delay parameter calculation speed of the existing ultrasound front-end system is slow and the delay accuracy is not high, thus affecting the subsequent imaging effect.

[0006] On the one hand, an embodiment of the present invention provides a multi-channel modular ultrasound front-end system based on FPGA, comprising:

[0007] Host computer, FPGA main control module, high-voltage drive circuit, ultrasonic probe, receiving conditioning circuit and power control module; wherein the power control module is used to supply power to each module of the system;

[0008] The transmission process includes: the transmission module inside the FPGA main control module generates a control signal based on the delay parameter, triggering the high-voltage drive circuit to generate a high-voltage pulse signal; the high-voltage pulse signal excites the ultrasonic probe according to the delay law to generate a transmission beam that moves and focuses toward the detection site;

[0009] The receiving process includes: the ultrasonic probe converts the beam reflected by the detected part into an electrical signal, which is transmitted as an echo signal to the receiving conditioning circuit for processing; the processed echo signal is transmitted to the receiving module of the FPGA master control, and forms a focusing signal which is transmitted to the host computer;

[0010] The receiving module includes a delay signal and a focus signal calculation module; wherein,

[0011] The delay signal calculation module adopts a combination of coarse delay and fine delay based on the radix 4-CORDIC algorithm to convert the processed echo signal into a delay signal based on the delay parameter; the focusing signal calculation module adopts the radix 4-CORDIC algorithm to calculate the focusing signal according to the delay signal.

[0012] Specifically, the delay parameters include: the time t1, t2, ..., t2 of the ultrasonic beam emitted by each array element of the probe to propagate to the focus F. N , and the delay time between other array elements and the array element with the shortest propagation time Δt1, Δt2, ..., Δt N ;in,

[0013] Δt q =t q -t min (q=1,2,...,N)

[0014] Where N is the number of array elements of the probe; q is the array element index; the coordinates of the focus F are provided by the host computer; t min is t1, t2, ..., t N The minimum value in .

[0015] Specifically, a focal law calculator is used to calculate the time t1, t2, ..., t2 for the ultrasonic beam emitted by each array element to propagate to the focus F. N ; Wherein, the array element and the focus are in different media, and the ultrasonic beam is refracted at the interface between the two media;

[0016] The focal law calculator calculates the time t from the ultrasonic beam emitted by the array element q to the focal point F. q The idea is:

[0017] Based on the array element coordinate r in medium 1 q , the focal coordinate of medium 2 is F = (x F ,y F), the propagation speeds of sound waves in medium 1 and medium 2 c1 and c2, and obtain t i The expression is:

[0018]

[0019] Where X is located at the refraction interface [0, x F ) in; S1 is the path from the coordinates of the array element in medium 1 to X, and S2 is the path from X to the focus F;

[0020] Get X c , so that the propagation time t q (X c ) is minimized, that is, the propagation path of the sound wave is: r q →X c →F is the shortest;

[0021] Let X = X c , substitute t q (X), we can get the time t that the ultrasonic beam emitted by array element i propagates to the focus F. q .

[0022] An interval compression method is used to obtain the shortest propagation path of the emitted sound wave.

[0023] Furthermore, the interval compression method is used to obtain the X that minimizes the sound wave propagation time. c ;

[0024] The interval compression method is used to quickly search for the root of a univariate high-order equation f(X)=0. The root of the equation is X c ; Among them, function f(X) = t i ′(X), that is, function t i The derivative of (X) with respect to X is t i ′(X);

[0025] The interval [0, x F ) According to the unit length Equally divided; the value of n is determined by the resolution of the system;

[0026] Use interval compression method to iterate n times and find X c The idea of ​​approximating the value is:

[0027] For the i-th iteration, where i≤n-1, let Substitute f(X) into f(X) to calculate f(X p );

[0028] Judgement|f(X i )| is it less than the accuracy error Δ, the accuracy error is determined by the system resolution; if so, output X i As X c; Otherwise, judge f(X i ) is greater than 0;

[0029] If so, at the i+1th iteration, take X i+1 =X p +d; otherwise, take

[0030] Specifically, a 12-bit digital ultrasound system is used, and the resolution of the system is: The number of iterations of the interval compression method is n=12.

[0031] Specifically, the receiving module obtains the delayed signal of each array element, including the following steps:

[0032] Array element delay parameter Δt calculated based on focal law q and coarse delay duration Get detailed delay duration

[0033] Based on fine delay duration Get the rotation angle between two vectors in CORDIC algorithm vector mode Among them, f s represents the sampling frequency of the system; the two vectors are respectively the processed echo signal x q and the delayed signal D to be solved q ;

[0034] The rotation mode of the base 4-CORDIC algorithm is used to solve the values ​​of each element of the rotation matrix between the processed echo signal and the delayed signal; the rotation matrix is

[0035] Apply the rotation matrix to the processed echo signal x i , we can get the delayed signal D corresponding to the array element q q (I q , Q q );where I q , Q q They represent the two orthogonal components of the delayed signal respectively.

[0036] Furthermore, the focus signal R N The focusing signal is obtained by superimposing the delayed signals of each array element and performing a square root operation using the vector mode of the radix 4-CORDIC algorithm:

[0037]

[0038] in,

[0039] Specifically, the base 4-CORDIC algorithm iteration formula is:

[0040]

[0041] The calibration factor is:

[0042]

[0043] Among them, the rotation factor σ i ∈{-2, -1, 0, 1, 2}.

[0044] Furthermore, by constructing the rotation factor σ i The selection function optimizes the base 4-CORDIC algorithm; specifically:

[0045] In the rotation mode, let the weight w i =4 i z i , when the number of iterations i = 0, the rotation factor is selected according to the following formula:

[0046]

[0047] When the number of iterations i>0, the rotation factor is selected according to the following formula:

[0048]

[0049] The rotation factor σ i The selection function in vector mode is:

[0050] In vector mode, let the weight w i =4 i y i , the rotation factor is selected according to the following formula:

[0051]

[0052] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0053] 1. The delay parameters are calculated by the focusing rule based on the interval compression method, which can quickly calculate the delay parameters while meeting the engineering requirements.

[0054] 2. A receiving module based on the radix 4-CORDIC algorithm is used. The trigonometric function value and the vector modulus value are calculated using the radix 4-CORDIC algorithm respectively, which can quickly solve the focusing signal and improve the efficiency of the ultrasonic system.

[0055] 3. When the receiving module calculates the delayed signal, a combination of coarse delay and fine delay based on the radix 4-CORDIC algorithm is adopted to achieve a high-precision delay process and improve the subsequent imaging effect.

[0056] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. In the entire drawings, the same reference symbols represent the same components;

[0058] Figure 1 It is a schematic diagram of a multi-channel modular ultrasound front-end system based on FPGA;

[0059] Figure 2 This is a schematic diagram of the internal single-channel structure of AFE5805;

[0060] Figure 3 Read and write controller state flow chart for AFE5805 chip;

[0061] Figure 4 This is a schematic diagram of the sound wave emitted by the central array element and propagating to the focus;

[0062] Figure 5 It is a schematic diagram of the iterative process of the interval compression method;

[0063] Figure 6 This is the internal structure diagram of the DDRIO register;

[0064] Figure 7 Schematic diagram of calculating the delay signal for the 4-CORDIC algorithm;

[0065] Figure 8 Schematic diagram of calculating the delay signal and the focusing signal using the 4-CORDIC algorithm. DETAILED DESCRIPTION

[0066] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0067] The embodiment of the present invention provides a multi-channel modular ultrasound front-end system based on FPGA, such as Figure 1 As shown, it includes: a host computer, an FPGA main control module, a high-voltage drive circuit, an ultrasonic probe, a receiving conditioning circuit and a power control module; wherein the power control module is used to supply power to each module of the system; the host computer module is mainly used to display the ultrasonic signals during the debugging process of each module of the circuit to verify the validity of the data.

[0068] During implementation, the transmission process includes: the host computer provides the focal coordinates, the focusing law calculator calculates the delay parameters of each array element, the transmission module inside the FPGA main control module generates a control signal based on the delay parameters, triggers the high-voltage drive circuit to generate a high-voltage pulse signal; the high-voltage pulse signal excites the ultrasonic probe according to the delay law, and generates a transmission beam that moves and focuses toward the detection part; wherein, the focal coordinates are provided by the host computer according to the position of the detected part.

[0069] The receiving process includes: the ultrasonic probe converts the beam reflected by the detected part into an electrical signal, and transmits it as an echo signal to the receiving conditioning circuit for processing; the processed echo signal is transmitted to the receiving module of the FPGA master control, forming a focusing signal and transmitting it to the host computer.

[0070] The receiving module includes a delay signal calculation module for each array element and a focusing signal calculation module; wherein the delay signal calculation module adopts a combination of coarse delay and fine delay based on a base 4-CORDIC algorithm, and converts the processed echo signal into a delay signal based on the delay parameter calculated by the focal law calculator; the focusing signal calculation module adopts a base 4-CORDIC algorithm to calculate the focusing signal according to the delay signal.

[0071] For each position of the detection part, the host computer provides the corresponding focal coordinates. According to the focal coordinates provided each time, the above system is used to perform the focusing deflection transmission of the transmitted sound wave and the receiving focusing process of the echo signal to complete the collection of the focusing signal at the corresponding position of the detection part. The host computer performs subsequent filtering, demodulation, and gain compensation processing on the focused signal collected each time, extracts the echo signal with diagnostic value, and finally reconstructs the image to obtain a high-quality ultrasound image.

[0072] Specifically, the high-voltage drive circuit uses the MAX4940 chip. The MAX4940 chip has 4 logic input channels, each of which consists of three input terminals: positive logic INP, negative logic INN, and enable EN, and can generate a transmission pulse with a maximum voltage of 220V. The control signal of the MAX4940 chip is jointly determined by the INP and INN signals. INP controls the P-channel field effect transistor, and INN controls the N-channel field effect transistor. During normal operation, only one of the field effect transistors controlled by the two signals is turned on, otherwise it will cause a short circuit in the high-voltage power supply.

[0073] The receiving conditioning circuit is responsible for high-speed acquisition, processing and transmission of the echo signal to the FPGA. Preferably, the receiving conditioning circuit adopts the AFE5805 chip, which has high integration and low power consumption. Specifically, each channel of the chip includes a low noise amplifier (LNA), a voltage controlled attenuator (VCA), a programmable gain amplifier (PGA), a low pass filter (LPF), and a 12-bit analog-to-digital converter (ADC). Finally, the converted data is output through the LVDS interface. Among them, the operating frequency of the ADC is 10-50MSPS. When the conversion rate is 40MSPS, the power consumption of each channel is 122mV. The chip communicates with the FPGA main control module in SPI mode.

[0074] AFE5805 internal single channel structure diagram is as follows Figure 2 The signal processing flow is as follows: first, the LNA is used to amplify the millivolt-level echo signal to reduce noise and improve the noise ratio of the output signal; then, the signal gain control is achieved through the VCA and PGA, and the high-frequency noise signal is filtered out by the LPF; finally, the ADC is used to perform A / D conversion on the ultrasonic signal, and the converted digital signal is output through the LVDS interface in the form of a low voltage differential signal.

[0075] AFE5805 has two selection modes, namely continuous Doppler (CW) mode and time gain control (TGC) mode. In CW mode, the signal will pass through LNA, V / I conversion, CW matrix switch, and finally CW / I signal output; in TGC mode, the signal will pass through LNA, VCA, PGA, LPF, A / D conversion in sequence, which can achieve signal amplification, filtering, analog-to-digital conversion and other medical ultrasound imaging requirements, and better meet practical applications. Therefore, the present invention prefers TGC mode.

[0076] Specifically, the idea of ​​reading AFE5805 data is:

[0077] Using a state machine design, when the rising edge of the data clock arrives, the odd bits in the 12-bit data are read; when the falling edge of the data clock arrives, the even bits in the 12-bit data are read; when the rising edge of the data frame clock arrives, the 12-bit data is spliced ​​and measured into a single sampled data.

[0078] For the communication control of the analog front end AFE5805, it is necessary to configure the corresponding configuration registers of each module of LNA, VCA, PGA, LPF, and ADC through the serial peripheral SPI under the control of FPGA. The SPI interface mainly realizes the configuration operation of the on-chip register through the chip select signal CS, the register reset signal RESET, the serial clock signal SCLK, and the serial data signal SDATA.

[0079] AFE5805 chip read and write controller state flow chart as follows Figure 3 As shown. First, the system starts the RESET signal to initialize the SPI communication module, and starts to transmit data when the write data signal WR is high. When the first clock falling edge of WR is high, the chip select signal CS is set to 0, the AFE5805 chip is selected, and the DATA data and address signal addr are read at the same time, and the highest bit is mounted on the SDATA line to output the first byte, and SCLK is mounted on the clock. When all data transmission is completed, the CS signal is set to 1, SCLK is set to 1, SDATA is set to 0, and finally the ACK signal is given to show that the data transmission has been completed.

[0080] The power supply module is responsible for providing the power supply voltage required for stable operation of each module, thereby ensuring the normal power supply of each module. Specifically, the present invention adopts a power supply mode of multiple voltage modules, and the modules with low voltage adopt low voltage. On the one hand, compared with the mode of adopting the same voltage module as a whole, the multiple voltage module is conducive to reducing the power consumption of the system; on the other hand, the power supplies of each module do not interfere with each other, ensuring the stability of the system.

[0081] Specifically, one part of the power module is mainly used to provide high-voltage power to the probe, and the other part is used to provide power to the echo receiving circuit AFE5805 chip, in order to achieve high integration of the entire ultrasound system. The power module uses an integrated chip, specifically: the transmitting circuit module uses the MAX4940 high-voltage transmitting chip, which requires a total of five power supplies: VDD (+3.3V), VCC (+5V), VEE (-5V), VPP (+58V), and VNN (-58V); for the input power supply, a +5V / 1A adapter is used; for the +3.3V power supply, AMS117-3.3V is preferred; for the design of the high-voltage power supply, an external switching power supply is used to generate it. Before connecting to the transmitting front end, first connect a 10 The μF / 63V capacitor is used for filtering, thereby greatly reducing the interference of high-frequency noise in the switching power supply; the power supply design of the AFE5805 module requires a clean and stable power supply to obtain excellent LVDS timing performance and maximum signal-to-noise ratio; the AFE5805 module requires 1.8V, 3.3V and 5V power supplies, among which the 1.8V power supply is mainly used to power the LVDS timing driver, the 3.3V power supply is used for the analog power supply of VCA and the digital power supply of VCA, and the 5V power supply is used for the analog power supply of VCA. In view of the above design characteristics of the AFE5805 power supply, the 1.8V power supply is preferably the TPS79318 chip of TI, the 3V power supply is preferably the TPS79633 chip; and the 5V power supply is preferably the TPS54331 chip, which has a large current output capability and can be used as a 1.8V and 3.3V power supply.

[0082] The voltage controlled attenuator VCA requires an additional DAC module to adjust its external voltage, so as to realize the control of VCA. Preferably, the DAC081C085 chip is selected to control the output voltage of the voltage controlled attenuator. The chip is an 8-bit single-channel digital-to-analog converter with a controllable voltage range of +2.7 to +5.5V, and adopts the control method of SPI communication interface. The voltage required by this system is 0 to +1.2V, and the voltage can be controlled by writing address and writing data in sequence.

[0083] Specifically, the delay parameters include: the time t1, t2, ..., t2 of the ultrasonic beam emitted by each array element of the probe to propagate to the focus F. N , and the delay time between other array elements and the array element with the shortest propagation time Δt1, Δt2, ..., Δt N ;in,

[0084] Δt q =t q -t min (q=1,2,...,N)

[0085] Where N is the number of array elements of the probe; q is the array element index; the coordinates of the focus F are provided by the host computer; t min is t1, t2, ..., t N The minimum value in .

[0086] Specifically, the present invention uses a focal law calculator to calculate the time t1, t2, ..., t2 for the ultrasonic beam emitted by each array element to propagate to the focus F. N .like Figure 4 As shown, the array element and the focus are in different media, and the ultrasonic beam is refracted at the interface between the two media; the focal law calculator calculates the time t for the array element q to transmit the ultrasonic beam to the focus F. q The idea is:

[0087] Based on the array element coordinate r in medium 1 q , the focal coordinate of medium 2 is F = (x F ,y F ), the propagation speeds of sound waves in medium 1 and medium 2 c1 and c2, and obtain t i The expression is:

[0088]

[0089] Where X is located at the refraction interface [0, x F ) in; S1 is the path from the coordinates of the array element in medium 1 to X, and S2 is the path from X to the focus F;

[0090] Get X c , so that the propagation time tq (X c ) is minimized, that is, the propagation path of the sound wave is: r q →X c →F is the shortest;

[0091] Let X = X c , substitute t q (X), we can get the time t that the ultrasonic beam emitted by array element i propagates to the focus F. q .

[0092] Furthermore, the interval compression method is used to obtain the X that minimizes the sound wave propagation time. c ;

[0093] The interval compression method is used to quickly search for the root of a univariate high-order equation f(X)=0. The root of the equation is X c ; Among them, function f(X) = t i ′(X), that is, function t i The derivative of (X) with respect to X is t i ′(X);

[0094] The interval [0, x F ) According to the unit length Equally divided; the value of n is determined by the resolution of the system;

[0095] Use interval compression method to iterate n times and find X c The idea of ​​approximating the value is:

[0096] For the i-th iteration, where i≤n-1, let Substitute f(X) into f(X) to calculate f(X i );

[0097] Judgement|f(X i )| is it less than the accuracy error Δ, the accuracy error is determined by the system resolution; if so, output X i As X c ; Otherwise, judge f(X i ) is greater than 0;

[0098] If so, at the i+1th iteration, take X i+1 =X i +d; otherwise, take X i+1 =X i -d.

[0099] For example, Figure 4 As shown, Taking the array element at the center as an example, the focus rule based on the interval compression method is used to calculate the delay parameter t q The process:

[0100] The center element is located on the y-axis, with coordinates (0, H0). The refraction interface is parallel to the x-axis. α and β are the angles of incidence and refraction, respectively. The coordinates of the focus F are (x F ,y F ), S1 and S2 are the acoustic paths of the transmitting beam of the central array element in the air and in the detection part, respectively, and c1 and c2 are the velocities of the acoustic wave in the air and in the detection part, respectively.

[0101] The time it takes for the central array element to transmit the beam to the focus F satisfies the following expression:

[0102]

[0103] According to the principle of the shortest path propagation of the sound beam, solving the above equation is equivalent to solving [0, x F ) within the range, we get Minimum, therefore, Find the partial derivative:

[0104]

[0105] Let f(X) = 0, and we get the equation:

[0106]

[0107] The above equation is a single-variable high-order equation. Solving X is very complicated and difficult to achieve in actual engineering.

[0108] Therefore, the present invention proposes an interval compression method to quickly search for a univariate high-order engineering solution X.

[0109] The principle of interval compression method is as follows, and the iterative process is as follows Figure 5 As shown:

[0110] Since the above one-variable high-order equation is in X∈[0,x F ) is continuously differentiable, and there is only one minimum real number solution X c , so in X∈[0,X c ) is monotonically decreasing, X∈[X c , x F ) is monotonically increasing, so the solution can be searched for in small intervals by continuously dividing the interval into equal parts. The specific search process is:

[0111] The interval [0, x F ) is divided into equal lengths of equal parts.

[0112] The first search will Substitute into f(X) and find the value

[0113] The second search, if but Will Substitute the value like but Will Substitute the value Repeat the above search steps;

[0114] Therefore, for the i-1th search, the value of the dependent variable for the i-1th search iteration is f(X i-1 ), then according to f(X i-1 ) determines the value of the next iteration independent variable:

[0115]

[0116] When |f(X i )| is less than the precision error Δ, the search can be stopped and X can be output i As X c ; Substitution The time it takes for the central array element to transmit the beam to the focus F can be calculated

[0117] In the above method, the time function The maximum relative error is:

[0118]

[0119] In the present invention, for a 12-bit digital ultrasound system, the resolution is Then recursion n = 12 times can meet the engineering requirements.

[0120] Similarly, the delay parameters of the remaining array elements are t1, t2, ..., t N It can be calculated according to the above focusing law.

[0121] Each time the focal law calculator calculates the focal law, N delay parameters are required: t1, t2, ..., t N , take the minimum value t min ; Then the relative delay differences between other array elements and the minimum value are: Δt q =t q -t min , q=1,2,…,N.

[0122] The focal law precise transmission delay of the present invention is controlled by FPGA, and the specific algorithm is implemented by a digital phase-locked loop PLL and a dual-rate input and output DDRIO port.

[0123] The delay time can be controlled by a sequential logic circuit. Since the DDRIO register can control the sending and receiving of data at both the rising and falling edges of the clock, compared with the counter delay scheme that only performs counting control at a certain valid clock edge, the DDRIO register can send or capture data at twice the clock frequency and has a delay accuracy of half a cycle, that is, the delay accuracy can be doubled.

[0124] Figure 6 The internal structure diagram of the DDRIO designed for the present invention. It consists of two circuits: the data Data_p and Data_n are input into two D flip-flops respectively; the clock signal clk is used as an enable signal to control the 2_to_1MUX to double the data rate. Taking the half cycle of the clock signal clk as a unit, the delay control of the output signal Data_out can be achieved by simply selecting the appropriate values ​​of Data_p and Data_n. When the clock rises, the register captures the data Data_p and Data_n, and the output is fed to a 2_to_1 MUX with clock control clk, so that the rate of the output signal Data_out is doubled.

[0125] Specifically, the DDRIO input and output logic relationship is set to: {Data_p, Data_n} = '10', the output signal Data_out jumps from '0' to '1' within half a cycle, and the Data_out output signal is Delay (T s = clock cycle); {Data_p, Data_n} = '11' or '00', the output signal Data_out remains unchanged; {Data_p, Data_n} = '01', the output signal Data_out changes from '1' to '0' within half a cycle, and the output signal Data_out changes from '1' to '0' within half a cycle. Delay.

[0126] In the ultrasonic system of the present invention, the relative delay T of any two pulses B0 and B1 is realized. delay This can be achieved through the following solutions:

[0127] (1) When N is an odd number (i.e., N = 2n + 1, n∈Z + ):

[0128] When pulse B0 is generated, {Data_p, Data_n} inputs {0,0}|t0, {1,0}|t1, {1,1}|t2, ..., {1,1}|t2 to DDRIO according to the clock beat. M , {0, 1}|t M+1 , {0, 0}|t M+2 value (the value-taking moment M is determined by the resonance period of the probe).

[0129] When pulse B1 is generated, {Data_p, Data_n} inputs {0, 0}|t0, {0, 0}|t1, ..., {0, 0}|t to DDRIO according to the clock beat. n ,{1,0}|t n+1 ,{1,1}|t n+2 , ..., {1, 1}|t M , {0, 1}|t M+1 , {0, 0}|t M+2 value.

[0130] (2) When N is an even number (i.e., N = 2n, n∈Z + ):

[0131] When pulse B0 is generated, {Data_p, Data_n} inputs {0,0}|t0, {1,1}|t1, {1,1}|t2, ..., {1,1}|t2 to DDRIO according to the clock beat. M , {0, 0}|t M+1 value.

[0132] When pulse B1 is generated, {Data_p, Data_n} inputs {0, 0}|t0, {0, 0}|t1, ..., {0, 0}|t to DDRIO according to the clock beat. n ,{1,1}|t n+1 , ..., {1, 1}|t M , {0, 0}|t M+1 value.

[0133] Exemplarily, the system clock period T is set in the present invention s =5ns, probe frequency 5MHz (i.e. resonance period 200ns), which generates pulses B0 and B1 emission relative delay Td elay =5ns, then {Data_p, Data_n} inputs {0,0}|t0, {1,1}|t1, {1,1}|t2, ..., {1,1}|t to DDRIO according to the clock beat. 20 ,{1,1}|t 21 and {0,0}|t0, {0,0}|t1, {1,1}|t2, ..., {1,1}|t 21 ,{1,1}|t 22 value.

[0134] The present invention realizes the relative delay T delay = 2.5ns, {Data_p, Data_n} inputs {0,0}|t0, {1,0}|t1, {1,1}|t2, ..., {0,1}|t 21 , {0, 0}|t22 and {0,0}|t0, {0,0}|t1, {1,0}|t2, {1,1}|t3, ..., {0,1}|t 22 , {0, 0}|t 23 value.

[0135] In summary, the present invention analyzes the working process of DDRIO and s At the clock cycle frequency, it can be achieved The periodic ultrasonic pulse excitation is precisely delayed, which is only possible with T s The delay precision clock control system can increase the delay precision by 2 times.

[0136] The receiving delay Δt of the present invention q By the coarse delay Δt qc With fine delay Δt qx The coarse delay accuracy depends on the system clock cycle, and can be read and written according to different clock beats through the timing circuit. The fine delay calculation of the present invention is different from the traditional PLL implementation, and the vector mode under the optimized base 4-CORDIC algorithm is used to solve the angle between two vectors.

[0137] Specifically, the receiving module obtains the delayed signal of each array element, including the following steps:

[0138] Array element delay parameter Δt calculated based on focal law q and the coarse delay time Δt qc , get the fine delay time Δt qx =Δt q -Δt qc ;

[0139] Based on the fine delay time Δt qx , get the rotation angle between two vectors in CORDIC algorithm vector mode Among them, f s represents the sampling frequency of the system; the two vectors are respectively the processed echo signal x q and the delayed signal D to be solved q ;

[0140] The rotation mode of the base 4-CORDIC algorithm is used to solve the values ​​of each element of the rotation matrix between the processed echo signal and the delayed signal; the rotation matrix is

[0141] Apply the rotation matrix to the processed echo signal x i , we can get the delayed signal D corresponding to the array element q q (I q , Q q );where I q , Qq They represent the two orthogonal components of the delayed signal respectively.

[0142] The above process is as follows Figure 7 As shown, firstly, the echo signal of any array element is orthogonalized as the input signal x, and its phase is rotated to obtain the delayed signal D(I, Q) output by the array element. Among them, the input and output signals satisfy:

[0143]

[0144]

[0145] Furthermore, the focus signal R N The focusing signal is obtained by superimposing the delayed signals of each array element and performing a square root operation using the vector mode of the radix 4-CORDIC algorithm:

[0146]

[0147] in,

[0148] Specifically, the base 4-CORDIC algorithm iteration formula is:

[0149]

[0150] The calibration factor is:

[0151]

[0152] Among them, the rotation factor σ i ∈{-2, -1, 0, 1, 2}.

[0153] Furthermore, due to the rotation factor σ i The selected interval has some overlapping areas, which is the standardized σ i Select and simplify the algorithm to construct a specific rotation factor σ i Select function to optimize 4-CORDIC algorithm σ i By constructing the rotation factor σ i The selection function optimizes the base 4-CORDIC algorithm, specifically:

[0154] In the rotation mode, let the weight w i =4 i z i , when the number of iterations i = 0, the rotation factor is selected according to the following formula:

[0155]

[0156] When the number of iterations i>0, the rotation factor is selected according to the following formula:

[0157]

[0158] Initialization Value After n iterations, we get

[0159] The rotation factor σ i The selection function in vector mode is:

[0160] In vector mode, let the weight w i =4 i y i , the rotation factor is selected according to the following formula:

[0161]

[0162] Initialization Value After n iterations, we get

[0163] The above-mentioned process of solving the focusing signal based on the base 4-CORDIC algorithm is as follows: Figure 8 In general, the delay value Δt is calculated by the focal law q And the fine delay value Δt qx , get the phase radian value The echo vector delay signal value is solved based on the rotation mode of the 4-CORDIC algorithm, and the focusing signal formed by the N array element delay signals is completed based on the vector mode of the 4-CORDIC algorithm; the focusing signal R can be solved quickly in real time. N , which is very suitable for FPGA parallel computing.

[0164] In general, the technical solution of the present invention can at least achieve the following beneficial effects:

[0165] 1) By combining coarse delay and fine delay, the transmission delay accuracy of the present invention is improved, the side lobes are better suppressed, and the resolution of the synthesized sound beam is increased, thereby improving the imaging quality;

[0166] 2) Using the focal law calculator based on the interval search method, the delay parameters can be quickly calculated under the condition of meeting the engineering requirements;

[0167] 3) The power supply system of the present invention adopts a multi-voltage module, which reduces the power consumption of the system, and the power supplies of each module do not interfere with each other, and the stability is high; at the same time, the power supply adopts an integrated chip, the size of the device is reduced, and the portability of the system is improved.

[0168] 4) By using the DDRIO register to control the transmission delay, the ultrasonic pulse excitation precise delay of half a clock cycle can be achieved. Compared with a simple clock control system, the delay accuracy is improved by 2 times.

[0169] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0170] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A multi-channel modular ultrasound front-end system based on FPGA, characterized in that: include: FPGA main control module, high voltage drive circuit, ultrasonic probe and receiving conditioning circuit; the FPGA main control module includes a transmitting module and a receiving module; During the transmission process, the transmission module generates a control signal based on the delay parameter, triggering the high-voltage drive circuit to generate a high-voltage pulse signal; the high-voltage pulse signal excites the ultrasonic probe according to the delay law, generating a transmission beam that moves and focuses toward the detection site; During the receiving process, each array element of the ultrasonic probe converts the beam reflected by the detected part into an electrical signal, which is sent as an echo signal to the receiving conditioning circuit for processing; The processed echo signal is transmitted to the receiving module to form a focusing signal; The receiving module includes a delay signal calculation module and a focus signal calculation module; wherein, The delay signal calculation module adopts a combination of coarse delay and fine delay based on the radix 4-CORDIC algorithm to convert the processed echo signals of each array element into delay signals based on the delay parameters; the focusing signal calculation module adopts the radix 4-CORDIC algorithm to calculate the focusing signal based on each delay signal.

2. The FPGA-based multi-channel modular ultrasound front-end system according to claim 1, characterized in that: The delay parameters include: the time t1, t2, ..., t2 for the ultrasonic beam emitted by each array element of the probe to propagate to the focus F. N , and the delay time between other array elements and the array element with the shortest propagation time Δt1, Δt2, ..., Δt N ;in, Δt q =t q -t min (q=1,2,...,N) Where N is the number of array elements of the probe; q is the array element index; the coordinates of the focus F are provided by the host computer; t min is t1, t2, ..., t N The minimum value in .

3. The FPGA-based multi-channel modular ultrasound front-end system according to claim 2, characterized in that: The FPGA main control module also includes a focal law calculator; the focal law calculator calculates the time t1, t2, ..., t2 for the ultrasonic beam emitted by each array element to propagate to the focal point F based on the focal point coordinates received from the host computer. N ; Wherein, the array element and the focus are in different media, and the ultrasonic beam is refracted at the interface between the two media; The focal law calculator calculates the time t from the ultrasonic beam emitted by the array element q to the focal point F. q ,include: Based on the array element coordinate r in medium 1 q , the focal coordinate of medium 2 is F = (x F ,y F ), the propagation speeds of sound waves in medium 1 and medium 2 c1 and c2, and obtain t i The expression is: Where X is located at the refraction interface [0, x F ) in; S1 is the path from the coordinates of the array element in medium 1 to X, and S2 is the path from X to the focus F; Get X c , so that the propagation time t q (X c ) is minimized, that is, the propagation path of the sound wave is: r q →X c →F is the shortest; Let X = X c , substitute t q (X), we can get the time t that the ultrasonic beam emitted by array element i propagates to the focus F. q .

4. The FPGA-based multi-channel modular ultrasound front-end system according to claim 3, characterized in that: Get the X that makes the sound wave travel time the shortest c ,include: Use interval compression method to quickly search for the root of a univariate high-order equation f(X) = 0. The root of the equation is X c ; Among them, function f(X) = t i ′(X), that is, function t i The derivative of (X) with respect to X is t i ′(X); The interval [0, x F ) According to the unit length Equally divided; the value of n is determined by the resolution of the system; Use interval compression method to iterate n times and find X c Approximation value, where For the i-th iteration, where i≤n-1, let Substitute f(X) into f(X) to calculate f(X i ); Judgement|f(X i )| is it less than the accuracy error Δ, the accuracy error is determined by the system resolution; if so, output X i As X c ; Otherwise, judge f(X i ) is greater than 0; If so, at the i+1th iteration, take X i+1 =X i +d; otherwise, take X i+1 =X i -d.

5. The FPGA-based multi-channel modular ultrasound front-end system according to claim 4, characterized in that: Using a 12-bit digital ultrasound system, the resolution of the ultrasound front-end system is: The number of iterations of the interval compression method is n=12.

6. The FPGA-based multi-channel modular ultrasound front-end system according to claim 5, characterized in that: The receiving module obtains the delayed signal of each array element, including the following steps: Array element delay parameter Δt calculated based on focal law q and coarse delay duration Get detailed delay duration Based on fine delay duration Get the rotation angle between two vectors in CORDIC algorithm vector mode Among them, f s represents the sampling frequency of the system; the two vectors are respectively the processed echo signal x q and the delayed signal D to be solved q ; The rotation mode of the radix 4-CORDIC algorithm is used to solve the values ​​of each element of the rotation matrix between the processed echo signal and the delayed signal; the rotation matrix is Apply the rotation matrix to the processed echo signal x i , we can get the delayed signal D corresponding to the array element q q (I q , Q q );where I q , Q q They represent the two orthogonal components of the delayed signal respectively.

7. The FPGA-based multi-channel modular ultrasound front-end system according to claim 6, characterized in that: Focus signal R N The superposition of the delayed signals of each array element is obtained by using the vector mode of the base 4-CORDIC algorithm to perform square root operation: in, 8. The FPGA-based multi-channel block ultrasound front-end system according to any one of claims 1 to 7, characterized in that: The base 4-CORDIC algorithm iteration formula is: The calibration factor is: Among them, the rotation factor σ i ∈{-2, -1, 0, 1, 2}.

9. The FPGA-based multi-channel modular ultrasound front-end system according to claim 8, characterized in that: By constructing the rotation factor σ i The selection function optimizes the base 4-CORDIC algorithm; specifically: In the rotation mode, let the weight w i =4 i z i , when the number of iterations i = 0, the rotation factor is selected according to the following formula: When the number of iterations i>0, the rotation factor is selected according to the following formula:

10. The FPGA-based multi-channel modular ultrasound front-end system according to claim 9, characterized in that: The rotation factor σ i The selection function in vector mode is: In vector mode, let the weight w i =4 i y i , the rotation factor is selected according to the following formula:

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