Three-dimensional electromagnetic interference isolation structure, preparation method and chip

Abstract

The invention relates to the technical field of electromagnetic interference shielding in a chip, and provides a three-dimensional electromagnetic interference isolation structure, a preparation method and a chip, and the three-dimensional electromagnetic interference isolation structure comprises a plurality of grounding metal gaskets and a plurality of grounding holes. The grounding metal gasket is arranged on the surface of the chip; the plurality of grounding metal gaskets are arranged along the length direction of the gap between the adjacent function modules; one grounding metal gasket corresponds to two grounding holes; one end of the grounding hole is connected with the grounding metal gasket, and the other end of the grounding hole is connected with the grounding layer of the chip; and a bonding wire is bridged between every two adjacent grounding metal gaskets. According to the invention, the electromagnetic interference between two adjacent functional modules needing to be isolated in the chip can be reduced, various packaging designs can be compatible, the consistency of products is ensured, and the later debugging is also facilitated under the condition that the layout design of the chip is not changed, so that the risk caused by the redesign of the chip due to the electromagnetic interference is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of electromagnetic interference shielding inside a chip, and in particular to a three-dimensional electromagnetic interference isolation structure, a preparation method and a chip. Background Art

[0002] With the development of chip technology, more and more circuit functions are integrated into single-chip chips. However, with the increase of chip integration and chip operating frequency, the electromagnetic interference problem of each functional module inside the chip has become more and more prominent. In order to effectively solve the electromagnetic interference problem of each functional module inside the chip, the industry has adopted a variety of technologies and strategies, mainly including the following ways:

[0003] 1. Shielding technology

[0004] (1) Metal shielding

[0005] Metal shielding is used on chip packages and circuit boards to isolate sensitive circuits and high radiation areas. This method can effectively isolate electromagnetic interference between chips, but it cannot solve the mutual interference between sub-modules inside the chip.

[0006] (2) Electromagnetic shielding materials

[0007] By bonding absorbing materials to the metal shield of a single chip, the spatial electromagnetic coupling path near the chip is changed to reduce the propagation of electromagnetic interference. This method is highly random and requires constant manual attempts to find the sensitive location of spatial coupling. Moreover, this method is difficult to ensure consistency, making it difficult to meet the requirements of mass production.

[0008] 2. Grounding and wiring strategy

[0009] (1) Grounding strategy

[0010] Grounding holes are arranged in the electromagnetic coupling sensitive area inside the chip to form a metal shield inside the chip substrate. This method can effectively block the electromagnetic coupling inside the chip substrate, but it cannot reduce the electromagnetic spatial coupling near the chip.

[0011] (2) Wiring strategy

[0012] The signal transmission lines inside the chip are optimized, so that the multiple transmission lines that may generate large spatial radiation interference are routed away and vertically to reduce the mutual interference between signals. This method can reduce the spatial coupling interference between the modules of the chip, but due to the limitations of chip size and design, the wiring is often not designed in an ideal way to achieve a perfect effect.

[0013] 3. Software and hardware collaborative design

[0014] (1) EMI simulation and analysis

[0015] Use EMI simulation tools during the design phase to predict and analyze possible interference sources and perform preventive design.

[0016] 4. Packaging technology

[0017] (1) Low interference packaging

[0018] Develop low EMI packaging technologies, such as Flip-Chip, BGA (Ball Grid Array), etc., to reduce the inductance effect of internal leads.

[0019] EMI simulation and analysis and low-interference packaging can effectively reduce possible electromagnetic interference problems. However, since the accuracy of simulation tools and simulation methods can only approach the actual results as closely as possible, the design cannot be changed after packaging. Once electromagnetic interference problems occur, the design can only be modified and re-stripped, which will bring huge time and economic costs.

[0020] In view of this, this application is hereby filed. Summary of the invention

[0021] The technical problem to be solved by the present invention is that the prior art has poor shielding effect on electromagnetic interference between functional modules inside a chip, and is limited by chip size and chip layout design, which is not conducive to ensuring product consistency and subsequent debugging.

[0022] In order to solve the above technical problems, the present invention is implemented by the following technical solutions:

[0023] In the first aspect, a three-dimensional electromagnetic interference isolation structure is proposed, including: multiple grounding metal gaskets and multiple grounding holes; the grounding metal gaskets are arranged on the surface of the chip; the multiple grounding metal gaskets are arranged along the length direction of the gap between adjacent functional modules; one grounding metal gasket corresponds to two grounding holes; one end of the grounding hole is connected to the grounding metal gasket, and the other end of the grounding hole is connected to the grounding layer of the chip; a bonding wire is connected between each two adjacent grounding metal gaskets.

[0024] Furthermore, a plurality of bonding wires with different heights are connected across every two adjacent grounding metal pads.

[0025] Furthermore, the bonding wire is a gold wire, an aluminum wire or a copper wire.

[0026] In the second aspect, a method for preparing a three-dimensional electromagnetic interference isolation structure is proposed, comprising the following steps: on the surface of the chip, a plurality of grounding metal gaskets are arranged along the length direction of the gap between adjacent functional modules; two grounding holes are arranged on the chip near each of the grounding metal gaskets, one end of the grounding hole is connected to the grounding metal gasket, and the other end of the grounding hole is connected to the grounding layer of the chip; and a bonding wire is bridged between each two adjacent grounding metal gaskets.

[0027] Furthermore, the method for preparing the three-dimensional electromagnetic interference isolation structure also includes the following steps: connecting a plurality of bonding wires of different heights across between every two adjacent grounding metal pads.

[0028] Furthermore, the bonding wire is a gold wire, an aluminum wire or a copper wire.

[0029] In a third aspect, a chip with internal electromagnetic interference self-isolation function is proposed, including a three-dimensional electromagnetic interference isolation structure described in the first aspect; the three-dimensional electromagnetic interference isolation structure is located in the gap between adjacent functional modules, and the three-dimensional electromagnetic interference isolation structure is arranged along the length direction of the gap.

[0030] Compared with the prior art, the present invention has the following advantages and beneficial effects: by using the metal bonding wires in chip assembly and use, in conjunction with the grounding metal gaskets on the chip surface, through the connection of the bonding wires and multiple metal gaskets, a metal barrier is formed in the three-dimensional space between different functional modules of the chip in the form of jumpers, so as to achieve the purpose of shielding electromagnetic interference, and reduce the electromagnetic interference between two adjacent functional modules that need to be isolated inside the chip. In addition, since the structure is located between different functional modules of the chip and the structure is fixed, it is compatible with various packaging designs, ensuring the consistency of the product, and without changing the chip layout design, it is also convenient for later debugging, thereby reducing the risk of chip redesign due to electromagnetic interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 A top view of the structure of a chip with two metal microstrip lines provided in Embodiment 1 of the present invention;

[0033] Figure 2A three-dimensional diagram of a chip packaging structure having two metal microstrip lines provided in Embodiment 1 of the present invention;

[0034] Figure 3 A curve diagram showing a change in a first electromagnetic coupling result formed by electromagnetic interference generated by a first signal port on a third signal port in a chip having only two metal microstrip lines provided in Embodiment 1 of the present invention;

[0035] Figure 4 A curve diagram showing a change in a third electromagnetic coupling result formed by electromagnetic interference generated by a first signal port on a fourth signal port in a chip having only two metal microstrip lines provided in Embodiment 1 of the present invention;

[0036] Figure 5 A schematic diagram of a three-dimensional electromagnetic interference isolation structure with one bonding wire provided in Example 1 of the present invention;

[0037] Figure 6 A diagram showing the relationship between a first electromagnetic coupling result change curve and a second electromagnetic coupling result change curve provided in Example 1 of the present invention;

[0038] Figure 7 A diagram showing a relationship between a third electromagnetic coupling result change curve and a fourth electromagnetic coupling result change curve provided in Example 1 of the present invention;

[0039] Figure 8 A schematic diagram of a three-dimensional electromagnetic interference isolation structure with two bonding wires provided in Embodiment 2 of the present invention;

[0040] Fig. 9 A diagram showing the relationship between the second electromagnetic coupling result change curve and the fifth electromagnetic coupling result change curve provided in Example 2 of the present invention;

[0041] Fig.10 This is a relationship diagram between the fourth electromagnetic coupling result change curve and the sixth electromagnetic coupling result change curve provided in Example 2 of the present invention.

[0042] Marks and corresponding parts names in the attached drawings:

[0043] 1-ground metal pad, 2-ground hole, 3-bonding wire, 4-first metal microstrip line, 5-second metal microstrip line, 6-first electromagnetic coupling result change curve, 7-second electromagnetic coupling result change curve, 8-third electromagnetic coupling result change curve, 9-fourth electromagnetic coupling result change curve, 10-fifth electromagnetic coupling result change curve, 11-sixth electromagnetic coupling result change curve, 14-chip substrate, 15-packaging layer, 41-first signal port, 42-second signal port, 51-third signal port, 52-fourth signal port. DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.

[0045] In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present invention. However, it is apparent to one of ordinary skill in the art that these specific details are not necessarily employed to practice the present invention. In other embodiments, in order to avoid obscuring the present invention, well-known structures, circuits, materials, or methods are not specifically described.

[0046] Throughout the specification, references to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "one embodiment," "an embodiment," "an example," or "an example" appearing in various places throughout the specification do not necessarily all refer to the same embodiment or example. In addition, particular features, structures, or characteristics may be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. In addition, it will be appreciated by those of ordinary skill in the art that the figures provided herein are for illustrative purposes and that the figures are not necessarily drawn to scale. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0047] In the description of the present invention, the directions or positional relationships indicated by terms such as “front”, “rear”, “left”, “right”, “up”, “down”, “vertical”, “horizontal”, “high”, “low”, “inside” and “outside” are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limiting the scope of protection of the present invention.

[0048] Embodiment 1: Figure 1The chip shown has two independent functional modules, namely, a first metal microstrip line 4 and a second metal microstrip line 5, and the first metal microstrip line 4 and the second metal microstrip line 5 are parallel to each other. The first metal microstrip line 4 and the second metal microstrip line 5 can transmit signals simultaneously. Among them, one end of the first metal microstrip line 4 is connected to the first signal port 41 inside the chip, and the other end of the first metal microstrip line 4 is connected to the second signal port 42 inside the chip, and the signal can be fed in and the signal size can be detected through the first signal port 41 and the second signal port 42; one end of the second metal microstrip line 5 is connected to the third signal port 51 inside the chip, and the other end of the second metal microstrip line 5 is connected to the fourth signal port 52 inside the chip, and the signal can be fed in and the signal size can be detected through the third signal port 51 and the fourth signal port 52.

[0049] Figure 2 In the embodiment, the encapsulation layer 15 is inverted on the chip substrate 14, and the opening edge of the encapsulation layer 15 is closely attached to the surface of the chip substrate 14. The chip is located below the encapsulation layer 15, and the medium above the chip can be air or plastic. When the first metal microstrip line 4 and the second metal microstrip line 5 transmit signals at the same time, due to the spatial coupling and dielectric coupling of electromagnetic waves between the chip substrate 14 and the medium, the signal transmitted on the first metal microstrip line 4 and the signal transmitted on the second metal microstrip line 5 generate electromagnetic interference with each other, and the magnitude of the magnetic interference can be calculated through electromagnetic simulation.

[0050] When the first signal port 41, the second signal port 42, the third signal port 51, and the fourth signal port 52 are connected to a 50ohm load and a 0dBm RF signal with a frequency ranging from 0hZ to 50GhZ is fed into the first signal port 41, the signal size of the RF signal coupled at the third signal port 51 and the fourth signal port 52 is calculated through electromagnetic simulation. This signal size can reflect the size of the electromagnetic interference between the first metal microstrip line 4 and the second metal microstrip line 5. Figure 3 shows a first electromagnetic coupling result variation curve 6, Figure 4 The third electromagnetic coupling result change curve 8 is shown. The first electromagnetic coupling result change curve 6 is a curve showing the magnitude change of the electromagnetic interference generated by the first signal port 41 to the third signal port 51 in a chip having only two metal microstrip lines; the third electromagnetic coupling result change curve 8 is a curve showing the magnitude change of the electromagnetic interference generated by the first signal port 41 to the fourth signal port 52 in a chip having only two metal microstrip lines. Figure 3 and Figure 4 It can be seen from the simulation results that within the frequency band from 0hZ to 50GhZ, as the frequency increases, the size of the interference signal generated by the RF signal fed from the first signal port 41 on the third signal port 51 and the fourth signal port 52 increases.

[0051] A three-dimensional electromagnetic interference isolation structure proposed in this embodiment is as follows Figure 5 As shown, it is composed of 12 grounding holes 2, 6 grounding metal pads 1 and 5 bonding wires 3. In this embodiment, the number of grounding holes 2, the number of grounding metal pads 1 and the number of bonding wires 3 are only one case. In other following embodiments, the number of grounding holes 2, the number of grounding metal pads 1 and the number of bonding wires 3 need to be determined according to the structure of each functional module inside the chip. Among them, the grounding metal pad 1 is used as a connection point for the bonding wire 3 and is arranged on the surface of the chip. The 6 grounding metal pads 1 are arranged along the length direction of the gap between adjacent functional modules (the 6 grounding metal pads 1 in this embodiment are arranged at intervals along the length direction of the gap between the first metal microstrip line 4 and the second metal microstrip line 5). Figure 5 In the embodiment, one grounding metal pad 1 corresponds to two grounding holes 2. One end of the grounding hole 2 is connected to the grounding layer on the back of the chip in the form of a via to achieve the purpose of grounding; the other end of the grounding hole 2 is connected to the grounding metal pad 1 (in this embodiment, the other ends of the two grounding holes 2 are respectively connected to the two wings of the grounding metal pad 1). Figure 5 , a bonding wire 3 is connected between every two adjacent grounding metal pads 1. The bonding wire 3 used in this embodiment is a gold wire. In some other implementations, the bonding wire 3 may also be an aluminum wire or a copper wire.

[0052] The 12 grounding holes 2, the 6 grounding metal pads 1 and the 5 bonding wires 3 together form a well-grounded three-dimensional metal barrier, which can play an electromagnetic shielding role between the first metal microstrip line 4 and the second metal microstrip line 5 to reduce electromagnetic interference.

[0053] It should be noted that: first, the grounding hole 2 and the grounding metal pad 1 can be set in advance in the chip design layout; second, the height and shape of the bonding wire 3 can be flexibly set according to the structure of each functional module in the chip.

[0054] Figure 6 The relationship between the first electromagnetic coupling result change curve 6 and the second electromagnetic coupling result change curve 7 is shown. The first electromagnetic coupling result change curve 6 is a change curve of the coupling size of the first signal port 41 to the third signal port 51 in a chip without a three-dimensional electromagnetic interference isolation structure; the second electromagnetic coupling result change curve 7 is a change curve of the coupling size of the first signal port 41 to the third signal port 51 in a chip with a three-dimensional electromagnetic interference isolation structure. Figure 7The relationship between the third electromagnetic coupling result change curve 8 and the fourth electromagnetic coupling result change curve 9 is shown. The third electromagnetic coupling result change curve 8 is a change curve of the coupling size of the first signal port 41 to the fourth signal port 52 in a chip without a three-dimensional electromagnetic interference isolation structure; the fourth electromagnetic coupling result change curve 9 is a change curve of the coupling size of the first signal port 41 to the fourth signal port 52 in a chip with a three-dimensional electromagnetic interference isolation structure. Figure 6 and Figure 7 It can be seen that the three-dimensional electromagnetic interference structure proposed in this embodiment has an obvious isolation and weakening effect on the electromagnetic coupling between the first metal microstrip line 4 and the second metal microstrip line 5 in the chip in the full frequency band (0hZ~50GhZ). Figure 3 and Figure 4 In comparison, the maximum optimized coupling isolation can reach 7dB.

[0055] Embodiment 2: Based on the three-dimensional electromagnetic interference isolation structure proposed in Embodiment 1, this embodiment proposes another improved structure, such as Figure 8 As shown. Compared with Example 1, the only difference is that in the improved three-dimensional electromagnetic interference isolation structure, two bonding wires 3 of different heights are connected between each two adjacent grounding metal gaskets 1, and together with 12 grounding holes 2 and 6 grounding metal gaskets 1, a three-dimensional electromagnetic barrier is formed. The two bonding wires 3 of different heights can form a denser metal barrier to better isolate electromagnetic interference. Furthermore, more bonding wires 3 of different heights can be connected between each two adjacent grounding metal gaskets 1, so as to achieve a better isolation effect.

[0056] Fig. 9 The relationship between the second electromagnetic coupling result change curve 7 and the fifth electromagnetic coupling result change curve 10 is shown. The second electromagnetic coupling result change curve 7 is a change curve of the coupling size of the first signal port 41 to the third signal port 51 in a chip including a three-dimensional electromagnetic interference isolation structure (having one bonding wire 3); the fifth electromagnetic coupling result change curve 10 is a change curve of the coupling size of the first signal port 41 to the third signal port 51 in a chip including a three-dimensional electromagnetic interference isolation structure (having two bonding wires 3). Fig.10 The relationship between the fourth electromagnetic coupling result change curve 9 and the sixth electromagnetic coupling result change curve 11 is shown. The fourth electromagnetic coupling result change curve 9 is a curve showing the change in coupling size of the first signal port 41 to the fourth signal port 52 in a chip containing a three-dimensional electromagnetic interference isolation structure (having one bonding wire 3); the sixth electromagnetic coupling result change curve 11 is a curve showing the change in coupling size of the first signal port 41 to the fourth signal port 52 in a chip containing a three-dimensional electromagnetic interference isolation structure (having two bonding wires 3). Fig. 9 and Fig.10 It can be seen that compared with the three-dimensional electromagnetic interference structure with only one bonding wire 3 proposed in Example 1, the three-dimensional electromagnetic interference structure with two bonding wires 3 proposed in this embodiment can reduce the electromagnetic coupling between the first metal microstrip line 4 and the second metal microstrip line 5 in the chip by about 5dB in the full frequency band (0hZ~50GhZ).

[0057] Embodiment 3: This embodiment proposes a method for preparing a three-dimensional electromagnetic interference isolation structure as shown in Embodiment 1, comprising the following steps:

[0058] Step 1: On the surface of the chip, a plurality of grounding metal pads are arranged along the length direction of the gaps between adjacent functional modules.

[0059] Step 2: two grounding holes are arranged on the chip near each of the grounding metal pads, one end of the grounding hole is connected to the grounding metal pad, and the other end of the grounding hole is connected to the grounding layer of the chip.

[0060] Step 3: Connect a bonding wire between every two adjacent ground metal pads.

[0061] In order to improve the isolation, in step 3, multiple bonding wires of different heights can be connected between each two adjacent grounding metal pads. Similarly, the bonding wires selected in this embodiment are gold wires. In some other implementations, the bonding wires can also be selected from aluminum wires or copper wires.

[0062] Embodiment 4: This embodiment provides a chip with internal electromagnetic interference self-isolation function. The chip has a three-dimensional electromagnetic interference isolation structure as provided in Embodiment 1 or Embodiment 2. The three-dimensional electromagnetic interference isolation structure is located at the gap between adjacent functional modules and is arranged along the length direction of the gap.

[0063] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A three-dimensional electromagnetic interference isolation structure, characterized in that: include: A plurality of grounding metal pads (1) and a plurality of grounding holes (2); the grounding metal pads (1) are arranged on the surface of the chip; A plurality of the grounding metal pads (1) are arranged along the length direction of the gap between adjacent functional modules; one of the grounding metal pads (1) corresponds to two of the grounding holes (2); one end of the grounding hole (2) is connected to the grounding metal pad (1), and the other end of the grounding hole (2) is connected to the grounding layer of the chip; and a bonding wire (3) is bridged between each two adjacent grounding metal pads (1).

2. A three-dimensional electromagnetic interference isolation structure according to claim 1, characterized in that: A plurality of bonding wires (3) of different heights are bridged between each two adjacent grounding metal pads (1).

3. A three-dimensional electromagnetic interference isolation structure according to claim 1 or 2, characterized in that: The bonding wire (3) is a gold wire, an aluminum wire or a copper wire.

4. A method for preparing a three-dimensional electromagnetic interference isolation structure, characterized in that: The following steps are involved: On the surface of the chip, a plurality of grounding metal pads are arranged along the length direction of the gaps between adjacent functional modules; Two grounding holes are provided on the chip near each of the grounding metal pads, one end of the grounding hole is connected to the grounding metal pad, and the other end of the grounding hole is connected to the grounding layer of the chip; A bonding wire is connected across every two adjacent grounding metal pads.

5. The method for preparing a three-dimensional electromagnetic interference isolation structure according to claim 4, characterized in that: The following steps are also included: A plurality of bonding wires with different heights are connected across each two adjacent grounding metal pads.

6. A method for preparing a three-dimensional electromagnetic interference isolation structure according to claim 4 or 5, characterized in that: The bonding wire is a gold wire, an aluminum wire or a copper wire.

7. A chip with internal electromagnetic interference self-isolation function, characterized in that: It comprises a three-dimensional electromagnetic interference isolation structure as described in any one of claims 1 to 3; the three-dimensional electromagnetic interference isolation structure is located in the gap between adjacent functional modules, and the three-dimensional electromagnetic interference isolation structure is arranged along the length direction of the gap.

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