Inter-chip data transmission method and device for data packet splicing, and storage medium

Abstract

The invention discloses a data packet spliced inter-chip data transmission method and device and a storage medium, and the method comprises the steps: analyzing to-be-transmitted network data, obtaining to-be-transmitted data packets, and mapping the to-be-transmitted data packets to a plurality of data flow queues; constructing an initial DMA chip to carry out packet splicing processing on the to-be-transmitted data packets in the data flow queue to obtain a chained DMA chip; if the cache length of the chained DMA chip exceeds a preset cache length or the current packet splicing time exceeds a preset waiting time, transmitting the chained DMA chip to a next chip; and if the chained DMA chip is transmitted to an exit chip, obtaining all the data packets to be transmitted from the chained DMA chip and sending the data packets. According to the method, the multiple data packets are combined into one chained DMA chip for transmission through packet splicing processing, the overall transmission efficiency can be improved, and efficient transmission of a large amount of data among chips is ensured by dynamically adjusting the size and the transmission strategy of the chained DMA chip.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and more specifically, to a data packet splicing inter-chip data transmission method, device and storage medium. Background Art

[0002] Network communication equipment is deployed on a public network and processes the received data according to specific protocol requirements before forwarding it. In order to meet the needs of reducing development cycles, improving processing performance, controlling hardware costs, and ensuring isolation security, a multi-chip coordinated hardware architecture is usually adopted, involving general-purpose processors, network-specific processors, programmable logic devices and other hardware chips. DMA technology is often used between chips to move data between chips.

[0003] In the DMA technology, during the transmission process, the CPU first configures the DMA controller and sets the transmission parameters, such as the source address, the destination address, and the number of bytes to be transferred. When the source chip is ready for data, it sends a request to the DMA controller. After obtaining the bus control right, the DMA controller starts to control the data bus, the address bus, and the control bus to transfer data. After the transmission is completed, the DMA controller releases the bus control right and may generate an interrupt signal to notify the CPU. This technology reduces the burden on the CPU and improves the efficiency of data transmission and the performance of the entire system.

[0004] However, the current data transmission based on Ethernet technology mostly involves shorter data packets such as handshakes, ACKs, and heartbeats. Limited by the fixed preparation cycle and release cycle of DMA, for communication scenarios with more short data packets, a large amount of processing time is spent on controlling the transmission and reception rather than the data movement itself, which reduces the overall data processing capabilities of network communication equipment and leads to problems such as low actual network communication rate and large latency. Summary of the invention

[0005] In response to at least one defect or improvement need in the prior art, the present invention provides a chip-to-chip data transmission method, device and storage medium for data packet splicing, which are used to solve the problem that the prior art is limited by the fixed preparation cycle and release cycle of DMA. When faced with a large number of short data packet communication scenarios, a large amount of processing time is spent on controlling the sending and receiving of data rather than the data movement itself, which reduces the overall data processing capability of the network communication equipment and leads to the problems of low actual network communication rate and large latency.

[0006] To achieve the above object, according to a first aspect of the present invention, a method for inter-chip data transmission with data packet splicing is provided, the method comprising:

[0007] Parsing the network data to be transmitted to obtain the data packets to be transmitted, and mapping the data packets to be transmitted to several data flow queues;

[0008] Construct an initial DMA slice to assemble the data packets to be transmitted in the data stream queue to obtain a chain DMA slice;

[0009] If the buffer length of the chained DMA chip exceeds the preset buffer length or the current packet assembly time exceeds the preset waiting time, the chained DMA chip is transferred to the next chip;

[0010] If the chain DMA chip transmits to the egress chip, all data packets to be transmitted are obtained from the chain DMA chip and the packet sending process is performed.

[0011] In a possible implementation, parsing the network data to be transmitted to obtain the data packets to be transmitted, and mapping the data packets to be transmitted to a plurality of data flow queues further includes:

[0012] Analyze and process the network data to be transmitted to obtain data packet parameters;

[0013] Calculate the data packet hash value according to the data packet parameters, and save the data packet hash value to the data packet to be transmitted;

[0014] Based on the hash value of the data packet, the data packets to be transmitted are mapped to several data flow queues, and datagrams with the same hash value are queued in order.

[0015] In a possible implementation, constructing an initial DMA slice to assemble the data packets to be transmitted in the data stream queue to obtain a chain DMA slice also includes:

[0016] Construct a corresponding initial DMA slice for each data packet to be transmitted;

[0017] Assign the address information of the data packet to be transmitted to the corresponding initial DMA slice;

[0018] The assigned initial DMA slices are linked in sequence according to the assignment order to obtain chained DMA slices.

[0019] In a possible implementation, if the buffer length of the chained DMA slice exceeds the preset buffer length or the current packet assembly time exceeds the preset waiting time, the chained DMA slice is transferred to the next chip, further comprising:

[0020] If the sum of the total length of the chained DMA slices, the preset DMA slice header length, and the length of the current data packet to be transmitted exceeds the preset buffer length, the packet assembly process is stopped and the chained DMA slice is transferred to the next chip;

[0021] The current packetization time is calculated according to the total length of the chained DMA chips, the preset data forwarding rate, the timestamp of the first packetization and the current packetization timestamp. If the current packetization time exceeds the preset waiting time, the chained DMA chips are transferred to the next chip.

[0022] In a possible implementation, parsing the network data to be transmitted to obtain the data packets to be transmitted, and mapping the data packets to be transmitted to a plurality of data flow queues further includes:

[0023] If the longest depth or average depth of the data flow queue exceeds the preset flow queue depth, the total number of data flow queues is expanded;

[0024] Extract hash values ​​of all data packets and remap the data packets to be transmitted to the expanded data flow queue.

[0025] In a possible implementation, parsing the network data to be transmitted to obtain the data packets to be transmitted, and mapping the data packets to be transmitted to a plurality of data flow queues further includes:

[0026] Set the priority weight for the data stream queue according to the data packet hash value;

[0027] The number of data packets to be transmitted mapped to the data flow queue is determined based on the priority weight.

[0028] In a possible implementation, the data packet to be transmitted includes a control field identifier; if the chained DMA chip transmits to the egress chip, all the data packets to be transmitted are obtained from the chained DMA chip and are processed for packet transmission, further comprising:

[0029] According to the control field identifier, the chained DMA slice is unpacked to obtain the data packet to be transmitted;

[0030] According to the priority weight, a corresponding number of data packets to be transmitted are obtained for packet sending processing.

[0031] In a possible implementation, the network data to be transmitted is parsed to obtain data packets to be transmitted, and the data packets to be transmitted are mapped to a plurality of data flow queues, and then the following is further included:

[0032] Establish a hash value cache library based on the data packet hash value;

[0033] The data packets to be transmitted in the data stream queue are processed based on the preset policy rules, and the processing results are stored in the hash value cache.

[0034] According to a second aspect of the present invention, there is also provided a chip data transmission device for data packet splicing, which comprises at least one processing unit and at least one storage unit, wherein the storage unit stores a computer program, and when the computer program is executed by the processing unit, the processing unit executes any step of the above-mentioned chip data transmission method for data packet splicing.

[0035] According to the third aspect of the present invention, there is also provided a storage medium storing a computer program executable by an access authentication device, wherein when the computer program runs on the access authentication device, the access authentication device executes any of the steps of the inter-chip data transmission method for data packet splicing described above.

[0036] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0037] The present invention provides a data packet splicing chip data transmission method, which supports mapping data packets to multiple data stream queues. By mapping the data packets to be transmitted to multiple data stream queues, the method can process data in parallel, reduce waiting time, thereby improving the throughput of data transmission, and at the same time, the data stream queue based on the hash value ensures orderly transmission. When facing a communication scenario with a large number of short data packets, through packet splicing processing, multiple data packets are merged into a chain DMA slice for transmission, which can significantly reduce the number of transmissions and transmission overhead, thereby improving the overall transmission efficiency. At the exit chip, all data packets to be transmitted can be extracted from the chain DMA slice at one time and processed for packet sending, further reducing processing time and delay. By transmitting the data packet in the form of a chain DMA slice, the number of transmissions and waiting time of the data packet between chips are reduced, the risk of loss and damage of the data packet during transmission is reduced, and the integrity and accuracy of data transmission are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 A schematic flow chart of an embodiment of a method for inter-chip data transmission by data packet splicing provided by the present invention;

[0040] Figure 2 A schematic diagram of a flow chart of an embodiment of step S101 in 1 provided by the present invention;

[0041] Figure 3 A schematic diagram of a flow chart of an embodiment of step S102 in 1 provided by the present invention;

[0042] Figure 4 A schematic diagram of the structure of an inter-chip data transmission device for data packet splicing provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0044] The terms "first", "second", "third", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0045] The present invention provides a data packet splicing inter-chip data transmission method, device and storage medium, which are described below respectively.

[0046] See also Figure 1 , Figure 1 A flowchart of an embodiment of a method for inter-chip data transmission by combining data packets provided by the present invention is provided. In a specific embodiment of the present invention, a method for inter-chip data transmission by combining data packets is disclosed. The method comprises:

[0047] S101, parsing the network data to be transmitted to obtain data packets to be transmitted, and mapping the data packets to be transmitted to a plurality of data flow queues;

[0048] S102, constructing an initial DMA slice to assemble the data packets to be transmitted in the data stream queue to obtain a chain DMA slice;

[0049] S103, if the buffer length of the chained DMA slice exceeds the preset buffer length or the current packet assembly time exceeds the preset waiting time, the chained DMA slice is transferred to the next chip;

[0050] S104: If the chained DMA chip transmits to the egress chip, all data packets to be transmitted are obtained from the chained DMA chip and processed for packet transmission.

[0051] In the above embodiment, it is necessary to parse the data to be transmitted received from the network. The data may come from various data sources, such as network requests, file transfers, etc. The parsed data is organized into data packets to be transmitted. In order to effectively manage these data packets, they are mapped to several data flow queues, which can be classified according to the priority, source or other attributes of the data for subsequent processing. Through classification and queue management, data packets can be scheduled and processed more effectively, reducing delays and conflicts in data processing.

[0052] DMA is a technology that allows hardware devices to directly access main memory (without CPU intervention). Here, DMA slices are used as the basic unit of data transmission. The data packets to be transmitted are taken from the data stream queue and assembled into one or more chained DMA slices. Chained DMA slices refer to multiple DMA slices linked together in some way (such as a linked list structure) to form a larger data transmission unit. Packet assembly can reduce the number of data transmissions and improve transmission efficiency. At the same time, the structure of chained DMA slices makes data transmission more flexible and efficient.

[0053] It is necessary to monitor the cache length and current packet assembly time of the chained DMA chip in real time. If the cache length of the chained DMA chip exceeds the preset cache length threshold, or the current packet assembly time exceeds the preset waiting time threshold, the transfer operation will be triggered. After the transfer conditions are met, the chained DMA chip is transferred to the next chip. Through conditional judgment, the timeliness and effectiveness of data transmission can be ensured, and data can be prevented from being accumulated in the cache for too long or being transmitted too frequently.

[0054] At the end of the data transmission path, one or more egress chips are responsible for splitting the received chained DMA slices into the original data packets to be transmitted and performing packet processing. Packet processing can include operations such as packet verification, reorganization, encryption / decryption, etc. to ensure the integrity and security of the data. Finally, the data packet is sent to the target address or network. Packet processing at the egress chip can ensure the integrity and security of the data during transmission while meeting the target's reception requirements.

[0055] Compared with the prior art, the present embodiment provides a data packet splicing inter-chip data transmission method, which supports mapping data packets to multiple data stream queues. By mapping the data packets to be transmitted to multiple data stream queues, the method can process data in parallel, reduce waiting time, and thus improve the throughput of data transmission. When facing a communication scenario with a large number of short data packets, through packet splicing processing, multiple data packets are merged into a chain DMA slice for transmission, which can significantly reduce the number of transmissions and transmission overhead, thereby improving the overall transmission efficiency. At the egress chip, all data packets to be transmitted can be extracted from the chain DMA slice at one time and processed for packet sending, further reducing processing time and delay. By transmitting data packets in the form of chain DMA slices, the number of transmissions and waiting time of data packets between chips are reduced.

[0056] See also Figure 2 , Figure 2 The present invention provides a flowchart of an embodiment of step S101 in step 1. In some embodiments of the present invention, parsing the network data to be transmitted to obtain the data packets to be transmitted, mapping the data packets to be transmitted to a plurality of data flow queues, and further comprising:

[0057] S201, parsing the network data to be transmitted to obtain data packet parameters;

[0058] S202, calculating a data packet hash value according to data packet parameters, and saving the data packet hash value to the data packet to be transmitted;

[0059] S203, mapping the data packets to be transmitted to a plurality of data flow queues based on the hash values ​​of the data packets, and the datagrams with the same hash value are queued in order.

[0060] In the above embodiment, the original data streams from the network are first received. These data streams may contain various types of data packets, such as TCP / IP data packets, UDP data packets, etc. These original data streams need to be parsed to extract the key parameters of each data packet. These key parameters may include the source address, destination address, port number, protocol type, data length, checksum, etc. of the data packet, which are crucial for the subsequent data packet processing.

[0061] After obtaining the data packet parameters, hash calculation is performed on these parameters using a hash algorithm (such as MD5, SHA-1, SHA-256, etc.) to generate a unique hash value. The generated hash value is attached to the data packet as an attribute of the data packet. After obtaining the hash value of the data packet, the data packet is mapped to different data flow queues according to the hash value. The mapping strategy can be designed according to actual needs, such as range mapping based on hash values, modular operation mapping based on hash values, etc. The data flow queue is a data structure set up to manage data packets. It can be classified according to the priority, type or other attributes of the data packet. By mapping the data packets to different data flow queues, the data packets with the same parameters must enter the same queue in order, ensuring the order of the data based on the flow, and more efficient parallel data processing. Through the mapping strategy based on the hash value, the uniform distribution of data packets in the data flow queue can be ensured, avoiding overload or idleness of a queue, thereby improving the efficiency and fairness of data transmission.

[0062] See also Figure 3 , Figure 3 The present invention provides a flowchart of an embodiment of step S102 in step 1. In some embodiments of the present invention, constructing an initial DMA slice to assemble the data packets to be transmitted in the data stream queue to obtain a chain DMA slice also includes:

[0063] S301, constructing a corresponding initial DMA slice for each data packet to be transmitted;

[0064] S302, assigning the address information of the data packet to be transmitted to the corresponding initial DMA slice;

[0065] S303 , linking the assigned initial DMA slices in sequence according to the assignment order to obtain chained DMA slices.

[0066] In the above embodiment, for each data packet to be transmitted in the data stream queue, a corresponding initial DMA slice is created. The DMA slice is the basic unit of data transmission, which contains the necessary information of the data packet, such as data length, data address, etc. Each initial DMA slice usually includes a header area and a data area. The header area is used to store the control information of the DMA slice, such as the starting address, data length, transmission direction, etc. of the data packet; the data area is used to store the actual data packet content. By constructing a corresponding initial DMA slice for each data packet, it can be ensured that each data packet has an independent transmission unit, which is convenient for subsequent data transmission and processing.

[0067] The address information here refers to the physical address or virtual address of the data packet to be transmitted in the memory. This address is necessary to access and transmit the data packet. After the initial DMA slice is constructed, the address information of each data packet needs to be assigned to the header area of ​​the corresponding DMA slice. In this way, when the DMA controller accesses the DMA slice, it can find and transmit the data packet according to the address information in the header area. By assigning address information to the DMA slice, it can ensure that the DMA controller can accurately access and transmit the data packet, avoiding data loss or erroneous transmission.

[0068] Each assigned initial DMA slice is linked in the order of assignment to form a chained DMA slice. The linking operation usually involves adding a pointer or link field at the head or tail of the DMA slice to point to the next DMA slice. A chained DMA slice is a data structure composed of multiple initial DMA slices connected in series through the link field. It allows multiple data packets to be transferred in a continuous manner without interrupt processing after each transfer. By building a chained DMA slice, multiple data packets can be transferred at one time, reducing the number of interrupts and CPU intervention, thereby improving the efficiency and throughput of data transmission.

[0069] In some embodiments of the present invention, if the buffer length of the chained DMA slice exceeds the preset buffer length or the current packet assembly time exceeds the preset waiting time, the chained DMA slice is transferred to the next chip, further comprising:

[0070] If the sum of the total length of the chained DMA slices, the preset DMA slice header length, and the length of the current data packet to be transmitted exceeds the preset buffer length, the packet assembly process is stopped and the chained DMA slice is transferred to the next chip;

[0071] The current packetization time is calculated according to the total length of the chained DMA chips, the preset data forwarding rate, the timestamp of the first packetization and the current packetization timestamp. If the current packetization time exceeds the preset waiting time, the chained DMA chips are transferred to the next chip.

[0072] In the above embodiment, in the process of constructing the chained DMA slices, the total length of the chained DMA slices is continuously monitored, and this total length is the sum of the data lengths of all DMA slices in the chain, plus the preset DMA slice header length (used to store control information and metadata). If the total length of the chained DMA slices (including the sum of the preset DMA slice header length and the length of the current data packet to be transmitted) exceeds the preset buffer length threshold, this indicates that the current buffer space may not be sufficient to accommodate more data packets, or in order to avoid buffer overflow and data loss, the packet assembly process needs to be stopped. In this case, further packet assembly process is stopped, and the constructed chained DMA slice is transferred to the next chip for subsequent processing or transmission.

[0073] The current packetization time is calculated based on the total length of the chained DMA slice, the preset data forwarding rate, and the timestamp information, which includes the timestamp of the first packetization (i.e., the time point when the packetization starts) and the timestamp of the current packetization (i.e., the current time point). The data transmission rate is the ability to transmit data, usually expressed in bits (bps) or bytes (Bps) transmitted per second. By calculating the difference between the current timestamp and the timestamp of the first packetization, the time spent on the packetization process can be obtained. If the calculated current packetization time exceeds the preset waiting time threshold, this indicates that the packetization process has taken too long, possibly because the data packet is large or the load is high. In order to avoid further delays and possible performance degradation, the chained DMA slice needs to be transferred to the next chip as soon as possible. The chained DMA slice is immediately transferred to the next chip to continue processing or sending data packets.

[0074] In some embodiments of the present invention, parsing the network data to be transmitted to obtain the data packets to be transmitted, and mapping the data packets to be transmitted to a plurality of data flow queues further includes:

[0075] If the longest depth or average depth of the data flow queue exceeds the preset flow queue depth, the total number of data flow queues is expanded;

[0076] Extract hash values ​​of all data packets and remap the data packets to be transmitted to the expanded data flow queue.

[0077] In the above embodiment, the maximum depth and average depth of each data flow queue are continuously monitored. The maximum depth indicates the maximum number of data packets in the queue, while the average depth indicates the average number of data packets in the queue. The depth information reflects the load of the queue and its processing capacity. If the maximum depth or average depth of a data flow queue exceeds the preset flow queue depth threshold, this indicates that the queue may be overloaded or about to be overloaded. In order to avoid data loss or transmission delay, the total number of data flow queues will be dynamically expanded as needed, which can be achieved by adding new queues or splitting existing queues. After expanding the data flow queue, it is necessary to extract the hash value of all data packets to be transmitted. The hash value is a unique identifier based on the content of the data packet, which is used to ensure the correctness and integrity of the data packet. According to these hash values, and possible other factors (such as the priority of the data packet, the target address, etc.), the data packets to be transmitted are remapped to the expanded data flow queue. The remapping process ensures that the data packets can be evenly distributed to each queue, thereby improving the overall throughput and transmission efficiency.

[0078] In some embodiments of the present invention, parsing the network data to be transmitted to obtain the data packets to be transmitted, and mapping the data packets to be transmitted to a plurality of data flow queues further includes:

[0079] Set the priority weight for the data stream queue according to the data packet hash value;

[0080] The number of data packets to be transmitted mapped to the data flow queue is determined based on the priority weight.

[0081] In the above embodiment, a priority weight is assigned to each data flow queue according to the hash value of the data packet. The weight can be obtained by some mapping or conversion based on the hash value. For example, a preset priority table is indexed by the hash value to obtain the corresponding priority weight. The priority weight can be a numerical value, indicating the relative priority of the data flow queue when processing or transmitting the data packet. The larger the numerical value, the higher the priority.

[0082] When mapping the data packets to be transmitted to the data flow queues, the number of data packets mapped to each queue is determined according to the priority weight of each data flow queue, which can be achieved through a dynamic allocation mechanism, which dynamically adjusts the number of data packets mapped to each queue according to factors such as the current load, the priority weight of the data flow queue, and the size of the data packet. For example, if a data flow queue has a higher priority weight and a lower current load, more data packets can be mapped to the queue to prioritize processing or transmission of these data packets.

[0083] By allocating the number of packets to be transmitted based on priority weights, load balancing and resource optimization can be better achieved. High-priority data flow queues can get more processing or transmission resources, thereby ensuring timely transmission and processing of critical data; while low-priority data flow queues can be processed when resources are sufficient to avoid resource waste.

[0084] In some embodiments of the present invention, the data packet to be transmitted includes a control field identifier; if the chained DMA chip is transmitted to the egress chip, all the data packets to be transmitted are obtained from the chained DMA chip and the packet sending process is performed, further comprising:

[0085] According to the control field identifier, the chained DMA slice is unpacked to obtain the data packet to be transmitted;

[0086] According to the priority weight, a corresponding number of data packets to be transmitted are obtained for packet sending processing.

[0087] In the above embodiment, when the chained DMA slices arrive at the egress chip, each DMA slice in the chained DMA slices is first checked and the control field identifier is read. The control field identifier contains important information about the data packet, such as the start and end positions of the data packet, the type of the data packet (such as TCP, UDP, etc.), the priority value, etc. Based on this information, the chained DMA slices are unpacked, that is, the chained DMA slices are decomposed into individual data packets to be transmitted, ensuring that each data packet can be correctly identified and extracted.

[0088] After the unpacking process is completed, the priority weight of each data packet is used to determine which data packets should be processed first. The priority weight is dynamically assigned based on the content, source, destination or other relevant factors of the data packet, and is used to indicate the relative importance of the data packet during processing or transmission. According to the current resource status, network congestion and the priority weight of the data packet, a certain number of data packets to be transmitted are dynamically selected for packet processing, ensuring that high-priority data packets can be processed first, thereby improving the efficiency and reliability of data transmission.

[0089] Once the data packets to be transmitted are determined, they will be sent to the next node or target device in the network. The packet processing may include steps such as data packet encapsulation, encryption, and verification to ensure the integrity and security of the data packets during transmission. At the same time, the sending status of each data packet will be recorded for retransmission or error handling when necessary.

[0090] In some embodiments of the present invention, the network data to be transmitted is parsed to obtain data packets to be transmitted, and the data packets to be transmitted are mapped to a plurality of data flow queues, and then the following steps are further included:

[0091] Establish a hash value cache library based on the data packet hash value;

[0092] The data packets to be transmitted in the data stream queue are processed based on the preset policy rules, and the processing results are stored in the hash value cache.

[0093] In the above embodiment, the hash value is stored in a dedicated hash value cache library, which may be an in-memory data structure, such as a hash table or a dictionary, for quickly storing and retrieving the hash value and its corresponding data packet information.

[0094] The data packets to be transmitted in the data stream queue are processed according to preset policy rules, which may include packet filtering, priority sorting, data compression, encryption, etc. The processing process may involve modifying the content of the data packet, adding additional metadata or tags, etc. After the processing is completed, the processing results (such as modified data packets, additional metadata, etc.) are associated with the hash value of the original data packet, and the hash value cache is updated. In this way, when a specific data packet needs to be retrieved or processed, the corresponding processing result can be quickly found through its hash value without reprocessing the entire data packet.

[0095] The hash value cache library allows you to quickly retrieve and identify packets without traversing the entire data stream queue. The cache library can cache the processing results of repeated or frequently accessed packets, thereby reducing the overhead of repeated processing and data transmission. Packets can be processed according to complex policy rules and the processing results can be stored in the cache library so that these policies can be quickly applied later.

[0096] See also Figure 4 , Figure 4 A schematic diagram of the structure of an inter-chip data transmission device for data packet splicing provided by an embodiment of the present invention. Based on the above-mentioned inter-chip data transmission method for data packet splicing, the present invention also provides an inter-chip data transmission device for data packet splicing, which can be a computing device such as a mobile terminal, a desktop computer, a notebook, a PDA, and a server. The inter-chip data transmission device 400 for data packet splicing includes a processor 410, a memory 420, and a display 430. Figure 4 Only some components of the chip-to-chip data transmission device for data packet splicing are shown, but it should be understood that it is not required to implement all the components shown, and more or fewer components may be implemented instead.

[0097] In some embodiments, the memory 420 may be an internal storage unit of the data packet splicing inter-chip data transmission device 400, such as a hard disk or memory of the data packet splicing inter-chip data transmission device 400. In other embodiments, the memory 420 may also be an external storage device of the data packet splicing inter-chip data transmission device 400, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the data packet splicing inter-chip data transmission device 400. Further, the memory 420 may also include both the internal storage unit of the data packet splicing inter-chip data transmission device 400 and an external storage device. The memory 420 is used to store application software and various types of data installed in the data packet splicing inter-chip data transmission device 400, such as the program code of the data packet splicing inter-chip data transmission device 400. The memory 420 may also be used to temporarily store data that has been output or is to be output. In one embodiment, the memory 420 stores a data packet splicing inter-chip data transmission program 440, which can be executed by the processor 410, thereby implementing the data packet splicing inter-chip data transmission method of each embodiment of the present application.

[0098] In some embodiments, the processor 410 may be a central processing unit (CPU), a microprocessor or other data processing chip, used to run program codes stored in the memory 420 or process data, such as executing an inter-chip data transmission method for data packet splicing.

[0099] In some embodiments, the display 430 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch device, etc. The display 430 is used to display information of the inter-chip data transmission device 400 for data packet splicing and to display a visual user interface. The components 410-430 of the inter-chip data transmission device 400 for data packet splicing communicate with each other through a system bus.

[0100] In one embodiment, when the processor 410 executes the inter-chip data transmission program 440 of data packet splicing in the memory 420 , the steps in the above inter-chip data transmission method of data packet splicing are implemented.

[0101] This embodiment further provides a computer-readable storage medium on which a data packet-joined inter-chip data transmission program is stored. When the data packet-joined inter-chip data transmission program is executed by a processor, the following steps are implemented:

[0102] Parsing the network data to be transmitted to obtain the data packets to be transmitted, and mapping the data packets to be transmitted to several data flow queues;

[0103] Construct an initial DMA slice to assemble the data packets to be transmitted in the data stream queue to obtain a chain DMA slice;

[0104] If the buffer length of the chained DMA chip exceeds the preset buffer length or the current packet assembly time exceeds the preset waiting time, the chained DMA chip is transferred to the next chip;

[0105] If the chain DMA chip transmits to the egress chip, all data packets to be transmitted are obtained from the chain DMA chip and the packet sending process is performed.

[0106] In summary, the present invention provides a data packet splicing chip-to-chip data transmission method, which supports mapping data packets to multiple data stream queues. By mapping the data packets to be transmitted to multiple data stream queues, the method can process data in parallel, reduce waiting time, and thus improve the throughput of data transmission. When facing a communication scenario with a large number of short data packets, through packet splicing processing, multiple data packets are merged into a chain DMA slice for transmission, which can significantly reduce the number of transmissions and transmission overhead, thereby improving the overall transmission efficiency. At the exit chip, all data packets to be transmitted can be extracted from the chain DMA slice at one time and processed for packet sending, further reducing processing time and delay. By transmitting data packets in the form of chain DMA slices, the number of transmissions and waiting time of data packets between chips are reduced, the risk of loss and damage of data packets during transmission is reduced, and the integrity and accuracy of data transmission are improved.

[0107] The present application also provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, the steps of the above method are implemented. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a micro drive, and a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), or any type of medium or device suitable for storing instructions and / or data.

[0108] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0109] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0110] In the several embodiments provided in the present application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0111] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0112] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0113] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: U disk, read-only memory (ROM), random access memory (RAM), mobile hard disk, disk or optical disk and other media that can store program code.

[0114] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable memory, which can include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0115] The above is only an exemplary embodiment of the present disclosure, and the scope of the present disclosure cannot be limited thereto. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the specification and practicing the disclosure here, those skilled in the art will easily think of the implementation scheme of the present disclosure. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not recorded in the present disclosure. The description and examples are regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.

[0116] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A data packet splicing inter-chip data transmission method, characterized in that: The method includes: Parsing the network data to be transmitted to obtain data packets to be transmitted, and mapping the data packets to be transmitted to a plurality of data flow queues; Constructing an initial DMA slice to process the data packets to be transmitted in the data stream queue to obtain a chain DMA slice; If the buffer length of the chained DMA slice exceeds the preset buffer length or the current packet assembly time exceeds the preset waiting time, the chained DMA slice is transferred to the next chip; If the chained DMA chip is transmitted to the egress chip, all data packets to be transmitted are obtained from the chained DMA chip and packet processing is performed.

2. The chip-to-chip data transmission method of data packet splicing according to claim 1, characterized in that: The step of parsing the network data to be transmitted to obtain data packets to be transmitted, and mapping the data packets to be transmitted to a plurality of data flow queues, further includes: Parsing the network data to be transmitted to obtain data packet parameters; Calculating a data packet hash value according to the data packet parameters, and saving the data packet hash value to the data packet to be transmitted; The data packets to be transmitted are mapped to a plurality of data flow queues based on the hash values ​​of the data packets, and datagrams with the same hash values ​​are queued in order.

3. The chip-to-chip data transmission method of data packet splicing according to claim 1, characterized in that: The constructing of the initial DMA slice performs packet processing on the data packets to be transmitted in the data stream queue to obtain a chain DMA slice, and further includes: Constructing a corresponding initial DMA slice for each of the data packets to be transmitted; Assigning the address information of the data packet to be transmitted to the corresponding initial DMA slice; The assigned initial DMA slices are linked in sequence according to the assignment order to obtain chained DMA slices.

4. The chip-to-chip data transmission method of data packet splicing according to claim 1, characterized in that: If the buffer length of the chained DMA slice exceeds the preset buffer length or the current packet assembly time exceeds the preset waiting time, the chained DMA slice is transferred to the next chip, and further includes: If the sum of the total length of the chained DMA slices, the preset DMA slice header length, and the length of the current data packet to be transmitted exceeds the preset buffer length, the packet assembly process is stopped and the chained DMA slices are transmitted to the next chip; The current packetization time is calculated according to the total length of the chained DMA slice, the preset data forwarding rate, the timestamp of the first packetization and the current packetization timestamp. If the current packetization time exceeds the preset waiting time, the chained DMA slice is transferred to the next chip.

5. The chip-to-chip data transmission method of data packet splicing according to claim 2, characterized in that: The step of parsing the network data to be transmitted to obtain data packets to be transmitted, and mapping the data packets to be transmitted to a plurality of data flow queues, further includes: If the longest depth or average depth of the data flow queue exceeds the preset flow queue depth, the total number of data flow queues is expanded; All the data packets hash values ​​are extracted to remap the data packets to be transmitted to the expanded data flow queue.

6. The chip-to-chip data transmission method of data packet splicing as claimed in claim 2, characterized in that: The step of parsing the network data to be transmitted to obtain data packets to be transmitted, and mapping the data packets to be transmitted to a plurality of data flow queues, further includes: Setting a priority weight for the data stream queue according to the hash value of the data packet; The number of data packets to be transmitted mapped to the data flow queue is determined based on the priority weight.

7. The chip-to-chip data transmission method of data packet splicing according to claim 6, characterized in that: The data packet to be transmitted includes a control field identifier; if the chained DMA chip is transmitted to the egress chip, all data packets to be transmitted are obtained from the chained DMA chip and packet processing is performed, and further comprising: Unpacking the chained DMA slice according to the control field identifier to obtain the data packet to be transmitted; A corresponding number of the data packets to be transmitted are obtained according to the priority weights for packet sending processing.

8. The chip-to-chip data transmission method of data packet splicing according to claim 1, characterized in that: The method further includes: parsing the network data to be transmitted to obtain data packets to be transmitted, and mapping the data packets to be transmitted to a plurality of data flow queues; and then: Establish a hash value cache library based on the data packet hash value; The data packets to be transmitted in the data stream queue are processed based on preset policy rules, and the processing results are stored in the hash value cache.

9. An inter-chip data transmission device for data packet splicing, characterized in that: The invention comprises at least one processing unit and at least one storage unit, wherein the storage unit stores a computer program, and when the computer program is executed by the processing unit, the processing unit executes the steps of the chip-to-chip data transmission method for data packet splicing according to any one of claims 1 to 8.

10. A storage medium, characterized in that: It stores a computer program executable by an access authentication device. When the computer program runs on the access authentication device, the access authentication device executes the steps of the chip-to-chip data transmission method for data packet splicing according to any one of claims 1 to 8.

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