Host level error detection and fault correction

Abstract

A processing system [100] includes a processing device [230] coupled to a memory [106] configured to verify and correct faults in requested data. In response to correcting the failure of the requested data, the memory sends corrected data and unused check bits as a plurality of fetch returns to the processing device. The memory also sends a parity fetch to the processing device based on the correction data and one or more operations. Upon receiving the plurality of fetch returns and the unused check bits, the processing device verifies each fetch return for a fault based on the unused check bits. In response to determining that the fetch return includes a fault, the processing device erases the fetch return and reconstructs the fetch return based on one or more other received fetch returns and the parity fetch.

Description

Background Art

[0001] In a memory structure, data stored in a memory bank of a storage layer may include uncorrected errors due to corruption of the stored data. In order to detect and correct these errors, some memory structures implement on-chip error correction codes that generate check bits for the stored data. When the data is read out from the memory bank, these memory structures detect and correct errors in the data by using the generated check bits. However, even with such on-chip error correction, when the data is read out to the processing system, failures that are not limited to a fixed number of bits in the data may still occur. Such unrestricted failures may reduce the reliability of the processing system because the unrestricted failures may cause the processing system to fail, resulting in field replacement unit events. These field replacement unit events require the replacement of one or more components of the processing system, thereby increasing the cost of maintaining the processing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.The use of the same reference numbers in different drawings indicates similar or identical items.

[0003] Figure 1 is a block diagram of a processing system for host-level error detection and correction, according to some embodiments.

[0004] Figure 2 is a block diagram of a processing system for host-level error detection and correction using stacked memory, according to some embodiments.

[0005] Figure 3 is a block diagram of a processing system for host-level error correction and detection on one or more memory pseudo channels, according to some embodiments.

[0006] Figure 4 is a flow chart of an exemplary process for performing host-level error correction during a read operation, according to some embodiments.

[0007] Figure 5 is a flow chart of an exemplary process for correcting one or more failures in a fetch return, according to some embodiments.

[0008] Figure 6 is a flow chart of an exemplary method for host-level error correction during a read operation, according to some embodiments.

[0009] Figure 7 is a flow chart of an exemplary process for performing host-level error correction during write operations, according to some embodiments. DETAILED DESCRIPTION

[0010] The techniques and systems described herein solve the problem of providing host-level error detection and correction in a processing system. Using the techniques disclosed herein, a processor performs error detection for each fetch return in a group of fetch returns from a memory based on one or more check bits provided from the memory. For example, the group of fetch returns collectively corresponds to a cache line read from the memory. In response to detecting an error in one of the fetch returns (e.g., referred to as a fail return), the processor reconstructs data for the fail return from other fetch returns in the group and additional parity fetches provided by the memory. Therefore, the processor improves error correction of the fetch data, and thus improves the overall reliability of the processing system.

[0011] To illustrate the technology and system, a processing system includes one or more processing devices (e.g., CPU, GPU) communicatively coupled to a memory, the memory being configured to implement one or more error correction codes (ECC) such that one or more portions of data stored in the memory (e.g., cache lines of storage) are associated with one or more check bits. A processing device of the processing system generates a set of extraction portions identifying data to be read out of the memory, and provides the set of extraction portions to the memory. In response to receiving the set of extraction portions, the memory is configured to read out the data identified in the extraction portion, check the read data for one or more faults (e.g., drive fault, storage body fault), and correct one or more detected faults. The memory uses one or more check bits associated with the read data to check and correct faults in the read data. Then, the memory sends the corrected data and one or more unused check bits associated with the read data (e.g., check bits not used to detect or correct faults) to the processing device as a set of extraction returns. In addition, the memory sends an additional parity extraction, which includes data obtained by performing one or more operations on the extraction return (e.g., on the data contained in the extraction return). In response to receiving an extraction return, the processing device is configured to use unused parity bits to detect a fault in the received extraction return. After detecting the fault in the received extraction return, the processing device erases the extraction return and reconstructs the extraction return using data and parity extractions in one or more other received extraction returns. In this manner, any detected faults limited to a single extraction return are corrected, thereby improving the reliability of the processing system by improving the detection and correction of such faults. Therefore, the chance of the system experiencing a field replacement unit event, termination of an application using the memory, a system reboot, or any combination thereof is reduced, thereby helping to reduce the cost of maintaining the system.

[0012] In addition, the processing device is configured to generate a set of write portions for identifying data to be written to the memory. For example, the set of write portions corresponds to a cache line to be written to the memory. Based on the set of write portions, the processing device is also configured to generate a write parity check, which includes data obtained by performing one or more operations on the data identified in the write portion. Then, the processing device generates a corresponding check value for each write portion and the write parity check based on the ECC implemented by the processing device. After the check value is generated, the write portion, the check value and the write parity check are sent and stored in the memory. In this way, the reliability of the data written to the memory is improved. For example, in response to detecting one or more errors in the data written to the memory, the data is reconstructed using other data stored in the memory and the data of the write parity check. Therefore, as the reliability of the data is improved, the possibility of a field replacement unit event, the termination of an application using the memory, a system restart or any combination thereof is reduced.

[0013] Figure 1 1 is a block diagram of a processing system 100 for high memory bandwidth host error correction according to some embodiments. The processing system 100 includes or has access to a memory 106 or other storage components implemented using non-transitory computer-readable media, such as dynamic random access memory (DRAM), static random access memory, non-volatile RAM, or any combination thereof, to name a few. In an embodiment, the memory 106 includes a three-dimensional (3D) stacked synchronous dynamic random access memory (SDRAM) having one or more storage layers, each storage layer having one or more storage banks, storage sub-banks, or both. The memory 106 includes an interface including hardware and software configured to communicatively couple the memory 106 to one or more portions of the processing system 100, such as a high bandwidth memory (HBM) interface, a second generation high bandwidth memory (HBM2) interface, a third generation high bandwidth memory (HBM3) interface, etc. According to an embodiment, the memory 106 is located external to the processing unit implemented in the processing system 100, while in other embodiments, the memory 106 is located internal to the processing unit implemented in the processing system 100. The processing system 100 also includes a bus 112 to support communications between entities implemented in the processing system 100, such as a central processing unit (CPU) 102 and a graphics processing unit (GPU) 114. Some embodiments of the processing system 100 include other buses, bridges, switches, routers, etc., which are not described in detail for clarity. Figure 1 Shown in.

[0014] In various embodiments, the techniques described herein are used with any of a variety of parallel processors (e.g., vector processors, CPUs, GPUs, general-purpose GPUs (GPGPUs), non-scalar processors, highly parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, other multi-threaded processing units, etc.), scalar processors, serial processors, or any combination thereof. Figure 1 An example of a parallel processor, and in particular a GPU 114, is shown according to some embodiments. The GPU 114 renders an image for presentation on a display 120. For example, the GPU 114 renders an object to generate pixel values ​​that are provided to the display 120, which uses the pixel values ​​to display an image representing the rendered object. The GPU 114 implements multiple processor cores 116-1 through 116-N that execute instructions concurrently or in parallel. According to various embodiments, one or more of the processor cores 116 operate as single instruction multiple data (SIMD) units that perform the same operation on different sets of data. Although in Figure 1 In the exemplary embodiment shown, three cores (116-1, 116-2, 116-N) are presented to represent N cores, but the number of processor cores 116 implemented in GPU 114 is a matter of design choice. Therefore, in other embodiments, GPU 114 may include any number of cores 116. Some embodiments of GPU 114 are used for general-purpose computing. GPU 114 executes instructions (such as program code 108 stored in memory 106), and GPU 114 stores information (such as the results of the executed instructions) in memory 106.

[0015] Processing system 100 also includes CPU 102, which is connected to bus 112 and thus communicates with GPU 114 and memory 106 via bus 112. CPU 102 implements multiple processor cores 104-1 to 104-N that execute instructions concurrently or in parallel. In various embodiments, one or more processor cores 104 operate as SIMD units that perform the same operation on different data sets. Although in Figure 1In the exemplary embodiment shown, three cores (104-1, 104-2, 104-M) are presented, representing M cores, but the number of processor cores 104 implemented in CPU 102 is a matter of design choice. Therefore, in other embodiments, CPU 102 may include any number of cores 104. In some embodiments, CPU 102 and GPU 114 have equal numbers of cores 104, 116, while in other embodiments, CPU 102 and GPU 114 have different numbers of cores 104, 116. Processor cores 104 execute instructions (such as program code 110 stored in memory 106), and CPU 102 stores information (such as the results of the executed instructions) in memory 106. CPU 102 is also capable of initiating graphics processing by issuing draw calls to GPU 114. In various embodiments, CPU 102 implements multiple processor cores that execute instructions concurrently or in parallel (for clarity) Figure 1 not shown).

[0016] In an embodiment, CPU 102, GPU 114 or both are configured to generate an extraction request and send the extraction request (e.g., cache line extraction) to memory 106. For example, CPU 102, GPU 114 or both are configured to generate a load or read operation requesting data (e.g., cache line) from memory 106. The extraction request identifies and requests data, for example, data necessary for one or more instructions executed on CPU 102, GPU 114 or both, which is auxiliary or helpful to the one or more instructions. That is, the extraction request is identified and requests data for a read or load operation. In response to receiving the extraction request, memory 106 is configured to read out the data identified in the extraction request and provide it to CPU 102, GPU 114 or both. According to an embodiment, CPU 102, GPU 114 or both are configured to divide the extraction request into two or more extraction parts, each extraction part including data representing at least a portion of the extraction request. For example, CPU 102, GPU 114 or both are configured to divide the extraction request into two or more extraction parts, each extraction part represents a different part of the request data identified in the extraction request. In an embodiment, the size of each obtained extraction part is equal. For example, CPU 102, GPU 114 or both are configured to divide a 128-bit extraction request (i.e., an extraction request identifying 128 bits of request data) into four extraction parts, each extraction part representing a different 32-bit part of the extraction request. In response to receiving the extraction part, memory 106 is configured to read the corresponding extraction return, and provide the corresponding extraction return to CPU 102, GPU 114 or both, and the extraction return includes the data identified in the extraction part.

[0017] In an embodiment, the CPU 102, the GPU 114, or both are configured to generate a write request (e.g., a cache line write request) and send the write request to the memory 106. The write request identifies data to be written to a portion or portions of the memory 106 from one or more caches included in or otherwise communicatively coupled to the CPU 102, the GPU 114, or both. In response to receiving the write request, the memory 106 is configured to write the data identified in the write request to one or more portions of the memory 106. In an embodiment, the CPU 102, the GPU 114, or both are configured to divide the write request into four write portions, each of which represents a different portion of the data identified in the write request. In response to receiving the write portion, the memory 106 is configured to write the data identified in the write portion to one or more portions of the memory 106.

[0018] According to an embodiment, the CPU 102, the GPU 114, or both are configured to generate a parity request in response to generating one or more extraction parts from an extraction request. That is, when the extraction request is divided into one or more extraction parts, the CPU 102, the GPU 114, or both generate a parity request. The parity request identifies each extraction part and one or more operations to be performed. For example, the parity request identifies one or more operations to be performed on the data identified in each extraction part. In response to receiving the parity request, the memory 106 is configured to generate a parity extraction and return it to the CPU 102, the GPU 114, or both. The parity extraction includes data obtained by performing the operation identified in the parity request on the data identified in the one or more extraction requests. For example, in response to receiving a parity request identifying an XOR operation and four extraction parts (where each extraction part indicates a portion of the data (e.g., D0, D1, D2, D3)), the memory 106 is configured to generate a parity extraction, which includes data obtained by performing an XOR operation on the data returned from each extraction (e.g., ). Similarly, in an embodiment, CPU 102, GPU 114, or both are configured to generate write parity in response to generating one or more write portions from a write request. That is, when a write request is divided into one or more write portions, CPU 102, GPU 114, or both generate write parity. Write parity includes data resulting from performing one or more operations on the write portions. That is, data resulting from performing one or more operations on data identified in the write portions divided from the write request. For example, in response to dividing a write request into four write portions, each of which identifies a portion of data (e.g., W0, W1, W2, W3), CPU 102, GPU 114, or both are configured to generate write parity that includes data from each write portion (e.g., ) is performed on the data obtained by performing an XOR operation on the write parity. In response to receiving the write parity, the memory 106 is configured to store the data of the write parity in one or more portions of the memory 106.

[0019] According to an embodiment, the memory 106 is configured to implement one or more error correction codes (ECCs) for data stored in the memory 106. For example, in response to receiving a request to store data (e.g., a write request) in the memory 106, the memory 106 is configured to implement one or more ECCs so that one or more check bits are generated for the data to be stored. In response to generating the check bits, the memory 106 stores the memory and the check bits in at least a portion of the memory 106. Such ECCs include, for example, on-chip ECC, single error correction (SEC) codes, symbol-based codes (e.g., Reed-Solomon codes), cyclic redundancy check (CRC) codes, longitudinal redundancy check (LRC) codes, checksum codes, parity check codes, Hamming codes, binary convolutional codes, or any combination thereof, to name a few. For example, for every 128 bits stored in the memory 106 (e.g., a cache line), the memory 106 is configured to generate 32 check bits and store the check bits in at least a portion of the memory 106. In response to receiving one or more extraction parts, the memory 106 is configured to read the data identified in the received extraction part, and implement ECC so as to detect and correct one or more faults in the read data. According to some embodiments, the memory 106 is configured to detect and correct faults limited to a predetermined number of bits in the read data. That is, the fault is limited to the corresponding part of the read data, and each part includes a predetermined number of bits. For example, the memory 106 is configured to detect and correct faults limited to the 16-bit part of the read data. The memory 106 is configured to detect and correct faults by, for example, comparing the check bits associated with the read data with one or more values ​​(e.g., thresholds, values, strings), performing one or more operations on the check bits associated with the data, or both. In response to detecting, correcting, or simultaneously detecting and correcting one or more faults, the memory 106 is configured to generate an extraction return using the correction data, and the extraction return is sent to the CPU 102, the GPU 114, or both. In the embodiment, in response to the memory 106 detecting and correcting the fault limited to a predetermined number of bits in the read data, one or more check bits associated with the read data are not used. That is, in response to the memory 106 detecting and correcting a fault limited to a predetermined number of bits, not every check bit associated with the read data is used to detect and correct errors in the read data, thereby leaving one or more unused check bits. For example, in response to the memory 106 detecting and correcting a fault in the read data limited to a 16-bit portion of the read data, only 16 of the 32 check bits associated with the read data are needed to detect and correct the fault in the 16-bit portion. Therefore, only 16 check bits are used, thereby leaving 16 unused check bits.

[0020] According to the embodiment, the memory 106 is configured to send one or more unused check bits and one or more extraction returns to the CPU 102, the GPU 114, or both. For example, in response to receiving a set of extraction parts (e.g., cache lines) identifying the request data, the memory 106 is configured to send a set of extraction returns to the CPU 102, the GPU 114, or both, which includes the read request data and one or more unused check bits. In some embodiments, the memory 106 is configured to add one or more unused check bits associated with the data in the extraction return to each extraction return, while in other embodiments, the memory 106 sends the unused check bits separately from the extraction return. For example, the memory 106 is configured to add the unused check bits associated with the read data in the extraction return to the extraction return, so that the extraction return includes the read data identified in the corresponding extraction part and one or more unused check bits. The unused check bits include, for example, metadata related to the extraction return, which indicates, for example, the error state of the extraction part. For example, in response to receiving a set of 32-bit extract portions (i.e., extract portions identifying 32-bit request data) corresponding to an extract request (e.g., a requested cache cache line), the memory 106 is configured to provide a set of extract returns, each of which includes 32 bits of read data identified in the corresponding extract portion and 16 unused check bits (e.g., check bits that are not used to detect or correct errors in the data returned by the extract). In response to receiving the extract returns, the CPU 102, the GPU 114, or both are configured to implement one or more ECCs to detect one or more faults in the received extract returns. Such ECCs include, for example, CRC codes (e.g., CRC-9, CRC-12, CRC-16), symbol-based codes, LRC codes, checksum codes, parity check codes, Hamming codes, binary convolutional codes, or any combination thereof, to name a few. For example, the CPU 102, the GPU 114, or both are configured to implement a CRC-12 code for each extract return. In an embodiment, CPU 102, GPU 114, or both are configured to detect one or more failures in the fetch return using one or more unused check bits associated with the fetch return (e.g., included in the fetch return, returned with the fetch return, or both) in accordance with one or more ECCs implemented by CPU 102, GPU 114, or both. To this end, CPU 102, GPU 114, or both are configured to detect failures in the fetch return, for example, by comparing the one or more unused check bits associated with the fetch return to one or more values ​​(e.g., thresholds, values, strings), performing one or more operations on the one or more unused check bits associated with the fetch return in accordance with the implemented ECC, or both.For example, to detect one or more failures in a fetch return, CPU 102, GPU 114, or both are configured to perform one or more operations on one or more unused check bits associated with the fetch return according to a CRC-12 implemented by CPU 102, GPU 114, or both.

[0021] In response to detecting one or more faults in the extraction return, the CPU 102, the GPU 114, or both are configured to correct the detected faults. The CPU 102, the GPU 114, or both are configured to correct the detected faults by, for example, erasing the extraction return including one or more faults and reconstructing the erased extraction return. That is, in response to detecting one or more faults in the extraction return, the CPU 102, the GPU 114, or both are configured to erase the extraction return. After erasing the extraction return, the CPU 102, the GPU 114, or both are configured to reconstruct the erased extraction return from other received extraction returns and parity extraction. For example, the CPU 102, the GPU 114, or both are configured to reconstruct the erased extraction return by performing an XOR operation on the data in the other received extraction returns and the parity extraction. In this way, any faults (e.g., word line driver faults, storage body faults) that are limited to a single extraction return will be corrected. By correcting the faults in this way, the fault detection coverage and correction rate of the system are improved, thereby improving the reliability of the system. Thus, the chance of the system experiencing a field change unit event, termination of an application using the memory, a system reboot, or any combination thereof is reduced.

[0022] In an embodiment, CPU 102, GPU 114 or both are configured to implement one or more ECCs to generate one or more check values ​​for each write portion and write parity generated by CPU 102, GPU 114 or both. Such ECCs include, for example, CRC codes (e.g., CRC-9, CRC-12, CRC-16), symbol-based codes, LRC codes, checksum codes, parity codes, Hamming codes, binary convolutional codes, or any combination thereof, to name a few. For example, CPU 102, GPU 114 or both are configured to implement CRC-12 codes and write parity for each write portion, thereby generating a 12-bit check value for each write portion and the write parity associated with the write portion. According to an embodiment, when each write portion is sent to memory 106, the corresponding check value generated for each write portion is included in the write portion, and when each write parity is sent to memory 106, the corresponding check value for each write parity is included in the write parity. Thus, in response to receiving a write portion, the memory 106 is configured to store the data identified in the write portion or the write parity and check value in one or more portions of the memory 106. In this way, the reliability of the data written to the memory is improved. For example, in response to detecting one or more errors in the data written to the memory, the data is reconstructed using other data stored in the memory and the write parity, which improves the reliability of the system.

[0023] Reference now Figure 2 , presents a block diagram of a processing system 200 for host-level error detection and correction. The processing system 200 includes a processing device 230 similar or identical to the CPU 102, the GPU 114, or both, which is communicatively coupled to a cache 236 and a memory 206 similar or identical to the memory 106. The cache 236 includes, for example, one or more private caches, shared caches, or both, which are included in the processing device 230 or otherwise communicatively coupled to the processing device. According to an embodiment, the processing system 200 is disposed in a single package, wherein at least the memory 206 and the processing device 230 are disposed on the same substrate of the package (not shown for clarity). In an embodiment, the processing device 230 and the memory 206 are communicatively coupled via a silicon interposer disposed on the substrate.

[0024] The memory 206 includes one or more stacked memory layers 224, each of which includes one or more memory banks, memory subgroups, or both. For example, the memory 206 includes a 3D stacked SDRAM having one or more memory layers 224, each of which includes one or more memory banks. Figure 2The exemplary embodiment shown in 206 presents a memory 206 having eight storage layers (224-1, 224-2, 224-3, 224-4, 224-5, 224-6, 224-7) representing N storage layers, but in other embodiments, the memory 206 can have any number of storage layers 224. According to an embodiment, each storage layer 224 includes two channels, such as two 64-bit channels, which are configured to allow access, modification, and deletion of data stored in a storage bank, a storage sub-bank, or both of the storage layer 224. For example, each channel of the storage layer 224 is configured to allow access, modification, and deletion of data in different storage banks or storage sub-banks in the storage layer 224. In some embodiments, the memory 206 is configured to operate each channel as two or more pseudo-channels, so that each pseudo-channel of the channel allows access, modification, and deletion of data in different parts of the storage bank or storage sub-bank associated with the channel. For example, memory 206 is configured to operate a 64-bit channel as two 32-bit pseudo-channels that are each configured to allow access, modification, and deletion of data in a different portion of a memory bank or memory subbank associated with the 64-bit channel.

[0025] In the embodiment, the storage layer 224 includes one or more silicon memory chips stacked on each other. That is, each storage layer 224 includes a silicon memory chip, and the chip of each storage layer 224 is arranged to form a stack of memory chips. According to the embodiment, one or more through silicon vias (TSV) (not shown for clarity) pass through the stacked one or more storage layers 224 to communicatively couple one or more storage layers 224. In order to control the data stored in the storage layer 224 of the memory 206, the memory 206 includes a logic layer 226, which includes hardware and software configured to access, modify and delete the data in the storage body and storage sub-body of the storage layer 224. For example, the logic layer 226 includes one or more memory controllers, each of which is configured to access, modify and delete the data in the storage body and storage sub-body of one or more storage layers 224. In the embodiment, the logic layer 226 is communicatively coupled to each storage layer 224 by, for example, one or more TSVs.

[0026] According to the embodiment, the logic layer 226 is configured to store data in one or more storage bodies, storage sub-bodies, or two storage layers in one or more storage layers 224. For example, the logic layer 226 includes one or more memory controllers, each memory controller is associated with a storage body or a storage sub-body, and is configured to store data in its associated storage body or storage sub-body. In the embodiment, the logic layer 226 is configured to implement one or more ECCs (e.g., CRC codes (e.g., CRC-9, CRC-12, CRC-16), symbol-based codes, LRC codes, checksum codes, parity check codes, Hamming codes, binary convolutional codes) for writing data to one or more data bodies or data sub-bodies of the memory 206. The logic layer 226 is configured to implement ECC, thereby generating one or more check bits for a predetermined amount of data written to one or more storage bodies or storage sub-bodies. For example, the logic layer 226 is configured to implement on-chip ECC so that 32 check bits are generated for each 256 bits of data stored. As another example, the logic layer 226 is configured to implement on-chip ECC such that one check bit is generated for each byte of data stored. In response to generating one or more check bits, the logic layer 226 is configured to store the check bits, for example, in the same memory bank or memory subbank that is allocated to store the data being written (i.e., the data used to generate the check bits).

[0027] In an embodiment, the processing device 230 is configured to generate one or more extraction requests (e.g., cache line requests) for requesting data stored in one or more storage layers 224 of the memory 206. For example, the processing device 230 generates an extraction request for requesting 128 bits of data from the memory 206. The processing device 230 is also configured to divide the extraction request into a group of extraction parts including one or more extraction parts, each of which identifies at least a portion of the data requested by the extraction request. For example, the processing device 230 is configured to divide the 128-bit extraction request (i.e., the extraction request identifying the 128-bit request data) into a group of four 32-bit extraction parts, each of which identifies a different 32-bit portion of the data requested in the 128-bit extraction request. According to an embodiment, the processing device 230 is configured to divide the extraction request into one or more extraction parts based on the channel of the memory 206. For example, in response to the memory 206 having two 64-bit channels per storage layer 224, the processing device 230 is configured to divide the 128-bit extraction request into two 64-bit extraction parts. As another example, in response to the memory 206 having two 64-bit channels operating in a pseudo-channel mode (e.g., each channel has two 32-bit pseudo-channels), the processing device 230 is configured to divide the 128-bit extraction request into four 32-bit extraction parts. After dividing the extraction request into one or more extraction parts, the processing device 230 is configured to send the extraction parts to the logic layer 226 of the memory 206. According to an embodiment, in response to dividing the extraction request into one or more extraction parts, the processing device 230 is configured to generate a parity request, which identifies each extraction part and one or more operations to be performed on the data identified in the extraction part. For example, the parity request identifies four extraction parts and the XOR operation to be performed on the data identified in each extraction part. After generating the parity request, the processing device 230 is configured to send the parity request together with the extraction part to the logic layer 226.

[0028] In response to receiving the extraction portion and the parity request, the logic layer 226 is configured to read the data identified in the extraction portion from one or more storage layers 224, and determine whether one or more faults exist in the read data. In order to determine whether one or more faults exist in the read data, the logic layer 226 checks the read data according to the ECC implemented by the logic layer 226. For example, the logic layer 226 checks the data read from the data sub-body of the storage layer 224 for faults according to the on-chip ECC implemented by the logic layer 226. In an embodiment, the logic layer 226 is configured to determine whether one or more faults exist in the read data by, for example, comparing one or more check bits associated with the read data with one or more values ​​(e.g., thresholds, values, strings), performing one or more operations on the check bits associated with the read data according to the implemented ECC, or both. For example, the logic layer 226 is configured to compare 16 check bits associated with the read data with one or more values ​​to determine the presence of one or more faults in the read data. According to an embodiment, the logic layer 226 is configured to detect and correct faults in the read data that are limited to a predetermined number of bits. That is, the fault is limited to the corresponding part of the read data, each part including a predetermined number of bits. For example, the logic layer 226 is configured to detect and correct the fault limited to the 16-bit part of the read data. In response to determining one or more faults in the read data, the logic layer 226 is configured to check one or more detected errors based on one or more check bits associated with the request data, the data stored in one or more storage layers 224 of the memory 206, one or more parity bits, or any combination thereof. According to the embodiment, the logic layer 226 is configured to detect and correct the fault associated with the predetermined number of bits in the read data, using only a part of the check bits associated with the read data, thereby retaining one or more unused check bits. For example, the logic layer 226 is configured to use 16 check bits in a total of 32 check bits to detect and correct the fault limited to 16 bits in the read data, thereby retaining 16 unused check bits.

[0029] After correcting the request data, the logic layer 226 is configured to generate a set of extract returns including one or more extract returns, each of which includes corrected read data associated with the corresponding received extract portion (e.g., corrected read data identified by the corresponding extract portion). For example, in response to receiving four 32-bit extract portions (i.e., the extract portions each include 32 bits identifying the request data), the logic layer 226 is configured to generate a set of four 32-bit extract returns, each of which includes the corrected data identified in the corresponding 32-bit extract portion. After generating the extract returns, the logic layer 226 is configured to generate parity extracts based on the received parity request. For example, the logic layer 226 is configured to perform one or more operations identified in the received parity request on the corrected data in each generated extract return. For example, in response to receiving a parity request identifying an XOR operation and generating four extract returns (the four extract returns each include a portion of the read data (e.g., D0, D1, D2, and D3)), the logic layer 226 is configured to perform one or more operations identified in the received parity request on the corrected data on the generated extract returns (e.g., D0, D1, D2, and D3). ) performs an XOR operation on the read data in to generate a parity extraction. In response to generating a parity extraction, the logic layer 226 is configured to send the generated extraction return and the parity extraction to the processing device 230. According to an embodiment, in response to generating a parity extraction, the logic layer 226 is also configured to send one or more unused check bits to the processing device 230. For example, the logic layer 226 is configured to include one or more unused check bits in one or more extraction returns, send one or more unused check bits separately from the extraction returns and the parity extraction, or a combination of the two. For example, in response to generating a parity extraction, the logic layer 226 is configured to send a set of extraction returns, parity extractions, and one or more unused check bits to the processing device 230.

[0030] The processing device 230 includes an error correction engine 234, which includes hardware and software configured to implement one or more ECCs (e.g., CRC codes (e.g., CRC-9, CRC-12, CRC-16), symbol-based codes, LRC codes, checksum codes, parity codes, Hamming codes, binary convolutional codes) for extraction returns received by the processing device 230 and write requests (e.g., write portions) generated by the processing device 230. In response to the processing device 230 receiving one or more extraction returns and one or more parity extractions, the error correction engine 234 is configured to check each extraction return for one or more faults based on the implemented ECC. For example, the error correction engine 234 is configured to check each extraction return for faults based on a CRC-12 code. In an embodiment, the error correction engine 234 is configured to use one or more unused check bits of the extraction return to determine whether the extraction return includes one or more faults (e.g., uncorrected errors). For example, the error correction engine 234 compares one or more unused check bits of the extraction return with one or more values ​​(e.g., thresholds, values, strings), performs one or more operations on the unused check bits of the extraction return, or both, to determine whether the extraction return contains one or more faults. In response to an extraction return with one or more errors (e.g., uncorrected errors), the error correction engine 234 is configured to erase and reconstruct the extraction return. The error correction engine 234 is configured to reconstruct the extraction return based on one or more other extraction returns, parity extractions, or both. For example, the error correction engine 234 is configured to reconstruct the extraction return based on the data in each other extraction return returned with the extraction return and the data in the parity extraction returned with the extraction return. By reconstructing the extraction return using the parity extraction, the detection coverage and fault correction rate of the system are improved, thereby improving the reliability of the system. Therefore, the chance of a field replacement unit event, the termination of an application using the memory, a system restart, or any combination thereof, is reduced. After reconstructing the data in the return extraction, the reconstructed return extraction and each other extraction return returned with the extraction return are stored in the cache 236. For example, the return fetch is provided to a data weave (not shown for clarity) that is communicatively coupled to the processing device 230 and the cache 236 .

[0031] According to an embodiment, the processing device 230 is configured to generate one or more write requests identifying data to be written in one or more portions of the memory 206. For example, the processing device 230 is configured to generate a write request that identifies data in the cache 236 to be written to one or more storage layers 224 of the memory 206. In an embodiment, the processing device 230 is configured to divide the write request into one or more write portions, each of which identifies a different portion of the data identified in the write request. For example, the processing device 230 is configured to divide the write request into one or more write portions based on the size of the channel of the memory 206. As an example, in response to each storage layer 224 having two 64-bit channels, the processing device 230 is configured to divide a 128-bit write request into two 64-bit write requests. As another example, in response to each storage layer 224 having two channels operating in a pseudo-channel mode (e.g., each channel has two pseudo-channels), the processing device 230 is configured to divide the 128-bit write request into four 32-bit write requests. In an embodiment, in response to generating one or more write portions, processing device 230 is configured to generate a write parity check that includes data resulting from performing one or more operations on data identified in the one or more write portions. For example, the write parity check includes data resulting from performing an XOR operation on data identified in four write portions divided from the write request.

[0032] According to the embodiment, the error correction engine 234 is configured to generate one or more check values ​​for the data identified in each write portion and each write parity based on the ECC implemented by the error correction engine 234. For example, the error correction engine 234 is configured to generate a 12-bit check value and a write parity for the data identified in each write portion based on the CRC-12 code implemented by the error correction engine 234. After the check value is generated, each check value is added to its corresponding write portion or write parity. That is, each write portion includes data identifying the data to be written to the memory 206, and a check value, and each write parity includes data obtained by performing one or more operations on the data to be written, and a check value. In response to the check value being added to the write portion and the write parity, the write portion and the write parity are sent to the logic layer 226 of the memory 206. In response to receiving one or more write portions and write parity, the logic layer 226 is configured to store the data identified in the write portion, the data of the write parity and the check value in one or more storage layers 224. For example, the logic layer 226 is configured to store the data identified in the written portion and the check value of the written portion to the storage sub-body of the storage layer 224. By storing the written portion with the check value and the write parity, the reliability of the data written to the memory is improved. For example, in response to detecting one or more errors in the data written to the memory, the data is reconstructed using other data stored in the memory and the write parity, which reduces the possibility of a field replacement unit event, termination of an application using the memory, a system restart, or any combination thereof.

[0033] Reference now Figure 3 , presents a block diagram of a processing system 300 for host-level error correction and detection on one or more memory pseudo-channels. The processing system 300 includes a processing device similar to or the same as the CPU 102, the GPU 114, or the processing device 230, which is communicatively coupled to a storage layer 324 of a memory similar to or the same as the memory 106, 206, which is similar to or the same as the storage layer 224. In an embodiment, the storage layer 324 is one of a plurality of layers in a 3D stacked SDRAM, and includes one or more memory banks, storage sub-banks, or both, each of which is each configured to store data. According to an embodiment, the storage layer 324 includes one or more channels 338, each of which is each configured to allow access to data in one or more memory banks, storage sub-banks, or both of the storage layer 324. In some embodiments, each channel 338 is configured to allow access to data in one or more different memory banks of the storage layer 324. For example, in Figure 3In the exemplary embodiment shown, the storage layer 324 includes a channel 0 338-1 configured to allow access to a first memory bank (not shown for clarity) and a channel 1 338-2 configured to allow access to a second memory bank (not shown for clarity). Each channel 338 has a width that represents the maximum amount of data that is allowed to be simultaneously read from or written to the memory bank associated with the channel 338. For example, each channel 338 has a width of 64 bits.

[0034] In an embodiment, storage layer 324 is configured to operate in pseudo-channel mode. When in pseudo-channel mode, each channel 338 of storage layer 324 operates as two or more different pseudo-channels 340. For example, in Figure 3 In the example embodiment shown, when in pseudo-channel mode, channel 0 338-1 operates as pseudo-channel 0 340-1 and pseudo-channel 1 340-2, and channel 1 338-2 operates as pseudo-channel 2 340-3 and pseudo-channel 3 340-4. Each pseudo-channel 340 is configured to allow access to data in at least a portion of a memory bank, a memory sub-bank, or both associated with its corresponding channel 338. For example, in Figure 3 In the exemplary embodiment shown, pseudo channel 0 340-1 is configured to allow access to a first storage sub-bank 342-1, which is a storage sub-bank of a storage bank associated with channel 0 338-1; pseudo channel 1 340-2 is configured to allow access to a second storage sub-bank 342-2, which is a second and different storage sub-bank of the storage bank associated with channel O 338-1. Each pseudo channel 340 has a width representing the maximum amount of data allowed to be read from or written to the storage bank, storage sub-bank, or both associated with the pseudo channel 340 at the same time. According to an embodiment, each pseudo channel has a width equal to half the width of its associated channel. For example, in Figure 3 In the example embodiment shown, channel 0 338-1 has a width of 64 bits, making pseudo channel 0 340-1 and pseudo channel 1 340-2 32 bits wide.

[0035] In an embodiment, the processing device 330 is communicatively coupled to the storage layer 324 via a channel 338. For example, the processing device 330 is coupled to the storage layer 324 via the channel 338 via a logic layer similar to or the same as the logic layer 226, which includes one or more storage controllers configured to control access, modification, and deletion of data stored in the storage layer 324. The processing device 330 is configured to generate one or more fetch requests (e.g., cache line fetches), each of which identifies data to be read from the storage layer 324, and transmit the fetch requests to the storage layer 324 via one or more channels 338 associated with the storage layer 324. According to an embodiment, the processing device 330 is configured to divide the fetch request into one or more fetch portions based on the width of the channel 338. For example, based on a 64-bit channel width, the processing device 330 is configured to divide a 128-bit fetch request into two 64-bit fetch portions. In an embodiment, when the storage layer 324 operates in pseudo-channel mode, the processing device 330 is configured to divide the extraction request into a group of one or more extraction parts based on the width of the pseudo-channel 340. For example, based on each pseudo-channel 340 having a width of 32 bits, the processing device 330 is configured to divide a 128-bit extraction request (i.e., an extraction request requesting 128 bits of data) into a group of four 32-bit extraction parts. After dividing the extraction request into two or more extraction parts, the processing device 330 is configured to provide the extraction parts to the logic layer that controls access to the storage layer 324 via one or more channels 338, pseudo-channels 340, or both. That is, the processing device 330 uses one or more channels 338, pseudo-channels 340, or both to provide the extraction parts to the logic layer. For example, in Figure 3 In the exemplary embodiment shown, the processing device 330 is configured to divide a 128-bit fetch request (i.e., a fetch request requesting 128 bits of data) into a set of four 32-bit fetch portions, and transmit two of the fetch portions to the logic layer using pseudo channel 0 340-1 and the other two of the fetch portions to the logic layer using pseudo channel 1 340-2.

[0036] In response to receiving one or more extraction portions on one or more channels 338, pseudo-channels 340, or both, storage layer 324 is configured to read the data identified in the extraction portions from one or more memory banks, memory sub-banks, or both associated with channels 338, pseudo-channels 340, or both. Figure 3In the exemplary embodiment shown, in response to receiving the extraction portion on pseudo channel 2 340-3, the storage layer 324 (e.g., via the logic layer) is configured to read the data identified in the extraction portion from the storage sub-body 342-3. According to the embodiment, the storage layer 324 is configured to check the data identified in one or more received extraction portions for faults and read from one or more storage bodies, storage sub-bodies, or both. That is, the storage layer 324 is configured to check the read data for one or more faults (e.g., uncorrected errors). For example, the storage layer 324 (e.g., by using the logic layer) is configured to check the read data based on one or more ECCs implemented by the storage layer 324. In the embodiment, the storage layer 324 is configured to check the read data by comparing the check bits associated with the read data with one or more values ​​(e.g., thresholds, values, strings) (e.g., using the logic layer), performing one or more operations on the read data, or both. According to the embodiment, the check bits associated with the read data are stored in the storage body or storage sub-body where the data is stored. In response to determining that one or more faults exist in the read data, the storage layer 324 (e.g., using the logic layer) is configured to correct the data to be read using, for example, other data stored in one or more storage bodies, data stored in a storage sub-body, one or more parity bits, or both. In an embodiment, the storage layer 324 is configured to transmit the read data as one or more extraction returns to the processing device 330 using one or more channels 338, pseudo channels 340, or both. According to an embodiment, the storage layer 324 is configured to transmit the extraction returns on the same channel and pseudo channel on which the extraction portion of the data included in the extraction return is received. For example, in Figure 3 In the exemplary embodiment shown, in response to receiving an extraction portion identifying data to be read out on pseudo channel 1 340-2, storage layer 324 is configured to read out the data identified in the extraction portion and transmit the data as an extraction return on pseudo channel 1 340-2. In an embodiment, storage layer 324 is configured to send one or more unused check bits (e.g., check bits that are not used to detect or correct faults in the read data) along with the extraction return to processing device 330 using one or more channels 338, pseudo channel 340, or both.

[0037] According to the embodiment, the processing device 330 is configured to generate one or more parity requests, each of which is associated with one or more extraction requests, extraction parts or both. For example, the processing device 330 is configured to generate a parity request associated with one or more extraction parts divided from the same extraction request. For example, each parity request identifies one or more extraction parts and one or more operations to be performed on the data identified in the extraction part. In the embodiment, the processing device 330 is configured to send the parity request to the storage layer 324 (for example, via the logical layer) using one or more channels 338, pseudo channels 340 or both. For example, the processing device 330 is configured to send the parity request using the pseudo channel 340 identical to the pseudo channel 340 on which the extraction part associated with the parity request is sent to the storage layer 324. In response to receiving the parity request, the storage layer 324 is configured to generate and return the parity extraction. In order to generate the parity extraction, the storage layer 324 is configured to (for example, using the logical layer) perform one or more operations of identification on the read data identified in the parity request. For example, the storage layer 324 is configured to perform an XOR operation on the read data identified in the four extraction parts identified by the parity request. In some embodiments, the storage layer 324 is configured to perform the operation identified in the parity request on the data identified in the parity request after using one or more ECC check data and correcting the fault. In this way, the storage layer 324 (e.g., using the logic layer) is configured to generate a parity extraction so that the parity extraction includes data obtained by performing one or more operations on the data identified in the parity request. For example, based on the parity request, the storage layer 324 is configured to generate a parity extraction, which includes data obtained by performing an XOR operation on the data identified in the four extraction parts associated with the parity extraction. In response to generating the parity extraction, the storage layer 324 (e.g., using the logic layer) is configured to send the parity extraction to the processing device 330 via one or more channels 338, pseudo channels 340, or both. For example, the storage tier 324 is configured to send a parity extraction to the processing device 330 using a pseudo channel 340 for sending an associated parity request (eg, a parity request for generating the parity extraction) from the processing device 330 to the storage tier 324 .

[0038] In response to receiving one or more extraction returns on one or more channels or pseudo-channels, the processing device 330 is configured to check the received extraction returns for one or more faults (e.g., uncorrected errors). In order to check the extraction returns for faults, the processing device 330 includes an error correction engine 334 similar to or identical to the error correction engine 234, which includes hardware and software configured to check the extraction returns for one or more faults based on one or more ECCs (e.g., CRC codes (e.g., CRC-9, CRC-12, CRC-16), symbol-based codes, LRC codes, checksum codes, parity check codes, Hamming codes, binary convolutional codes). According to an embodiment, the error correction engine 334 is configured to use unused check bits returned with the one or more extraction returns to check the faults of the one or more extraction returns. For example, in response to the processing device 330 receiving the extraction returns and one or more check bits, the error correction engine 334 is configured to check the data of the extraction returns for one or more faults based on the CRC code and the unused check bits. In an embodiment, the error correction engine 334 is configured to check the one or more faults returned by the extraction by comparing one or more unused check bits to one or more values ​​(e.g., thresholds, values, strings), performing one or more operations, or both. For example, the error correction engine 334 is configured to check the one or more faults returned by the extraction by performing one or more operations on the unused check bits according to the implemented ECC.

[0039] In response to determining one or more faults in the extraction return, the error correction engine 334 is configured to erase and reconstruct the extraction return. In an embodiment, the error correction engine 334 is configured to use one or more other extraction returns, one or more parity extractions, or data in both to reconstruct the extraction return. For example, the error correction engine 334 is configured to use one or more associated extraction returns (e.g., extraction returns based on the same extraction request, associated extraction parts, or both) and parity extractions associated with the extraction returns (e.g., parity extractions based on the same extraction request, associated extraction parts, or both) to reconstruct the extraction return. After reconstructing the extraction return, the reconstructed extraction return and any associated extraction returns (e.g., extraction returns based on the same extraction request, associated extraction parts, or both) are sent to a cache similar to or identical to the cache 236, which is included in the processing device 330 or otherwise communicatively coupled to the processing device. In an embodiment, the reconstructed extraction return and any associated extraction return are sent to a data weave communicatively coupled to the processing device 330 and the cache.

[0040] According to the embodiment, the processing device 330 is configured to generate one or more write requests, which identify the data to be stored in the storage layer 324 in one or more caches communicatively coupled to the processing device 330. In the embodiment, the processing device 330 is configured to divide the write request into one or more write parts based on the width of the channel 338. For example, based on the 64-bit channel width, the processing device 330 is configured to divide the 128-bit write request into two 64-bit write parts. When the storage layer 324 operates in the pseudo-channel mode, the processing device 330 is configured to divide the write request into one or more write parts based on the width of the pseudo-channel 340. For example, based on each pseudo-channel 340 with a 32-bit width, the processing device 330 is configured to divide the 128-bit write request into four 32-bit write parts. In the embodiment, the error correction engine 334 is configured to generate a check value for each write request according to one or more implemented ECCs. That is, the error correction engine 334 generates a check value for the data identified in the write part according to one or more ECCs. For example, the error correction engine 334 is configured to generate a check value using a CRC-9 code. In response to generating a check value for a write portion, the check value is added to the write portion so that the write portion includes data identifying the data to be written to the storage layer 324 (e.g., data stored in one or more caches communicatively coupled to the processing device 330) and the check value generated for the write portion. After generating a write portion for each write portion of the write request (e.g., all write portions divided from the write request), the processing device is configured to send the write request to the logic layer communicatively coupled to the storage layer 324 using one or more channels 338, pseudo channels 340, or both. The logic layer is configured to store the data identified in the write request and the check value of the write request in one or more storage bodies associated with the channel 338 or pseudo channel 340 that received the write request. For example, in response to receiving a write portion on pseudo channel 3 340-4, the logic layer is configured to store the data identified in the write portion and the check value of the write portion to the storage sub-body 342-4.

[0041] Reference now Figure 4, presents a flow chart of an exemplary process 400 for host-level error correction during a read operation. Process 400 includes a processing device 430 similar or identical to CPU 102, GPU 114, processing device 230, 330, or any combination thereof, configured to generate an extraction request identifying requested data. That is, processing device 430 generates an extraction request identifying data to be read from a memory 406 similar or identical to memory 106, 206. Processing device 430 is also configured to divide the extraction request into one or more extraction portions (e.g., 405-1, 405-2, 405-3, 405-4), each of which identifies a different portion of the data identified in the extraction request. For example, processing device 430 is configured to divide a 128-bit extraction request (i.e., an extraction request requesting 128 bits of data) into a group of four 32-bit extraction portions 405. Although in Figure 4 In the exemplary embodiment shown, processing device 430 divides the extraction request into a set of four extraction portions (405-1, 405-2, 405-3, 405-4), but in other embodiments, processing device 430 can be configured to divide the extraction request into any number of extraction portions. In response to generating one or more extraction portions 405, processing device 430 is configured to send a first number of extraction portions 405 to memory 406 using a first pseudo channel 440-1 and send a second number of extraction portions to memory 406 using a second pseudo channel 440-2. Although Figure 4 The exemplary embodiment shown presents two extraction portions (extraction portion 0 405-1 and extraction portion 1 405-2) being sent on pseudo channel 0 440-1, and two extraction portions (extraction portion 2 402-3 and extraction portion 3 402-4) being sent on pseudo channel 1 440-2, but in other embodiments, processing device 430 may send any number of extraction portions 405 on pseudo channel 0 440-1 and any number of extraction portions 405 on pseudo channel 1 440-2.

[0042] According to an embodiment, in response to dividing an extraction request into two or more extraction portions, processing device 430 is configured to generate a parity request 410 that identifies each extraction portion 405 associated with the extraction request and one or more operations to be performed on the data identified in the extraction portion. For example, parity request 410 identifies extraction portion 0 405-1, extraction portion 1 405-2, extraction portion 2 405-3, and extraction portion 3 405-4, and one or more operations to be performed on the data identified in extraction portion 0 405-1, extraction portion 1 405-2, extraction portion 2 405-3, and extraction portion 3 405-4 (e.g., data in extraction portion 1 Extract data from part 2 Extract data from part 3 In response to generating parity request 410, processing device 430 is configured to send parity request 410 to memory 406 using one or more pseudo channels used to send one or more of extraction portions 405. For example, in Figure 4 In the exemplary embodiment shown, processing device 430 is configured to send parity request 410 to memory 406 using pseudo channel 1 440 - 2 .

[0043] In response to receiving one or more extraction portions 405, the memory 406 is configured to read the data identified in the extraction portion 405 from one or more memory banks, memory sub-banks, or both associated with the pseudo-channel 440 from which the extraction portion was received. For example, in response to receiving extraction portion 0 405-1 on pseudo-channel 1 440-2, the memory 406 is configured to read the data identified in the extraction portion 405-1 from one or more memory banks, memory sub-banks, or both associated with pseudo-channel 1 440-2. According to an embodiment, in response to reading the data identified in the extraction portion 405, the memory 406 is configured to check the read data for one or more faults (e.g., uncorrected errors). In order to check the read data for one or more faults, the memory 406 is configured to compare one or more check bits associated with the read data with one or more values ​​(e.g., thresholds, values, strings), perform one or more operations on the check bits based on one or more ECCs (e.g., CRC codes) implemented by the memory 406, or both. In the embodiment, the check bits associated with the read data are stored in the same storage body, storage sub-body, or both as the read data. In response to the memory 406 detecting a fault in the read data, the memory 406 is configured to use other data stored in one or more storage bodies, storage sub-body, or both of the memory 406, using one or more parity check bits or both to correct the fault. According to the embodiment, the memory 406 is configured to read data for one or more fault checks limited to a predetermined number of bits. That is, the fault is limited to the corresponding part of the read data, each part including a predetermined number of bits. In order to read data for one or more fault checks limited to a predetermined number of bits, the memory 406 is configured to use multiple check bits based on a predetermined number of bits. For example, in order to read data for a fault check limited to 16 bits, the memory 406 is configured to use 16 check bits. Therefore, in response to reading data for one or more fault checks limited to a predetermined number of bits, one or more check bits associated with the read data are not used (for example, they are not used for reading data for fault check). That is, in response to checking the read data for one or more faults limited to a predetermined number of bits, the memory 406 is configured to use a plurality of check bits to check for the one or more faults, thereby leaving one or more unused check bits.

[0044] According to an embodiment, memory 406 is configured to generate one or more extract returns 415 for each received extract portion 405. Each extract return 415 includes the read data identified (i.e., requested) in the corresponding extract portion 405. In an embodiment, memory 406 is configured to send a plurality of extract returns 415 on a first pseudo-channel 440-1 and to send a second number of extract returns 415 on a second pseudo-channel 440-2. For example, memory 406 is configured to send each extract return 415 on the same pseudo-channel 440 in which the associated extract portion 405 (e.g., the extract portion identifying the data contained in the extract return) was received. As an example, Figure 4 The example implementation shown in presents Extract Return 0 415-1 and Extract Return 1 415-2 sent on pseudo channel 1 440-2 for receiving Extract Part 0 405-1 and Extract Part 405-2, and Extract Return 2 415-3 and Extract Return 3 415-4 sent on pseudo channel O 440-1 for receiving Extract Part 2 405-3 and Extract Part 3 405-4.

[0045] In response to generating one or more extraction returns 415, memory 406 is configured to generate parity extraction 420. Parity extraction 420 includes data resulting from performing one or more operations identified in parity request 410 on the read data included in extraction return 415. For example, in Figure 4 In the exemplary embodiment shown, extract return 0 415-1 includes a first set of read data (D0), extract return 1 415-2 includes a second set of read data (D1), extract return 2 415-3 includes a third set of read data (D2), and extract return 3 415-4 includes a fourth set of read data (D3). In the exemplary embodiment, memory 406 is configured to generate parity extraction 420 by performing one or more operations (e.g., XOR operations) identified in parity request 410 on D0, D1, D2, and D3. That is, parity extraction 420 includes performing an XOR operation on the read data (e.g., ) performs an XOR operation on the data obtained by performing an XOR operation. In response to generating a parity extraction 420, the memory 406 is configured to send the parity extraction 420 to the processing device 430 using one or more pseudo channels 440. In addition, in response to generating one or more extraction returns 415, the memory 406 is configured to send one or more unused check bits 425 to the processing device 430 using one or more pseudo channels 440. That is, the memory 406 is configured to send one or more check bits that are not used to check the read data in the extraction return for one or more faults limited to a predetermined number of bits. According to an embodiment, the number of unused check bits 425 sent to the processing device 430 is based on the predetermined number of limited faults checked in the read data. For example, in response to the memory 406 checking the read data for faults limited to 16 bits, 16 unused check bits are sent to the processing device 430. In some embodiments, the one or more unused check bits 425 are returned as part of the one or more extraction returns 415, while in other embodiments the unused check bits 425 are returned separately from the extraction returns 415.

[0046] In response to receiving the extraction returns 415, the parity extractions 420, and the check bits 425, the processing device 430 is configured to check each extraction return 415 for faults (e.g., uncorrected errors) according to one or more implemented ECC checks. For example, the processing device 430 includes an error correction engine similar to or the same as the error correction engine 234, 334, which is configured to check each extraction return 415 for faults by using one or more unused check bits 425 associated with the extraction returns 415 (e.g., unused check bits 425 returned with the extraction returns 415, unused check bits included in the extraction returns 415, or both). In an embodiment, the processing device 430 is configured to determine whether there are one or more errors in the extraction return 415 by comparing one or more of the unused check bits 425 to one or more values ​​(e.g., thresholds, values, strings), performing one or more operations on the one or more check bits 425, or both. For example, the processing device checks for one or more failures of the extraction return 415 by performing one or more operations on one or more check bits 425 according to an implemented ECC (e.g., CRC-12). In response to detecting one or more failures in the extraction return 415, the processing device 430 is configured to erase and reconstruct the extraction return 415. According to an embodiment, the processing device 430 is configured to reconstruct the extraction return 415 using data from one or more other extraction returns, the parity extraction 420, or both. For example, in Figure 4In the exemplary embodiment shown, processing device 430 is configured to reconstruct extract return 2 415-3 using data from extract return 0 415-1, extract return 1 415-2, extract return 3 415-4, and parity extract 420. In this manner, any failures that are limited to a single extract return are corrected. Correcting failures in this manner helps improve system reliability and reduces the chances of field replacement unit events, termination of applications using the memory, system reboots, or any combination thereof.

[0047] Reference now Figure 5 , presents a flow chart of an exemplary process 500 for correcting one or more faults in a fetch return. In an embodiment, process 500 includes a processing device similar or identical to CPU 102, GPU 114, processing device 230, 330, 430, or any combination thereof, configured to perform a fault detection operation 502 on one or more received fetch returns 515 similar or identical to fetch return 415. Although Figure 5 The exemplary embodiment shown in FIG. 5 presents four extract returns (extract return 0 515-1, extract return 1 515-2, extract return 2 515-3, extract return 3 515-4) received by the processing device, but in other embodiments, any number of extract returns 515 may be received. According to the embodiment, each extract return 515 includes at least a portion of the data readout of a memory similar or identical to memory 106, 206, 306, 406. For example, in Figure 5 In an exemplary embodiment of the present invention, extraction return 0 515-1 includes a first portion (D0) of the read data, extraction return 1 515-2 includes a second portion (D1) of the read data, extraction return 2 515-3 includes a third portion (D2) of the read data, and extraction return 3 515-4 includes a fourth portion (D3) of the read data. Fault detection operation 502 includes a processing device checking data of each extraction return 515 (e.g., D0, D1, D2, D3) for one or more faults based on an ECC implemented by the processing device and one or more unused check bits received from a memory (e.g., check bits not used by the memory to check D0, D1, D2, or D3 for one or more faults). For example, the processing device checks D0, D1, D2, and D3 for one or more faults based on a CRC-12 code and one or more unused check bits.

[0048] In response to the processing device detecting a fault in one or more fetch returns 515 (e.g., a fault in the data of one or more fetch returns), the processing device performs a fetch return erase operation 504 on the fetch returns that include the fault (e.g., the faulty fetch). Figure 5In an exemplary embodiment of , in response to the processing device detecting a fault in D1, the processing device performs an extraction return erase operation 504 on extraction return 1 515-2. The extraction return erase operation 504 includes erasing an extraction return that includes one or more faults (e.g., a faulty extraction). In response to erasing one or more extraction returns (e.g., a faulty extraction), the processing device performs an extraction return reconstruction operation 506, which includes reconstructing one or more erased extraction returns 515 based on one or more other extraction returns 515 associated with the erased extraction return (e.g., extraction returns 515 returned together with the erased extraction return, extraction returns 515 of the same group as the erased extraction, extraction returns 515 corresponding to the same extraction request), parity extractions 520 associated with the erased extraction return that are similar or identical to the parity extraction 420 (e.g., returned together with the erased extraction return and corresponding to the same extraction request), or both, thereby generating a reconstructed extraction return 530. For example, in Figure 5 In an example embodiment of, extract reconstruction operation 506 includes reconstructing extract return 1 515-1 based on extract return 0 515-1, extract return 2 515-3, extract return 3 515-4, and parity extraction 520. According to an embodiment, parity extraction 520 includes data resulting from one or more operations performed by the memory on the data of extract return 515 before the data is received by the processing device. For example, in Figure 5 In the exemplary embodiment of the present invention, parity extraction 520 includes extracting the parity from memory pairs D0, D1, D2, and D3 (eg, ) is performed on the data obtained by performing an XOR operation ... Figure 5 In the exemplary embodiment of the present invention, the extraction return reconstruction operation 506 includes extracting return 0 515-1 (D0), extracting return 2 515-3 (D2), extracting return 3 515-4 (D3), and parity extraction 520 According to an embodiment, the reconstructed extraction return 530 includes data resulting from performing one or more operations on data included in one or more other extraction returns 515 associated with the erased extraction return 515, data included in the parity extraction 520, or both. For example, the reconstructed extraction return 530 includes extraction return 0 515-1 (D0), extraction return 2 515-3 (D2), extraction return 3 515-4 (D3), and parity extraction 520. Data obtained by performing an XOR operation on the data included in to generate, for example, D1.

[0049] Reference now Figure 6 , presents a flow chart of an exemplary method 600 for host-level error detection during a read operation. After step 605 of method 600, a processing device similar or identical to CPU 102, GPU 114, processing device 230, 330, 430, or any combination thereof is configured to generate an extraction request for requesting to read data from a memory similar or identical to memory 106, 206, 406. According to an embodiment, the memory includes a 3D stacked SDRAM having two or more stacked storage layers, each of the two or more stacked storage layers having two or more channels. In an embodiment, the processing device divides the extraction request into one or more extraction portions, each of which identifies a different portion of the data requested in the extraction request. For example, the processing device divides a 128-bit extraction request (i.e., an extraction request identifying 128 bits of request data) into four 32-bit extraction portions, each of which identifies a 32-bit portion of the data requested in the 128-bit extraction request. In addition, at step 605, the processing device generates a parity request based on the extraction portions divided from the extraction request. The parity request indicates the data identified in each extraction portion and one or more operations performed on the identified data. For example, the parity request indicates the data identified in each extraction portion and an XOR operation. In response to generating the extraction portion and the parity request, the processing device sends the extraction portion and the parity request to the memory using one or more channels, pseudo channels, or both associated with the memory.

[0050] At step 610, in response to receiving one or more extraction portions, the memory reads the data identified in the extraction portion from one or more storage bodies, storage sub-bodies, or both. For example, the memory reads the data identified in the read portion from the storage sub-body associated with the pseudo-channel receiving the extraction portion. In response to reading the data identified in the read portion, the memory checks the read data for one or more faults (e.g., uncorrected errors) based on one or more implemented ECCs. For example, the memory detects one or more faults in the read data based on the on-chip ECC implemented by the memory. According to an embodiment, the memory detects one or more faults in the read data by, for example, comparing one or more check bits associated with the read data with one or more values ​​(e.g., thresholds, values, strings), performing one or more operations on one or more check bits according to one or more implemented ECCs, or both. In response to detecting one or more faults in the read data, the memory uses data stored in one or more storage bodies, storage sub-bodies, or both of the memory, uses one or more parity check bits stored in the memory, or both to correct the fault. In an embodiment, the memory is configured to detect one or more faults limited to a predetermined number of bits in the read data. For example, the memory is configured to detect a fault limited to 16 bits in the read data. According to an embodiment, in order to detect one or more faults limited to a predetermined number of bits in the read data, the memory is configured to use a plurality of check bits based on the predetermined number of bits, thereby leaving one or more unused check bits. For example, in order to determine one or more faults limited to 16 bits in the read data, the memory is configured to use 16 check bits, thereby leaving 16 unused check bits.

[0051] After detecting and correcting any fault, the memory generates one or more extraction returns. Each extraction return includes the read data identified in the corresponding received extraction part. That is, the memory generates a corresponding extraction return for each received extraction part. In addition, at step 610, the memory generates a parity extraction and extraction return based on the received parity request. The parity extraction includes the data obtained by performing the operation identified in the parity request on the read data of the generated extraction return. For example, the parity extraction includes the data obtained by performing an XOR operation on the read data of each extraction return. After generating the extraction return and the parity extraction, the memory sends the extraction return, one or more unused check bits (for example, check bits that are not used to detect or correct faults in the read data) and the parity extraction through one or more channels, pseudo channels or both of the memory, and receives them at the processing device.

[0052] At step 615, the processing device determines whether one or more of the extraction returns include a fault (e.g., an uncorrected error). In an embodiment, the processing device determines whether one or more of the extraction returns include a fault by comparing one or more received unused check bits with one or more values ​​(e.g., thresholds, values, strings), performing one or more operations based on the ECC implemented by the processing device, one or more unused check bits, or both. For example, the processing device determines whether there is a fault in the extraction return by performing one or more operations on one or more unused check bits according to a CRC-9 code. In response to the extraction return not including a fault, the system enters step 630, and the processing device sends the extraction return to the data weave coupled to the processing device and one or more caches similar to or identical to cache 236. In response to one or more extraction returns including a fault, the system will enter step 620. At step 620, the processing device erases the extraction return including the fault. At step 625, the processing device reconstructs the erased extraction return. In an embodiment, the processing device reconstructs the erased extraction return using data in one or more other extraction returns and parity extraction. That is, the processing device reconstructs the erased fetch return based on the read data and the data in the parity fetch included in the other fetch returns. In this way, faults limited to a single fetch return (e.g., drive failure, storage bank failure) are corrected, thereby improving the reliability of the system. After reconstructing the fetch return including the fault, the system enters step 630 and sends the fetch return (e.g., including the reconstructed fetch return) to a data weave and one or more caches communicatively coupled to the processing device.

[0053] Reference now Figure 7 , presents a flow chart of an exemplary process 700 for host-level error correction for write operations. Process 700 includes a processing device 730 similar or identical to CPU 102, GPU 114, processing device 230, 330, 430, or any combination thereof, the processing device being configured to generate a write request that identifies data to be written to one or more portions of a memory 706 that is similar or identical to memory 106, 206, 406. Processing device 730 is also configured to divide the write request into one or more write portions (e.g., 705-1, 705-2, 705-3, 705-4), each of which identifies a different portion of the data to be written identified in the write request. For example, processing device 730 is configured to divide a 128-bit write request into four 32-bit write portions 705. Although in Figure 6In the exemplary embodiment shown, the processing device 730 divides the write request into four write portions (705-1, 705-2, 705-3, 705-4), but in other embodiments, the processing device 730 can be configured to divide the write request into any number of write portions. In response to generating one or more write portions 705, the processing device 730 is configured to generate a check value for each write portion 705, and add the generated check value to the write portion 705, so that the write portion 705 includes data identifying the data to be written and a check value associated with the data to be written. In an embodiment, the processing device 730 is configured to generate a check value for the write portion 705 based on one or more ECCs (e.g., CRC-12 codes) implemented by the processing device 730. After adding the corresponding check value to each write portion 705, the processing device 730 is configured to send the first number of write portions 705 to the memory 706 using the first pseudo channel 740-1, and send the second number of write portions to the memory 706 using the second pseudo channel 740-2. Although Figure 7 The exemplary embodiment shown in shows two write portions (write portion 0 705-1 and write portion 1 705-2) being sent on pseudo channel 0 740-1 and two write portions (write portion 2 602-3 and write portion 3 602-4) being sent on pseudo channel 1 740-2, but in other embodiments, the processing device 730 can send any number of write portions 705 on pseudo channel 0 740-1 and any number of write portions 705 on pseudo channel 1 740-2.

[0054] According to an embodiment, the processing device 730 is further configured to generate a write parity 710 based on the data to be written identified in each write portion 705. The write parity 710 includes, for example, data resulting from performing one or more operations on the data to be written identified in each write portion 705. For example, based on the data to be written identified in write portion 0 705-1 (W0), write portion 1 705-2 (W1), write portion 2 705-3 (W2), and write portion 3 705-3 (W3), the processing device 730 is configured to generate a write parity 710 by performing one or more operations on W0, W1, W2, and W3. An XOR operation is performed to generate write parity 710. In response to generating write parity 710, processing device 730 is configured to send write parity 710 to memory 706 using one or more pseudo channels 740 of memory 706. In response to receiving write portion 705 and write parity 710, memory 706 is configured to store data identified in write portion 705, a check value for the write portion, and data of write parity 710 in one or more portions of memory 706. In an embodiment, memory 706 is configured to store data of write portion 705, write parity 710, or both based on pseudo channel 740 over which write portion 705 or write parity 710 was received. For example, in response to receiving write portion 0 705-1 and write portion 1 705-2 on pseudo channel 1 740-2, the memory is configured to store the data identified in write portion 0 705-1 and write portion 1 705-2 and the check values ​​of write portion 0 705-1 and write portion 1 705-2 in one or more storage bodies, storage sub-bodies, or both associated with pseudo channel 1 740-2.

[0055] As disclosed herein, in some embodiments, the method includes: in response to receiving a check bit and a plurality of extraction returns at a processing device, determining that an extraction return in the plurality of extraction returns includes a fault based on the check bit; in response to determining that the extraction return includes a fault, reconstructing the extraction return based on a parity extraction associated with the plurality of extraction returns and one or more other extraction returns in the plurality of extraction returns; and sending the reconstructed extraction to one or more caches communicatively coupled to the processing device. In one aspect, the method includes sending a plurality of extraction portions to a memory, the plurality of extraction portions each identifying request data; and sending a parity request to the memory, the parity request identifying the plurality of extraction portions and one or more operations. In another aspect, determining that an extraction return in the plurality of extraction returns includes a fault includes: performing an operation on the check bit according to an error correction code implemented by the processing device.

[0056] In one aspect, the error correction code comprises a cyclic redundancy check code. In another aspect, the method comprises, at a memory communicatively coupled to a processing device, checking request data identified in a plurality of extraction returns for one or more faults based on an error correction code implemented by the memory. In another aspect, the check bits comprise check bits that are not used at the memory for checking request data identified in a plurality of extraction returns for one or more faults. In another aspect, the error correction code implemented by the memory comprises an on-chip error correction code. In another aspect, a first number of extraction returns is received at a processing device on a first pseudo-channel of the memory, and a second number of extraction returns is received at the processing device on a second pseudo-channel of the memory. In another aspect, the memory comprises a three-dimensional stacked synchronous dynamic random access memory.

[0057] In some embodiments, a system includes: a memory having two or more pseudo channels; and a processing device coupled to the memory via the two or more pseudo channels, the processing device being configured to, in response to receiving a check bit and a plurality of extraction returns from the memory, determine that an extraction return in the plurality of extraction returns includes a fault based on the check bit; in response to determining that the extraction return includes a fault, reconstruct the extraction return based on a parity extraction associated with the plurality of extraction returns and one or more other extraction returns in the plurality of extraction returns; and send the reconstructed extraction to a data weave communicatively coupled to the processing device. In one aspect, the processing device is further configured to: send a plurality of extraction portions to the memory, the plurality of extraction portions each identifying request data; and send a parity request to the memory, the parity request identifying the plurality of extraction portions and one or more operations.

[0058] In one aspect, the memory is further configured to: check the requested data identified in the plurality of fetch returns for one or more faults based on an error correction code implemented by the memory. In another aspect, the memory is further configured to: generate a check bit based on an error correction code implemented by the memory. In another aspect, the error correction code implemented by the memory includes an on-chip error correction code. In another aspect, a first number of fetch returns is received at a processing device on a first pseudo-channel of the memory, and a second number of fetch returns is received at a processing device on a second pseudo-channel of the memory. In one aspect, the memory includes a three-dimensional stacked synchronous dynamic random access memory.

[0059] In some embodiments, the method includes: generating a check value for each of a plurality of write portions at a processing device based on an error correction code implemented by the processing device, each of the plurality of write portions identifying a corresponding portion of data to be written to a memory; determining a write parity based on a corresponding portion of data to be written to the memory of each of the plurality of write portions and an operation; and sending the write portion, the check value, and the write parity to the memory. In one aspect, the memory includes a three-dimensional stacked synchronous dynamic random access memory. In another aspect, a first number of write portions are sent to the memory on a first pseudo-channel of the memory, and a second number of write portions are sent to the memory on a second pseudo-channel of the memory. In another aspect, the error correction code includes a cyclic redundancy check code.

[0060] In some embodiments, the above-described apparatus and techniques are implemented in a system that includes one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as those described above with reference to Figures 1 to 6 A processing system for host error correction for read and write operations is described. Electronic design automation (EDA) and computer-aided design (CAD) software tools can be used in the design and manufacture of these IC devices. These design tools are generally represented as one or more software programs. One or more software programs include codes that can be executed by a computer system to manipulate the computer system to operate on the code representing the circuit of one or more IC devices so as to perform at least a part of the process for designing or adjusting the manufacturing system to manufacture the circuit. The code may include instructions, data, or a combination of instructions and data. Software instructions representing design tools or manufacturing tools are generally stored in a computer-readable storage medium that can be accessed by a computing system. Similarly, codes representing one or more stages of the design or manufacture of IC devices can be stored in and accessed from the same computer-readable storage medium or different computer-readable storage media.

[0061] Computer-readable storage media may include any non-transitory storage media or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact disks (CDs), digital versatile disks (DVDs), Blu-ray disks), magnetic media (e.g., floppy disks, tapes, or magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or micro-electromechanical system (MEMS)-based storage media. Computer-readable storage media may be embedded in a computing system (e.g., system RAM or ROM), fixedly attached to a computing system (e.g., a magnetic hard drive), removably attached to a computing system (e.g., an optical disk or a flash memory based on a universal serial bus (USB)), or coupled to a computer system via a wired or wireless network (e.g., a network accessible storage device (NAS)).

[0062] In some embodiments, certain aspects of the techniques described above may be implemented by one or more processors of a processing system that executes software. The software includes one or more sets of executable instructions that are stored or otherwise tangibly embodied on a non-transient computer-readable storage medium. The software may include instructions and certain data that manipulate one or more processors to perform one or more aspects of the above-described techniques when executed by one or more processors. The non-transient computer-readable storage medium may include, for example, a disk or optical disk storage device, a solid-state storage device such as a flash memory, a cache memory, a random access memory (RAM), or other one or more non-volatile memory devices, etc. The executable instructions stored on the non-transient computer-readable storage medium may be source code, assembly language code, object code, or other instruction formats interpreted or otherwise executed by one or more processors.

[0063] It should be noted that not all activities or elements described above in the general description are required, a portion of a particular activity or device may not be required, and one or more additional activities may be performed, or elements may be included in addition to those described. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. In addition, these concepts have been described with reference to specific embodiments. However, it is understood by those of ordinary skill in the art that various modifications and changes may be made without departing from the scope of the present disclosure as set forth in the following claims. Therefore, the specification and drawings are to be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the present disclosure.

[0064] The preposition "or" used in the context "at least one of A, B, or C" is used herein to mean "including or". That is, in the above and similar contexts, "or" is used to mean "at least one of..." or any combination thereof. For example, "at least one of A, B, and C" is used to mean "at least one of A, B, C, or any combination thereof".

[0065] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, benefits, advantages, solutions to problems, and any features that may cause any benefit, advantage, or solution to appear or become more significant should not be interpreted as key, essential, or basic features of any or all claims. In addition, the specific embodiments disclosed above are merely illustrative, as the disclosed subject matter may be modified and practiced in different but equivalent ways that are obvious to those skilled in the art who benefit from the teachings herein. Except as described in the following claims, it is not intended to limit the details of the construction or design shown herein. Therefore, it is apparent that the specific embodiments disclosed above may be changed or modified, and all such changes are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is as set forth in the following claims.

Claims

1. A method, comprising: in response to receiving a check bit and a plurality of extraction returns at a processing device, determining, based on the check bit, that an extraction return in the plurality of extraction returns includes a fault; In response to determining that the fetch return includes a fault, reconstructing the fetch return based on a parity fetch associated with the plurality of fetch returns and one or more other fetch returns of the plurality of fetch returns; as well as The reconstructed fetch is sent to one or more caches communicatively coupled to the processing device.

2. The method according to claim 1, further comprising: sending a plurality of extraction portions to a memory, each extraction portion identifying request data; as well as A parity request is sent to the memory, the parity request identifying the plurality of fetch portions and one or more operations.

3. The method of claim 1 , wherein determining that an extraction return in the plurality of extraction returns includes a failure comprises: An operation is performed on the check bits according to an error correction code implemented by the processing device. The method of claim 3 , wherein the error correction code comprises a cyclic redundancy check code.

5. The method according to claim 1, further comprising: At a memory communicatively coupled to the processing device, request data identified in the plurality of fetch returns is checked for one or more faults based on an error correction code implemented by the memory. 6 . The method of claim 5 , wherein the check bits include check bits that are not used at the memory to check the request data identified in the plurality of fetch returns for one or more failures.

7. The method of claim 5, wherein the error correction code implemented by the memory comprises an on-chip error correction code.

8. The method of claim 1, wherein a first number of the fetch returns are received at the processing device on a first pseudo channel of the memory, and a second number of the fetch returns are received at the processing device on a second pseudo channel of the memory.

9. The method of claim 8, wherein the memory comprises a three-dimensional stacked synchronous dynamic random access memory.

10. A system, comprising: a memory having two or more pseudo channels; and a processing device, the processing device being coupled to the memory via the two or more pseudo channels, the processing device being configured to: in response to receiving a check bit and a plurality of fetch returns from the memory, determining based on the check bit that an fetch return in the plurality of fetch returns includes a fault; In response to determining that the fetch return includes a fault, reconstructing the fetch return based on a parity fetch associated with the plurality of fetch returns and one or more other fetch returns of the plurality of fetch returns; as well as The reconstructed extraction is sent to a data fabric communicatively coupled to the processing device.

11. The system according to claim 10, wherein the processing device is further configured to: sending a plurality of extraction portions to the memory, the plurality of extraction portions each identifying request data; and A parity request is sent to the memory, the parity request identifying the plurality of fetch portions and one or more operations.

12. The system of claim 10, wherein the memory is further configured to: Request data identified in the plurality of fetch returns is checked for one or more faults based on an error correction code implemented by the memory.

13. The system of claim 10, wherein the memory is further configured to: The check bits are generated based on an error correction code implemented by the memory.

14. The system of claim 13, wherein the error correction code implemented by the memory comprises an on-chip error correction code.

15. The system of claim 10, wherein a first number of the fetch returns are received at the processing device on a first pseudo channel of the memory, and a second number of the fetch returns are received at the processing device on a second pseudo channel of the memory.

16. The system of claim 10, wherein the memory comprises a three-dimensional stacked synchronous dynamic random access memory.

17. A method comprising: generating, at a processing device, a check value for each of a plurality of write portions based on an error correction code implemented by the processing device, each of the plurality of write portions identifying a corresponding portion of data to be written to a memory; determining a write parity based on the corresponding portion of data to be written to the memory of each of the plurality of write portions and an operation; as well as The written portion, the check value, and the write parity are sent to the memory.

18. The method of claim 17, wherein the memory comprises a three-dimensional stacked synchronous dynamic random access memory.

19. The method of claim 17, wherein a first number of the write portions are sent to the memory on a first pseudo channel of the memory, and a second number of the write portions are sent to the memory on a second pseudo channel of the memory.

20. The method of claim 17, wherein the error correction code comprises a cyclic redundancy check code.

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