Built-in self-test circuit and memory

Abstract

The invention relates to a built-in self-test circuit and a memory. The built-in self-test circuit comprises a storage array, a command / address generation module, a processing module and a repair module. After entering the self-test mode, the command / address generation module generates and sends an internal test command and an internal test address according to a preset test mode. The processing module writes preset data into a storage unit corresponding to the internal test address in the storage array according to the internal test command and a preset test mode, and reads storage data from the storage unit corresponding to the internal test address in the storage array; and generating and outputting a fault mark according to a comparison result of the storage data read each time and the corresponding written preset data. And the repairing module latches the internal test address corresponding to the currently read storage data as an error address according to the fault mark, and repairs the storage unit corresponding to the error address after the self-test mode exits. According to the invention, internal automatic detection and automatic repair can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a built-in self-test circuit and a memory. Background Art

[0002] In DDR DRAM (Double Rate Synchronous Dynamic Random Access Memory), taking DDR5 as an example, after MRW (Mode Register Write) is enabled and three sets of Guard keys are given, DDR DRAM can enter Mbist mode, after which the alert_n pin automatically changes to a low level. During the self-test (tSelftest) period, DDR DRAM can automatically detect and record 1-bit or multi-bit errors in the memory array. Although existing DDRDRAM can detect errors, it cannot automatically repair the memory cells corresponding to the errors and addresses. Summary of the invention

[0003] Based on this, it is necessary to provide a built-in self-test circuit and memory that can realize internal automatic detection and automatic repair.

[0004] In a first aspect, a built-in self-test circuit is provided, the built-in self-test circuit comprising:

[0005] Storage arrays;

[0006] A command / address generation module, used to generate and send internal test commands and internal test addresses according to a preset test mode after entering the self-test mode;

[0007] a processing module, connected to the command / address generation module and the storage array respectively, for receiving the internal test command and the internal test address; writing preset data to the storage unit corresponding to the internal test address in the storage array according to the preset test mode according to the internal test command, and reading storage data from the storage unit corresponding to the internal test address in the storage array; and generating and outputting a fault flag according to a comparison result of the storage data read each time with the corresponding preset data written; the fault flag indicates whether there is a data error in the storage data currently read;

[0008] A repair module is connected to the command / address generation module and the processing module respectively, and is used to latch the internal test address corresponding to the storage data currently read as an error address according to the fault flag, and repair the storage unit corresponding to the error address after exiting the self-test mode.

[0009] In one embodiment, the storage array includes M storage body groups, each of which includes N storage bodies, where M and N are both positive integers; the preset data includes M*N preset sub-data, which correspond to the M*N storage bodies one by one, and each preset sub-data includes P-bit target write data; the storage data includes M*N storage sub-data, which correspond to the M*N storage bodies one by one, and each storage sub-data includes P-bit target read data, where P is a positive integer; the processing module includes:

[0010] M*N judgment units are connected to the storage bodies in the storage array in a one-to-one correspondence, and each of the judgment units is used to read a corresponding storage sub-data from the P storage cells corresponding to the internal test address in the corresponding storage body, and compare the P-bit target read data in the storage sub-data with the P-bit target write data in the corresponding preset sub-data bit by bit, and respectively generate and output P first comparison results corresponding to the P storage cells; wherein, if the target read data and the target write data are the same, the output first comparison result indicates that there is no data error in the corresponding storage cell; otherwise, if the target read data and the target write data are different, the output first comparison result indicates that there is a data error in the corresponding storage cell;

[0011] M*N first compression units are connected to the M*N judgment units in a one-to-one correspondence; each of the first compression units is used to obtain P first comparison results of P storage units in the corresponding storage body and perform compression processing to obtain a second comparison result of the corresponding storage body, wherein the second comparison result indicates whether there is a data error in the corresponding storage body;

[0012] The second compression unit is connected to the M*N first compression units respectively, and is used to obtain and compress the second comparison results corresponding to the M*N storage bodies, generate and output the fault flag and storage body flag, and the storage body flag is used to indicate the storage body with data errors.

[0013] In one embodiment, the determining unit includes:

[0014] P XOR gates correspond one-to-one to the P bits of the target read data in the corresponding storage sub-data and the P bits of the target write data in the corresponding preset sub-data, and the two input ends of each XOR gate are respectively used to receive one bit of the target read data read from a corresponding storage unit and one bit of the target write data written thereto, and the output end is used to output the first comparison result of the corresponding storage unit.

[0015] In one embodiment, the first compression unit comprises:

[0016] A compression engine, connected to the corresponding judgment unit, for receiving the first comparison result of each storage unit in the corresponding storage body and adopting a compression mode to obtain multi-bit intermediate data, wherein the multi-bit intermediate data carries information on whether there is a data error in the storage body;

[0017] The auxiliary compression circuit is connected to the compression engine and is used for compressing the multi-bit intermediate data into one-bit output data, and using the output data as the second comparison result of the corresponding storage body.

[0018] In one embodiment, when the compression engine outputs four-bit intermediate data, the auxiliary compression circuit includes:

[0019] Two first NOR gates, each input end of which is connected to the compression engine respectively, for receiving corresponding one-bit intermediate data;

[0020] The first NAND gate has two input terminals connected one by one with the output terminals of the two first NOR gates, and an output terminal used for outputting one-bit output data.

[0021] In one embodiment, the second compression unit comprises:

[0022] M block compression circuits, corresponding one to one with the M memory bank groups, each of the block compression circuits being connected to the first compression unit corresponding to each memory bank in the corresponding memory bank group; each of the block compression circuits being used to obtain the second comparison result of each memory bank in the corresponding memory bank group and perform compression and logic operation, and generate and output the third comparison result and memory bank selection flag of the corresponding memory bank group, the memory bank selection flag being used to indicate the memory bank with data errors in the corresponding memory bank group, and the third comparison result indicating whether there are data errors in the corresponding memory bank group;

[0023] a set compression circuit, connected to the M block compression circuits respectively, for obtaining the third comparison result of each memory bank group and performing compression and logic operation, generating and outputting the fault flag and the memory bank group selection flag, wherein the memory bank group selection flag is used to indicate the memory bank group with data errors;

[0024] The output unit is connected to the block compression circuit and the set compression circuit respectively, and is used to determine the storage body flag according to the storage body selection flag and the storage body group selection flag.

[0025] In one embodiment, the block compression circuit comprises:

[0026] a memory bank selection flag generating circuit, configured to obtain a second comparison result of each memory bank in the corresponding memory bank group, and when at least one memory bank in the corresponding memory bank group has a data error, select one of the memory banks with the data error in accordance with a preset order, and generate the memory bank selection flag, wherein the memory bank selection flag indicates a row address corresponding to the selected memory bank;

[0027] The block fault compression circuit is used to obtain the second comparison result of each of the storage banks in the corresponding storage bank group, and generate a third comparison result of the corresponding storage bank group according to the second comparison results of each of the storage banks in the corresponding storage bank group.

[0028] In one of the embodiments, when there are no data errors in the N storage bodies in the corresponding storage body group, the storage body selection flag indicates that the storage body of the storage row address is the first or last storage body in the corresponding storage body group in a preset order.

[0029] In one embodiment, when N=4, each of the memory bank groups includes a first memory bank, a second memory bank, a third memory bank and a fourth memory bank; and the memory bank selection flag generation circuit includes:

[0030] A first NOT gate, an input end of which is used to receive a second comparison result of the first storage body;

[0031] A second NOT gate, an input end of which is used to receive a second comparison result of the second storage bank;

[0032] A second NAND gate, two input terminals of which are respectively connected to the output terminal of the first NAND gate and the output terminal of the second NAND gate;

[0033] A third NAND gate, a first input end of which is used to receive the second comparison result of the third memory bank, and a second input end of which is connected to the output end of the second NAND gate;

[0034] The fourth NAND gate has two input terminals respectively connected to the output terminal of the first NAND gate and the output terminal of the third NAND gate, and the output terminal of the fourth NAND gate cooperates with the output terminal of the second NAND gate to output the storage body selection flag.

[0035] In one embodiment, the block fault compression circuit comprises:

[0036] Two second NOR gates, whose input ends are respectively used to receive the second comparison result of a corresponding one of the storage banks;

[0037] a fifth NAND gate, whose input terminals are respectively connected to the output terminals of the two second NOR gates;

[0038] The third NOT gate has an input end connected to the output end of the fifth NAND gate, and an output end used for outputting the third comparison result of the memory bank group.

[0039] In one embodiment, the aggregate compression circuit comprises:

[0040] a memory bank group selection flag generating circuit, configured to obtain the third comparison result of each of the memory bank groups, and when at least one of the memory bank groups has a data error, select one of the memory bank groups having the data error in accordance with a preset order, and generate the memory bank group selection flag;

[0041] The collective fault compression circuit is used to obtain the third comparison result of each of the memory bank groups and generate the fault flag according to the third comparison result of each of the memory bank groups.

[0042] In one of the embodiments, when there are no data errors in the M memory bank groups, the memory bank group selection flag indicates the memory bank group that is located at the front or the back of the preset sequence.

[0043] In one embodiment, when M=8, the M memory bank groups include: a first memory bank group, a second memory bank group, a third memory bank group, a fourth memory bank group, a fifth memory bank group, a sixth memory bank group, a seventh memory bank group, and an eighth memory bank group; the memory bank group selection flag includes: a first memory bank selection flag, a second memory bank selection flag, and a third memory bank selection flag;

[0044] The memory bank group selection flag generating circuit comprises: a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a tenth NOT gate, an eleventh NOT gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate, a ninth NAND gate, a tenth NAND gate, an eleventh NAND gate, a twelfth NAND gate, a thirteenth NAND gate, a fourteenth NAND gate, a fifteenth NAND gate, a third NOR gate, a fourth NOR gate, a fifth NOR gate and a sixth NOR gate;

[0045] The input end of the fourth NOT gate is used to receive the third comparison result of the third storage body group; the input end of the fifth NOT gate is used to receive the third comparison result of the fourth storage body group; the input end of the sixth NOT gate is used to receive the third comparison result of the fifth storage body group; the input end of the seventh NOT gate is used to receive the third comparison result of the sixth storage body group; the input end of the eighth NOT gate is used to receive the third comparison result of the seventh storage body group; the input end of the ninth NOT gate is used to receive the third comparison result of the eighth storage body group; the first input end of the sixth NAND gate is connected to the output end of the fourth NAND gate, and the second input end of the sixth NAND gate is used to receive the third comparison result of the second storage body group; the first input end of the seventh NAND gate is connected to the output end of the sixth NAND gate, and the input end of the seventh NAND gate is connected to the output end of the sixth NAND gate. The second input end is connected to the output end of the fifth NOT gate; the first input end of the eighth NAND gate is connected to the output end of the seventh NAND gate, and the second input end of the eighth NAND gate is connected to the output end of the sixth NAND gate; the first input end of the ninth NAND gate is connected to the output end of the eighth NAND gate, and the second input end of the ninth NAND gate is connected to the output end of the seventh NAND gate; the first input end of the tenth NAND gate is connected to the output end of the ninth NAND gate, and the second input end of the tenth NAND gate is connected to the output end of the eighth NAND gate; the first input end of the eleventh NAND gate is connected to the output end of the tenth NAND gate, and the second input end of the eleventh NAND gate is connected to the output end of the ninth NAND gate, and the output end of the eleventh NAND gate is used to generate the first memory bank group selection flag;

[0046] The first input end of the third NOR gate is used to receive the third comparison result of the fifth memory bank group, and the second input end of the third NOR gate is used to receive the third comparison result of the sixth memory bank group; the input end of the tenth NOR gate is used to receive the third comparison result of the third memory bank group; the input end of the eleventh NOR gate is used to receive the third comparison result of the fourth memory bank group; the first input end of the sixth NOR gate is used to receive the third comparison result of the seventh memory bank group, and the second input end of the sixth NOR gate is used to receive the third comparison result of the eighth memory bank group; the twelfth NAND gate is used to receive the third comparison result of the eighth memory bank group; The first input end of is connected to the output end of the tenth NOT gate, the second input end of the twelfth NAND gate is connected to the output end of the eleventh NAND gate; the first input end of the thirteenth NAND gate is connected to the output end of the third NOR gate, the second input end of the thirteenth NAND gate is connected to the output end of the twelfth NAND gate; the first input end of the fourteenth NAND gate is connected to the output end of the thirteenth NAND gate, the second input end of the fourteenth NAND gate is connected to the output end of the sixth NOR gate, and the output end of the fourteenth NAND gate is used to generate the second memory bank group selection flag;

[0047] The first input end of the fourth NOR gate is used to receive the third comparison result of the fifth memory bank group, and the second input end of the fourth NOR gate is used to receive the third comparison result of the sixth memory bank group; the first input end of the fifth NOR gate is used to receive the third comparison result of the seventh memory bank group, and the second input end of the fifth NOR gate is used to receive the third comparison result of the eighth memory bank group; the first input end of the fifteenth NAND gate is connected to the output end of the fourth NOR gate, the second input end of the fifteenth NAND gate is connected to the output end of the fifth NOR gate, and the output end of the fifteenth NAND gate is used to generate the third memory bank group selection flag;

[0048] The collective fault compression circuit includes: a seventh NOR gate, an eighth NOR gate, a ninth NOR gate, a tenth NOR gate, an eleventh NOR gate, a sixteenth NAND gate and a seventeenth NAND gate;

[0049] The first input end of the seventh NOR gate is used to receive the third comparison result of the first memory bank group, and the second input end of the seventh NOR gate is used to receive the third comparison result of the second memory bank group; the first input end of the eighth NOR gate is used to receive the third comparison result of the third memory bank group, and the second input end of the eighth NOR gate is used to receive the third comparison result of the fourth memory bank group; the first input end of the ninth NOR gate is used to receive the third comparison result of the fifth memory bank group, and the second input end of the ninth NOR gate is used to receive the third comparison result of the sixth memory bank group; the first input end of the tenth NOR gate is used to receive the third comparison result of the seventh memory bank group, and the second input end of the tenth NOR gate is used to receive the third comparison result of the seventh memory bank group. The second input end of the NOR gate is used to receive the third comparison result of the eighth storage body group; the first input end of the sixteenth NAND gate is connected to the output end of the seventh NOR gate, and the second input end of the sixteenth NAND gate is connected to the output end of the eighth NOR gate; the first input end of the seventeenth NAND gate is connected to the output end of the ninth NOR gate, and the second input end of the seventeenth NAND gate is connected to the output end of the tenth NOR gate; the first input end of the eleventh NOR gate is connected to the output end of the sixteenth NAND gate, and the second input end of the eleventh NOR gate is connected to the output end of the seventeenth NAND gate, and the output end of the eleventh NOR gate is used to generate the fault flag.

[0050] In one of the embodiments, the repair module is also used to receive the storage body flag, latch the storage body flag when the fault flag indicates that there is a data error in the storage data currently being read, and repair the storage unit corresponding to the error address in the storage body indicated by the storage body flag after exiting the self-test mode.

[0051] In one embodiment, the command / address generation module includes:

[0052] a clock generating unit, configured to receive a self-test enable signal, and to generate and output a clock signal when the self-test enable signal is at a valid level;

[0053] A command generation unit, connected to the clock generation unit, for sequentially generating an activation command, a write command / read command and a precharge command that meet the read / write operation timing requirements according to the clock signal;

[0054] The internal test address includes an internal test row address and an internal test column address;

[0055] The address generating unit is connected to the clock generating unit and the address generating unit respectively, and is used to generate an internal test row address according to the activation command and the clock signal, and to generate an internal test column address according to the write command / the read command and the clock signal.

[0056] In one embodiment, the command generation unit is further used to receive a test mode signal; when the test mode signal is at a first level, indicate that the preset test mode is a row priority test mode, and generate the internal test command according to a row priority addressing mode; when the test mode signal is at a second level, indicate that the preset test mode is a column priority test mode, and generate the internal test command according to a column priority addressing mode;

[0057] The address generation unit is also used to receive a test mode signal; when the test mode signal is at a first level, it indicates that the preset test mode is a row priority test mode, and generates the internal test address according to the row priority addressing method; when the test mode signal is at a second level, it indicates that the preset test mode is a column priority test mode, and generates the internal test address according to the column priority addressing method.

[0058] In one of the embodiments, the repair module is connected to the address generation unit and the processing module to receive the fault flag, and is also connected to the address generation unit to receive the internal test row address or the internal test column address, and when the fault flag indicates that there is a data error in the storage data currently being read, the internal test row address or the internal test column address corresponding to the storage data currently being read is latched as an error address, and the storage cell row or storage cell column corresponding to the error address is repaired after the self-test mode is exited.

[0059] In one embodiment, the built-in self-test circuit further includes:

[0060] The alarm module is used to generate a test alarm signal according to the self-test enable signal and send the test alarm signal to the memory controller.

[0061] In one embodiment, the self-test enable signal switches to a valid level when the storage array enters a self-test mode defined by a protocol or a setting mode.

[0062] In a second aspect, a memory is provided, the memory comprising the built-in self-test circuit provided in the first aspect.

[0063] The above-mentioned built-in self-test circuit and memory include a storage array, a command / address generation module, a processing module and a repair module. The command / address generation module first generates and sends an internal test command and an internal test address according to a preset test mode after entering the self-test mode. The processing module then writes preset data to the storage unit corresponding to the internal test address in the storage array according to the preset test mode according to the internal test command, and reads the storage data from the storage unit corresponding to the internal test address in the storage array, and generates and outputs a fault flag of whether there is a data error in the currently read storage data according to the comparison result of the storage data read each time and the corresponding preset data written, thereby realizing automatic detection inside the chip. The repair module latches the internal test address corresponding to the currently read storage data as an error address according to the fault flag, and repairs the storage unit corresponding to the error address after exiting the self-test mode, thereby realizing automatic repair inside the memory chip. In this way, testing and repair can be automatically performed in the production test stage, which can effectively reduce the production cost of the chip and improve the yield of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0065] Figure 1 A schematic diagram of the structure of a built-in self-test circuit according to an embodiment;

[0066] Figure 2 A schematic diagram of the structure of a storage array and a processing module in a built-in self-test circuit according to an embodiment;

[0067] Figure 3 A schematic diagram of the structure of a judgment unit in a built-in self-test circuit according to an embodiment;

[0068] Figure 4 and Figure 5is a schematic structural diagram of a first compression unit in a built-in self-test circuit according to an embodiment;

[0069] Figure 6 is a schematic structural diagram of a second compression unit in a built-in self-test circuit according to an embodiment;

[0070] Figure 7 A schematic diagram of the structure of a block compression circuit in a built-in self-test circuit according to an embodiment;

[0071] Figure 8 A schematic diagram of the structure of a memory bank selection flag generating circuit in a built-in self-test circuit according to an embodiment;

[0072] Fig. 9 A schematic diagram of the structure of a block fault compression circuit in a built-in self-test circuit according to an embodiment;

[0073] Fig.10 A schematic diagram of the structure of a collective compression circuit in a built-in self-test circuit according to an embodiment;

[0074] Fig.11 A schematic diagram of the structure of a memory bank group selection flag generation circuit in a built-in self-test circuit according to an embodiment;

[0075] Fig.12 A schematic diagram of the structure of a collective fault compression circuit in a built-in self-test circuit according to an embodiment;

[0076] Fig.13 A schematic diagram of the structure of a built-in self-test circuit according to another embodiment;

[0077] Fig.14 A schematic diagram of the structure of a command / address generation module in a built-in self-test circuit according to an embodiment;

[0078] Fig.15 A schematic diagram of the structure of a built-in self-test circuit according to another embodiment;

[0079] Fig.16 FIG. 4 is a schematic diagram of the structure of a built-in self-test circuit according to another embodiment.

[0080] Description of reference numerals:

[0081] 10. storage array, 20. command / address generation module, 30. processing module, 40. repair module, 50. alarm module;

[0082] 31. Judgment unit, 311. XOR gate;

[0083] 32, a first compression unit, 321, a compression engine, 322, an auxiliary compression circuit, 3221, a first NOR gate, 3222, a first NAND gate;

[0084] 33. A second compression unit, 331. A block compression circuit, 3311. A storage body selection flag generation circuit, 3312. A block fault compression circuit, 332. A collection compression circuit, 3321. A storage body group selection flag generation circuit, 3322. A collection fault compression circuit, 333. An output unit. DETAILED DESCRIPTION

[0085] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0086] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0087] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0088] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0089] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0090] Figure 1 FIG. 1 is a schematic diagram of a structure of a built-in self-test circuit according to an embodiment of the present invention. Figure 1As shown, the built-in self-test circuit includes a storage array 10, a command / address generation module 20, a processing module 30 and a repair module 40. The command / address generation module 20 is used to generate and send an internal test command and an internal test address according to a preset test mode after entering the self-test mode. The processing module 30 is connected to the command / address generation module 20 and the storage array 10 respectively, and is used to receive the internal test command and the internal test address; according to the internal test command, write preset data to the storage unit corresponding to the internal test address in the storage array 10 according to the preset test mode, and read the storage data from the storage unit corresponding to the internal test address in the storage array 10; and generate and output a fault flag according to the comparison result of the storage data read each time with the corresponding preset data written. Among them, the fault flag indicates whether there is a data error in the storage data currently read. The repair module 40 is connected to the command / address generation module 20 and the processing module 30 respectively, and is used to latch the internal test address corresponding to the storage data currently read as an error address according to the fault flag, and repair the storage unit corresponding to the error address after the self-test mode is exited.

[0091] The memory array 10 includes a plurality of memory groups, each memory group includes a plurality of memory cells, and each memory cell includes a plurality of memory cells arranged in an array. The self-test mode is that the chip automatically tests the memory cells in the memory array 10. The preset test mode is a pre-set test area and test method, such as the memory cells to be tested in the memory array 10, the order of testing each memory cell, and the order of operations on each memory cell.

[0092] The internal test command includes an activation command for activating the row address corresponding to the storage unit, a write command for writing preset data into the storage unit, a read command for reading the data stored in the storage unit, and a precharge command, etc. The internal test address includes the row address and column address corresponding to the storage unit for writing preset data and reading the storage data, specifically including the internal test row address and the internal test column address. Since the repair of the storage array includes two repair methods, row repair and column repair, that is, it can be to replace the storage unit of the entire row or replace the storage unit of the entire column, the address transmitted to the repair module 40 for latching is usually one of the row address or the column address, and it is not necessary to transmit the row address and the column address at the same time. A row address / column address corresponds to multiple storage units respectively, that is, the error address is also one of the row address or the column address, corresponding to all the storage units of a storage unit row or a storage unit column. As for whether to repair the sampling row or column, the optimal repair method can be selected based on the statistics and calculation of the storage units with data errors in the memory.

[0093] In the above embodiment, the built-in self-test circuit includes a storage array 10, a command / address generation module 20, a processing module 30 and a repair module 40. The command / address generation module 20 first generates and sends an internal test command and an internal test address according to a preset test mode after entering the self-test mode. The processing module 30 then writes preset data to the storage unit corresponding to the internal test address in the storage array 10 according to the internal test command and the preset test mode, and reads the storage data from the storage unit corresponding to the internal test address in the storage array 10, and generates and outputs a fault flag of whether there is a data error in the currently read storage data according to the comparison result of the storage data read each time and the corresponding preset data written, thereby realizing automatic detection inside the chip. The repair module 40 latches the internal test address corresponding to the currently read storage data as an error address according to the fault flag, and repairs the storage unit corresponding to the error address after exiting the self-test mode, thereby realizing automatic repair inside the chip. In this way, testing and repair can be automatically performed in the production test stage, which can effectively reduce the production cost of the chip and improve the yield of the chip.

[0094] In one embodiment, the storage array 10 includes M storage bank groups, each storage bank group includes N storage banks. Wherein, M and N are both positive integers. The preset data includes M*N preset sub-data, which correspond to the M*N storage banks one by one, and each preset sub-data includes P-bit target write data. The storage data includes M*N storage sub-data, which correspond to the M*N storage banks one by one, and each storage sub-data includes P-bit target read data. Wherein, P is a positive integer.

[0095] Exemplarily, the storage array 10 is a dynamic random access memory (DRAM), and one storage unit usually stores one bit of data. P-bit target write data are respectively written into P storage units of the same storage unit, and P-bit target read data are respectively read from the P storage units. M*N preset sub-data are respectively written into N storage units of M storage unit groups, that is, respectively written into M*N storage units; M*N stored sub-data are read from the M*N storage units.

[0096] Figure 2 FIG. 1 is a schematic diagram of the structure of a processing module according to an embodiment of the present invention. Figure 2As shown, in one embodiment, the processing module 30 includes M*N judgment units 31, M*N first compression units 32 and second compression units 33. The M*N judgment units 31 are connected to the storage bodies 11 in the storage array 10 in a one-to-one correspondence, and each judgment unit 31 is used to read a corresponding storage sub-data from P storage cells corresponding to the internal test address in a corresponding storage body, and compare the P-bit target read data in the storage sub-data with the P-bit target write data in a corresponding preset sub-data bit by bit, and respectively generate and output P first comparison results corresponding to the P storage cells; wherein, if the target read data and the target write data are the same, the output first comparison result indicates that there is no data error in the corresponding storage cell; conversely, if the target read data and the target write data are different, the output first comparison result indicates that there is a data error in the corresponding storage cell. The M*N first compression units 32 are connected to the M*N judgment units 31 in a one-to-one correspondence. Each first compression unit 32 is used to obtain the first comparison result of each storage unit in the corresponding storage body and perform compression processing to obtain the second comparison result of the corresponding storage body, and the second comparison result indicates whether there is a data error in the corresponding storage body. The second compression unit 33 is connected to the M*N first compression units 32 respectively, and is used to obtain the second comparison results corresponding to the M*N storage bodies and compress them, and generate and output a fault flag and a storage body flag. Among them, the storage body flag is used to indicate a storage body with a data error.

[0097] Among them, the internal test address corresponds to multiple storage units, and the internal test address includes an internal test row address and an internal test column address. The internal test row address and the internal test column address jointly select the storage unit that needs to perform the read / write operation. First, all the storage units of the target row corresponding to the internal test row address are opened based on the activation command containing the internal test row address, and then the storage sub-data / preset sub-data are read from the target row to the selected corresponding storage unit based on the internal test column address in the read command / write command. Take an internal test address corresponding to P storage units in the same storage body as an example, and one storage unit stores one bit of data. The judgment unit 31 selects the P storage units corresponding to the internal test address from each storage unit in the corresponding storage body to obtain their respective storage data, and obtains P-bit target read data, that is, one storage sub-data. M*N judgment units 31 obtain M*N storage sub-data. Correspondingly, the preset data written corresponding to the P storage units is P-bit target write data, that is, one preset sub-data. M*N judgment units 31 correspond to M*N storage sub-data.

[0098] The first comparison result of a storage unit indicates whether the storage unit has a data error. If a target read data bit in the storage unit is the same as the corresponding target written data bit, it means that the data of the storage unit is correct, that is, there is no data error; if a target read data bit in the storage unit is different from the corresponding target written data bit, it means that there is a data error in the storage unit.

[0099] The second comparison result of a memory bank indicates whether the memory bank has data errors. If all memory cells have no data errors, it means that the memory bank has no data errors; if at least one memory cell has data errors, it means that the memory bank has data errors.

[0100] The fault flag indicates whether there is a data error in the storage array 10. If there is no data error in all the storage banks 11, it means that there is no data error in the storage array 10, and the storage bank flag indicates a default storage bank in the storage array 10; if there is a data error in at least one storage bank 11, it means that there is a data error in the storage array 10, and the storage bank flag indicates a storage bank 11 in the storage array 10 with a data error.

[0101] In the above embodiment, the processing module 30 includes M*N judgment units 31, M*N first compression units 32 and second compression units 33. Each judgment unit 31 reads a corresponding storage sub-data from P storage units corresponding to the internal test address in a corresponding storage body, and compares the P-bit target read data in the storage sub-data with the P-bit target write data in a corresponding preset sub-data bit by bit, and respectively generates and outputs P first comparison results corresponding to the P storage units, so as to realize the automatic test of the storage unit. Each first compression unit 32 first obtains the first comparison result of each storage unit in the corresponding storage body and performs compression processing to obtain the second comparison result of the corresponding storage body. The second compression unit 33 then obtains the second comparison results corresponding to the M*N storage bodies and performs compression, generates and outputs the fault flag and the storage body flag, so as to compress the results of the automatic test of the storage unit and reduce the amount of data.

[0102] Figure 3 FIG. 1 is a schematic diagram of a structure of a judgment unit according to an embodiment of the present invention. Figure 3 As shown, optionally, the judgment unit 31 includes P XOR gates 311, which correspond one-to-one to the P-bit target read data in the corresponding storage sub-data and the P-bit target write data in the corresponding preset sub-data, and the two input ends of each XOR gate 311 are respectively used to receive a bit of target read data read from a corresponding storage unit and a bit of target write data written thereto, and the output end is used to output the first comparison result of the corresponding storage unit.

[0103] For example, if the one-bit target read data received by an XOR gate 311 is the same as the one-bit target write data written to it, that is, the data received by the two input terminals of the XOR gate 311 is the same, then the output terminal of the XOR gate 311 outputs a low level representing data "0" to indicate that there is no data error in the storage unit corresponding to the XOR gate 311. If the one-bit target read data received by an XOR gate 311 is different from the one-bit target write data written to it, that is, the data received by the two input terminals of the XOR gate 311 is different, then the output terminal of the XOR gate 311 outputs a high level representing data "1" to indicate that there is a data error in the storage unit corresponding to the XOR gate 311.

[0104] Exemplarily, an internal test address corresponds to P storage cells in the same storage body, and P XOR gates 311 respectively receive one bit of target read data and one bit of corresponding target write data from each corresponding storage cell in the storage body corresponding to the judgment unit 31, and obtain the first comparison result of the corresponding storage cell, and a total of the first comparison results of the P storage cells in the storage body corresponding to the judgment unit 31 are obtained.

[0105] In the above embodiment, the judgment unit 31 includes P XOR gates 311, which correspond to P-bit target read data and P-bit target write data respectively. The two input ends of each XOR gate 311 are respectively used to receive a bit of target read data read from a corresponding storage unit and a bit of target write data written thereto, and the output end is used to output the first comparison result of the corresponding storage unit. Each judgment unit 31 can read a bit of target read data in each storage unit corresponding to the internal test address from a corresponding storage body and compare it with the corresponding bit of target read data written thereto, thereby generating and outputting P first comparison results corresponding to the P storage units respectively.

[0106] Figure 4 is a schematic structural diagram of a first compression unit according to an embodiment, as shown in Figure 4 As shown, optionally, the first compression unit 32 includes a compression engine 321 and an auxiliary compression circuit 322. The compression engine 321 is connected to the corresponding judgment unit 31, and is used to receive the first comparison result of each storage unit in the corresponding storage body and adopt a compression mode to obtain multi-bit intermediate data. Among them, the multi-bit intermediate data carries information whether there is a data error in the storage body. The auxiliary compression circuit 322 is connected to the compression engine 321, and is used to compress the multi-bit intermediate data into one-bit output data, and use the output data as the second comparison result of the corresponding storage body.

[0107] In actual applications, a test engine for other test circuits is set inside the chip, such as a circuit for testing and repairing fuse units before leaving the factory. Based on the need for repair, this test engine will use 32 bits as a group of repaired units, so it is necessary to split 128 bits into 4 groups for separate compression, and determine a group of units where errors occur based on the compression results to make corresponding modifications. In the above embodiment, the first compression unit 32 includes a compression engine 321 and an auxiliary compression circuit 322. The compression engine 321 first receives P first comparison results of P storage units in the corresponding storage body and adopts a compression mode to obtain multi-bit intermediate data. The auxiliary compression circuit 322 then compresses the multi-bit intermediate data into one-bit output data, and uses the output data as the second comparison result of the corresponding storage body. In this way, the compression engines of other test circuits can be reused to reduce the overall occupied space and implementation cost of the chip.

[0108] Exemplarily, the auxiliary compression circuit 322 includes at least one compression combination, each compression combination is used to compress 4-bit data into 1-bit data.

[0109] For example, the compression engine 321 outputs 16-bit intermediate data, and each 4-bit intermediate data corresponds to a compression combination. In this case, the auxiliary compression circuit 322 includes four compression combinations, and each compression combination compresses 4-bit data into 1-bit data. Finally, the outputs of the four compression combinations are logically ORed to obtain the second comparison result of the storage bank corresponding to the first compression unit 32.

[0110] Figure 5 FIG. 1 is a schematic diagram of the structure of an auxiliary compression circuit according to an embodiment of the present invention. Figure 5 As shown, exemplarily, when the compression engine 321 outputs four-bit intermediate data, the auxiliary compression circuit 322 includes two first NOR gates 3221 and a first NAND gate 3222. Each input end of the two first NOR gates 3221 is connected to the compression engine 321 respectively, and the two first NOR gates 3221 are used to receive the corresponding one-bit intermediate data. The two input ends of the first NAND gate 3222 are connected one-to-one with the output ends of the two first NOR gates 3221, and the output end of the first NAND gate 3222 is used to output one-bit output data.

[0111] In the above embodiment, when the compression engine 321 outputs four-bit intermediate data, the auxiliary compression circuit 322 includes two first NOR gates 3221 and a first NAND gate 3222, which can compress the multi-bit intermediate data into one-bit output data and use the output data as the second comparison result of the corresponding storage body.

[0112] For details, please refer to Figure 3 ,if Figure 3If the first comparison result outputted from the output terminal of the XOR gate 311 is a high level indicating data "1", it indicates that a data error exists in the storage unit corresponding to the XOR gate 311; Figure 5 , the P first comparison results corresponding to the P storage units output by the P XOR gates 311 corresponding to a storage body are input to the compression engine 321. When the first comparison result output by any XOR gate 311 is "1", the corresponding 1-bit intermediate data in the 4-bit intermediate data output by the compression engine 321 is output as "1". After the logic operation of the auxiliary compression circuit 322 (two NOR gates 3221 and one NAND gate 3222), the corresponding output second comparison result is also a high level "1", indicating that the corresponding storage body has a data error; conversely, if the P first comparison results are all "0", the 4-bit intermediate data output by the compression engine 321 are also all "0". After the logic operation of the auxiliary compression circuit 322, the corresponding output second comparison result is a low level "0", indicating that the corresponding storage body does not have a data error.

[0113] Figure 6 FIG. 1 is a schematic diagram of the structure of the second compression unit of an embodiment, Figure 6 As shown, optionally, the second compression unit 33 includes M block compression circuits 331, a collection compression circuit 332 and an output unit 333. The M block compression circuits 331 correspond to the M storage body groups one by one, and each block compression circuit 331 is connected to the first compression unit 32 corresponding to each storage body in the corresponding storage body group. Each block compression circuit 331 is used to obtain the second comparison result of each storage body in the corresponding storage body group and perform compression and logical operations, generate and output the third comparison result and storage body selection flag of the corresponding storage body group. Among them, the storage body selection flag is used to indicate the storage body with data errors in the corresponding storage body group, and the third comparison result indicates whether there is a data error in the corresponding storage body group. The collection compression circuit 332 is connected to the M block compression circuits 331 respectively, and is used to obtain the third comparison result of each storage body group and perform compression and logical operations, generate and output the fault flag and the storage body group selection flag. Among them, the storage body group selection flag is used to indicate the storage body group with data errors. The output unit 333 is connected to the block compression circuit 331 and the set compression circuit 332 respectively, and is used to determine the storage body flag according to the storage body selection flag and the storage body group selection flag.

[0114] In the above embodiment, the second compression unit 33 includes M block compression circuits 331, a collection compression circuit 332 and an output unit 333. Each block compression circuit 331 first obtains the second comparison result of each storage body in the corresponding storage body group and performs compression and logic operation, generates and outputs the third comparison result and storage body selection flag of the corresponding storage body group, and the collection compression circuit 332 then obtains the third comparison result of each storage body group and performs compression and logic operation, generates and outputs the fault flag and the storage body group selection flag, and the output unit 333 finally determines the storage body flag according to the storage body selection flag and the storage body group selection flag. By performing multi-level compression on the second comparison result of each storage body, the amount of data is reduced, and the storage body with data errors can be locked (the storage body flag can be used to determine which storage body in which storage body group has data errors), and a storage unit row or a storage unit column with data errors is determined in combination with the internal test address for repair.

[0115] Figure 7 FIG. 1 is a schematic diagram of a block compression circuit according to an embodiment of the present invention. Figure 7 As shown, optionally, the block compression circuit 331 includes a storage bank selection flag generation circuit 3311 and a block fault compression circuit 3312. The storage bank selection flag generation circuit 3311 is used to obtain the second comparison result of each storage bank in the corresponding storage bank group, and when at least one storage bank in the corresponding storage bank group has a data error, select one of the storage banks with data errors in a preset order to generate a storage bank selection flag. The block fault compression circuit 3312 is used to obtain the second comparison result of each storage bank in the corresponding storage bank group, and generate a third comparison result of the corresponding storage bank group according to the second comparison results of each storage bank in the corresponding storage bank group.

[0116] In the above embodiment, the block compression circuit 331 includes a memory bank selection flag generation circuit 3311 and a block fault compression circuit 3312. The memory bank selection flag generation circuit 3311 obtains the second comparison result of each memory bank in the corresponding memory bank group, and when at least one memory bank in the corresponding memory bank group has a data error, selects one of the memory banks with data errors in a preset order to generate a memory bank selection flag. The block fault compression circuit 3312 generates a third comparison result of the corresponding memory bank group according to the second comparison results of each memory bank in the corresponding memory bank group to indicate whether there is a data error in the corresponding memory bank group. Through the coordination of the memory bank selection flag and the third comparison result, it can be known whether there is a data error in the corresponding memory bank group, and when at least one memory bank in the memory bank group has a data error, a memory bank in the memory bank group with a data error is determined to be repaired.

[0117] Optionally, when there are no data errors in N storage banks in the corresponding storage bank group, the storage bank selection mark indicates a storage bank that is located at the front or the back of a preset sequence in the corresponding storage bank group.

[0118] Since the third comparison result indicates whether there is a data error in the corresponding memory bank group, the memory bank selection flag indicates a memory bank without data errors in the corresponding memory bank group, and the memory bank without data errors will not be repaired.

[0119] Figure 8 FIG. 1 is a schematic diagram of a memory bank selection flag generating circuit in a built-in self-test circuit according to an embodiment of the present invention. Figure 8 As shown, exemplarily, when N=4, each memory bank group includes a first memory bank, a second memory bank, a third memory bank and a fourth memory bank. The memory bank selection flag generation circuit 3311 includes a first NOT gate 33111, a second NOT gate 33112, a second NAND gate 33113, a third NAND gate 33114 and a fourth NAND gate 33115. The input end of the first NOT gate 33111 is used to receive the second comparison result of the first memory bank. The input end of the second NOT gate 33112 is used to receive the second comparison result of the second memory bank. The two input ends of the second NAND gate 33113 are respectively connected to the output end of the first NOT gate 33111 and the output end of the second NOT gate 33112. The first input end of the third NAND gate 33114 is used to receive the second comparison result of the third memory bank, and the second input end of the third NAND gate 33114 is connected to the output end of the first NOT gate 33111. Two input terminals of the fourth NAND gate 33115 are respectively connected to the output terminals of the first NAND gate 33111 and the third NAND gate 33114. The output terminals of the fourth NAND gate 33115 and the second NAND gate 33113 are used to output the bank selection flag Bank<1:0>.

[0120] When the second comparison result of the first storage bank indicates that there is a data error in the first storage bank, the input end of the first NOT gate 33111 receives a high level signal indicating "1", and the output end of the first NOT gate 33111 outputs a low level signal indicating "0". At this time, regardless of whether the second comparison result of the second storage bank, the second comparison result of the third storage bank, and the second comparison result of the fourth storage bank are high level signals or low level signals (i.e., whether there is a data error in the second storage bank, the third storage bank, and the fourth storage bank), the output end of the second NAND gate 33113 and the output end of the fourth NAND gate 33115 both output a high level signal indicating "1", Bank <1> and Bank <0> All are 1, and the bank selection flag Bank<1:0> is 11, indicating that the data error in the first bank in the corresponding bank group is to be repaired. It can be seen from this that when there is a data error in the first bank, regardless of whether there are data errors in other banks in the same bank group, the bank selection flag Bank<1:0>=11 indicating the first bank is output, so that the first bank in the same bank group can be repaired first according to the bank selection flag Bank<1:0>=11, that is, the preset order (repair order) of the first bank is higher than that of the other three banks.

[0121] When the second comparison result of the first memory bank indicates that there is no data error in the first memory bank, the input end of the first NOT gate 33111 receives a low level signal indicating "0", and the output end of the first NOT gate 33111 outputs a high level signal indicating "1". At this time, the output of the second NAND gate 33113 and the output of the fourth NAND gate 33115 are both determined by the input value of the other input end. If the second comparison result of the second memory bank indicates that there is a data error in the second memory bank, the input end of the second NOT gate 33112 receives a high level signal indicating "1", and the output end of the second NOT gate 33112 outputs a low level signal indicating "0"; the two input ends of the second NAND gate 33113 receive a high level signal indicating "1" and a low level signal indicating "0" respectively, and the output end of the second NAND gate 33113 outputs a high level signal indicating "1";

[0122] The second input end of the third NAND gate 33114 is connected to the output end of the second NOT gate 33112, and receives a low level signal indicating "0". At this time, no matter whether the second comparison result of the third storage bank and the second comparison result of the fourth storage bank are high level signals or low level signals (i.e., whether there are data errors in the third storage bank and the fourth storage bank), the output end of the third NAND gate 33114 outputs a high level signal indicating "1", and the two input ends of the fourth NAND gate 33115 receive the high level signal indicating "1" and the high level signal indicating "1" respectively, and the output end of the fourth NAND gate 33115 outputs a low level signal indicating "0". Bank <1> and Bank <0> 1 and 0 respectively, and the bank selection flag Bank<1:0> is 10, indicating that the data error in the second bank in the corresponding bank group is to be repaired. It can be seen from this that when there is no data error in the first bank and there is a data error in the second bank, regardless of whether there is a data error in the third bank and the fourth bank in the same bank group, the bank selection flag Bank<1:0>=10 indicating the second bank is output, so that according to the bank selection flag Bank<1:0>=10, when the first bank does not need to be repaired, the second bank in the same bank group is repaired first, that is, the preset order (repair order) of the second bank is higher than that of the other two banks.

[0123] When the second comparison result of the first memory bank indicates that there is no data error in the first memory bank and the second comparison result of the second memory bank indicates that there is no data error in the second memory bank, the input end of the first NOT gate 33111 and the input end of the second NOT gate 33112 both receive a low level signal indicating "0", and the output end of the first NOT gate 33111 and the output end of the second NOT gate 33112 both output a high level signal indicating "1". At this time, the output end of the second NAND gate 33113 outputs a low level signal indicating "0", that is, Bank <1> is 0, and the output of the fourth NAND gate 33115 is determined by the input value of another input terminal (the output of the third NAND gate 33114), the second input terminal of the third NAND gate 33114 is connected to the output terminal of the second NAND gate 33112, and receives a high-level signal indicating "1". At this time, the output of the third NAND gate 33114 is determined by the input value of the first input terminal, that is, determined by the second comparison result of the third storage bank. At this time, if the first comparison result of the third storage bank indicates that there is a data error in the third storage bank, the first input terminal of the third NAND gate 33114 receives a high-level signal indicating "1", and the third NAND gate 33114 outputs a low-level signal indicating "0", and the two input terminals of the fourth NAND gate 33115 respectively receive a high-level signal indicating "1" and a low-level signal indicating "0", and the output terminal of the fourth NAND gate 33115 outputs a high-level signal indicating "1", Bank <0> =1, the bank selection flag Bank<1:0> is 01, indicating that the data error in the third bank in the corresponding bank group is to be repaired. It can be seen that when there is no data error in the first bank and the second bank and there is a data error in the third bank, no matter whether there is a data error in the fourth bank in the same bank group, the bank selection flag Bank<1:0>=01 indicating the third bank is output, so that according to the bank selection flag Bank<1:0>=01, when neither the first bank nor the second bank needs to be repaired, the third bank in the same bank group is repaired first, that is, the preset order (repair order) of the third bank is higher than that of the fourth bank.

[0124] When the second comparison result of the first memory bank, the second comparison result of the second memory bank and the second comparison result of the third memory bank respectively indicate that there is no data error in the first memory bank, the second memory bank and the third memory bank, the input end of the first NOT gate 33111 and the input end of the second NOT gate 33112 both receive a low level signal indicating "0", the first input end of the third NAND gate 33114 receives a low level signal indicating "0", the output end of the first NOT gate 33111 and the output end of the second NOT gate 33112 both output a high level signal indicating "1", the output end of the third NAND gate 33114 outputs a high level signal indicating "1", at this time, the output end of the second NAND gate 33113 and the output end of the fourth NAND gate 33115 both output a low level signal indicating "0", that is, Bank 1 is <1> and Bank <0> All are 0, and the bank selection flag Bank<1:0> is 00, indicating that the data error in the fourth bank in the corresponding bank group is to be repaired. It can be seen from this that when there is no data error in the first bank, the second bank, and the third bank, regardless of whether there is a data error in the fourth bank in the same bank group, the bank selection flag Bank<1:0>=00 indicating the fourth bank is output, so that according to the bank selection flag Bank<1:0>=00, when no other banks need to be repaired, the fourth bank in the same bank group is repaired, that is, the repair order of the fourth bank is the lowest, and when there is no data error in all banks (that is, when the second comparison results corresponding to several banks are all low-level signals), the bank selection flag Bank<1:0>=00 indicates by default that the last bank (the fourth bank) in the preset order is to be repaired.

[0125] In the above embodiment, when N=4, the storage body selection flag generating circuit 3311 includes a first NOT gate 33111, a second NOT gate 33112, a second NAND gate 33113, a third NAND gate 33114 and a fourth NAND gate 33115, which can be used to select one of the storage bodies with data errors in a preset order when there is a data error in at least one storage body in the corresponding storage body group.

[0126] Fig. 9 FIG. 1 is a schematic diagram of a block fault compression circuit in a built-in self-test circuit according to an embodiment of the present invention. Fig. 9As shown, exemplarily, the block fault compression circuit 3312 includes two second NOR gates 33121, a fifth NAND gate 33122 and a third NAND gate 33123. The input ends of the two second NOR gates 33121 are respectively used to receive the second comparison result of a corresponding memory bank. The input end of the fifth NAND gate 33122 is respectively connected to the output ends of the two second NOR gates 33121. The input end of the third NAND gate 33123 is connected to the output end of the fifth NAND gate 33122, and the output end of the third NAND gate 33123 is used to output the third comparison result of the memory bank group.

[0127] In the above embodiment, the block fault compression circuit 3312 includes two second NOR gates 33121, a fifth NAND gate 33122 and a third NAND gate 33123, which can generate a third comparison result of the corresponding storage body group according to the second comparison results of each storage body in the corresponding storage body group to indicate whether there is a data error in the corresponding storage body group.

[0128] Fig.10 FIG. 1 is a schematic diagram of the structure of a collective compression circuit in a built-in self-test circuit according to an embodiment of the present invention. Fig.10 As shown, optionally, the aggregate compression circuit 332 includes a memory bank group selection flag generation circuit 3321 and a aggregate fault compression circuit 3322. The memory bank group selection flag generation circuit 3321 is used to obtain the third comparison result of each memory bank group, and when there is a data error in at least one memory bank group, select one of the memory bank groups with data errors according to a preset order to generate a memory bank group selection flag. The aggregate fault compression circuit 3322 is used to obtain the third comparison result of each memory bank group, and generate a fault flag according to the third comparison result of each memory bank group.

[0129] In the above embodiment, the set compression circuit 332 includes a storage body group selection flag generation circuit 3321 and a set fault compression circuit 3322. When there is a data error in at least one storage body group, the storage body group selection flag generation circuit 3321 selects one of the storage body groups with data errors in accordance with a preset order, and generates a storage body group selection flag to indicate which storage body group among the M storage body groups has a data error. The set fault compression circuit 3322 generates a fault flag based on the third comparison result of each storage body group to indicate whether there is a data error in the storage data currently read. By cooperating with the storage body group selection flag and the fault flag, it can be known whether there is a data error in all the storage data currently read from the storage array, and when there is a data error in at least one storage body group, a storage body group with a data error in the storage array 10 is determined to be repaired.

[0130] Optionally, when there are no data errors in the M memory bank groups, the memory bank group selection flag indicates a memory bank group that is located at the front or the back of the preset sequence.

[0131] Since the fault flag indicates whether there is a data error in the currently read storage data, when there is no storage bank with data error in the storage array 10, the storage bank without data error will not be repaired.

[0132] As an example, when M=8, the M memory bank groups include: a first memory bank group, a second memory bank group, a third memory bank group, a fourth memory bank group, a fifth memory bank group, a sixth memory bank group, a seventh memory bank group, and an eighth memory bank group. The memory bank group selection flag includes: a first memory bank selection flag, a second memory bank selection flag, and a third memory bank selection flag.

[0133] Fig.11 FIG. 1 is a schematic diagram of a memory bank selection flag generating circuit in a built-in self-test circuit according to an embodiment of the present invention. Fig.11As shown, illustratively, the memory bank group selection flag generating circuit 3321 includes: a fourth NOT gate 33211a, a fifth NOT gate 33211b, a sixth NOT gate 33211c, a seventh NOT gate 33211d, an eighth NOT gate 33211e, a ninth NOT gate 33211f, a tenth NOT gate 33211g, an eleventh NOT gate 33211h, a sixth NAND gate 33212a, a seventh NAND gate 33212b, an eighth NAND gate 33212c, a ninth NAND gate 33212d, a tenth NAND gate 33212e, an eleventh NAND gate 33212f, a twelfth NAND gate 33212g, a thirteenth NAND gate 33212h, a fourteenth NAND gate 33212i, a fifteenth NAND gate 33212j, a third NOR gate 33212a, a seventh NAND gate 33212b, an eighth NAND gate 33212c, a ninth NAND gate 33212d, a tenth NAND gate 33212e, an eleventh NAND gate 33212f, a twelfth NAND gate 33212g, a thirteenth NAND gate 33212h, a fourteenth NAND gate 33212i, a fifteenth NAND gate 33212j, and a third NOR gate 33212 The fourth NOT gate 33211a is used to receive the third comparison result of the third memory bank group; the fifth NOT gate 33211b is used to receive the third comparison result of the fourth memory bank group; the sixth NOT gate 33211c is used to receive the third comparison result of the fifth memory bank group; the seventh NOT gate 33211d is used to receive the third comparison result of the sixth memory bank group; the eighth NOT gate 33211e is used to receive the third comparison result of the seventh memory bank group; the ninth NOT gate 33211f is used to receive the third comparison result of the seventh memory bank group; the ... ninth NOT gate 33211f is used to receive the third comparison result of the seventh memory bank group; the fifth NOT gate 33211c is used to receive the third comparison result of the fifth memory bank group; the seventh NOT gate 33211d is used to receive the third comparison result of the sixth memory bank group; the eighth NOT gate 33211e is used to receive the third comparison result of the seventh memory bank group; the ninth NOT gate 33211f is used to receive the third comparison result of the seventh memory bank group; the fifth NOT gate 33211b is used to receive the third comparison result of the fourth memory bank group; the sixth NOT gate 33211c is used to receive the third comparison result of the fifth memory bank group; the seventh NOT gate 33211d is used to receive the third The third comparison result of the eighth memory bank group; the first input end of the sixth NAND gate 33212a is connected to the output end of the fourth NAND gate 33211a, and the second input end of the sixth NAND gate 33212a is used to receive the third comparison result of the second memory bank group; the first input end of the seventh NAND gate 33212b is connected to the output end of the sixth NAND gate, and the second input end of the seventh NAND gate 33212b is connected to the output end of the fifth NAND gate 33211b; the first input end of the eighth NAND gate 33212c is connected to the output end of the seventh NAND gate, and the second input end of the eighth NAND gate 33212c is connected to the output end of the sixth NAND gate; the ninth NAND gate 33 The first input terminal of the NAND gate 33212d is connected to the output terminal of the eighth NAND gate, and the second input terminal of the ninth NAND gate 33212d is connected to the output terminal of the seventh NAND gate; the first input terminal of the tenth NAND gate 33212e is connected to the output terminal of the ninth NAND gate 33212d, and the second input terminal of the tenth NAND gate 33212e is connected to the output terminal of the eighth NAND gate; the first input terminal of the eleventh NAND gate 33212f is connected to the output terminal of the tenth NAND gate 33212e, and the second input terminal of the eleventh NAND gate 33212f is connected to the output terminal of the ninth NAND gate, and the output terminal of the eleventh NAND gate 33212f is used to generate a first memory bank group selection flag BG <0> ;The first input end of the third NOR gate 33213a is used to receive the third comparison result of the fifth memory bank group, and the second input end of the third NOR gate 33213a is used to receive the third comparison result of the sixth memory bank group; the input end of the tenth NOR gate 33211g is used to receive the third comparison result of the third memory bank group; the input end of the eleventh NOR gate 33211h is used to receive the third comparison result of the fourth memory bank group; the first input end of the sixth NOR gate 33213d is used to receive the third comparison result of the seventh memory bank group, and the second input end of the sixth NOR gate 33213d is used to receive the third comparison result of the eighth memory bank group; the first input end of the twelfth NAND gate 33212g is connected to the tenth NOR gate 33 211g is connected to the output end of the first NAND gate 33212g, the second input end of the twelfth NAND gate 33212g is connected to the output end of the eleventh NAND gate 33211h; the first input end of the thirteenth NAND gate 33212h is connected to the output end of the third NOR gate 33213a, the second input end of the thirteenth NAND gate 33212h is connected to the output end of the twelfth NAND gate 33212g; the first input end of the fourteenth NAND gate 33212i is connected to the output end of the thirteenth NAND gate 33212h, the second input end of the fourteenth NAND gate 33212i is connected to the output end of the sixth NOR gate 33213d, and the output end of the fourteenth NAND gate 33212i is used to generate a second memory bank group selection flag BG <1> ;

[0134] The first input end of the fourth NOR gate 33213b is used to receive the third comparison result of the fifth memory bank group, and the second input end of the fourth NOR gate 33213b is used to receive the third comparison result of the sixth memory bank group; the first input end of the fifth NOR gate 33213c is used to receive the third comparison result of the seventh memory bank group, and the second input end of the fifth NOR gate 33213c is used to receive the third comparison result of the eighth memory bank group; the first input end of the fifteenth NAND gate 33212j is connected to the output end of the fourth NOR gate 33213b, the second input end of the fifteenth NAND gate 33212j is connected to the output end of the fifth NOR gate 33213c, and the output end of the fifteenth NAND gate 33212j is used to generate a third memory bank group selection flag BG <2> .

[0135] Fig.12 FIG. 1 is a schematic diagram of a structure of a collective fault compression circuit in a built-in self-test circuit according to an embodiment of the present invention. Fig.12As shown, exemplarily, the collective fault compression circuit 3322 includes: a seventh NOR gate 33213e, an eighth NOR gate 33213f, a ninth NOR gate 33213g, a tenth NOR gate 33213h, an eleventh NOR gate 33213i, a sixteenth NAND gate 33212k and a seventeenth NAND gate 33212l; the first input end of the seventh NOR gate 33213e is used to receive the third comparison result of the first memory bank group, and the second input end of the seventh NOR gate 33213e is used to receive the second memory bank group. the third comparison result of the group; the first input end of the eighth NOR gate 33213f is used to receive the third comparison result of the third memory bank group, and the second input end of the eighth NOR gate 33213f is used to receive the third comparison result of the fourth memory bank group; the first input end of the ninth NOR gate 33213g is used to receive the third comparison result of the fifth memory bank group, and the second input end of the ninth NOR gate 33213g is used to receive the third comparison result of the sixth memory bank group; the first input end of the tenth NOR gate 33213h is used to receive the third comparison result of the seventh memory bank group, and the second input end of the tenth NOR gate 33213h is used to receive the third comparison result of the eighth memory bank group; the first input end of the sixteenth NAND gate 33212k is connected to the output end of the seventh NOR gate 33213e, and the second input end of the sixteenth NAND gate 33212k is connected to the output end of the eighth NOR gate 33213f; the first input end of the seventeenth NAND gate 33212l is connected to the ninth NOR gate 33 213g is connected, the second input terminal of the seventeenth NAND gate 33212l is connected to the output terminal of the tenth NOR gate 33213h; the first input terminal of the eleventh NOR gate 33213i is connected to the output terminal of the sixteenth NAND gate 33212k, the second input terminal of the eleventh NOR gate 33213i is connected to the output terminal of the seventeenth NAND gate 33212l, and the output terminal of the eleventh NOR gate 33213i is used to generate the fault flag FAIL_BG_EN.

[0136] Fig.13 FIG. 1 is a schematic diagram of the structure of a built-in self-test circuit according to another embodiment of the present invention. Fig.13 As shown, exemplarily, the repair module is also used to receive a storage body flag (for example: BG<2:0> and Bank<1:0>), latch the storage body flag when the fault flag indicates that there is a data error in the storage data currently being read, and repair the storage cell corresponding to the error address in the storage body indicated by the storage body flag (for example: BG<2:0> is 111, Bank<1:0> is 10, indicating the second storage body in the first storage body group) after exiting the self-test mode.

[0137] Fig.14FIG. 1 is a schematic diagram of a command / address generation module in a built-in self-test circuit according to an embodiment of the present invention. Fig.14 As shown, in one embodiment, the command / address generation module 20 includes a clock generation unit 21, a command generation unit 22 and an address generation unit 23. The clock generation unit 21 is used to receive a self-test enable signal, and to generate and output a clock signal when the self-test enable signal is at a valid level. The command generation unit 22 is connected to the clock generation unit 21, and is used to sequentially generate an activation command, a write command / read command and a precharge command that meet the read / write operation timing requirements according to the clock signal. The internal test address includes an internal test row address and an internal test column address; the address generation unit 23 is respectively connected to the clock generation unit 21 and the address generation unit 22, and is used to generate an internal test row address according to the activation command and the clock signal, and to generate an internal test column address according to the write command / read command and the clock signal.

[0138] In the above embodiment, the command / address generation module 20 includes a clock generation unit 21, a command generation unit 22 and an address generation unit 23. The clock generation unit 21 first generates and outputs a clock signal when the self-test enable signal is at a valid level. The command generation unit 22 then generates an activation command, a write command / read command and a precharge command that meet the read / write operation timing requirements in sequence according to the clock signal. The address generation unit 23 finally generates an internal test row address according to the activation command and the clock signal, and generates an internal test column address according to the write command / read command and the clock signal, thereby achieving the generation and sending of internal test commands and internal test addresses (including internal test row addresses and internal test column addresses) according to a preset test mode after entering the self-test mode.

[0139] Optionally, the command generation unit 22 is also used to receive a test mode signal; when the test mode signal is at a first level, it indicates that the preset test mode is a row priority test mode, and generates an internal test command according to a row priority addressing method; when the test mode signal is at a second level, it indicates that the preset test mode is a column priority test mode, and generates an internal test command according to a column priority addressing method.

[0140] The address generation unit 23 is also used to receive a test mode signal; when the test mode signal is at a first level, it indicates that the preset test mode is a row priority test mode, and generates an internal test address according to a row priority addressing method; when the test mode signal is at a second level, it indicates that the preset test mode is a column priority test mode, and generates an internal test address according to a column priority addressing method.

[0141] In the row priority test mode, the internal test commands generated by the command generation unit 22 are as follows: the activation command, write command / read command and precharge command of the first row and the first column, the activation command, write command / read command and precharge command of the second row and the first column, and the activation command, write command / read command and precharge command of the third row and the first column. In the row priority test mode, the time required to test the entire memory chip is shown in Table 1 below.

[0142] Table 1. Row-first test mode

[0143]

[0144] Referring to the contents of Table 1, after entering the test mode (Load test mode), first, determine a column address (i.e., determine a column of the storage array), and test the storage cells corresponding to each row address (each row) in this column in turn (first perform a write data operation), until all the storage cells in this column are tested (see number 2 in Table 1). Secondly, test the next column according to the process of the previous step until all column tests are completed (see number 3 in Table 1). Then, determine a column address (determine a column of the storage array), and test the storage cells corresponding to each row address (each row) in this column in turn (perform a read data operation), until all the storage cells in this column are tested (see number 4 in Table 1). Finally, test the next column according to the process of the previous step until all columns are read.

[0145] In the test sequence corresponding to Table 1, the clock cycle corresponding to a column address in each row of the storage array is: tRCD+tWR+tRP; where tRCD (RAS to CASDelay) is the delay time for the memory row address to be transferred to the column address; tWR (Write Recovery Time) is the write recovery delay, that is, the delay write recovery time from writing data to the precharge command; tRP (Row Precharge Time) is the row address precharge time. Table 1 takes tRCD of 5, tRP of 5, and tWR of 6 as an example. For a row number of 2 16 For a storage array with 64 columns, after the operation of sequence number 2 in Table 1, the storage array 2 can be obtained. 16 The clock cycle corresponding to a column address of a row can be (5+6+5)*2 16 =1048576; all columns are tested according to the operation of sequence number 3 in Table 1, and 2 in the storage array 16 The clock cycle corresponding to the 64 column addresses of a row is 1048576*64=67108864, and the corresponding time consumed is 335.54432ms; after the operation of sequence number 4 in Table 1, the 2 16The clock cycle corresponding to a column address of a row can be (5+6+5)*216=1048576; all column tests are completed according to the operation of sequence number 5 in Table 1, and the clock cycle corresponding to the 64 column addresses of 216 rows in the storage array is 1048576*64=67108864, and the corresponding time consumed is 335.54432ms.

[0146] In the column priority test mode, the internal test commands generated by the command generation unit 22 are as follows: the activation command, write command / read command and precharge command of the first row, the activation command, write command / read command and precharge command of the second row, and the activation command, write command / read command and precharge command of the third row. In the column priority test mode, the time required to test the entire memory chip is shown in Table 2 below.

[0147] Table 2. Column-first test mode

[0148]

[0149] Referring to the contents of Table 2, after entering the test mode (Load test mode), first, determine a row address (determine a row of the storage array), and test the storage cells corresponding to each column address (each column) in this row in turn (first perform the write data operation), until all the storage cells in this row are tested (see sequence number 2 in Table 2). Secondly, test the next row according to the process of the previous step until all rows are written (see sequence number 3 in Table 2). Thirdly, determine a row address (determine a row of the storage array), and test the storage cells corresponding to each column address (each column) in this row in turn (perform the read data operation), until all the storage cells in this row are tested (see sequence number 4 in Table 2). Then, test the next row according to the process of the previous step until all rows are read (see sequence number 5 in Table 2). Finally, repeat all the above steps to complete the reading of all rows in another storage unit (see sequence number 6 in Table 2).

[0150] Under the test sequence corresponding to Table 2, in the storage array, the clock cycle corresponding to the reading of consecutive column addresses in each row is: tRCD+tCCD*number of columns+tWR+tRP; among them, tRCD (RAS to CASDelay) is the delay time for the memory row address to be transmitted to the column address; tCCD is an important event of DRAM architecture and bandwidth, which is the delay time for the transmission between adjacent memory column addresses; tWR (Write Recovery Time) is the write recovery delay, that is, the delay write recovery time from writing data to the precharge command; tRP (Row Precharge Time) is the row address precharge time.

[0151] Table 2 takes tRCD of 5, tRP of 5, tWR of 6, and tCCD of 4 as an example. 15 For a storage array with 63 columns, after the operation of sequence number 2 in Table 2, it can be obtained that the clock cycle corresponding to all column addresses corresponding to each row in the storage array can be 5+4*63+6+5=268, and the corresponding consumption time is 0.0013ms; after the operation of sequence number 3 in Table 2, all rows are written, and 2 in the storage array are 15 The clock cycle corresponding to the 63 column addresses of a row is 267*2 15 =8781824, the corresponding time consumed is 43.75ms; after the operation of No. 4 in Table 2, it can be obtained that the clock cycle corresponding to all column addresses corresponding to each row in the storage array is 5+4*63+6+5=268; after the operation of No. 5 in Table 2, all rows are read, and 2 in the storage array 15 The clock cycle corresponding to the 63 column addresses of a row is 268*215=8781824, and the corresponding time consumed is 43.75. The operation of No. 6 in Table 2: repeat all the above steps to complete the reading of all rows of another storage unit, and the time consumed is about 87.50ms.

[0152] Exemplarily, the command generation unit 22 and the address generation unit 23 are both used to receive a self-test enable signal, and are in a working state when the self-test enable signal is at a valid level, and are in a non-working state when the self-test enable signal is at an invalid level.

[0153] Fig.15 FIG. 4 is a schematic diagram of a built-in self-test circuit according to another embodiment of the present invention. Fig.15 As shown, in one embodiment, the repair module 40 is connected to the processing module 30 for receiving a fault flag. The repair module 40 is also connected to the address generation unit 23 for receiving an internal test row address or an internal test column address, and when the fault flag indicates that there is a data error in the storage data currently being read, the internal test row address or the internal test column address corresponding to the storage data currently being read is latched as an error address, and the storage cell row or storage cell column corresponding to the error address is repaired after the self-test mode is exited.

[0154] Fig.16 FIG. 4 is a schematic diagram of a built-in self-test circuit according to another embodiment of the present invention. Fig.16 As shown, in one embodiment, the built-in self-test circuit further includes an alarm module 50. The alarm module 50 is used to generate a test alarm signal according to the self-test enable signal, and send the test alarm signal to the memory controller.

[0155] In one embodiment, the self-test enable signal switches to a valid level when the memory array enters a self-test mode defined by a protocol or a setting mode.

[0156] Based on the same inventive concept, a memory is also provided, the memory comprising a built-in self-test circuit as provided in any of the above embodiments.

[0157] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0158] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0159] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A built-in self-test circuit, characterized in that: The built-in self-test circuit comprises: Storage arrays; A command / address generation module, used to generate and send internal test commands and internal test addresses according to a preset test mode after entering the self-test mode; a processing module, connected to the command / address generation module and the storage array respectively, for receiving the internal test command and the internal test address; writing preset data to the storage unit corresponding to the internal test address in the storage array according to the preset test mode according to the internal test command, and reading storage data from the storage unit corresponding to the internal test address in the storage array; and generating and outputting a fault flag according to a comparison result of the storage data read each time with the corresponding preset data written; the fault flag indicates whether there is a data error in the storage data currently read; A repair module is connected to the command / address generation module and the processing module respectively, and is used to latch the internal test address corresponding to the storage data currently read as an error address according to the fault flag, and repair the storage unit corresponding to the error address after exiting the self-test mode.

2. The built-in self-test circuit according to claim 1, characterized in that: The storage array includes M storage body groups, each of which includes N storage bodies, where M and N are both positive integers; the preset data includes M*N preset sub-data, which correspond to the M*N storage bodies one by one, and each preset sub-data includes P-bit target write data; the storage data includes M*N storage sub-data, which correspond to the M*N storage bodies one by one, and each storage sub-data includes P-bit target read data, where P is a positive integer; the processing module includes: M*N judgment units are connected to the storage bodies in the storage array in a one-to-one correspondence, and each of the judgment units is used to read a corresponding storage sub-data from the P storage cells corresponding to the internal test address in the corresponding storage body, and compare the P-bit target read data in the storage sub-data with the P-bit target write data in the corresponding preset sub-data bit by bit, and respectively generate and output P first comparison results corresponding to the P storage cells; wherein, if the target read data and the target write data are the same, the output first comparison result indicates that there is no data error in the corresponding storage cell; otherwise, if the target read data and the target write data are different, the output first comparison result indicates that there is a data error in the corresponding storage cell; M*N first compression units are connected to the M*N judgment units in a one-to-one correspondence; each of the first compression units is used to obtain P first comparison results of P storage units in the corresponding storage body and perform compression processing to obtain a second comparison result of the corresponding storage body, wherein the second comparison result indicates whether there is a data error in the corresponding storage body; The second compression unit is connected to the M*N first compression units respectively, and is used to obtain and compress the second comparison results corresponding to the M*N storage bodies, generate and output the fault flag and storage body flag, and the storage body flag is used to indicate the storage body with data errors.

3. The built-in self-test circuit according to claim 2, characterized in that: The judging unit comprises: P XOR gates correspond one-to-one to the P bits of the target read data in the corresponding storage sub-data and the P bits of the target write data in the corresponding preset sub-data, and the two input ends of each XOR gate are respectively used to receive one bit of the target read data read from a corresponding storage unit and one bit of the target write data written thereto, and the output end is used to output the first comparison result of the corresponding storage unit.

4. The built-in self-test circuit according to claim 2, characterized in that: The first compression unit comprises: A compression engine, connected to the corresponding judgment unit, for receiving the first comparison result of each storage unit in the corresponding storage body and adopting a compression mode to obtain multi-bit intermediate data, wherein the multi-bit intermediate data carries information on whether there is a data error in the storage body; The auxiliary compression circuit is connected to the compression engine and is used for compressing the multi-bit intermediate data into one-bit output data, and using the output data as the second comparison result of the corresponding storage body.

5. The built-in self-test circuit according to claim 4, characterized in that: When the compression engine outputs four-bit intermediate data, the auxiliary compression circuit includes: Two first NOR gates, each input end of which is connected to the compression engine respectively, for receiving corresponding one-bit intermediate data; The first NAND gate has two input terminals connected one by one with the output terminals of the two first NOR gates, and an output terminal used for outputting one-bit output data.

6. The built-in self-test circuit according to claim 2, characterized in that: The second compression unit comprises: M block compression circuits, corresponding to the M memory bank groups one by one, each of the block compression circuits being connected to the first compression unit corresponding to each memory bank in the corresponding memory bank group; each of the block compression circuits being used to obtain the second comparison result of each memory bank in the corresponding memory bank group and perform compression and logic operation, and generate and output the third comparison result and memory bank selection flag of the corresponding memory bank group, the memory bank selection flag being used to indicate the memory bank with data errors in the corresponding memory bank group, and the third comparison result indicating whether there are data errors in the corresponding memory bank group; a set compression circuit, connected to the M block compression circuits respectively, for obtaining the third comparison results of the M memory bank groups and performing compression and logic operations, generating and outputting the fault flag and the memory bank group selection flag, wherein the memory bank group selection flag is used to indicate the memory bank group with data errors; The output unit is connected to the block compression circuit and the set compression circuit respectively, and is used to determine the storage body flag according to the storage body selection flag and the storage body group selection flag.

7. The built-in self-test circuit according to claim 6, characterized in that: The block compression circuit comprises: a memory bank selection flag generating circuit, configured to obtain a second comparison result of each memory bank in the corresponding memory bank group, and when at least one memory bank in the corresponding memory bank group has a data error, select one of the memory banks with the data error in accordance with a preset order, and generate the memory bank selection flag; The block fault compression circuit is used to obtain the second comparison result of each of the storage banks in the corresponding storage bank group, and generate a third comparison result of the corresponding storage bank group according to the second comparison results of each of the storage banks in the corresponding storage bank group.

8. The built-in self-test circuit according to claim 7, characterized in that: When there are no data errors in the N storage bodies in the corresponding storage body group, the storage body selection mark indicates a storage body in the storage body group that is located at the front or the back of the preset order.

9. The built-in self-test circuit according to claim 8, characterized in that: When N=4, each of the memory bank groups includes a first memory bank, a second memory bank, a third memory bank and a fourth memory bank; The memory bank selection flag generation circuit comprises: A first NOT gate, an input end of which is used to receive a second comparison result of the first storage body; A second NOT gate, an input end of which is used to receive a second comparison result of the second storage bank; A second NAND gate, two input terminals of which are respectively connected to the output terminal of the first NAND gate and the output terminal of the second NAND gate; A third NAND gate, wherein the first input terminal is used to receive the second comparison result of the third memory bank, and the second input terminal is connected to the output terminal of the second NAND gate; The fourth NAND gate has two input terminals respectively connected to the output terminal of the first NAND gate and the output terminal of the third NAND gate, and the output terminal of the fourth NAND gate cooperates with the output terminal of the second NAND gate to output the storage body selection flag.

10. The built-in self-test circuit according to claim 9, characterized in that: The block fault compression circuit comprises: Two second NOR gates, whose input ends are respectively used to receive the second comparison result of a corresponding one of the storage banks; a fifth NAND gate, whose input terminals are respectively connected to the output terminals of the two second NOR gates; The third NOT gate has an input end connected to the output end of the fifth NAND gate, and an output end used for outputting the third comparison result of the memory bank group.

11. The built-in self-test circuit according to claim 6, characterized in that: The collective compression circuit comprises: a memory bank group selection flag generating circuit, configured to obtain the third comparison result of each of the memory bank groups, and when at least one of the memory bank groups has a data error, select one of the memory bank groups having the data error in accordance with a preset order, and generate the memory bank group selection flag; The collective fault compression circuit is used to obtain the third comparison result of each of the memory bank groups and generate the fault flag according to the third comparison result of each of the memory bank groups.

12. The built-in self-test circuit according to claim 11, characterized in that: When there are no data errors in the M memory bank groups, the memory bank group selection flag indicates a memory bank group that is located at the front or the back of a preset sequence.

13. The built-in self-test circuit according to claim 12, characterized in that: When M=8, the M memory bank groups include: a first memory bank group, a second memory bank group, a third memory bank group, a fourth memory bank group, a fifth memory bank group, a sixth memory bank group, a seventh memory bank group and an eighth memory bank group; the memory bank group selection flag includes: a first memory bank selection flag, a second memory bank selection flag and a third memory bank selection flag; The memory bank group selection flag generating circuit comprises: a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a tenth NOT gate, an eleventh NOT gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate, a ninth NAND gate, a tenth NAND gate, an eleventh NAND gate, a twelfth NAND gate, a thirteenth NAND gate, a fourteenth NAND gate, a fifteenth NAND gate, a third NOR gate, a fourth NOR gate, a fifth NOR gate and a sixth NOR gate; The input end of the fourth NOT gate is used to receive the third comparison result of the third storage body group; the input end of the fifth NOT gate is used to receive the third comparison result of the fourth storage body group; the input end of the sixth NOT gate is used to receive the third comparison result of the fifth storage body group; the input end of the seventh NOT gate is used to receive the third comparison result of the sixth storage body group; the input end of the eighth NOT gate is used to receive the third comparison result of the seventh storage body group; the input end of the ninth NOT gate is used to receive the third comparison result of the eighth storage body group; the first input end of the sixth NAND gate is connected to the output end of the fourth NAND gate, and the second input end of the sixth NAND gate is used to receive the third comparison result of the second storage body group; the first input end of the seventh NAND gate is connected to the output end of the sixth NAND gate, and the input end of the seventh NAND gate is connected to the output end of the sixth NAND gate. The second input end is connected to the output end of the fifth NOT gate; the first input end of the eighth NAND gate is connected to the output end of the seventh NAND gate, and the second input end of the eighth NAND gate is connected to the output end of the sixth NAND gate; the first input end of the ninth NAND gate is connected to the output end of the eighth NAND gate, and the second input end of the ninth NAND gate is connected to the output end of the seventh NAND gate; the first input end of the tenth NAND gate is connected to the output end of the ninth NAND gate, and the second input end of the tenth NAND gate is connected to the output end of the eighth NAND gate; the first input end of the eleventh NAND gate is connected to the output end of the tenth NAND gate, and the second input end of the eleventh NAND gate is connected to the output end of the ninth NAND gate, and the output end of the eleventh NAND gate is used to generate the first memory bank group selection flag; The first input end of the third NOR gate is used to receive the third comparison result of the fifth memory bank group, and the second input end of the third NOR gate is used to receive the third comparison result of the sixth memory bank group; the input end of the tenth NOR gate is used to receive the third comparison result of the third memory bank group; the input end of the eleventh NOR gate is used to receive the third comparison result of the fourth memory bank group; the first input end of the sixth NOR gate is used to receive the third comparison result of the seventh memory bank group, and the second input end of the sixth NOR gate is used to receive the third comparison result of the eighth memory bank group; the twelfth NAND gate is used to receive the third comparison result of the eighth memory bank group; The first input end of is connected to the output end of the tenth NOT gate, the second input end of the twelfth NAND gate is connected to the output end of the eleventh NAND gate; the first input end of the thirteenth NAND gate is connected to the output end of the third NOR gate, the second input end of the thirteenth NAND gate is connected to the output end of the twelfth NAND gate; the first input end of the fourteenth NAND gate is connected to the output end of the thirteenth NAND gate, the second input end of the fourteenth NAND gate is connected to the output end of the sixth NOR gate, and the output end of the fourteenth NAND gate is used to generate the second memory bank group selection flag; The first input end of the fourth NOR gate is used to receive the third comparison result of the fifth memory bank group, and the second input end of the fourth NOR gate is used to receive the third comparison result of the sixth memory bank group; the first input end of the fifth NOR gate is used to receive the third comparison result of the seventh memory bank group, and the second input end of the fifth NOR gate is used to receive the third comparison result of the eighth memory bank group; the first input end of the fifteenth NAND gate is connected to the output end of the fourth NOR gate, the second input end of the fifteenth NAND gate is connected to the output end of the fifth NOR gate, and the output end of the fifteenth NAND gate is used to generate the third memory bank group selection flag; The collective fault compression circuit includes: a seventh NOR gate, an eighth NOR gate, a ninth NOR gate, a tenth NOR gate, an eleventh NOR gate, a sixteenth NAND gate and a seventeenth NAND gate; The first input end of the seventh NOR gate is used to receive the third comparison result of the first memory bank group, and the second input end of the seventh NOR gate is used to receive the third comparison result of the second memory bank group; the first input end of the eighth NOR gate is used to receive the third comparison result of the third memory bank group, and the second input end of the eighth NOR gate is used to receive the third comparison result of the fourth memory bank group; the first input end of the ninth NOR gate is used to receive the third comparison result of the fifth memory bank group, and the second input end of the ninth NOR gate is used to receive the third comparison result of the sixth memory bank group; the first input end of the tenth NOR gate is used to receive the third comparison result of the seventh memory bank group, and the second input end of the tenth NOR gate is used to receive the third comparison result of the seventh memory bank group. The second input end of the NOR gate is used to receive the third comparison result of the eighth storage body group; the first input end of the sixteenth NAND gate is connected to the output end of the seventh NOR gate, and the second input end of the sixteenth NAND gate is connected to the output end of the eighth NOR gate; the first input end of the seventeenth NAND gate is connected to the output end of the ninth NOR gate, and the second input end of the seventeenth NAND gate is connected to the output end of the tenth NOR gate; the first input end of the eleventh NOR gate is connected to the output end of the sixteenth NAND gate, and the second input end of the eleventh NOR gate is connected to the output end of the seventeenth NAND gate, and the output end of the eleventh NOR gate is used to generate the fault flag.

14. The built-in self-test circuit according to claim 2, characterized in that: The repair module is also used to receive the storage body flag, latch the storage body flag when the fault flag indicates that there is a data error in the storage data currently being read, and repair the storage unit corresponding to the error address in the storage body indicated by the storage body flag after exiting the self-test mode.

15. The built-in self-test circuit according to any one of claims 1 to 14, characterized in that: The command / address generation module comprises: a clock generating unit, configured to receive a self-test enable signal, and to generate and output a clock signal when the self-test enable signal is at a valid level; A command generation unit, connected to the clock generation unit, for sequentially generating an activation command, a write command / read command and a precharge command that meet the read / write operation timing requirements according to the clock signal; The internal test address includes an internal test row address and an internal test column address; The address generating unit is connected to the clock generating unit and the address generating unit respectively, and is used to generate an internal test row address according to the activation command and the clock signal, and to generate an internal test column address according to the write command / the read command and the clock signal.

16. The built-in self-test circuit according to claim 15, characterized in that: The command generation unit is further used to receive a test mode signal; when the test mode signal is at a first level, indicate that the preset test mode is a row priority test mode, and generate the internal test command according to a row priority addressing mode; When the test mode signal is at the second level, indicating that the preset test mode is a column priority test mode, and generating the internal test command according to the column priority addressing mode; The address generation unit is also used to receive a test mode signal; when the test mode signal is at a first level, it indicates that the preset test mode is a row priority test mode, and generates the internal test address according to the row priority addressing method; when the test mode signal is at a second level, it indicates that the preset test mode is a column priority test mode, and generates the internal test address according to the column priority addressing method.

17. The built-in self-test circuit according to claim 15, characterized in that: The repair module is connected to the processing module and is used to receive the fault flag, and is also connected to the address generation unit and is used to receive the internal test row address or the internal test column address, and when the fault flag indicates that there is a data error in the storage data currently being read, the internal test row address or the internal test column address corresponding to the storage data currently being read is latched as an error address, and the storage cell row or storage cell column corresponding to the error address is repaired after the self-test mode is exited.

18. The built-in self-test circuit according to claim 15, characterized in that: The built-in self-test circuit also includes: The alarm module is used to generate a test alarm signal according to the self-test enable signal and send the test alarm signal to the memory controller.

19. The built-in self-test circuit according to claim 15, characterized in that: The self-test enable signal turns to a valid level when the storage array enters a self-test mode defined by a protocol or a setting mode.

20. A memory, characterized in that: The memory comprises a built-in self-test circuit as claimed in any one of claims 1 to 19.

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